IDT ICS650-41 Packaged in 16-pin tssop Datasheet

DATASHEET
ICS650-41
SPREAD SPECTRUM CLOCK SYNTHESIZER
Description
Features
The ICS650-41 is a spread spectrum clock synthesizer
intended for video projector applications. It generates an
EMI optimized 50 MHz clock signal (EMI peak reduction of
7 to 14 dB on 3rd through 19th harmonics) through the use
of Spread Spectrum techniques from a 25 MHz crystal or
clock input. For the 50 MHz output, the modulation rate is
50 kHz.
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In addition to the EMI optimized clock signal, the device
generates a 48 MHz clock for USB.
Packaged in 16-pin TSSOP (173 mil)
Supply voltages: VDD = 3.3 V, VDDO = 2.5 V
Peak-to-peak jitter: ±125 ps typ
Output duty cycle 45/55% (worst case)
Guarantees +85°C operational condition
25 MHz crystal or reference clock input
Zero (0) ppm frequency error on all output clocks
Advanced, low-power CMOS process
Industrial temperature range
Block Diagram
VDDO
VDD
25 MHz crystal
or clock input
3
X1/CLKIN
PLL1 with
Spread
Spectrum
Crystal
OSC
X2
50M
External capacitors are
required with a crystal
input.
FS3:0
SS_EN
Control
Logic
PLL2
48M
2
GND
PDTS
IDT™ / ICS™ SPREAD SPECTRUM CLOCK SYNTHESIZER
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ICS650-41
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ICS650-41
SPREAD SPECTRUM CLOCK SYNTHESIZER
CLOCK SYNTHESIZER
Pin Assignment
Spread Spectrum and Output
Configuration Table
X1/CLKIN
1
16
X2
FS0
2
15
VDD
FS1
3
14
PDTS
0
SS_EN
4
13
FS2
VDD
5
12
GND
6
FS3
48M
FS3 FS2
0
0
FS1
0
FS0
0
Spread Type
Center
SS Out
±0.25
0
0
1
Center
±0.50
0
0
1
0
Center
±0.75
VDD
0
0
1
1
Center
±1.00
11
GND
0
1
0
0
Center
±1.25
7
10
VDDO
0
1
0
1
Center
±1.50
8
9
0
1
1
0
Center
±1.75
0
1
1
1
Center
±2.00
1
0
0
0
Down
-0.5
1
0
0
1
Down
-0.75
1
0
1
0
Down
-1.0
1
0
1
1
Down
-1.25
1
1
0
0
Down
-1.5
1
1
0
1
Down
-1.75
1
1
1
0
Down
-2.0
1
1
1
1
Down
-2.25
50M
16-pin (173 mil) TSSOP
IDT™ / ICS™ SPREAD SPECTRUM CLOCK SYNTHESIZER
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SPREAD SPECTRUM CLOCK SYNTHESIZER
CLOCK SYNTHESIZER
Pin Descriptions
Pin
Number
1
X1/CLKIN
Pin
Type
Input
2
3
4
5
6
7
8
9
10
11
12
13
14
FS0
FS1
SS_EN
VDD
GND
FS3
48M
50M
VDDO
GND
VDD
FS2
PDTS
Input
Input
Input
Power
Power
Input
Output
Output
Power
Power
Power
Input
Input
15
16
VDD
X2
Power
Output
Pin Name
Pin Description
Crystal input. Connect this pin to a 25 MHz crystal or external input
clock.
Select pin 0. Internal pull-up resistor. See table on page 2.
Select pin 1. Internal pull-up resistor. See table on page 2.
Spread spectrum enable pin. Internal pull-up resistor. Enabled = high.
Connect to +3.3 V.
Connect to ground.
Select pin 3. Internal pull-up resistor. See table on page 2.
Fixed 48 MHz output. Weak internal pull-down when tri-state.
Spread Spectrum output. Weak internal pull-down when tri-stated.
Connect to +2.5 V.
Connect to ground.
Connect to +3.3 V.
Select pin 2. Internal pull-up resistor. See table on page 2.
Powers down entire chip. Tri-states CLK outputs when low. Internal
pull-up.
Connect to +3.3 V.
Crystal Output. Connect this pin to a 25 MHz crystal. Do not connect if
clock input is used.
External Components
Decoupling Capacitor
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
As with any high-performance mixed-signal IC, the
ICS650-41 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between each VDD and the PCB ground plane.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω.
The value (in pF) of these crystal caps should equal (CL -6
pF)*2. In this equation, CL= crystal load capacitance in pF.
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 20 pF [(16-6) x 2] = 20.
Crystal Load Capacitors
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
PCB Layout Recommendations
The device crystal connections should include pads for
IDT™ / ICS™ SPREAD SPECTRUM CLOCK SYNTHESIZER
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CLOCK SYNTHESIZER
3) To minimize EMI, the 33Ω series termination resistor (if
needed) should be placed close to the clock output.
1) The 0.01µF decoupling capacitors should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitors and VDD pins. The PCB trace to VDD pins
should be kept as short as possible, as should the PCB
trace to the ground via.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
ICS650-41. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS650-41. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
0 to +85° C
Storage Temperature
-65 to +150° C
Junction Temperature
125° C
Soldering Temperature (max. of 10 seconds)
260° C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
Units
0
–
+85
°C
Power Supply Voltage (measured in respect to GND)
+3.135
+3.3
+3.465
V
Power Supply Voltage (VDDO)
+2.375
+2.5
+2.625
V
4
ms
Ambient Operating Temperature
Power Supply Ramp Time, Figure 4
IDT™ / ICS™ SPREAD SPECTRUM CLOCK SYNTHESIZER
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CLOCK SYNTHESIZER
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, VDDO = 2.5 V ±5% , Ambient Temperature 0 to +85° C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
no load
27
mA
PDTS = 0, no load
40
uA
no load
4
mA
PDTS = 0, no load
1
uA
IDD
Operating Supply Current
IDDO
Input High Voltage
VIH
FS3:0, PDTS, SS_EN
Input Low Voltage
VIL
FS3:0, PDTS, SS_EN
Input High Voltage
VIH
X1/CLKIN
Input Low Voltage
VIL
X1/CLKIN
Output High Voltage
VOH
IOH = -4 mA
Output Low Voltage
VOL
IOL = 4 mA
Short Circuit Current
IOS
±50
mA
Nominal Output
Impedance
ZO
20
Ω
Internal Pull-up Resistor
Input Leakage Current
2
V
0.8
0.7 x
VDD
V
V
0.3 x
VDD
1.8
V
V
0.6
V
RPU
FS3:0, PDTS, SS_EN
360
kΩ
II
FS3:0, PDTS, SS_EN,
VIN=VDD
1
uA
900
kΩ
4
pF
Internal Pull-down
Resistor
RPD
CLK outputs
Input Capacitance
CIN
Inputs
IDT™ / ICS™ SPREAD SPECTRUM CLOCK SYNTHESIZER
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CLOCK SYNTHESIZER
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, VDDO = 2.5 V ±5%, Ambient Temperature 0 to +85° C
Parameter
Input Frequency
Symbol
FIN
Conditions
Min.
Crystal or clock input
Spread Spectrum Modulation
Frequency
Duty Cycle
t2/t1
at VDD/2, Note 1 and
Figures 1 and 2
45
Typ.
Max. Units
25
MHz
50
kHz
50
55
%
Output Fall Time
t3
80% to 20%, Note 1
and Figures 1 & 3
1.5
ns
Output Rise Time
t4
20% to 80%, Note 1
and Figures 1 & 3
1.5
ns
Note 1
30
ps
ps
One Sigma Clock Period Jitter
Absolute Jitter, Peak-to-Peak
tja
Deviation from mean,
SS_EN=0, Note1 &
Figures 1 and 6
±125
Output Enable Time
tEN
PDTS high to PLL
locked to within 1% of
final value, Figure 5
2.5
Output Disable Time
tDIS
PDTS low to tri-state,
Figure 5
20
tP
PLL lock-time from
power-up to 1% of final
value, Figure 4
6
Power-up Time
5
ms
ns
10
ms
Note 1: Measured with 15 pF load.
IDT™ / ICS™ SPREAD SPECTRUM CLOCK SYNTHESIZER
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Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ.
Max. Units
Thermal Resistance Junction to
Ambient
θ JA
Still air
78
° C/W
θ JA
1 m/s air flow
70
° C/W
θ JA
3 m/s air flow
68
° C/W
Thermal Resistance Junction to Case
θ JC
37
° C/W
Marking Diagram
16
9
650GI41L
######
YYWW
1
8
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and the week number that the part was assembled.
IDT™ / ICS™ SPREAD SPECTRUM CLOCK SYNTHESIZER
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Timing Diagrams
VDDs
Outputs
0.01µF
t1
t2
C LOAD
DUT
VDDO
50% of VD D O
C lo c k
GND
0V
Figure 1: Test and Measurement Setup
t4
t3
Figure 2: Duty Cycle Definitions
Power Up
Tim e
VCO Ram p
Tim e
PLL Locked
VDD
VDDO
80% of VDDO
0V
20% of VDDO
0V
Clock
Output
VDD
0V
0 ms
4 ms
10 m s
Figure 3: Rise and Fall Time Definitions
Figure 4: Power Up and PLL Lock Timing
PDTS
1 .25 V
1.25 V
1%
t D IS
t EN
C LK
O utputs
Mean value
VOH
Absolute jitter
(p - p)
0V
tJA
Figure 6: Short Term Jitter Definition
Figure 5: PDTS to Stable Clock Output Timing
IDT™ / ICS™ SPREAD SPECTRUM CLOCK SYNTHESIZER
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ICS650-41
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ICS650-41
SPREAD SPECTRUM CLOCK SYNTHESIZER
CLOCK SYNTHESIZER
Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
16
Symbol
E1
A
A1
A2
b
C
D
E
E1
e
L
α
aaa
E
INDEX
AREA
1 2
D
Min
Inches
Max
-1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
4.90
5.1
6.40 BASIC
4.30
4.50
0.65 Basic
0.45
0.75
0°
8°
-0.10
Min
Max
-0.047
0.002
0.006
0.032
0.041
0.007
0.012
0.0035 0.008
0.193
0.201
0.252 BASIC
0.169
0.177
0.0256 Basic
0.018
0.030
0°
8°
-0.004
A
A2
A1
c
-Ce
b
SEATING
PLANE
L
aaa C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
650GI-41LF
650GI-41LFT
650GI41L
Tubes
16-pin TSSOP
0 to +85° C
650GI41L
Tape and Reel
16-pin TSSOP
0 to +85° C
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ SPREAD SPECTRUM CLOCK SYNTHESIZER
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ICS650-41
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SPREAD SPECTRUM CLOCK SYNTHESIZER
CLOCK SYNTHESIZER
Revision History
Rev.
Originator
Date
B
P.Griffith
10/07/04
Changed the input frequency from 14.31818 to 25 MHz; changed Short Circuit Current
from ±70 to ±50; added separate Pull-up resistor spec for SS_EN; added “I” to part
ordering number
C
P. Griffith
11/15/04
Changed AC and DC parameters to reflect measured char values: IDD, IDDO, VIH, VIL,
RPU, II, RPD, t1,.t2, t3, t4, tja, tEN, tDIS, tP. Added Figures for key parameters.
D
P. Griffith
12/06/04
Changed jitter spec to +/-150 ps and duty cycle to 45% min, 55% max.
E
P. Griffith
1/17/05
Renamed pin 1 to X1/CLKin on page2, improved jitter spec to +/-125 ps on front page and
in electrical tables, changed rise and fall time to 1.5 ns typical to reflect balanced drive,
changed typical ID spec to 4 ma, updated graphs on page 8 to reflect separate VDDO and
correct bypass capacitor value, updated marking diagram and ordering table to reflect
Pb-free device.
10/27/09
Updated ordering information
G
Description of Change
IDT™ / ICS™ SPREAD SPECTRUM CLOCK SYNTHESIZER
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ICS650-41
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ICS650-41
SPREAD SPECTRUM CLOCK SYNTHESIZER
CLOCK SYNTHESIZER
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