ACT–F512K8 High Speed
4 Megabit Monolithic FLASH
CIRCUIT TECHNOLOGY
www.aeroflex.com
Features
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Low Power Monolithic 512K x 8 FLASH
TTL Compatible Inputs and CMOS Outputs
Access Times of 60, 70, 90, 120 and 150ns
+5V Programing, 5V ±10% Supply
100,000 Erase / Program Cycles
Low Standby Current
Page Program Operation and Internal
Program Control Time
Supports Full Chip Erase
Embedded Erase and Program Algorithms
Supports Full Chip Erase
MIL-PRF-38534 Compliant Circuits Available
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Industry Standard Pinouts
Packaging – Hermetic Ceramic
32 Lead, 1.6" x .6" x .20" Dual-in-line Package (DIP),
Aeroflex code# "P4"
● 32 Lead, .82" x .41" x .11" Ceramic Flat Package
(FP), Aeroflex code# "F6"
● 32 Lead, .82" x .41" x .132" Ceramic Flat Package
(FP Lead Formed), Aeroflex code# "F7"
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Sector Architecture
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8 Equal size sectors of 64K bytes each
Any Combination of Sectors ccan be erased with one
command sequence.
Commercial, Industrial and Military
Temperature Ranges
DESC SMD Pending
5962-96692 (P4,F6,F7)
Block Diagram – DIP (P4) & Flat Packages (F6,F7)
CE
WE
OE
A0 – A18
Vss
512Kx8
Vcc
8
I/O0-7
Pin Description
I/O0-7
Data I/O
A0–18 Address Inputs
WE
Write Enable
CE
Chip Enable
OE
Output Enable
VCC
Power Supply
VSS
Ground
NC
Not Connected
General Description
The ACT–F512K8 is a high
speed, 4 megabit CMOS
monolithic
Flash
module
designed for full temperature
range military, space, or high
reliability applications.
This device is input TTL and
output CMOS compatible. The
command register is written by
bringing WE to a logic low level
(VIL), while CE is low and OE is
at logic high level (VIH). Reading
is accomplished by chip Enable
(CE) and Output Enable (OE)
being logically active, see
Figure 9. Access time grades of
60ns, 70ns, 90ns, 120ns and
150ns maximum are standard.
The
ACT–F512K8
is
available
in a
choice of
eroflex Circuit Technology - Advanced Multichip Modules © SCD1668 REV A 4/28/98
General Description, Cont’d,
second. Erase is accomplished by
executing the erase command sequence.
This will invoke the Embedded Erase
Algorithm which is an internal algorithm
that automatically preprograms the array, (if
it is not already programmed before)
executing the erase operation. During
erase, the device automatically times the
erase pulse widths and verifies proper cell
margin.
The device is typically erased and
verified in 1.5 seconds (if already
completely preprogrammed).
Also the device features a sector erase
architecture. The sector mode allows for
64K byte blocks of memory to be erased
and reprogrammed without affecting other
blocks. The ACT-F512K8 is erased when
shipped from the factory.
The device features single 5.0V power
supply operation for both read and write
functions.
lnternally
generated
and
regulated voltages are provided for the
program and erase operations. A low VCC
detector
automatically
inhibits
write
operations on the loss of power. The end of
program or erase is detected by Data
Polling of D7 or by the Toggle Bit feature on
D6. Once the end of a program or erase
cycle has been completed, the device
internally resets to the read mode.
All bits of each die, or all bits within a
sector of a die, are erased via
Fowler-Nordhiem tunneling. Bytes are
programmed one byte at a time by hot
electron injection.
A DESC Standard Military Drawing
(SMD) number is pending.
hermetically sealed ceramic packages; a
32 lead .82" x .41" x .11" flat package in
both formed or unformed leads or a 32 pin
1.6"x.60" x.20" DIP package for operation
over the temperature range -55°C to
+125°C
and
military
environmental
conditions.
The flash memory is organized as
512Kx8
bits and is designed to be
programmed in-system with the standard
system 5.0V Vcc supply. A 12.0V VPP is
not required for write or erase operations.
The device can also be reprogrammed with
standard EPROM programmers (with the
proper socket).
The standard ACT–F512K8 offers
access times between 60ns and 150ns,
allowing
operation
of
high-speed
microprocessors without wait states. To
eliminate bus contention, the device has
separate chip enable (CE), write enable
(WE) and output enable (OE) controls. The
ACT–F512K8 is command set compatible
with JEDEC standard 1 Mbit EEPROMs.
Commands are written to the command
register using standard microprocessor
write timings. Register contents serve as
input to an internal state-machine which
controls the erase and programming
circuitry. Write cycles also internally latch
addresses and data needed for the
programming and erase operations.
Reading data out of the device is similar
to reading from 12.0V Flash or EPROM
devices. The ACT–F512K8 is programmed
by executing the program command
sequence. This will invoke the Embedded
Program Algorithm which is an internal
algorithm that automatically times the
program pulse widths and verifies proper
cell margin. Typically, each sector can be
programmed and verified in less than 0.3
Aeroflex Circuit Technology
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SCD1668 REV A 4/28/98
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z
Absolute Maximum Ratings
Parameter
Symbol
Range
Units
Case Operating Temperature
TC
-55 to +125
°C
Storage Temperature Range
TSTG
-65 to +150
°C
Supply Voltage Range
VCC
-2.0 to +7.0
V
Signal Voltage Range (Any Pin Except A9) Note 1
VG
-2.0 to +7.0
V
Maximum Lead Temperature (10 seconds)
300
°C
Data Retention
10
Years
100,000 Minimum
Endurance (Write/Erase cycles)
-2.0 to +14.0
VID
A9 Voltage for sector protect, Note 2
V
Note 1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VSS to -2.0v for periods of
up to 20ns. Maximum DC voltage on input and I/O pins is VCC + 0.5V. During voltage transitions, inputs and I/O pins may
overshoot to VCC + 2.0V for periods up to 20 ns.
Note 2. Minimum DC input voltage on A9 is -0.5V. During voltage transitions, A9 may undershoot VSS to -2.0V for periods of up to 20ns.
Maximum DC input voltage on A9 is +12.5V which may overshoot to 14.0V for periods up to 20ns.
Normal Operating Conditions
Symbol
Parameter
Minimum
Maximum
Units
VCC
Power Supply Voltage
+4.5
+5.5
V
VIH
Input High Voltage
+2.0
VCC + 0.5
V
VIL
Input Low Voltage
-0.5
+0.8
V
Tc
Operating Temperature (Military)
-55
+125
°C
VID
A9 Voltage for sector protect
11.5
12.5
V
Capacitance
(VIN= 0V, f = 1MHz, Tc = 25°C)
Symbol
CAD
COE
Parameter
Maximum
Units
A0 – A18 Capacitance
15
pF
OE Capacitance
15
pF
CWE
Write Enable Capacitance
15
pF
CCE
Chip Enable Capacitance
15
pF
I/O0 – I/O7 Capacitance
15
pF
CI/O
Parameters Guaranteed but not tested
DC Characteristics – CMOS Compatible
(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C, unless otherwise indicated)
Parameter
Input Leakage Current
Output Leakage Current
Sym
ILI
Speeds 60, 70, 90, 120 & 150ns
Conditions
Minimum
VCC = 5.5V, VIN = GND to VCC
ILOX32 VCC = 5.5V, VIN = GND to VCC
Maximum
Units
10
µA
10
µA
Active Operating Supply Current for Read (1)
ICC1
CE = VIL, OE = VIH, f = 5MHz
50
mA
Active Operating Supply Current for Program or Erase (2)
ICC2
CE = VIL, OE = VIH
60
mA
Operating Standby Supply Current
ICC3
VCC = 5.5V, CE = VIH, f = 5MHz
1.6
mA
Output Low Voltage
VOL
IOL = +8.0 mA, VCC = 4.5V
0.45
V
Output High Voltage
VOH
IOH = –2.5 mA, VCC = 4.5V
Low Power Supply Lock-Out Voltage (4)
VLKO
0.85 x VCC
V
3.2
V
Note 1. The Icc current listed includes both the DC operating current and the frequency dependent component (At 6 MHz). The frequency
component typically is less than 2 mA/MHz, with OE at VIN.
Note 2. Icc active while Embedded Algorithm (Program or Erase) is in progress.
Note 3. DC Test conditions: VIL = 0.3V, VIH = VCC - 0.3V, unless otherwise indicated.
Note 4. Parameter Guaranteed by design, but not tested.
Aeroflex Circuit Technology
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SCD1668 REV A 4/28/98
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AC Characteristics – Read Only Operations
(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)
Symbol
Parameter
–60
–70
–90
–120
–150
JEDEC Stand’d Min Max Min Max Min Max Min Max Min Max
Read Cycle Time
tAVAV
tRC
60
70
90
120
150
Units
ns
Address Access Time
tAVQV
tACC
60
70
90
120
150
ns
Chip Enable Access Time
tELQV
tCE
60
70
90
120
150
ns
Output Enable to Output Valid
tGLQV
tOE
30
35
35
50
55
ns
Chip Enable to Output High Z (1)
tEHQZ
tDF
20
20
20
30
35
ns
Output Enable High to Output High Z(1)
tGHQZ
tDF
35
ns
Output Hold from Address, CE or OE Change, Whichever is First
tAXQX
tOH
20
0
20
0
20
0
30
0
0
ns
Note 1. Guaranteed by design, but not tested
AC Characteristics – Write/Erase/Program Operations, WE Controlled
(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)
Symbol
Parameter
–60
–70
–90
–120
–150
JEDEC Stand’d Min Max Min Max Min Max Min Max Min Max
Units
Write Cycle Time
tAVAC
tWC
60
70
90
120
150
ns
Chip Enable Setup Time
tELWL
tCE
0
0
0
0
0
ns
Write Enable Pulse Width
tWLWH
tWP
40
45
45
50
50
ns
Address Setup Time
tAVWL
tAS
0
0
0
0
0
ns
Data Setup Time
tDVWH
tDS
40
45
45
50
50
ns
Data Hold Time
tWHDX
tDH
0
0
0
0
0
ns
Address Hold Time
tWLAX
tAH
45
45
45
50
50
ns
Write Enable Pulse Width High
tWHWL
tWPH
20
20
20
20
20
ns
Duration of Byte Programming Operation
Typ = 16 µs
tWHWH1
Sector Erase Time
tWHWH2
Read Recovery Time before Write
14 TYP 14 TYP 14 TYP 14 TYP 14 TYP
30
tGHWL
tVCE
Vcc Setup Time
30
30
30
Sec
0
0
0
0
0
µs
50
50
50
50
50
µs
Chip Programming Time
tWHWH3
Chip Erase Time
30
µs
50
50
50
50
50
Sec
120
120
120
120
120
Sec
AC Characteristics – Write/Erase/Program Operations, CE Controlled
(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)
Parameter
Symbol
–60
–70
–90
–120
–150
JEDEC Stand’d Min Max Min Max Min Max Min Max Min Max
Write Cycle Time
tAVAC
tWC
60
70
90
Write Enable Setup Time
tWLEL
tWS
0
0
0
Chip Enable Pulse Width
tELEH
tCP
40
45
45
120
Units
150
ns
0
0
ns
50
55
ns
Address Setup Time
tAVEL
tAS
0
0
0
0
0
ns
Data Setup Time
tDVEH
tDS
40
45
45
50
55
ns
Data Hold Time
tEHDX
tDH
0
0
0
0
0
ns
Address Hold Time
tELAX
tAH
45
45
45
50
55
ns
Chip Select Pulse Width High
tEHEL
tCPH
20
20
20
20
20
Duration of Byte Programming
tWHWH1
Sector Erase Time
tWHWH2
Read Recovery Time
tGHEL
Chip Programming Time
Chip Erase Time
Aeroflex Circuit Technology
tWHWH3
4
ns
14 TYP 14 TYP 14 TYP 14 TYP 14 TYP
30
0
30
0
30
0
30
0
30
0
µs
Sec
ns
50
50
50
50
50
Sec
120
120
120
120
120
Sec
SCD1668 REV A 4/28/98
Plainview NY (516) 694-6700
WRITE
Device Operation
Device erasure and programming are accomplished via
the command register. The contents of the register
serve as input to the internal state machine. The state
machine outputs dictate the function of the device.
The command register itself does not occupy an addressable memory location. The register is a latch used to
store the command, along with address and data information needed to execute the command. The command
register is written by bringing WE to a logic low level
(VIL), while CE is low and OE is at VIH. Addresses are
latched on the falling edge of WE or CE, whichever happens later. Data is latched on the rising edge of the WE
or CE whichever occurs first. Standard microprocessor
write timings are used. Refer to AC Program Characteristics and Waveforms, Figures 3, 8 and 13.
The ACT–F512K8 Monolithic is composed of One, Four
megabit flash device. Programming of the ACT–F512K8
is accomplished by executing the program command
sequence. The program algorithm, which is an internal
algorithm, automatically times the program pulse widths
and verifies proper cell status. Sectors can be programed and verified in less than 1 second. Erase is
accomplished by executing the erase command
sequence. The erase algorithm, which is internal, automatically preprograms the array if it is not already programed before executing the erase operation. During
erase, the device automatically times the erase pulse
widths and verifies proper cell status. The entire memory is typically erased and verified in 1.5 seconds (if
pre-programmed). The sector mode allows for 64K byte
blocks of memory to be erased and reprogrammed without affecting other blocks.
Command Definitions
Device operations are selected by writing specific
address and data sequences into the command register.
Table 3 defines these register command sequences.
Bus Operation
READ
The ACT–F512K8 has two control functions, both of
which must be logically active, to obtain data at the outputs. Chip Enable (CE) is the power control and should
be used for device selection. Output-Enable (OE) is the
output control and should be used to gate data to the
output pins of the chip selected. Figure 7 illustrates AC
read timing waveforms.
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command register. Microprocessor read cycles retrieve array data from
the memory. The device remains enabled for reads until
the command register contents are altered.
The device will automatically power-up in the read/reset
state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will
retrieve array data.
The device will automatically
power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard
Microprocessor read cycles will retrieve array data. This
default value ensures that no spurious alteration of the
memory content occurs during the power transition.
Refer to the AC Read Characteristics and Figure 7 for
the specific timing parameters.
OUTPUT DISABLE
With Output-Enable at a logic high level (VIH), output
from the device is disabled. Output pins are placed in a
high impedance state.
STANDBY MODE
The ACT-F512K8 standby mode consumes less than 6.5
mA. In the standby mode the outputs are in a high
impedance state, independent of the OE input. If the
device is deselected during erasure or programming, the
device will draw active current until the operation is completed.
BYTE PROGRAMING
The device is programmed on a byte-byte basis. Programming is a four bus cycle operation. There are two
"unlock" write cycles. These are followed by the program
Table 2 – Sector Addresses Table
Table 1 – Bus Operations
Operation
CE OE WE A0 A1 A9
I/O
A14
Address Range
READ
L
L
H
A0 A1 A9
DOUT
SA0
0
0
0
00000h – 03FFFh
STANDBY
H
X
X
X
HIGH Z
SA1
0
0
1
04000h – 07FFFh
HIGH Z
SA2
0
1
0
08000h – 0BFFFh
SA3
0
1
1
0C000h – 0FFFFh
SA4
1
0
0
10000h – 13FFFh
SA5
1
0
1
14000h – 17FFFh
SA6
1
1
0
18000h – 1BFFFh
SA7
1
1
1
1C000h – 1FFFFh
X
OUTPUT DISABLE
L
H
H
X
WRITE
L
H
L
A0 A1 A9
ENABLE SECTOR
PROTECT
VERIFY SECTOR
PROTECT
Aeroflex Circuit Technology
L
L
VID
L
L
H
X
L
X
X
X
H
X
VID
VID
A16 A15
DIN
X
Code
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SCD1668 REV A 4/28/98
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Table 3 — Commands Definitions
Command
Sequence
Bus
Write
Cycles
Required
First Bus Write Second Bus Write Third Bus Write
Cycle
Cycle
Cycle
Addr
Data
Read/Reset
1
XXXH
F0H
Read/Reset
4
5555H
Autoselect
4
5555H
Fourth Bus
Read/Write Cycle
Addr
Data
Addr
Data
Addr
Data
AAH
2AAAH
55H
5555H
F0H
RA
RD
AAH
2AAAH
55H
5555H
90H
Fifth Bus Write Sixth Bus Write
Cycle
Cycle
Addr
Data
Addr
Data
Byte Program
6
5555H
AAH
2AAAH
55H
5555H
A0H
PA
PD
Chip Erase
6
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
5555H
10H
Sector Erase
6
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
SA
30H
Sector Erase Suspend Erase can be suspended during sector erase with Address (Don’t care), Data (B0H)
Sector Erase Resume
Erase can be resumed after suspend with Address (Don’t care), Data (30H)
NOTES:
1. Address bit A15, A16, A17 and A18 = X = Don't Care. Write Sequences may be initiated with A15 in either state.
2. Address bit A15, A16, A17 and A18 = X = Don't Care for all address commands except for Program Address (PA) and Sector Address (SA).
3. RA = Address of the memory location to be read
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.
SA = Address of the sector to be erased. The combination of A18, A17, A16 will uniquely select any sector.
4. RD = Data read from location RA during read Operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
SECTOR ERASE
set-up command and data write cycles. Addresses are
latched on the falling edge of CE or WE, whichever
occurs later, while the data is latched on the rising edge
of CE or WE whichever occurs first. The rising edge of
CE or WE begins programming. Upon executing the program algorithm command sequence the system is not
required to provide further controls or timings. The
device will automatically provide adequate internally
generated program pulses and verity the programmed
cell status. The automatic programming operation is
completed when the data on D7 is equivalent to data
written to this bit at which time the device returns to the
read mode and addresses are no longer latched. The
device requires a valid address be supplied by the System at this time. Data Polling must be performed at the
memory location which is being programmed.
Programming is allowed in any address sequence and
across sector boundaries.
Figure 3 illustrates the programming algorithm using typical command strings and bus operations.
Sector erase is a six bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"setup" command. Two more "unlock" write cycles are
then followed by the sector erase command. The sector
address (any address location within the desired sector)
is latched on the falling edge of WE, while the command
(data) is latched on the rising edge of WE. A time-out of
100µs from the rising edge of the last sector erase command will initiate the sector erase command(s).
Multiple sectors may be erased concurrently by writing
the six bus cycle operations as described above. This
sequence is followed with writes of the sector erase command 30H to address in other sectors desired to be concurrently erased. A time-out of 100µs from the rising
edge of the WE pulse for the last sector erase command
will initiate the sector erase. If another sector erase
command is written within the 100µs time-out window
the timer is reset. Any command other than sector erase
within the time-out window will reset the device to the
read mode, ignoring the previous command string.
Loading the sector erase buffer may be done in any
sequence and with any number of sectors (0 to 7).
Sector erase does not require the user to program the
device prior to erase. The device automatically programs all memory locations in the sector(s) to be erased
prior to electrical erase. When erasing a sector or sectors the remaining unselected sectors are not affected.
The system is not required to provide any controls or timings during these operations.
CHIP ERASE
Chip erase is a six bus cycle operation. There are two
'unlock' write cycles. These are followed by writing the
'set-up' command. Two more 'unlock' write cycles are
then followed by the chip erase command.
Chip erase does not require the user to program the
device prior to erase. Upon executing the erase algorithm (Figure 4) sequence the device automatically will
program and verify the entire memory for an all zero data
pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last
WE pulse in the command sequence and terminates
when the data in D7 is "1" (see Write Operation Status
section - Table 4) at which time the device returns to read
the mode. See Figures 4 and 9.
Aeroflex Circuit Technology
Data Protection
The ACT–F512K8 is designed to offer protection against
accidental erasure or programming caused by spurious
system level singles that may exist during power transitions. During power up the device automatically resets
the internal state machine in the read mode. Also, with
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SCD1668 REV A 4/28/98
Plainview NY (516) 694-6700
rithm operation is close to being completed, data pins
(D7) change asynchronously while the output enable
(OE) is asserted low. This means that the device is driving status information on D7 at one instance of time and
then that byte's valid data at the next instant of time.
Depending on when the system samples the D7 Output,
it may read the status or valid data. Even if the device
has completed internal algorithm operation and D7 has a
valid data, the data outputs on D0 - D6 may be still
invalid. The valid data on D0 - D7 will be read on the successive read attempts. The Data Polling feature is only
active during the programming algorithm, erase algorithm, or sector erase time-out.
See Figures 6 and 10 for the Data Polling specifications.
its control register architecture, alteration of the memory
content only occurs after successful completion of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent
inadvertent write cycles resulting from Vcc power-up and
power-down transitions or system noise.
LOW Vcc WRITE INHIBIT
To avoid initiation of a write cycle during Vcc power-up
and power-down, a write cycle is locked out for VCC less
than 3.2V (typically 3.7V). If VCC < VLKO, the command
register is disabled and all internal program/erase circuits are disabled. Under this condition the device will
reset to read mode. Subsequent writes will be ignored
until the Vcc level is greater than VLKO. It is the users
responsibility to ensure that the control pins are logically
correct to prevent unintentional writes when Vcc is above
3.2V.
D6
TOGGLE BIT
The ACT–F512K8 also features the "Toggle Bit" as a
method to indicate to the host system that algorithms are
in progress or completed.
During a program or erase algorithm cycle, successive
attempts to read data from the device will result in D6
toggling between one and zero. Once the program or
erase algorithm cycle is completed, D6 Will stop toggling
and valid data will be read on successive attempts. During programming the Toggle Bit is valid after the rising
edge of the fourth WE pulse in the four write pulse
sequence. For chip erase the Toggle Bit is valid after the
rising edge of the sixth WE pulse in the six write pulse
sequence. For Sector erase, the Toggle Bit is valid after
the last rising edge of the sector erase WE pulse. The
Toggle Bit is active during the sector time out.
See Figure 1 and 5.
WRITE PULSE GLITCH PROTECTION
Noise pulses of less than 5ns (typical) on OE, CE or WE
will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding anyone of OE = VIL, CE =
VIH or WE = VIH. To initiate a write cycle CE and WE
must be logical zero while OE is a logical one.
POWER-UP WRITE INHIBIT
Power-up of the device with WE = CE = VIL and OE =
VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the
read mode on power-up.
D5
EXCEEDED TIMING LIMITS
D5 will indicate if the program or erase time has
exceeded the specified limits. Under these conditions
D5 will produce a "1". The Program or erase cycle was
not successfully completed. Data Polling is the only
operation function of the device under this condition.
The CE circuit will partially power down the device under
these conditions by approximately 2 mA. The OE and
WE pins will control the output disable functions as
shown in Table 1. To reset the device, write the reset
command sequence to the device. This allows the system to continue to use the other active sectors in the
device.
Write Operation Status
D7
DATA POLLING
The ACT-F512K8 features Data Polling as a method to
indicate to the host that the internal algorithms are in
progress or completed. During the program algorithm, an
attempt to read the device will produce compliment data
of the data last written to D7. During the erase algorithm,
an attempt to read the device will produce a "0" at the D7
Output. Upon completion of the erase algorithm an
attempt to read the device will produce a "1" at the D7
Output.
For chip Erase, the Data Polling is valid after the rising
edge of the sixth WE pulse in the six write pulse
sequence. For sector erase, the Data Polling is valid after
the last rising edge of the sector erase WE pulse. Data
polling must be performed at a sector address within any
of the sectors being erased and not a protected sector.
Otherwise, the status may not be valid. Once the algoAeroflex Circuit Technology
D3
SECTOR ERASE TIMER
After the completion of the initial sector erase command
sequence the sector erase time-out will begin. D3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase command sequence.
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SCD1668 REV A 4/28/98
Plainview NY (516) 694-6700
00H for unprotected sector. In this mode, the lower order
addresses, except for 0, A1, and A6 are don't care.
It is also possible to verify if a sector is protected during
the sector protection operation. This is done by setting
A6 = CE = OE = VIL and WE = VIH (A9 remains high at
VID). Reading the device at address location XXX2H,
where the higher order addresses (A18, A17, and A16)
define a particular sector, will produce 01H at data outputs (D0 - D7) for a protected sector.
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, D3 may be
used to determine if the sector erase timer window is still
open. If D3 is high ("1") the internally controlled erase
cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle
Bit. If D3 is low ("0"), the device will accept additional
sector erase commands. To ensure the command has
been accepted, the software should check the status of
D3 prior to and following each subsequent sector erase
command. If D3 were high on the second status check,
the command may not have been accepted. See Table 4
SECTOR UNPROTECT
The ACT-F512K8 also features a sector unprotect mode,
so that a protected sector may be unprotected to incorporate any changes in the code. All sectors should be
protected prior to unprotecting any sector.
To activate this mode, the programming equipment must
force Vid on control pins OE, CE, and address pin A9.
The address pins A6, A16, and A12 should be set to VIH.
The unprotection mechanism begins on the falling edge
of the WE pulse and is terminated with the rising edge of
the same.
It is also possible to determine if a sector is unprotected
in the system by writing the autoselect command and A6
is set at VIH. Performing a read operation at address
location XXX2H, where the higher order addresses (A18,
A17, and A16) define a particular sector address, will produce 00H at data outputs (D0-D7) for an unprotected
sector.
Sector Protection
Algorithims
SECTOR PROTECTION
The ACT-F512K8 features hardware sector protection
which will disable both program and erase operations to
an individual sector or any group of sectors. To activate
this mode, the programming equipment must force VID
on control pin OE and address pin A9. The sector
addresses should be set using higher address lines A18,
A17, and A16. The protection mechanism begins on the
falling edge of the WE pulse and is terminated with the
rising edge of the same.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A16, A17, and A18) while (A6, A1, A0) =
(0, 1, 0,) will produce a logical "1" code at device output
D0 for a protected sector. Otherwise the device will read
Aeroflex Circuit Technology
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SCD1668 REV A 4/28/98
Plainview NY (516) 694-6700
Table 4 — Hardware Sequence Flags
In Progress
Status
D7
D6
Auto-Programming
D7
Toggle
0
0
0
Toggle
0
1
D7
Toggle
1
1
0
Toggle
1
1
Programming in Auto Erase
Exceeding Time Limits
Auto-Programming
Programming in Auto Erase
D5 D3
D2 – D0
D
D
Figure 1
AC Waveforms for Toggle Bit During Embedded Algorithm Operations
CE
tOEH
WE
tOES
OE
(1)
Data
D0-D7
D6=Toggle
D6=Toggle
D6
Stop Toggle
D0-D7
Valid
Note:
1. D6 stops toggling (The device has completed the embedded operation)
Figure 2
AC Test Circuit
Current Source
IOL
VZ ~ 1.5 V (Bipolar Supply)
To Device Under Test
CL =
50 pF
IOH
Parameter
Typical
Units
Input Pulse Level
0 – 3.0
V
5
ns
Input Rise and Fall
Input and Output Timing Reference Level
1.5
V
Output Lead Capacitance
50
pF
Current Source
Notes:
1) VZ is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance
ZO = 75Ω. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical
resistance load circuit. 6) ATE Tester includes jig capacitance.
Aeroflex Circuit Technology
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SCD1668 REV A 4/28/98
Plainview NY (516) 694-6700
Figure 3
Programming Algorithm
Bus
Operations
Command
Sequence
Comments
Program
Valid Address/Data Sequence
Standby (1)
Write
Read
Data Polling to Verify Programming
Standby (1)
Compare Data Output to Data Expected
Note:
1. Device is either powered-down, erase or program inhibit.
Start
Write Program Command Sequence
(See Below)
Data Poll Device
Increment
Address
No
Last Address
?
Yes
Programming Complete
Program Command Sequence (Address/Command):
5555H/AAH
2AAAH/55H
5555H/A0H
Programming Address/Program Data
Aeroflex Circuit Technology
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SCD1668 REV A 4/28/98
Plainview NY (516) 694-6700
Figure 4
Erase Algorithm
Bus
Operations
Command
Sequence
Comments
Program
Valid Address/Data Sequence
Standby
Write
Read
Data Polling to Verify Programming
Standby
Compare Data Output to Data Expected
Start
Write Erase Command Sequence
(See Below)
Data Poll or Toggle Bit
Successfully Completed
Erasure Completed
Chip Erase Command Sequence
(Address/Command)
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command)
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/80H
5555H/80H
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/10H
Sector Address/30H
Sector Address/30H
Additional Sector
Erase Commands
are Optional
Sector Address/30H
Aeroflex Circuit Technology
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SCD1668 REV A 4/28/98
Plainview NY (516) 694-6700
Figure 5
Toggle Bit Algorithm
Figure 6
Data Polling Algorithm
Start
Read Byte
D0-D7
Address = VA
D6 = Toggle
?
Start
VA = Byte Address for Programming
= Any of the Sector Addresses
within the sector being erased
during sector erase operation
= XXXXH during Chip Erase
Read Byte
D0-D7
Address = VA
No
D7 =
Toggle?
No
D5 = 1
?
D5 = 1
?
Yes
Yes
Read Byte
D0-D7
Address = VA
D6 =
Toggle?
(Note 1)
Yes
Read Byte
D0-D7
Address = VA
D7 =
Data
?
No
Pass
No
Fail
Yes
Pass
Fail
Note 1. D7 is rechecked even if D5 = "1" because D7 may change
simultaneously with D5.
Note 1. D6 is rechecked even if D5 = "1" because D6 may stop toggling at
the same time as D5 changes to "1".
Aeroflex Circuit Technology
Yes
No
Yes
No
VA = Byte Address for Programming
= Any of the Sector Addresses
within the sector being erased
during sector erase operation
= XXXXH during Chip Erase
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SCD1668 REV A 4/28/98
Plainview NY (516) 694-6700
Figure 7
AC Waveforms for Read Operations
tRC
Addresses
Addresses Stable
tACC
CE
tDF
OE
tOE
WE
tCE
tOH
High Z
Outputs
Output Valid
High Z
Figure 8
Write/Erase/Program
Operation, WE Controlled
Data Polling
Addresses
5555H
PA
tWC
tAS
PA
tRC
tAH
CE
tGHWL
OE
tWP
tWHWH1
tWPH
WE
tCE
tDF
tOE
tDH
AOH
Data
PD
D7
DOUT
tDS
tOH
5.0V
tCE
Notes:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the 0utput of the complement of the data written to the deviced.
4. Dout is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
Aeroflex Circuit Technology
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SCD1668 REV A 4/28/98
Plainview NY (516) 694-6700
Figure 9
AC Waveforms Chip/Sector
Erase Operations
Data Polling
tAH
5555H
Addresses
2AAAH
5555H
5555H
2AAAH
SA
tAS
CE
tGHWL
OE
tWP
WE
tCE
tWPH
tDH
AAH
Data
55H
80H
AAH
55H
10H/30H
tDS
VCC
tVCE
Notes:
1. SA is the sector address for sector erase.
Figure 10
AC Waveforms for Data Polling
During Embedded Algorithm Operations
tCH
CE
tDF
tOE
OE
tOEH
tCE
WE
tOH
*
DQ7
DQ7
High Z
DQ7=
Valid Data
tWHWH1 or 2
DQ0-DQ6
DQ0–DQ6
Valid Data
DQ0–DQ6=Invalid
tOE
* DQ7=Valid Data (The device has completed the Embedded operation).
Aeroflex Circuit Technology
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SCD1668 REV A 4/28/98
Plainview NY (516) 694-6700
Figure 11
Sector Protection Algorithm
Start
Set Up Sector Address
(A18, A17, A16)
PLSCNT = 1
OE = VID
A9 = VID, CE = VIL
Activate WE Pulse
Time Out 100µs
Increment
PLSCNT
Power Down OE
WE = VIH
CE = OE = VIH
A9 Should Remain VID
Read From Sector
Address = SA, A0 = 0, A1 = 1, A6 = 0
No
No
Data = 01H
?
PLSCNT = 25
?
Yes
Yes
Device Failure
Protect
Another
Sector?
Yes
No
Remove VID from A9
Write Reset Command
Sector Protection
Complete
Aeroflex Circuit Technology
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SCD1668 REV A 4/28/98
Plainview NY (516) 694-6700
Figure 12
Sector Unprotect Algorithm
Start
Protect All Sectors
PLSCNT = 1
Set Up Sector
Unprotect Mode
A12 = A16 = VIH
Set
OE = CE = A9 = VID
Activate WE Pulse
Increment
PLSCNT
Time Out 10 msms
Set OE = CE = VIL
A9 = VID
Setup Sector Address SA0
Set A1 = 1, A0 = 0, A6 = 1
Read Data
From Device
No
Increment
Sector Address
No
Data = 00H
?
Yes
No
Sector
Address = SA7
?
PLSCNT = 1000
?
Yes
Device Failure
Yes
Notes:
SA0 = Sector Address for initial sector
SA7 = Sector Address for last sector
Please refer to Table 2
Remove VID from A9
Sector Unprotect
Completed
Aeroflex Circuit Technology
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SCD1668 REV A 4/28/98
Plainview NY (516) 694-6700
Figure 13
Alternate CE Controlled Programming Operation Timings
Data Polling
Addresses
5555H
PA
tWC
tAS
PA
tAH
CE
tGHWL
OE
tCP
WE
tWHWH1
tCPH
tWS
tDH
AOH
Data
PD
D7
DOUT
tDS
5.0V
Notes:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the 0utput of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
Aeroflex Circuit Technology
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SCD1668 REV A 4/28/98
Plainview NY (516) 694-6700
Pin Numbers & Functions
32 Pins — DIP Package
1
A18
17
I/O3
2
A16
18
I/O4
3
A15
19
I/O5
4
A12
20
I/O6
5\
A7
21
I/O7
6
A6
22
CS
7
A5
23
A10
8
A4
24
OE
9
A3
25
A11
10
A2
26
A9
11
A1
27
A8
12
A0
28
A13
13
I/O0
29
A14
14
I/O1
30
A17
15
I/O2
31
WE
16
VSS
32
VCC
Package Outline "P4" — .590" x 1.67" DIP Package
1.686
1.654
Pin 32
.200
.145
Pin 1
.100
TYP
.020
.016
.055
.045
.048
.019
.125
MIN
.605
.580
.012
.009
.610
.590
All dimensions in inches
Aeroflex Circuit Technology
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SCD1668 REV A 4/28/98
Plainview NY (516) 694-6700
Pin Numbers & Functions
32 Pins — Flat Package
1
A18
17
I/O3
2
A16
18
I/O4
3
A15
19
I/O5
4
A12
20
I/O6
5
A7
21
I/O7
6
A6
22
CS
7
A5
23
A10
8
A4
24
OE
9
A3
25
A11
10
A2
26
A9
11
A1
27
A8
12
A0
28
A13
13
I/O0
29
A14
14
I/O1
30
A17
15
I/O2
31
WE
16
VSS
32
VCC
Package Outline "F6" — 32 Lead, Ceramic Flat Package
0.820
±.010
Pin 17
Pin 32
.410
±.005
Pin 16
Pin 1
0.400
MIN
All dimensions in inches
Aeroflex Circuit Technology
.125 MAX
+.002
.005 -.001
0.017
±.002
.750
(15 spaces at .050)
2 sides
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SCD1668 REV A 4/28/98
Plainview NY (516) 694-6700
Pin Numbers & Functions
32 Pins — Flat Package
1
A18
17
I/O3
2
A16
18
I/O4
3
A15
19
I/O5
4
A12
20
I/O6
5
A7
21
I/O7
6
A6
22
CS
7
A5
23
A10
8
A4
24
OE
9
A3
25
A11
10
A2
26
A9
11
A1
27
A8
12
A0
28
A13
13
I/O0
29
A14
14
I/O1
30
A17
15
I/O2
31
WE
16
VSS
32
VCC
Package Outline "F7" — 32 Lead, Ceramic Flat Package
.132
MAX
.006
TYP
0.820
±.010
Base Plane
.125
MAX
Pin 17
Pin 32
.530
±.005
.410
±.005
.068
TYP
.025
TYP
Pin 1
0.017
±.002
.750
(15 spaces at .050)
2 sides
Pin 16
+.002
.005 -.001
0° / -4°
.030
TYP
Seating Plane
All dimensions in inches
Aeroflex Circuit Technology
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SCD1668 REV A 4/28/98
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CIRCUIT TECHNOLOGY
Ordering Information
Model Number
DESC Drawing Number
Speed
Package
ACT–F512K8N–150F6Q
5962-9669201HUC*
150 ns
Flat Pack
ACT–F512K8N–120F6Q
5962-9669202HUC*
120 ns
Flat Pack
ACT–F512K8N–090F6Q
5962-9669203HUC*
90 ns
Flat Pack
ACT–F512K8N–070F6Q
5962-9669204HUC*
70 ns
Flat Pack
ACT–F512K8N–060F6Q
5962-9669205HUC*
60ns
Flat Pack
ACT–F512K8N–150F7Q
5962-9669201HTC*
150 ns
Flat Pack (Formed)
ACT–F512K8N–120F7Q
5962-9669202HTC*
120 ns
Flat Pack (Formed)
ACT–F512K8N–090F7Q
5962-9669203HTC*
90 ns
Flat Pack (Formed)
ACT–F512K8N–070F7Q
5962-9669204HTC*
70 ns
Flat Pack (Formed)
ACT–F512K8N–060F7Q
5962-9669205HTC*
60ns
Flat Pack (Formed)
ACT–F512K8N–150P4Q
5962-9669201HXC*
150 ns
DIP Pack
ACT–F512K8N–120P4Q
5962-9669202HXC*
120 ns
DIP Pack
ACT–F512K8N–090P4Q
5962-9669203HXC*
90 ns
DIP Pack
ACT–F512K8N–070P4Q
5962-9669204HXC*
70 ns
DIP Pack
ACT–F512K8N–060P4Q
5962-9669205HXC*
60ns
DIP Pack
* Pending
Part Number Breakdown
ACT– F 512K 8 N– 090 F6 Q
Aeroflex Circuit
Technology
Memory Type
Screening
F = FLASH EEPROM
C = Commercial Temp, 0°C to +70°C
I = Industrial Temp, -40°C to +85°C
T = Military Temp, -55°C to +125°C
M = Military Temp, -55°C to +125°C, Screening *
Q = MIL-PRF-38534 Compliant / SMD
Package Type & Size
Memory Depth
Memory Width, Bits
Options
Surface Mount Packages
F6 = .82" x .40" 32 Lead FP Unformed
F7 = .82" x .40" 32 Lead FP Formed
N = None
Memory Speed, ns
Thru-Hole Packages
P4 = 32 Pin DIP
*
Screened to the individual test methods of MIL-STD-883
Specifications subject to change without notice.
Aeroflex Circuit Technology
35 South Service Road
Plainview New York 11830
Aeroflex Circuit Technology
Telephone: (516) 694-6700
FAX:
(516) 694-6715
Toll Free Inquiries: 1-(800) 843-1553
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SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700