Intersil ISL70617SEHVF High voltage process control Datasheet

DATASHEET
36V Radiation Tolerant Precision Instrumentation Amp
with Rail-to-Rail Output Differential ADC Driver
ISL70617SEH
Features
The ISL70617SEH is a high performance, differential input,
differential output instrumentation amplifier designed for
precision analog-to-digital applications. It can operate over a
supply range of 8V (±4V) to 36V (±18V) and features a
differential input voltage range up to ±30V. The output stage
has rail-to-rail output drive capability optimized for differential
ADC driver applications. The output stage is powered by
separate supplies. This feature enables the output to be driven
by the same low voltage supplies powering the ADC, thereby
providing protection from high voltage signals and the low
voltage digital circuits. Its versatility makes it suitable for a
variety of general purpose applications. Additional features not
found in other instrumentation amplifiers enable high levels of
DC precision and excellent AC performance.
• Rail-to-rail differential output ADC driver
The gain of the ISL70617SEH can be programmed from 0.1 to
10,000 via two external resistors, RIN and RFB. The gain
accuracy is determined by the matching of RIN and RFB. The
gain resistors have Kelvin sensing, which removes gain error
due to PC trace resistance. The input and output stages have
individual power supply pins, which enable input signals riding
on a high common-mode voltage to be level shifted to a low
voltage device, such as an A/D converter. The rail-to-rail output
stage can be powered from the same supplies as the ADC,
which preserves the ADC maximum input dynamic range and
eliminates ADC input overdrive.
Applications
• Low input offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30µV
• Input bias current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.2nA
• Excellent CMRR and PSRR . . . . . . . . . . . . . . . . . . . . . . . 120dB
• Wide operating voltage range . . . . . . . . . . . . . . . ±4V to ±18V
• Closed loop -3dB BW 0.3MHz (AV = 1k) to 5.5MHz (AV = 0.1)
• Operating temperature range. . . . . . . . . . . .-55°C to +125°C
• Acceptance tested to 75krad(Si) (LDR) wafer-by-wafer
• Radiation tolerance
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . . . 75krad(Si)
- SEB LETTH (VS = ±18V). . . . . . . . . . . . . . . 60MeV•cm2/mg
• ADC driver
• Precision test and measurement
• High voltage process control
• Signal conditioning for remote powered sensors
• Satellite communication
Related Literature
• For a full list of related documents, visit our website
- ISL70617SEH product page
The ISL70617SEH is offered in a 24 Ld ceramic flatpack
package with an operating temperature range of -55°C to
+125°C.
SIGNAL WITH
HIGH VCM
+18V
RFB
-18V
+18V
HIGH VIN
SIGNAL
IN
RHADC
V REF
GND
V CC
Ch 1
+VFB
+VOUT
ISL70617SEH
VCMO
-RFB VEO
VEE
IN-18V
VCC
GND
GAIN = 0.1
+RFB
RFB
5V
5V
IN+
VCC
+RIN
VCO
-RIN
Ch 16
-VOUT
-VFB
Ch 16
ISL71830SEH
RIN
VCC
Ch 1
ISL71830SEH
RIN
IN+
GAIN = 10
VCC
+RIN VCO
+VFB
-RIN
+VOUT
ISL70617SEH
-VOUT
+RFB
VCMO -VFB
-RFB VEO
VEE
IN-
GND
ISL71090SEH25
ISL71090SEH25
FIGURE 1. COMPLETE SPACE GRADE ANALOG SIGNAL CHAIN
December 16, 2016
FN8697.4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC. 2015, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL70617SEH
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Simplified Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical Post Radiation Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input GM Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Feedback GM Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Amplifier A5, Output Amplifier A6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
18
18
18
Designing with the ISL70617SEH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting the Feedback Gain Resistor (RFB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting the Input Gain Resistor (RIN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Stage Overdrive Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting the Power Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Powering the Input and Feedback Stages (VCC, VEE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Powering the Rail-to-Rail Output Stage (VCO, VEO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rail-to-Rail Differential ADC Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Voltages by Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Performance Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Compensation Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Common-Mode Rejection Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
18
19
19
19
19
19
20
20
20
21
21
Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Estimating Amplifier DC and Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Calculating DC Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Calculating Noise Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Driving an ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input and Feedback Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rail-to-rail Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Offsets and Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Amplifier Usage Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
23
23
23
24
Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Weight of Packaged Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Lid Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Die Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interface Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assembly Related Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
25
25
25
Metalization Mask Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Ceramic Metal Seal Flatpack Packages (Flatpack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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2
FN8697.4
December 16, 2016
ISL70617SEH
Ordering Information
SMD/ORDERING NUMBER
(Note 1)
PART NUMBER
(Note 2)
TEMPERATURE RANGE
(°C)
PACKAGE
(RoHS COMPLIANT)
PKG.
DWG. #
5962L1524602VXC
ISL70617SEHVF
-55 to +125
24 Ld Flatpack
K24.A
N/A
ISL70617SEHF/PROTO
-55 to +125
24 Ld Flatpack
K24.A
5962L1524602V9A
ISL70617SEHVX
-55 to +125
Die
N/A
N/A
ISL70617SEHX/SAMPLE
-55 to +125
Die
N/A
N/A
ISL70617SEHEV1Z
Evaluation Board
NOTES:
1. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed must be
used when ordering.
2. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
TABLE 1. DIFFERENCES BETWEEN FAMILY OF PARTS
SMD/ORDERING
NUMBER
PART NUMBER
DIFFERENTIAL
INPUT
OUTPUT
PINOUTS
GAIN ERROR
LOW VOLTAGE
PIN 12
PIN 13
PIN 14
PIN17
5962L1524601VXC ISL70517SEHVF
Yes
Single-Ended
±0.2
VOUT
NC
VREF
NC
5962L1524602VXC ISL70617SEHVF
Yes
Differential
±0.1
+VOUT
- VOUT
- VFB
VCMO
Simplified Block Diagram
VCC
VCO
9
10
ISL70617SEH
IN+ 24
VCC
+RIN 21
+RINSENSE 20
A1
-RINSENSE 19
VEE
-RIN 18
IN- 23
12 +VOUT
A3
13 -VOUT
+VFB 11
VCC
+RFB 4
17 VCMO
+RFBSENSE 5
A2
-RFBSENSE 6
-RFB 7
VEE
-VFB 14
16
VEE
8
GND
15
VEO
FIGURE 2. SIMPLIFIED BLOCK DIAGRAM
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3
FN8697.4
December 16, 2016
ISL70617SEH
Pin Configuration
ISL70617SEH
(24 LD FLATPACK)
TOP VIEW
NC
DNC
1
2
24
IN+
IN-
DNC
3
23
22
+RFB
4
21
+RFB SENSE
5
20
-RFB SENSE
6
19
+RIN SENSE
-RIN SENSE
DNC
+RIN
-RFB
7
18
-RIN
GND
8
VCMO
VCC
VCO
9
17
16
10
15
11
14
-VFB
12
13
-VOUT
+VFB
+VOUT
VEE
VEO
NOTE: The small square mark is indicative of pin #1.
Pin Descriptions
PIN NAME
PIN NUMBERS
NC
1
DNC
2, 3, 22
+RFB
4
Feedback resistor RFB, positive terminal
+RFB SENSE
5
+RFB positive sense pin connects to the resistor RFB+ terminal to form the RFB+ Kelvin connection.
-RFB SENSE
6
-RFB negative sense pin connects to the resistor RFB- terminal to form the RFB- Kelvin connection.
-RFB
7
Feedback resistor RFB, negative terminal
GND
8
Ground pin is capacitively coupled to the internal ESD circuit and should be connected to power supply
common or signal GND. Also connected to the lid.
VCC
9
Positive supply for input stage and feedback amplifier
VCO
10
Positive supply for output stage
+VFB
11
Positive output feedback
+VOUT
12
Positive output
-VOUT
13
Negative output
-VFB
14
Negative output feedback
VEO
15
Negative supply for output stage
VEE
16
Negative supply for input stage and feedback amplifier
VCMO
17
Output common-mode reference input
-RIN
18
Input resistor RIN, negative terminal
-RIN SENSE
19
-RIN negative sense pin connects to the resistor RIN- terminal to form the RIN- Kelvin connection.
+RIN SENSE
20
+RIN positive sense pin connects to the resistor RIN+ terminal to form the RIN+ Kelvin connection.
+RIN
21
Input resistor RIN, positive terminal
IN-
23
Negative input
IN+
24
Positive input
LID
N/A
Package lid is internally connected to GND (Pin 8).
Submit Document Feedback
4
DESCRIPTION
No internal connection
For internal use. Do not connect
FN8697.4
December 16, 2016
ISL70617SEH
Absolute Maximum Ratings
Thermal Information
Maximum Supply Voltage (VCC to VEE or GND) . . . . . . . . . . . . . . . . . . . . 42V
Maximum Supply Voltage (VCO to VEO or GND) . . . . . . . . . . . . . . . . . . . . 42V
Maximum Voltage (VCO to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.5V, -40V
Maximum Voltage (VEO to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V, +40V
Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Max/Min Input Current for Input Voltage >VCC or <VEE . . . . . . . . . . ±10mA
Maximum Input Current (±RIN, ±RFB, ±RINSENSE, ±RFBSENSE) . . . ±5mA
Maximum Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V
Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . .(VEE - 0.5V) to (VCC +0.5V)
Output Short-Circuit Duration (1 Output at a Time) . . . . . . . . . . Continuous
ESD Rating
Human Body Model (Tested per MIL-STD-883 TM 3015) . . . . . . . . . 6kV
Machine Model (Tested per JESD22-A115-C) . . . . . . . . . . . . . . . . . . 250V
Charged Device Model (Tested per JS-002-2014) . . . . . . . . . . . . . . . 1kV
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
24 Ld CFP (Notes 3, 4) . . . . . . . . . . . . . . . . .
60
7
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature (TJMAX). . . . . . . . . . . . . . . . . . . . . .+150°C
Recommended Operating Conditions
Ambient Temperature Range (TA) . . . . . . . . . . . . . . . . . . .-55°C to +125°C
VCC, VEE Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . ±4V to ±18V
VCO, VEO Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . ±1.5V to ±18V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. JA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. For JC, the “case temp” location is the center of the ceramic on the package underside.
Electrical Specifications VCC = VCO = 18V, VEE = VEO = -18V, VCM = 0V, RL = 10kΩ, RFB = RIN = 30.1kΩ, TA = +25°C, unless otherwise
specified. Boldface limits apply across the operating temperature range, -55°C to +125°C and across a total ionizing dose of 75krad(Si) at +25°C with
exposure at a low dose rate of <10mrad(Si)/s, unless otherwise specified.
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5)
UNIT
VCC - 3V
V
100
µV
300
µV
INPUT DC SPECIFICATIONS
VCMIRIN
VOSIN
IN+, IN- Common-Mode Input Voltage Range
Verified via CMRR
Input Offset Voltage
(Notes 10, 11)
VEE + 3V
-100
±30
-300
TCVOSIN
IBIN
Input Offset Voltage Temperature Coefficient
Input Bias Current
(Note 12)
-4.0
±0.3
4.0
µV/°C
-2.0
±0.2
2.0
nA
25
nA
1.5
nA
18.5
nA
117
µA
-25
IOSIN
Input Offset Current
(Note 12)
-1.5
±0.2
-18.5
IRIN
Input Resistor Drive Current
(Current through RIN resistor)
(Note 9)
87
RINCM
Common-Mode Input Resistance
(Note 9)
CMRR
Common-Mode Rejection Ratio
VCC = VCO = 15V, VEE = VEO = -15V
Reference Figures 38 and 39
VEE +3V ≤ VCM ≤ VCC -3V
G=1
(Note 15)
110
VEE +3V ≤ VCM ≤ VCC -3V
G = 100
(Note 15)
120
102
80
GΩ
120
dB
97
dB
150
dB
120
dB
FEEDBACK DC SPECIFICATIONS
VCMIRFB
VOSFB
TCVOSFB
+FB, -FB Common-Mode Input Voltage Range Verified via CMRR
Feedback Input Offset Voltage
Feedback Input Voltage Temperature
Coefficient
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5
VEE + 3V
V
1600
µV
(Notes 10, 11) +25°C
-1600
(Notes 10, 11) -55°C to +125°C
-3000
3000
µV
(Notes 10, 11) +25°C post 75krad
-6000
6000
µV
15.0
µV/°C
15.0
±400
VCC - 3V
±2.6
FN8697.4
December 16, 2016
ISL70617SEH
Electrical Specifications VCC = VCO = 18V, VEE = VEO = -18V, VCM = 0V, RL = 10kΩ, RFB = RIN = 30.1kΩ, TA = +25°C, unless otherwise
specified. Boldface limits apply across the operating temperature range, -55°C to +125°C and across a total ionizing dose of 75krad(Si) at +25°C with
exposure at a low dose rate of <10mrad(Si)/s, unless otherwise specified. (Continued)
PARAMETER
MIN
(Note 5)
TYP
MAX
(Note 5)
-200
15
200
nA
87
102
117
µA
VCC = +18V, VEE = -18V,
VCO = +4V, VEO = -4V
RIN = RF = 121kΩIOUT = 0mA
(Note 13)
100
160
mV
160
mV
VCC = +18V, VEE = -18V,
VCO = +4V, VEO = -4V
RIN = RF = 121kΩIOUT = 1.5mA
150
200
mV
200
mV
VCC = +18V, VEE = -18V,
VCO = +4V, VEO = -4V
RIN = RF = 121kΩIOUT = 7.5mA
450
550
mV
550
mV
DESCRIPTION
TEST CONDITIONS
IBVFB
Input Bias Current at VFB ± Inputs
(Notes 8, 10, 11)
IRFB
Feedback Resistor Drive Current
(Current through RFB resistor)
(Note 9)
UNIT
OUTPUT DC SPECIFICATIONS
VOL
VOH
Output Voltage Low, VOUT to VEO
Output Voltage High, VOUT to VCO
VCC = +18V, VEE = -18V,
VCO = +4V, VEO = -4V
RIN = RF = 121kΩIOUT = 0mA
(Note 13)
VCC = +18V, VEE = -18V,
VCO = +4V, VEO = -4V
RIN = RF = 121kΩIOUT = -1.5mA
VCC = +18V, VEE = -18V,
VCO = +4V, VEO = -4V
RIN = RF = 121kΩIOUT = -7.5mA
VOLLV
VOHLV
ISC
EG
Output Voltage Low, VOUT to VEO
Output Voltage High, VOUT to VCO
Output Short-Circuit Current
Gain Error
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6
-160
mV
-160
-200
mV
-150
mV
-200
-550
mV
-450
mV
-550
mV
150
VCC = +4V, VEE = -4V,
VCO = +1.5V, VEO = -1.5V
RIN = RF = 121kΩIOUT = 1.5mA
VCC = +4V, VEE = -4V,
VCO = +1.5V, VEO = -1.5V
RIN = RF = 121kΩIOUT = 1.5mA
-100
-200
200
mV
200
mV
-150
mV
-200
mV
Output Sink Current VOUT = GND
(Note 12)
20
45
mA
Output Source Current VOUT = GND
(Note 12)
20
45
mA
VOUT = ±10V, RF = 121kΩ
G = 1 (Notes 6, 7, 13)
-0.020
-0.005
0.020
VOUT = ±10V, RF = 121kΩ
G = 100 (Notes 6, 7, 13)
-0.045
-0.020
0.045
VOUT = ±2.5V, RF = 30.1kΩ
G = 1 (Notes 6, 7, 13)
-0.040
0.006
0.040
%
%
%
FN8697.4
December 16, 2016
ISL70617SEH
Electrical Specifications VCC = VCO = 18V, VEE = VEO = -18V, VCM = 0V, RL = 10kΩ, RFB = RIN = 30.1kΩ, TA = +25°C, unless otherwise
specified. Boldface limits apply across the operating temperature range, -55°C to +125°C and across a total ionizing dose of 75krad(Si) at +25°C with
exposure at a low dose rate of <10mrad(Si)/s, unless otherwise specified. (Continued)
PARAMETER
EG LV
VOSOUT
MIN
(Note 5)
TYP
MAX
(Note 5)
VCC = +4V, VEE = -4V,
VCO = +1.5V, VEO = -1.5V
VOUT = ±0.1V, RF = 121kΩ
G = 1 (Notes 6, 7)
-0.100
±0.003
0.100
VCC = +4V, VEE = -4V,
VCO = +1.5V, VEO = -1.5V
VOUT = ±1.25V, RF = 121kΩ
G = 100 (Notes 6, 7)
-0.100
VCC = +4V, VEE = -4V,
VCO = +1.5V, VEO = -1.5V
VOUT = -0.1V to +0.1V, RF = 30.1kΩ
G = 1 (Notes 6, 7)
-0.1000
DESCRIPTION
Gain Error
Output Offset Voltage
TEST CONDITIONS
UNIT
%
±0.004
0.100
%
±0.0005
0.1000
%
RF = 30.1kΩ, (Notes 10, 11)
-10.0
RF = 121kΩ, (Notes 10, 11)
±0.5
10.0
mV
-40
40
mV
VEE + 3V
VCC - 3V
V
1.3
mV
6.0
mV
±200
600
nA
2.05
2.40
mA
OUTPUT COMMON-MODE SPECIFICATIONS
VCMOCMIR
VOSCM
IBVCMO
Output Common-Mode Control Input Voltage
Range
Verified by VOSCM and IBVCMO
Output Common-Mode Offset Voltage from
VCMO Input
(Note 12)
Input Bias Current at VCMO Input
(Note 12)
-1.3
±0.5
-6.0
-600
POWER SUPPLY SPECIFICATIONS
ICC
Input Stage Supply Current
RL = 10k, IN+ = IN- = 0V
(Note 10)
IEE
Input Stage Supply Current
RL = 10k, IN+ = IN- = 0V
(Note 10)
ICO
IEO
Output Stage Supply Current
Output Stage Supply Current
VCC to VEE
Input Supply Voltage
VCO to VEO
Output Supply Voltage
PSRR VCC to VEE
PSRR VCO to VEO
Input Power Supply Rejection Ratio
Output Power Supply Rejection Ratio
3.0
-2.40
mA
2.25
-2.60
mA
mA
-3.00
RL = 10k, IN+ = IN- = 0V
(Note 10)
RL = 10k, IN+ = IN- = 0V
(Note 10)
-2.05
2.60
mA
3.0
mA
-2.25
mA
-3.0
mA
±4
±18
V
±1.5
±18
V
VCC to VEE = ±4V to ±18V
123
(Note 15)
110
VCO to VEO = ±1.5V to ±18V
(Note 15)
110
130
dB
dB
120
90
dB
dB
AC SPECIFICATIONS
eN(RTO)
Total Noise Voltage Noise Density
Referred to Output
f = 1kHz, (Note 14)
86
nV/√Hz
Input Noise Voltage Density
f = 1kHz, (Note 14)
8.6
nV/√Hz
eN(FB)
Feedback Noise Voltage Density
f = 1kHz, (Note 14)
8.6
nV/√Hz
eN VP-P
Input VP-P Noise Voltage
f = 0.1Hz to 10Hz
5.7
µVP-P
Input Noise Current Density
f = 1kHz, (Note 14)
150
fA/√Hz
eN(I)
iN(I)
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FN8697.4
December 16, 2016
ISL70617SEH
Electrical Specifications VCC = VCO = 18V, VEE = VEO = -18V, VCM = 0V, RL = 10kΩ, RFB = RIN = 30.1kΩ, TA = +25°C, unless otherwise
specified. Boldface limits apply across the operating temperature range, -55°C to +125°C and across a total ionizing dose of 75krad(Si) at +25°C with
exposure at a low dose rate of <10mrad(Si)/s, unless otherwise specified. (Continued)
PARAMETER
iN(IERR)
iNIERR RMS
-3dB BW
-3dB BW
DESCRIPTION
TEST CONDITIONS
Total Internal Noise Current Density
f = 1kHz, (Note 14)
0.1Hz to 10Hz Total Internal RMS Noise
Current
f = 0.1Hz to 10Hz
-3dB Bandwidth vs Closed Loop Gain,
RFB = 30.1k
-3dB Bandwidth vs Closed Loop Gain,
RFB = 121k
SR
Slew Rate
tS
Settling Time to 0.01%
MIN
(Note 5)
TYP
MAX
(Note 5)
UNIT
2.6
pA/√Hz
4
pARMS
RFB = 30.1kΩ; RIN = 301kΩ; G = 0.1
5.5
MHz
RFB = 30.1kΩ; RIN = 30.1kΩ; G = 1
2.6
MHz
RFB = 30.1kΩ; RIN = 3.01kΩ; G = 10
2.2
MHz
RFB = 30.1kΩ; RIN = 301Ω; G = 100
2.0
MHz
RFB = 30.1kΩ; RIN = 30.1Ω; G = 1000
0.3
MHz
RFB = 121kΩ; RIN = 1.21MΩ; G = 0.1
5.0
MHz
RFB = 121kΩ; RIN = 121kΩ; G = 1
1.4
MHz
RFB = 121kΩ; RIN = 12.1kΩ; G = 10
0.5
MHz
RFB = 121kΩ; RIN = 1.21kΩ; G = 100
0.45
MHz
RFB = 121kΩ; RIN = 121Ω; G = 1000
0.4
MHz
4
V/µs
VOUT = ±2.4V, RF = 30.1kΩ
3
µs
VOUT = ±9.6V, RF = 121kΩ
11
µs
NOTES:
5. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.
6. Differential gain (AV) = RFB/RIN.
7. ±VOUT, clipping ~ IRF*RFB.
8. IBVFB = (VOSOUT - (RFB/RIN)*VOSIN - VOSFB)/RFB.
9. Compliance to datasheet limits is assured by design simulation.
10. VCC, VCO = 4V, 5V, 15V, 18V, VEE, VEO = -4V, -5V, -15V, -18V.
11. VCC = 18V, VEE = -18V, VCO = 1.5V, VEO = -1.5V.
12. VCC, VCO = 5V, 18V, VEE, VEO = -5V, -18V.
13. VCC, VCO = 18V, 21V, VEE, VEO = -18V, -21V.
14. Total noise calculated with Equation 17 on page 22.
15. Rejection ratio numbers are reported as absolute values.
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FN8697.4
December 16, 2016
ISL70617SEH
Typical Post Radiation Performance Curves
VCC = VCO = 18V, VEE = VEO = -18V, VCM = 0V, RL = Open,
unless otherwise specified. Error bars (if shown) are based on minimum and maximum data.
30
300
VOSIN 18V, BIASED
VOSIN 18V, GROUNDED
SPEC LIMIT
SPEC LIMIT
±18V SUPPLIES
200
100
0
-100
-200
INPUT BIAS CURRENT (nA)
INPUT OFFSET VOLTAGE (µV)
400
-300
-400
0
25
50
75
±18V SUPPLIES
20
10
0
-10
-20
-30
ANNEAL
0
TOTAL DOSE (krad(Si) AT 0.01rad(Si)/s)
25
30
10
0
-10
-20
0
±15V SUPPLIES
GAIN = 100
CMRR 15V, BIASED
CMRR 15V, GROUNDED
-120
SPEC LIMIT
-140
-160
-180
-200
0
25
50
75
ANNEAL
TOTAL DOSE (krad(Si) AT 0.01rad(Si)/s)
FIGURE 7. CMRR (RTI), GAIN = 100 vs TOTAL DOSE
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9
10
5
0
-5
-10
-15
-20
0
ANNEAL
25
50
75
TOTAL DOSE (krad(Si) AT 0.01rad(Si)/s)
FIGURE 6. INPUT OFFSET CURRENT vs TOTAL DOSE
COMMON-MODE REJECTION RATIO (dB)
FIGURE 5. INPUT BIAS CURRENT IBIN- vs TOTAL DOSE
±18V SUPPLIES
15
-25
25
50
75
ANNEAL
TOTAL DOSE (krad(Si) AT 0.01rad(Si)/s)
-100
IOSIN 18V , BIASED
IOSIN 18V, GROUNDED
SPEC LIMIT
SPEC LIMIT
20
INPUT OFFSET CURRENT (nA)
INPUT BIAS CURRENT (nA)
IBIN- 18V, BIASED
IBIN- 18V , GROUNDED
SPEC LIMIT
SPEC LIMIT
±18V SUPPLIES
20
COMMON-MODE REJECTION RATIO (dB)
25
50
75
ANNEAL
TOTAL DOSE (krad(Si) AT 0.01rad(Si)/s)
FIGURE 4. INPUT BIAS CURRENT IBIN+ vs TOTAL DOSE
FIGURE 3. INPUT OFFSET VOLTAGE vs TOTAL DOSE
-30
IBIN+ 18V, BIASED
IBIN+ 18V, GROUNDED
SPEC LIMIT
SPEC LIMIT
-80
±15V SUPPLIES
GAIN = 1
CMRR 15V, BIASED
CMRR 15V, GROUNDED
-100
SPEC LIMIT
-120
-140
-160
-180
0
25
50
75
ANNEAL
TOTAL DOSE (krad(Si) AT 0.01rad(Si)/s)
FIGURE 8. CMRR (RTI), GAIN = 1 vs TOTAL DOSE
FN8697.4
December 16, 2016
ISL70617SEH
Typical Post Radiation Performance Curves
250
4000
3000
±18V SUPPLIES
2000
1000
0
-1000
VOSFB 18V, BIASED
VosFB 18V, GROUNDED
SPEC LIMIT
SPEC LIMIT
-2000
-3000
-4000
0
FEEDBACK INPUT BIAS CURRENT (nA)
FEEDBACK INPUT OFFSET VOLTAGE (µV)
VCC = VCO = 18V, VEE = VEO = -18V, VCM = 0V, RL = Open,
unless otherwise specified. Error bars (if shown) are based on minimum and maximum data. (Continued)
200
100
50
0
-50
-100
IBFB 18V, BIASED
IBFB 18V, GROUNDED
SPEC LIMIT
SPEC LIMIT
-150
-200
-250
ANNEAL
25
50
75
TOTAL DOSE (krad(Si) AT 0.01rad(Si)/s)
±18V SUPPLIES
150
0
FIGURE 9. VOSFB vs TOTAL DOSE
0.03
0.06
±18V SUPPLIES
Eg120k, 18V , BIASED
Eg120k, 18V , GROUNDED
SPEC LIMIT
SPEC LIMIT
0.01
0
-0.01
0.04
GAIN ERROR (%)
GAIN ERROR (%)
FIGURE 10. IBFB vs TOTAL DOSE
±18V SUPPLIES
0.02
Eg100, 18V , BIASED
Eg100, 18V , GROUNDED
SPEC LIMIT
SPEC LIMIT
0.02
0
-0.02
-0.04
-0.02
-0.03
0
25
50
75
-0.06
ANNEAL
0
25
50
75
ANNEAL
TOTAL DOSE (krad(Si) AT 0.01rad(Si)/s)
TOTAL DOSE (krad(Si) AT 0.01rad(Si)/s)
FIGURE 11. GAIN ERROR (GAIN = 1) vs TOTAL DOSE
FIGURE 12. GAIN ERROR (GAIN = 100) vs TOTAL DOSE
0.06
15
± 18V SUPPLIES
RFB = 30.1k
0.04
0.02
0
-0.02
Eg30k , 18V, BIASED
Eg30k , 18V, GROUNDED
SPEC LIMIT
SPEC LIMIT
-0.04
-0.06
0
25
50
75
ANNEAL
TOTAL DOSE (krad(Si) AT 0.01rad(Si)/s)
FIGURE 13. GAIN ERROR (GAIN = 1) vs TOTAL DOSE
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10
OUTPUT OFFSET VOLTAGE (mV)
±18V SUPPLIES
GAIN ERROR (%)
25
50
75
ANNEAL
TOTAL DOSE (krad(Si) AT 0.01rad(Si)/s)
10
5
0
-5
VOSOUT 30k, BIASED
VOSOUT 30k, GROUNDED
SPEC LIMIT
SPEC LIMIT
-10
-15
0
25
50
75
ANNEAL
TOTAL DOSE (krad(Si) AT 0.01rad(Si)/s)
FIGURE 14. VOSOUT (GAIN = 1) vs TOTAL DOSE
FN8697.4
December 16, 2016
ISL70617SEH
Typical Post Radiation Performance Curves
VCC = VCO = 18V, VEE = VEO = -18V, VCM = 0V, RL = Open,
unless otherwise specified. Error bars (if shown) are based on minimum and maximum data. (Continued)
-100
PSRRI, BIASED
40
PSRRI, GROUNDED
±18V SUPPLIES
RFB = 120k
30
INPUT STAGE PSRR (dB)
OUTPUT OFFSET VOLTAGE (mV)
50
20
10
0
-10
-20
VOSOUT 120k, BIASED
VOSOUT 120k, GROUNDED
SPEC LIMIT
SPEC LIMIT
-30
-40
-50
0
25
50
75
SPEC LIMIT
-120
-140
-160
ANNEAL
0
25
50
75
ANNEAL
TOTAL DOSE (krad(Si) AT 0.01rad(Si)/s)
TOTAL DOSE (krad(Si) AT 0.01rad(Si)/s)
FIGURE 15. VOSOUT (Gain = 1) vs TOTAL DOSE
FIGURE 16. INPUT STAGE PSRR vs TOTAL DOSE
OUTPUT STAGE PSRR (dB)
-80
-100
-120
-140
PSRRO, BIASED
-160
PSRRO, GROUNDED
SPEC LIMIT
-180
0
25
50
75
ANNEAL
TOTAL DOSE (krad(Si) AT 0.01rad(Si)/s)
FIGURE 17. OUTPUT STAGE PSRR vs TOTAL DOSE
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FN8697.4
December 16, 2016
ISL70617SEH
Typical Performance Curves
VCC = VCO = 18V, VEE = VEO = -18V, VCM = 0V, RL = Open, unless
otherwise specified.
15
400
10
300
200
VOS IN (µV)
VOS IN (µV)
5
0
-5
100
0
-10
-100
-15
-20
0
±2.5
±5.0
±7.5
-200
-18
±10.0 ±12.5 ±15.0 ±17.5 ±20.0
-14
-10
-6
SUPPLY VOLTAGE (VCC - VEE)
0
0.2
-0.05
0
-0.10
6
10
14
18
-IB
-0.2
-0.15
IBIN (nA)
IBIN (nA)
2
FIGURE 19. VOSIN vs INPUT COMMON MODE VOLTAGE
FIGURE 18. VOSIN vs SUPPLY VOLTAGE
-IB
-0.20
-0.25
-0.4
+IB
-0.6
+IB
-0.8
-0.30
-0.35
±2.5
±5.0
-1.0
-15
±7.5 ±10.0 ±12.5 ±15.0 ±17.5 ±20.0 ±22.5
-10
SUPPLY VOLTAGE (VCC - VEE)
-5
0
5
10
15
VCM (V)
FIGURE 20. IBIN vs SUPPLY VOLTAGE
FIGURE 21. IBIN vs INPUT COMMON-MODE VOLTAGE (±15V)
0.2
82
81
-IB
0
80
79
IBVCMO (nA)
-0.2
IBIAS (nA)
-2
VCM (V)
-0.4
+IB
-0.6
78
77
76
75
74
-0.8
73
-1.0
-20
-15
-10
-5
0
5
10
15
VCM (V)
FIGURE 22. IB vs INPUT COMMON-MODE VOLTAGE (±18V)
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12
20
72
±2.0
±4.5
±7.0
±9.5 ±12.0 ±14.5 ±17.0 ±19.5 ±22.0
SUPPLY VOLTAGE
FIGURE 23. IBVCMO vs SUPPLY VOLTAGE (VCC - VEE)
FN8697.4
December 16, 2016
ISL70617SEH
Typical Performance Curves
VCC = VCO = 18V, VEE = VEO = -18V, VCM = 0V, RL = Open, unless
otherwise specified. (Continued)
1000
1.5
800
1.0
VOHLV AND VOLLV (V)
600
IBVCMO (nA)
400
200
0
-200
-400
-600
-800
-1000
-18
0.5
-VOUT
-0.5
-1.0
-1.5
-14
-10
-6
-2
2
6
10
14
18
-3
-2
-1
VCM (V)
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
2.05
2.00
1.95
2.45
2.25
2.05
1.85
1.65
1.45
1.90
±4
1.25
±6
±8
±10
±12
±14
±16
±18
±20
4
±22
9
80
60
40
GAIN (dB)
GAIN (dB)
RIN = 301
RFB = 30.1k
AV = 100
AV = 1
80
RIN = 30.1, RFB = 30.1k
RIN = 3.01k, RFB = 30.1k
AV = 10
RIN = 30.1k, RFB = 30.1k
20
0
AV = 0.1
100
-20
1k
10k
100k
1M
10M
100M
FIGURE 28. CLOSED LOOP GAIN (RFB = 30.1k) vs FREQUENCY
13
29
34
39
44
RIN = 1.21k
RFB = 121k
AV = 100
AV = 10
AV = 1
RIN = 12.1k, RFB = 121k
RIN = 121k, RFB = 121k
AV = 0.1
RIN = 1.21M, RFB = 121k
FREQUENCY (Hz)
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RIN = 121, RFB = 121k
AV = 1000
RIN = 301k, RFB = 30.1k
-40
10
19
FIGURE 27. ICO vs SUPPLY VOLTAGE (VCO - VEO)
FIGURE 26. ICC vs SUPPLY VOLTAGE (VCC - VEE)
AV = 1000
14
SUPPLY VOLTAGE (VCO - VEO)
SUPPLY VOLTAGE
-20
3
2.65
2.10
0
2
2.85
2.15
20
1
FIGURE 25. VOH AND VOL
2.20
40
0
INPUT VOLTAGE (V)
FIGURE 24. IBVCMO vs INPUT COMMON-MODE VOLTAGE
60
+VOUT
0
-40
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 29. CLOSED LOOP GAIN (RFB = 121k) vs FREQUENCY
FN8697.4
December 16, 2016
ISL70617SEH
Typical Performance Curves
VCC = VCO = 18V, VEE = VEO = -18V, VCM = 0V, RL = Open, unless
otherwise specified. (Continued)
140
AV = 100
AV = 1000
120
NEGATIVE PSRR (dB)
POSITIVE PSRR (dB)
140
100
80
60
AV = 0.1
40
AV = 1
20
100
1k
10k
100k
AV = 100
100
80
60
AV = 1
AV = 0.1
40
AV = 10
20
AV = 10
0
10
AV = 1000
120
0
10
1M
100
FREQUENCY (Hz)
FIGURE 30. POSITIVE PSRR VCC SUPPLY RTI (RF = 30.1k)
AV = 1000
POSITIVE PSRR (dB)
120
80
40
AV = 1
AV = 0.1
140
AV = 100
100
60
AV = 10
20
100k
AV = 1000
AV = 100
120
100
80
60
40
AV = 1
AV = 0.1
AV = 10
100
1k
10k
100k
0
10
1M
100
FREQUENCY (Hz)
1k
10k
100k
FIGURE 33. NEGATIVE PSRR VEO SUPPLY RTI (RF = 30.1k)
140
140
AV = 1000
120
NEGATIVE PSRR (dB)
AV = 100
100
80
60
AV = 0.1
AV = 1
20
0
10
1k
10k
100k
FREQUENCY (Hz)
FIGURE 34. POSITIVE PSRR VCC SUPPLY RTI (RF = 121k)
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AV = 1000
AV = 100
120
100
80
60
AV = 0.1
40
AV = 1
AV = 10
20
AV = 10
100
1M
FREQUENCY (Hz)
FIGURE 32. POSITIVE PSRR VC0 SUPPLY RTI (RF = 30.1k)
40
1M
20
0
10
POSITIVE PSRR (dB)
10k
FIGURE 31. NEGATIVE PSRR VEE SUPPLY RTI (RF = 30.1k)
NEGATIVE PSRR (dB)
140
1k
FREQUENCY (Hz)
1M
0
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 35. NEGATIVE PSRR VEE SUPPLY RTI (RF = 121k)
FN8697.4
December 16, 2016
ISL70617SEH
Typical Performance Curves
VCC = VCO = 18V, VEE = VEO = -18V, VCM = 0V, RL = Open, unless
otherwise specified. (Continued)
140
AV = 1000
100
80
AV = 1
60
40
AV = 0.1
100
80
60
0
10
100
1k
10k
AV = 0.1
AV = 1
20
100k
0
10
1M
100
1k
1M
140
AV = 1000
120
CMRR RFB = 121k (dB)
CMMR RFB = 30.1k (dB)
140
AV = 100
100
80
AV = 0.1
AV = 1
40
AV = 10
20
0
10
100
1k
10k
AV = 1000
120
AV = 100
100
80
60
40
AV = 1
AV = 0.1
20
100k
0
10
1M
AV = 10
100
FREQUENCY (Hz)
eN
100
1k
10k
0.01
100k
FREQUENCY (Hz)
FIGURE 40. INPUT VOLTAGE AND CURRENT NOISE
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INPUT NOISE VOLTAGE (V/√Hz)
0.1
100nV
INPUT NOISE CURRENT (pA/√Hz)
1
iN
10
100k
1M
10µV
10
1
10k
FIGURE 39. CMRR (RTI) RF = 121k
10µV
1µV
1k
FREQUENCY (Hz)
FIGURE 38. CMRR (RTI) RF = 30.1k
INPUT NOISE VOLTAGE (V/√Hz)
100k
FIGURE 37. NEGATIVE PSRR VE0 SUPPLY RTI (RF = 121k)
FIGURE 36. POSITIVE PSRR VCO SUPPLY RTI (RF = 121k)
10nV
0.1
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
60
AV = 10
40
AV = 10
20
AV = 100
120
NEGATIVE PSRR (dB)
POSITIVE PSRR (dB)
120
AV = 1000
140
AV = 100
AV = 1
RF = 121k
AV = 1
RF = 30k
1µV
100nV
10nV
1nV
0.1
AV = 100
RF = 30k
1
10
AV = 100
RF = 121k
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 41. INPUT NOISE VOLTAGE vs GAIN AND RF
FN8697.4
December 16, 2016
ISL70617SEH
Typical Performance Curves
VCC = VCO = 18V, VEE = VEO = -18V, VCM = 0V, RL = Open, unless
otherwise specified. (Continued)
0.15
4
3
OUTPUT VOLTAGE vs
INPUT VOLTAGE (V)
INPUT NOISE VOLTAGE (µVP-P)
5
2
1
0
-1
-2
-3
0.10
OUTPUT
0.05
0
INPUT
-0.05
-0.10
-4
-5
0
1
2
3
4
5
6
7
8
9
-0.15
10
0
50
100 150 200 250 300 350 400 450 500
TIME (µs)
TIME (s)
FIGURE 42. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz
FIGURE 43. SMALL SIGNAL RESPONSE (AV = 1, RF = 30.1k)
2.5
2.0
0.10
OUTPUT
0.05
0
INPUT
-0.05
-0.10
OUTPUT VOLTAGE vs
INPUT VOLTAGE (V)
OUTPUT VOLTAGE vs
INPUT VOLTAGE (V)
0.15
1.5
OUTPUT
1.0
0.5
0
-0.5
INPUT
-1.0
-1.5
-2.0
-0.15
0
50
-2.5
100 150 200 250 300 350 400 450 500
0
50
100 150 200
TIME (µs)
FIGURE 44. SMALL SIGNAL RESPONSE (AV = 1, RF = 121k)
30
CL= 4700pF
20
10
10
OUTPUT
5
0
INPUT
-5
GAIN (dB)
OUTPUT VOLTAGE vs
INPUT VOLTAGE (V)
400 450 500
FIGURE 45. LARGE SIGNAL RESPONSE (AV = 1, RF = 30.1k)
15
0
-10
-30
0
50
100 150 200 250 300 350 400 450 500
TIME (µs)
FIGURE 46. LARGE SIGNAL RESPONSE (AV = 1, RF = 121k)
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CL= 2700pF
CL= 1000pF
AV = 1
CL= 470pF
RIN = RFB = 30.1k
CL= 47pF
RL= 10k, VCC = VEE = ±18V
-20
-10
-15
250 300 350
TIME (µs)
CL= 4.7pF
VCO = VEO = ±4V
-40
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 47. CLOSED LOOP GAIN vs FREQUENCY vs CL
FN8697.4
December 16, 2016
ISL70617SEH
Applications Information
The ISL70617SEH instrumentation amplifier was developed to
accomplish the following:
“General Description” contains the ISL70617SEH functional and
performance objectives and description of operation.
• Provide a fully differential, rail-to-rail output for optimally
driving ADCs. Maximum differential voltage set by RFB
(Equation 8 on page 18).
“Designing with the ISL70617SEH” on page 18 contains the
application circuit design equations and guidelines for achieving
the desired DC and AC performance levels.
• Limit the output swing to prevent output overdrive
• Allow any gain, including attenuation
“Estimating Amplifier DC and Noise Performance” on page 22
provides equations for predicting DC offset voltage and noise of
the finished design.
• Maximize gain accuracy by removing on-chip component
tolerances and external PC board parasitic resistance
General Description
• Enable user control of amplifier precision level with choice of
external resistor tolerance
The ISL70617SEH is an elaboration of the simpler
current-feedback approach. The GMs are implemented with two
external resistors and very high-gain amplifiers that impose input
and feedback voltages upon them. The amplifiers have gains
around ten million and linearize the transistors errors well below
the 10ppm level. The overall gain is (RFB/RIN). With very high
gain in the pseudo-GMs, the circuit adds little gain error and only
RFB and RIN set gain to the 10ppm level. Thus, only the matching
of the external resistors sets gain error and the cost of the
resistors can be tailored to the accuracy needed. Note that the
input stage is completely unaffected by output biasing, which is
the right thing for an instrumentation amplifier.
• Maintain CMRR >100dB and remove CMRR sensitivity to gain
resistor tolerance
• Provide a level-shift interface from bipolar analog input signal
sources to unipolar and bipolar ADC output terminations
Functional Description
Figure 48 shows the functional block diagram for the
ISL70617SEH.
INPUT
FEEDBACK
OUTPUT
STAGE
STAGE
STAGE
VCO
0.1µF
VCC
A5
0.1µF
I2
I1
IN-
500Ω
IN+
500Ω
I3
+VOUT
I1, I3
I2, I4
I4
+
A6
-
-VOUT
VFB-
+
A1
-
Q1
Q2
+
A2
-
+
A3
-
IS1
A4
VFB+
+
-
VCMO
100µA
100µA
VEE
Q4
Q3
IS3 IS4
IS2
VEO
0.1µF
0.1µF
+RIN
RIN
-RIN
-RINSENSE
+RINSENSE
-RFB
-RFBSENSE
RFB
+RFB
GND
+RFBSENSE
GAIN RESISTORS AND
KELVIN CONNECTIONS
FIGURE 48. ISL70617SEH FUNCTIONAL BLOCK DIAGRAM
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FN8697.4
December 16, 2016
ISL70617SEH
Input GM Amplifier
Therefore, at equilibrium:
The input stage consists of high performance, wideband
amplifiers (A1, A2), GM drive transistors (Q1, Q2) and input gain
resistor (RIN). Current drive for Q1 and Q2 emitters are provided
by a matched pair of 100µA current sinks. A unity gain buffer
from each input (IN+, IN-) to the terminals of the input resistor,
RIN, is formed by the connection of the Kelvin resistor sense pins
and drive pins to the terminals of the input resistor, as shown in
Figure 48. In this configuration, the voltage across the input
resistor RIN is equal to the input differential voltage across IN+
and IN-.
I1 = I3 and I2 = I4
The input GM stage operates by creating a current difference in
the collector currents Q1 and Q2 in response to the voltage
difference between the IN+ and IN- pins. When the input voltage
applied to the IN+ and IN- pins is zero, the voltage across the
terminals to the gain resistor RIN, is also zero. Since there is no
current flow through the gain resistor, the transistors Q1 and Q2
collector currents (I1, I2) are equal.
A change in the input differential voltage causes an equivalent
voltage drop across the input gain resistor RIN, and the resulting
current flow through RIN causes an imbalance in Q1, Q2 collector
currents I1, I2, given by Equations 1 and 2:
I1 = 100µA + (VIN+- VIN-)/RIN
(EQ. 1)
I2 = 100µA - (VIN+- VIN-)/RIN
(EQ. 2)
Feedback GM Amplifier
The feedback amplifiers A3, A4 form a differential
transconductance amplifier identical to the input stage. The
input terminals (VFB+, VFB-) connect to the ISL70617SEH
differential output terminals (+VOUT, -VOUT) so that the output
voltage also appears across the feedback gain resistor RFB.
Operation is the same as the input GM stage and the differential
currents I3, I4 are given by Equations 3 and 4:
I3 = 100µA - {(+VOUT) - (-VOUT)}/RFB
(EQ. 3)
I4 =100µA +{(+VOUT) - (-VOUT)}/RFB
(EQ. 4)
Error Amplifier A5, Output Amplifier A6
Amplifiers A5 and A6 act together to form a high-gain,
differential I/O transimpedance amplifier. (Refer to Figure 48)
Differential current amplifier A5 sums the differential currents
(I1+I3, I2+I4) from the input and feedback GM amplifiers. From
that summation, a differential error voltage is sent to A6, which
generates the rail-to-rail differential output drive to the +VOUT and
-VOUT pins.
The external connection of the output pins to the feedback
amplifier closes a servo loop where a change in the differential
input voltage is converted into differential current imbalances at
I1, I2 (Equations 1 and 2) at the summing node inputs to A5.
Current I1 sums with current I3 from the feedback stage, and I2
sums with I4. A5 senses the difference between current pairs I1,
I3 and I2, I4. A different voltage is generated, amplified and fed
back to the feedback amplifier, which creates correction currents
at I3, I4 to match the currents at I1, I2 (Equations 3 and 4).
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(EQ. 5)
Combining Equations 1 and 3, (and their complements I2 and I4),
and solving for VOUT as a function of VIN, RIN and RFB, yields
Equation 6:
VOUT = VIN*RFB/RIN
(EQ. 6)
where VOUT = (+VOUT) - (-VOUT) and VIN = IN+ - INEquation 6 can be rearranged to form the gain Equation 7:
Gain = VOUT/VIN = RFB/RIN
(EQ. 7)
This is a general form of the gain equation for the ISL70617SEH.
Designing with the ISL70617SEH
To complete a working design, the following procedure is
recommended and explained in this section:
1. Define the output differential voltage swing
2. Set the feedback resistor value, RFB (Equation 8)
3. Set the input gain resistor value, RIN
4. Set the VCO and VEO power supply voltages
5. Set the VCC and VEE supply voltages
The gain of the instrumentation amplifier is set by the resistor
ratio RFB/RIN (Equation 7), and the maximum output swing is set
by the absolute value of the feedback resistor RFB (Equation 8).
VCO and VEO supply power to the rail-to-rail output stage and
define the maximum output voltage swing at the ±VOUT
differential output pins. Power supply pins VCC and VEE power the
feedback amplifiers, which require an additional ±3V beyond the
VCO and VEO voltages to maintain linear operation of the
feedback GM stage.
Setting the Feedback Gain Resistor (RFB)
Resistor RFB defines the maximum differential voltage at output
terminals +VOUT to -VOUT (Refer to Figures 48 and 49). External
resistor RFB and the differential 100µA current sources define
the maximum dynamic range of the feedback stage, which
defines the maximum differential output swing of the output
stage. Overload circuitry allows >100µA to flow through RFB to
maintain feedback, but linearity is degraded. Therefore, it is a
good practice to keep the maximum linear dynamic range to
within ±80% of the maximum I*R across the resistor.
VOUTDIFF= ±80µA * RFB
(EQ. 8)
In cases where large pulse overshoot is expected, the maximum
current in Equation 8 could be reduced to 50% for additional
margin (see “AC Performance Considerations” on page 20). The
penalty for increasing the feedback resistor value is higher DC
offset voltage and noise.
FN8697.4
December 16, 2016
ISL70617SEH
Output voltages that exceed the maximum dynamic range of the
feedback amplifier can degrade phase margin and cause
instability. The plot in Figure 49 shows the maximum differential
output voltage swing vs resistor value for RFB and RIN using the
80% and 50% current source levels.
IN-
VCC
DYNAMIC VOLTAGE RANGE (±V)
35
IN+
30
25
500Ω
500Ω
+
A1
-
Q1
RIN
+
A2
-
Q2
ESD
PROTECTION
ESD
PROTECTION
20
VOUT (V) AT 80%
15
100µA
100µA
10
VOUT (V) AT 50%
5
0
0
50
100
150
200
250
300
VEE
350
400
RFB, RIN VALUE (kΩ)
Setting the Power Supply Voltages
FIGURE 49. RFB, RIN vs DYNAMIC RANGE
Setting the Input Gain Resistor (RIN)
The input gain resistor (RIN) is scaled to the feedback resistor
according to the gain in Equation 9:
RIN = RFB/Gain
FIGURE 50. INPUT STAGE ESD PROTECTION DIODES
(EQ. 9)
The input GM stage uses the same differential current source
arrangement as the feedback stage. Therefore, the amount of
overdrive margin (50%, 80%) included in the calculation for RFB
is also included in the calculation for RIN (Refer to Figures 48 and
49).
Input Stage Overdrive Considerations
There are a few cases where the input stage can be overdriven,
which must be considered in the application. An input signal that
exceeds the maximum dynamic range of the gain resistor RIN,
calculated previously, can cause the ESD diodes to conduct.
When this occurs, a low impedance path from the inputs to the
input gain resistor RIN will result in signal distortion (Refer to
Figure 50).
High-speed input signals that remain within the maximum
dynamic range of the input stage can cause distortion if the input
slew rate exceeds the input stage slew rate (~4V/µs). When the
input slews at a faster rate than the GM stage can follow, the
voltage difference appears across the input ESD diodes from
each input and resistor RIN. When the voltage difference is large
enough to cause the diodes to conduct, the input terminals are
shunted to RIN through the 500Ω input protection resistors,
causing distortion during the rise and fall times of the transient
pulse. The distortion will last until the resistor voltage catches up
to the input voltage.
The ISL70617SEH power supplies are partitioned so that the
input stage and feedback stages are powered from a separate
pair of supply pins (VCC, VEE) than the differential output stage
(VCO, VEO). This partitioning provides the user with the ability to
adapt the ISL70617SEH to a wide variety of input signal power
sources that would not be possible if the supplies were strapped
together internally (VCC = VCO and VEE = VEO). However, powering
the input and output supplies from unequal supplies has
restrictions that are described in the next section.
Powering the Input and Feedback Stages
(VCC, VEE)
The input pins IN+, IN- cannot swing rail-to-rail, but have a
maximum input voltage range given by Equation 10:
VEE+ 3V < (VCMIRIN + VIN) < VCC - 3V;
(EQ. 10)
where VIN = maximum differential voltage IN+ to INThis requires the sum of the common-mode input voltage and
the differential input voltage to remain within 3V of either the VCC
or VEE rail, otherwise distortion will result.
The feedback pins VFB+ and VFB- have the same input
common-mode voltage constraint as the input pins IN+, IN-. The
maximum input voltage range of the feedback pins is given by
Equation 11:
VEE+ 3V < VCMIRFB < VCC - 3V
(EQ. 11)
where VCMIRFB = (+VOUT - -VOUT) +VCMO
To maintain stability, it is critical to respect the ±3V requirement
in Equation 11.
Powering the Rail-to-Rail Output Stage
(VCO, VEO)
The output stage (A6) is a rail-to-rail design, and is powered by
the VCO and VEO pins. The differential output pins +VOUT, -VOUT
connect to the +VFB, -VFB pins to close the output feedback loop.
The feedback stage is powered from the VCC and VEE pins. The
+VFB, -VFB have a common-mode input range 3V below the VCC
rail and 3V above the VEE rail. If the output voltage exceeds the
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FN8697.4
December 16, 2016
ISL70617SEH
feedback common-mode input voltage, loop instability will result.
Therefore, the voltages at the ±VOUT pins should always be 3V
away from either rail, as shown in Equation 12.
VEE+ 3V < VOUT < VCC - 3V;
(EQ. 12)
differential rail-to-rail signal needed by the ADC. The following
powering option is recommended:
• VCC = +10V, VEE = -10V
• VCO = +5V, VEO = GND
where VOUT = |+VOUT| or |-VOUT|
• VCMO = +2.5V
Rail-to-Rail Differential ADC Driver
• VCC, VEE power supply common connects to GND
The differential output stage of the ISL70617SEH is designed to
drive the differential input stage of an ADC. In this configuration,
the VCO, VEO power supply pins connect directly to the ADC power
supply pins. This output swing arrangement is ideal for driving
the rail-to-rail ADC drive without the possibility of overdriving the
ADC input.
EXAMPLE 2: HIGH VOLTAGE BIPOLAR I/O BUFFER
The output stage is capable of rail-to-rail operation when VCO, VEO
are powered from a single supply or from split supplies. It has a
single supply voltage range (VCO) from 3V to 15V (with VEO at
GND), and a ±1.5V to ±15V split supply voltage range. Under all
power supply conditions, VCC must be greater than VCO by 3V, and
VEE must be less than VEO by 3V to maintain the rail-to-rail output
drive capability.
The VCMO pin is an input to a very low bias current terminal and
sets the output common-mode reference voltage when driving a
differential input ADC, such that the output would have a ± input
signal span centered around an external DC reference voltage
applied to the VCMO pin.
Power Supply Voltages by Application
The ISL70617SEH can be adapted to a wide variety of
instrumentation amplifier applications where the signal source is
powered from supply voltages that are different from the supply
voltages powering downstream circuits. The following examples
are included as a guide to the proper connection and voltages
applied to the supply pins VCC, VEE, VCO, and VEO.
There are a common set of requirements across all power
applications:
1. A common ground connection from the input supplies, (VCC,
VEE) to the output supplies (VCO, VEO) is required for all
powering options.
2. The signal input pins (IN+, IN-) cannot float and must have a
DC return path to ground.
3. The input and output supplies cannot both be operated in
single supply mode due to the 3V feedback amplifier
common-mode headroom requirement in Equation 11.
The following are typical power examples:
EXAMPLE 1: BIPOLAR INPUT TO SINGLE SUPPLY
OUTPUT
The ISL70617SEH is configured as a 5V ADC driver in a high-gain
sensor bridge amplifier powered from a ±10V excitation source.
In this application, the ISL70617SEH must extract the low-level
bipolar sensor signal and shift the level to the 0V to +5V
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The ISL70617SEH is configured as a high impedance buffer
instrumentation amplifier in a ±15V industrial sensor
application. In this application, the ISL70617SEH must extract
and amplify the high impedance sensor signal and send it
downstream to a differential ADC operating from ±15V supplies.
The following powering options are recommended:
1. Input and output supplies are strapped to the same supplies
and rail-to-rail input to the ADC is not required.
VCC = VCO = +15V
VEE = VEO = -15V
VCMO = GND
VCC, VEE power supply common connects to GND
and VOUT = ±12V
2. ±15V rail-to-rail output is required, then:
-
-
VCC = +18V, VEE = -18V
VCO = +15V, VEO = -15V
VCMO = GND
VCC, VEE power supply common connects to GND
The VCO and VEO power supply pins connect to the ADC ±15V
power supply pins. Rail-to-rail output swing requires that
VCC = VCO +3V and VEE = VEO -3V, or ±18V.
EXAMPLE 3: GAINS LESS THAN 1
The ISL70617SEH is configured to a gain of 0.2V/V driving a
rail-to-rail 3V ADC. In this application, the maximum input
dynamic range is ±15V.
• VCC = +18V, VEE = -18V
• VCO = +3V, VEO = GND
• VCMO = +1.5V
• VCC, VEE power supply common connects to GND
In this attenuator configuration, the input signal range is ±15V,
which requires an additional ±3V of input overhead from the
input supplies. Thus, VCC and VEE = ±18V.
AC Performance Considerations
The ISL70617SEH closed loop frequency response is formed by
the feedback GM amplifier and gain resistor RFB and has the
characteristics of a current feedback amplifier. Therefore, the
-3dB gain does not significantly decrease at high gains as is the
case with the constant gain-bandwidth response of the classic
voltage feedback amplifier.
FN8697.4
December 16, 2016
ISL70617SEH
There are four behaviors of current feedback amplifiers that
must be considered:
1. Frequency response increases with decreasing values of RFB.
A comparison of the G = 100, -3db response (Figures 28 and
29) RFB at 30.1kΩ vs 121kΩ shows almost a 4X decrease
from 2MHz to 0.5MHz.
2. Gain peaking tends to increase with decreasing values of RFB
3. Wideband applications at gains less than 1 (Figures 28 and
29) can have high gain peaking resulting in high levels of
overshoot with pulsed input signals
4. Parasitic capacitance at the feedback resistor terminals
(+RFB, -RFB) and the Kelvin sense terminals (+RFBSENSE,
-RFBSENSE) will result in increasing levels of peaking and
transient response overshoot.
To minimize peaking, external PC parasitic capacitance should
be minimized as much as possible. The ISL70617SEH is
designed to be stable with PC board parasitic capacitance up to
20pF and feedback resistor values down to 30.1kΩ. At gains less
than 1, the maximum parasitic capacitance may have to be
limited further to avoid additional compensation.
Uncorrected gain peaking and high overshoot in the feedback
stage can cause loss of feedback loop stability if the transient
causes the feedback voltage to exceed the common-mode input
range of the feedback amplifier or the maximum linear range of
the feedback resistor RFB. Corrective actions include increasing
the size of the feedback resistor (see Figure 49 on page 19) and
rescaling the input gain resistor RIN, or adding input frequency
compensation described in the next section.
The penalty of increasing the RFB (and RIN rescaling) is increased
noise, so this is generally not the corrective action of choice.
AC Compensation Techniques
Input compensation with a low pass filter (Figure 51) can be an
effective way to block high frequency signals from the
differential amplifier inputs. It does not change the gain peaking
behavior of the feedback loop, but it does block signals from
creating overdrive instability. This method is useful after other
corrective measures have been implemented, and when there is
little control over the input signal frequency content.
IN-
R/2
DIFFERENTIAL
INPUT SIGNAL
COMMON-MODE
ERROR
IN+
The ISL70617SEH is capable of a very high level (110dB) of
CMRR performance from DC to as high as 1kHz for gains greater
than 100, (see Figures 38 and 39 on page 15). This high level of
performance over frequency is made possible by the high
common-mode input impedance (80GΩ) but requires careful
attention to the matching of the IN+ and IN- external impedances
to GND.
A mismatch in the series impedance in conjunction with parasitic
capacitance at the IN+, IN- terminals (Figure 51) will cause a
common-mode amplitude imbalance that will show up as a
differential input signal, rapidly degrading CMRR as the
common-mode frequency increases.
Maximum CMRR performance is achieved with attention to
balancing external components and attention to PC layout.
Layout Guidelines
The ISL70617SEH is a high precision device with wideband AC
performance. Maximizing DC precision requires attention to the
layout of the gain resistors. Achieving good AC response requires
attention to parasitic capacitance at the gain resistor terminals.
CMRR performance over frequency is ensured with symmetrical
component placement and layout of the input differential signals
to the IN+ and IN- terminals.
To ensure the highest DC precision, the location of the gain
resistors and PC trace connections to the Kelvin connections are
most important. Proper Kelvin connections remove trace
resistance errors so that the amplifier gain accuracy and gain
temperature coefficients are determined by the gain resistor
matching tolerance. Interconnect constraints preclude mounting
the gain resistors next to each other, so they should be located on
either side of the ISL70617SEH and as close to the device as
possible. The Kelvin connections are formed at the junction of
the sense pins (±RINSENSE, ±RFBSENSE) and the gain resistor
current drive terminals (±RIN, ±RFB). This junction should be
made at the terminal pads directly under the ends of each
resistor.
500Ω
Reduced trace lengths that maintain DC accuracy are also
important for minimizing the capacitance that can degrade AC
stability. This is especially true at gains less than one.
500Ω
Layout guidelines for high CMRR include matching trace lengths
and symmetrical component placement on the circuit that
connects the signal source to the IN+, IN- pins. This ensures
matching of the IN+ and IN- input impedances (Figure 51).
C
R/2
Input Common-Mode Rejection
Considerations
Power Supply Decoupling
TRACE
CAPACITANCE
GND
FIGURE 51. INPUT DIFFERENTIAL LOW PASS FILTER AND
PARASITIC CAPACITANCE
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21
Standard power supply decoupling consists of a single 0.1µF 50V
ceramic capacitor at the power supply terminals located as close
to the device as possible. In applications where the input and
output supplies are strapped to the same voltage (VEE = VEO,
VCC = VCO), the connection point should be as close to the device
as possible with a single 0.1µF 50V ceramic capacitor at the
junction. Applications using separate supplies require 0.1µF 50V
ceramic decoupling capacitors at each power supply terminal.
FN8697.4
December 16, 2016
ISL70617SEH
Estimating Amplifier DC and
Noise Performance
Equation 15 converts the output offset error (Equation 13) range
to an input referred error range [VOS(RTI)] and enables a
comparison with the DC component of the input signal.
The gain resistor ohmic values and ratios are all that is required
to estimate DC offset and noise. The following sections illustrate
methods to calculate DC offset and noise performance. These
estimates are useful for optimizing resistor values for noise and
DC offset.
VOS(RTI) = [(VOS(IN)) + (VOS(FB)/AV) + (IERR × RFB)/AV]
Calculating DC Offset Voltage
Output offset voltage, like output noise, has several contributors.
Also similar to output noise, the major offset contributor depends
on the gain configuration. In high-gain, VOS(I) dominates, while in
low-gain, offset due to IERR dominates.
The summation of DC offsets to arrive at a total DC offset error is
performed in two ways. Equation 13 is a simple addition of the
DC offsets appearing at the output, and is useful when defining
the minimum to maximum range of offset that can be expected.
The drawback is that the result defines the corner of the corners
of the error box, and is not a typical value given that these
sources are uncorrelated.
VOS(RTO) = [(AV × VOS(IN)) + (VOS(FB)) + (IERR × RFB)]
(EQ. 13)
Equation 14 expresses the total DC error as the RMS, or square
root of the sum of the squares to provide an estimate of a typical
value.
VOS(RTO)TYP = √[(AV×VOS(IN))²+(VOS(FB))²+(IERR×RFB)²]
(EQ. 14)
(EQ. 15)
Similarly, Equation 16 shows the typical DC offset value
(Equation 14) referred to the input.
VOS(RTI)TYP = √[VOS(IN))² + (VOS(FB)/AV)² + (IERR × RFB)/AV)²]
(EQ. 16)
These results are summarized in Table 2.
Calculating Noise Voltage
The calculation of noise spectral density at the output [eN(RTO)]
from all noise sources is given by Equation 17.
(EQ. 17)
eN(RTO) = √[(AV × eN(I))² + (2 × AV × iN(I) × 500Ω)² +
(AV)² x (4kT × RIN) + (4kT × RFB) + (RFB × iN(IERR))²+(eN(FB))²]
Equation 18 converts the output noise to the input referred value
when evaluating the input signal-to-noise ratio.
eN(RTI) = eN(RTO)/AV
(EQ. 18)
Table 3 on page 23 provides examples of the noise contribution
of each source by circuit gain and output voltage span.
In a high-gain configuration, the input noise is the dominant
noise source. In a low-gain configuration, the noise voltage from
the product of the internal noise current, IN(err), and the feedback
resistor, RFB, dominates. The contribution of the internal noise
current, IN(err), increases in proportion to RFB, but the
corresponding increase in output voltage with RFB keeps the ratio
of this noise voltage to output voltage constant.
TABLE 2. COMPUTING TYPICAL OUTPUT OFFSET VOLTAGE RANGES
VOS(FB)
(µV)
(Note 16)
IERR (5nA)
x RFB
(µV)
(Note 16)
TYPICAL
TYPICAL
VOS(RTO)
VOS(RTI)
VOS(RTO)
VOS(RTI)
(µV)
(µV)
(µV)
(µV)
(Equation 13) (Equation 15) (Equation 14) (Equation 16)
AV
VO(LIN)
RIN
(kΩ)
Rf
(kΩ)
AV x VOS(I)
(µV)
(Note 16)
1
±2.5
30.1
30.1
±30
±400
±150
±580
428
1
±10
121
121
±30
±400
±600
±1030
722
100
±2.5
0.301
301
±3000
±400
±150
±3550
±3005
3030
3000
100
±10
1.21
121
±3000
±400
±600
±4000
±3010
3085
3000
NOTE:
16. Chosen for illustration purposes and does not reflect actual device performance.
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22
FN8697.4
December 16, 2016
ISL70617SEH
TABLE 3. 1kHz INPUT NOISE AND THERMAL NOISE CONTRIBUTIONS
AV
RIN
(kΩ)
RFB
(kΩ)
AV x eN(I)
(nV/√Hz)
2 x AV x iN(I)
x 500Ω
(nV/√Hz)
1
30.1
30.1
8.6
0.15
22.3
1
121
121
8.6
0.15
100 0.301
301
860
100 1.21
121
860
AV x √(4kT x RIN) √(4kT x RFB)
(nV/√Hz)
(nV/√Hz)
eN (RTI)
INPUT
REFERRED
NOISE
(nV/√Hz)
eN (RTO)
OUTPUT
REFERRED
NOISE
(nV/√Hz)
RFB x iN(IERR)
(nV/√Hz)
eN(FB)
(nV/√Hz)
22.3
78
8.6
86
44.6
44.6
300
8.6
307
15
223
22.3
78
8.6
896
8.9
15
446
44.6
300
8.6
1015
10.15
NOTE:
17. eN and iN values are chosen for illustration purposes and may not reflect actual device performance.
Driving an ADC
DC Offsets and Noise
The output feedback loop is closed by the connection of +VOUT to
the +VFB pin and -VOUT to the -VFB. The VCMO pin is just an input to
a very low bias current terminal, and would be connected to a
mid-scale voltage when driving a single supply ADC, such that the
input would have a ± input signal span. Where VCMO is connected
to the ADC ground, only positive inputs would be converted by the
ADC.
There are three offset and noise sources in the ISL70617SEH:
the input, feedback, and IERR. The input has a low input noise
voltage and offset, which dominates at gains ~30 and above. The
feedback GM stage has similar errors, but is never dominant
compared to IERR and is generally ignored. IERR can be thought of
as the mistracking and noise of the internal 100µA current
sources. Use Equation 19 and quantify these errors at the output
(RTO).
Input and Feedback Amplifiers
The input and the output linear dynamic ranges are set by class-A
biasing on the RIN resistor for the input stage, and the RFB
resistor for the output stage (Figure 48). Unity gain buffers force
the differential voltages across each resistor to the maximum of
100µA*R produced by the current sources. While the voltages
impressed across these resistors will continue to move with
overloads beyond this value, they will not be linear. A good rule of
thumb is to keep the maximum linear dynamic range to less than
~80% of the maximum I*R voltage across the resistors
(Equation 8).
At equilibrium, the amplifier forces the resistor currents to be the
same so that their voltages match the desired gain ratio,
RFB/RIN; however, during transient conditions, the currents
remain unequal until the amplifier output settles. For this reason,
the current sources driving the feedback resistor are 20% higher
than those driving the input GM resistor to provide an extra
margin.
Rail-to-rail Output Stage
The output stage is of rail-to-rail design, and has separate
supplies from the rest of the IC. The input GM stage and
feedback amplifiers are driven from the VCC and VEE supply pins
and only the output stage is powered by the VCO and VEO pins. A
typical supply arrangement when driving a 5V ADC is to have VCO
connected to the ADC +5V supply and VEO to ground. Therefore,
the ADC can never be overdriven beyond its supply rails. In this
configuration, the common-mode input range of the feedback
amplifier limits the dynamic range of the output stage. The input
and feedback amplifiers are not rail-to-rail, so the VCC must be
more positive than VCO and VEE more negative than VEO by the
feedback amplifier saturation voltage (±3V).
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23
VOS(RTO) = VOS(IN)*Gain + IERR*RFB+VOS(FB)
(EQ. 19)
Similarly, Equation 20 for noise:
VN(RTO)2 = (VN(IN)*Gain)2 + (In(err)*RFB)2
(EQ. 20)
Reducing RFB to the minimum value required for linear output
swing will improve output offsets and noise directly.
Another result of scaling RFB is that the -3dB bandwidth is also
inversely scaled. Highest bandwidth will then be available at
lowest Rf. The ISL70617SEH is designed to be stable with
RFB = 30.1kΩ minimum.
Having set RFB to establish the output range, RIN is set to
establish Gain = RFB/RIN. While -3dB bandwidth does diminish
for RIN < 500Ω, this still allows fairly constant bandwidth over a
wide variety of gains. Similar to the resistor-oriented op amp
topology, parasitic capacitance at the RFB node will peak the
frequency response. The ISL70617SEH is designed to be tolerant
to parasitic capacitances at RFB from values of 2pF to 20pF. The
input stage is more tolerant, allowing 2pF to 30pF. Electronic
analog switches can be used to alter RIN selections for gain
switching, as long as the minimum RFB halves are connected to
the RIN pins directly, with the switch(es) in between the halves.
FN8697.4
December 16, 2016
ISL70617SEH
The following switch example (Figure 52) is a practical way to
isolate switch parasitic capacitances from the RIN pins:
+RIN
R0
2.5k
R1
2.5k
S0
R2
15k
S1
+RINSENSE
KELVIN
CONTACT
-RIN
S2
KELVIN
CONTACT
R4
95k
S3
FIGURE 52. SWITCH EXAMPLE
The RFB and RIN resistors are provided with Kelvin sense pins to
minimize interconnect resistance errors. This is especially useful
at high gains and small RIN.
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24
The external resistors, RFB and RIN, set both the voltage gain and
the linear output voltage range. The linear output voltage range
is the maximum differential signal that can appear at the output,
and is different from the common-mode range. The voltage gain
is shown in Equation 21.
(EQ. 21)
AV = (RFB/RIN)
-RINSENSE
R3
45k
Amplifier Usage Examples
Linear output voltage range is shown in Equation 22.
VO(LIN) = ±(RFB × IRIN)
(EQ. 22)
where IRFB is nominally set to 80% of IRIN.
For example, an application requiring a voltage gain of 100 and a
linear output range of ±2.5V might select a 30kΩ feedback
resistor and a 300Ω input resistor to ensure linear operation
throughout the required output span. The output offset voltage
(Table 2 on page 22) shows a few standard gain configurations
and linear output spans with appropriately sized resistors.
FN8697.4
December 16, 2016
ISL70617SEH
Package Characteristics
Weight of Packaged Device
1.33 grams (Typical)
TOP METALLIZATION
Type: AlCu (99.5%/0.5%)
Thickness: 30kÅ
BACKSIDE FINISH
Lid Characteristics
Silicon
Finish: Gold
Potential: Connected to Pin #8 (GND)
Case Isolation to Any Lead: 20 x 109 Ω (minimum)
Assembly Related Information
SUBSTRATE POTENTIAL
Floating
Die Characteristics
Additional Information
Die Dimensions
2960µm x 3210µm (117 mils x 127 mils)
Thickness: 483µm ±25µm (19 mils ±1 mil)
Interface Materials
WORST CASE CURRENT DENSITY
<2 x 105 A/cm2
PROCESS
Dielectrically Isolated Advanced Bipolar Technology- PR40
GLASSIVATION
Type: Silicon Nitride
Thickness: 15kÅ
Metalization Mask Layout
DNC
DNC
IN+
IN-
+RFB
DNC
+RFB SENSE
+RIN
+RIN SENSE
-RFB SENSE
-RIN SENSE
-RFB
-RIN
GND
VCMO
VCC
VEE
VCO
VEO
+VFB
Submit Document Feedback
25
+VOUT
-VOUT
-VFB
FN8697.4
December 16, 2016
ISL70617SEH
TABLE 4. DIE LAYOUT X-Y COORDINATES
X
(µm)
Y
(µm)
BOND WIRES PER PAD
(Note 19)
4
1
1292
1
+RFB SENSE
5
1
1032
1
-RFB SENSE
6
1
738.5
1
-RFB
7
1
478.5
1
GND
8
0
0
1
VCC
9
0
-273
1
VCO
10
1
-918.5
1
+VFB
11
158.5
-1131.5
1
+VOUT
12
421.5
-1131.5
1
-VOUT
13
2012.5
1160.5
-VFB
14
2288.5
-1160.5
1
VEO
15
2479.5
-960.5
1
VEE
16
2479.5
-307.5
1
VCMO
17
2479.5
-31.5
-RIN
18
2479.5
246.5
1
-RIN SENSE
19
2479.5
530
1
+RIN SENSE
20
2479.5
790
1
+RIN
21
2479.5
1069
1
DNC
22
IN-
23
2235.5
1569.5
1
IN+
24
1975.5
1569.5
1
PAD NAME
PAD NUMBER
NC
1
DNC
2
DNC
3
+RFB
NOTES:
18. Origin of coordinates is the centroid of GND.
19. Bond wire size is 1.25 mil (Al).
Submit Document Feedback
26
FN8697.4
December 16, 2016
ISL70617SEH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not
warranted. Please visit our website to make sure you have the latest revision.
DATE
REVISION
CHANGE
December 16, 2016
FN8697.4
Updated Related Literature section.
Added Note 15 and applicable cross-references.
July 5, 2016
FN8697.3
Boldface limits condition in “Electrical Specifications” on page 5 changed from “...or across” to “...and across”
and updated bolding of applicable specs.
April 28, 2016
FN8697.2
“Absolute Maximum Ratings” on page 5 - Changed CDM testing information from JESD22-C101F to
JS-002-2014.
“VOSFB” on page 5 - Updated Test Conditions by adding Temp ranges and adding Post 75krad conditions and
limits.
“VOSOUT” on page 7 - bolded MAX spec.
Equations 13 through 16 updated VOS(I) to VOS (IN)
Table 2 on page 22 Changed values in AV x Vos (I), Vos(RTO), Vos(RTI) and Typical Vos(RTO), Typical Vos(RTI).
January 7, 2016
FN8697.1
Added Figure 47 on page 16.
Updated Figure 48 on page 17.
Added reference to Equation 8 under “Designing with the ISL70617SEH” on page 18 item #2.
November 23, 2015
FN8697.0
Initial release
About Intersil
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For the most updated datasheet, application notes, related documentation, and related parts, please see the respective product
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that data sheets are
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Submit Document Feedback
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FN8697.4
December 16, 2016
ISL70617SEH
Ceramic Metal Seal Flatpack Packages (Flatpack)
K24.A MIL-STD-1835 CDFP4-F24 (F-6A, CONFIGURATION B)
A
e
24 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
A
INCHES
PIN NO. 1
ID AREA
-A-
D
-B-
S1
b
E1
0.004 M
H A-B S
D S
0.036 M
Q
H A-B S
D S
C
E
-D-
A
-C-
-HL
E2
E3
SEATING AND
BASE PLANE
c1
L
E3
BASE
METAL
(c)
b1
M
M
MAX
MIN
MAX
NOTES
A
0.045
0.115
1.14
2.92
-
b
0.015
0.022
0.38
0.56
-
b1
0.015
0.019
0.38
0.48
-
c
0.004
0.009
0.10
0.23
-
c1
0.004
0.006
0.10
0.15
-
D
-
0.640
-
16.26
3
E
0.350
0.420
9.14
10.67
-
E1
-
0.450
-
11.43
3
E2
0.180
-
4.57
-
-
E3
0.030
-
0.76
-
7
2
0.050 BSC
1.27 BSC
-
k
0.008
0.015
0.20
0.38
L
0.250
0.370
6.35
9.40
-
Q
0.026
0.045
0.66
1.14
8
S1
0.005
-
0.13
-
6
M
-
0.0015
-
0.04
-
N
(b)
NOTES:
MIN
e
LEAD FINISH
MILLIMETERS
SYMBOL
24
24
Rev. 0 5/18/94
SECTION A-A
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area
shown. The manufacturer’s identification shall not be used as a pin
one identification mark. Alternately, a tab (dimension k) may be
used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the limits
of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension M
applies to lead plating and finish thickness. The maximum limits
of lead dimensions b and c or M shall be measured at the centroid
of the finished lead surfaces, when solder dip or tin plate lead
finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric
materials shall be molded to the bottom of the package to cover
the leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
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For the most recent package outline drawing, see K24.A.
FN8697.4
December 16, 2016