TI MSP430F110AIPWR Mixed signal microcontroller Datasheet

SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004
D Low Supply Voltage Range 1.8 V to 3.6 V
D Ultralow-Power Consumption:
D Family Members Include:
D
D
D
D
D
D
− Active Mode: 200 µA at 1 MHz, 2.2 V
− Standby Mode: 0.8 µA
− Off Mode (RAM Retention): 0.1 µA
Wake-Up From Standby Mode in less
than 6 µs
16-Bit RISC Architecture, 125 ns
Instruction Cycle Time
Basic Clock Module Configurations:
− Various Internal Resistors
− Single External Resistor
− 32 kHz Crystal
− High Frequency Crystal
− Resonator
− External Clock Source
16-Bit Timer_A With Three
Capture/Compare Registers
Serial Onboard Programming,
No External Programming Voltage
Needed
MSP430F110:
D
1KB + 128B Flash Memory
128B RAM
MSP430F112: 4KB + 256B Flash Memory
256B RAM
Available in a 20-Pin Plastic Small-Outline
Wide Body (SOWB) Package and 20-Pin
Plastic Thin Shrink Small-Outline Package
(TSSOP)
For Complete Module Descriptions, Refer
to the MSP430x1xx Family User’s Guide,
Literature Number SLAU049
DW OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
TEST
VCC
P2.5/Rosc
VSS
XOUT/TCLK
XIN
RST/NMI
P2.0/ACLK
P2.1/INCLK
P2.2/TA0
20
19
18
17
16
15
14
13
12
11
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI
P1.5/TA0/TMS
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
P2.4/TA2
P2.3/TA1
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6µs.
The MSP430F11x series is an ultralow-power mixed signal microcontroller with a built in 16-bit timer and
fourteen I/O pins.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data and display them or transmit them to a host system. Stand alone RF sensor front-end is another
area of application.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1999 − 2004, Texas Instruments Incorporated
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AVAILABLE OPTIONS
PACKAGED DEVICES
TA
−40°C to 85°C
PLASTIC
20-PIN SOWB
(DW)
PLASTIC
20-PIN TSSOP
(PW)
MSP430F110IDW
MSP430F112IDW
MSP430F110IPW
MSP430F112IPW
functional block diagram
XIN
XOUT
VCC
VSS
P1
RST/NMI
JTAG
ROSC
Oscillator
System
Clock
ACLK
4KB Flash
256B RAM
SMCLK
1KB Flash
128B RAM
P2
8
I/O Port 1
8 I/Os, with
Interrupt
Capability
6
I/O Port 2
6 I/Os, with
Interrupt
Capability
MCLK
Test
MAB,
4 Bit
MAB,MAB,
16 Bit16-Bit
JTAG
CPU
MCB
Emulation
Module
Incl. 16 Reg.
Bus
Conv
MDB,
16-Bit
MDB,
16 Bit
MDB, 8 Bit
TEST
†
Watchdog
Timer
Timer_A3
POR
3 CC Reg
15/16-Bit
† A pulldown resistor of 30 kΩ is needed on F11x devices.
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Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
P1.0/TACLK
13
I/O
General-purpose digital I/O pin/Timer_A, clock signal TACLK input
P1.1/TA0
14
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit
P1.2/TA1
15
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2
16
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK/TCK
17
I/O
General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for device programming
and test
P1.5/TA0/TMS
18
I/O
General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select, input terminal for
device programming and test
P1.6/TA1/TDI
19
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input terminal
P1.7/TA2/TDO/TDI†
20
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output terminal or data input
during programming
P2.0/ACLK
8
I/O
General-purpose digital I/O pin/ACLK output
P2.1/INCLK
9
I/O
General-purpose digital I/O pin/Timer_A, clock signal at INCLK
P2.2/TA0
10
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0B input, compare: Out0 output/BSL receive
P2.3/TA1
11
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI1B input, compare: Out1 output
P2.4/TA2
12
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output
P2.5/ROSC
RST/NMI
3
I/O
General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal frequency
7
I
Reset or nonmaskable interrupt input
TEST
1
I
Selects test mode for JTAG pins on Port1. Must be tied low with less than 30 kΩ.
VCC
VSS
2
XIN
6
Supply voltage
4
Ground reference
I
Input terminal of crystal oscillator
XOUT/TCLK
5
I/O Output terminal of crystal oscillator or test clock input
† TDO or TDI is selected via JTAG instruction.
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short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g. ADD R4,R5
R4 + R5 −−−> R5
Single operands, destination only
e.g. CALL
PC −−>(TOS), R8−−> PC
Relative jump, un/conditional
e.g. JNE
R8
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
Indirect
D
D
D
D
D
Indirect
autoincrement
Register
Indexed
Symbolic (PC relative)
Absolute
Immediate
NOTE: S = source
4
S D
D
D
D
D
SYNTAX
EXAMPLE
MOV Rs,Rd
MOV R10,R11
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
OPERATION
R10
−−> R11
M(2+R5)−−> M(6+R6)
MOV EDE,TONI
M(EDE) −−> M(TONI)
MOV &MEM,&TCDAT
M(MEM) −−> M(TCDAT)
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) −−> M(Tab+R6)
D
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) −−> R11
R10 + 2−−> R10
D
MOV #X,TONI
MOV #45,TONI
D = destination
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#45
−−> M(TONI)
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operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode AM;
−
All clocks are active
D Low-power mode 0 (LPM0);
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
D Low-power mode 1 (LPM1);
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DCO’s dc-generator is disabled if DCO not used in active mode
D Low-power mode 2 (LPM2);
−
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D Low-power mode 3 (LPM3);
−
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
D Low-power mode 4 (LPM4);
−
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
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interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the memory with an address range of
0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction
sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog
WDTIFG (Note1)
KEYV (Note 1)
Reset
0FFFEh
15, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG (Notes 1 and 5)
OFIFG (Notes 1 and 5)
ACCVIFG (Notes 1 and 5)
(non)-maskable,
(non)-maskable,
(non)-maskable
0FFFCh
14
0FFFAh
13
0FFF8h
12
0FFF6h
11
Watchdog timer
WDTIFG
maskable
0FFF4h
10
Timer_A3
TACCR0 CCIFG
(Note 2)
maskable
0FFF2h
9
Timer_A3
TACCR1 and TACCR2
CCIFGs, TAIFG
(Notes 1 and 2)
maskable
0FFF0h
8
0FFEEh
7
0FFECh
6
0FFEAh
5
0FFE8h
4
I/O Port P2
(eight flags − see Note 3)
P2IFG.0 to P2IFG.7
(Notes 1 and 2)
maskable
0FFE6h
3
I/O Port P1
(eight flags)
P1IFG.0 to P1IFG.7
(Notes 1 and 2)
maskable
0FFE4h
2
0FFE2h
1
0FFE0h
0, lowest
NOTES: 1.
2.
3.
4.
5.
6
Multiple source flags
Interrupt flags are located in the module
There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0−5) are implemented on the ’11x devices.
Nonmaskable: neither the individual nor the general interrupt enable bit will disable an interrupt event.
(non)-maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot.
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special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.
interrupt enable 1 and 2
Address
7
6
0h
5
4
ACCVIE
NMIIE
rw-0
WDTIE:
OFIE:
NMIIE:
ACCVIE:
Address
3
2
1
OFIE
rw-0
0
WDTIE
rw-0
rw-0
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer
is configured in interval timer mode.
Oscillator fault enable
Nonmaskable interrupt enable
Flash access violation interrupt enable
7
6
5
6
5
4
3
2
4
3
2
1
0
01h
interrupt flag register 1 and 2
Address
7
02h
NMIIFG
rw-0
WDTIFG:
OFIFG:
NMIIFG:
Address
1
OFIFG
rw-1
0
WDTIFG
rw-(0)
Set on Watchdog Timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
Flag set on oscillator fault
Set via RST/NMI-pin
7
6
5
4
3
2
1
0
03h
Legend
rw:
rw-0,1:
rw-(0,1):
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device.
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memory organization
MSP430F110
FFFFh
FFE0h
FFDFh
Int. Vector
1 KB Flash
FC00h Segment0,1
MSP430F112
FFFFh
FFE0h
Int. Vector
FFDFh
4 KB
Main
Flash
Segment0−7 Memory
F000h
10FFh
1080h
0FFFh
0C00h
128B Flash
SegmentA
1 KB
Boot ROM
10FFh
2 × 128B
Information
Flash
Memory
1000h SegmentA,B
0FFFh
1 KB
Boot ROM
0C00h
02FFh
027Fh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
256B RAM
128B RAM
16b Per.
8b Per.
SFR
0200h
01FFh
16b Per.
0100h
00FFh
0010h
000Fh
0000h
8b Per.
SFR
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.
BSL Function
DW & PW Package Pins
Data Transmit
14 - P1.1
Data Receive
10 - P2.2
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A and B can be erased individually, or as a group with segments 0−n.
Segments A and B are also called information memory.
D New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
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Segment0 w/
Interrupt Vectors
0FDFFh
0FC00h
Segment1
0FBFFh
0FA00h
Segment2
0F9FFh
0F800h
Segment3
0F7FFh
0F600h
Segment4
0F5FFh
0F400h
Segment5
0F3FFh
0F200h
Segment6
0F1FFh
0F000h
Segment7
010FFh
01080h
SegmentA
0107Fh
01000h
SegmentB
Information
Memory
0FFFFh
0FE00h
Flash Main Memory
flash memory (continued)
NOTE: All segments not implemented on all devices.
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x1xx Family User’s Guide, literature
number SLAU049.
oscillator and system clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock
module is designed to meet the requirements of both low system cost and low-power consumption. The internal
DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The basic clock module provides the
following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
D Main clock (MCLK), the system clock used by the CPU.
D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
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digital I/O
There are two 8-bit I/O ports implemented—ports P1 and P2 (only six P2 I/O signals are available on external
pins):
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of port P1 and six bits of port P2.
Read/write access to port-control registers is supported by all instructions.
NOTE:
Six bits of port P2, P2.0 to P2.5, are available on external pins − but all control and data bits for port
P2 are implemented.
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number
Device Input Signal
Module Input Name
13 - P1.0
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
9 - P2.1
INCLK
INCLK
14 - P1.1
TA0
CCI0A
TA0
CCI0B
DVSS
DVCC
GND
10 - P2.2
15 - P1.2
TA1
VCC
CCI1A
11 - P2.3
TA1
CCI1B
16 - P1.3
10
DVSS
DVCC
TA2
GND
VCC
CCI2A
ACLK (internal)
CCI2B
DVSS
DVCC
GND
Module Block
Module Output Signal
Timer
NA
14 - P1.1
18 - P1.5
CCR0
TA0
10 - P2.2
15 - P1.2
19 - P1.6
CCR1
TA1
11 - P2.3
16 - P1.3
20 - P1.7
CCR2
VCC
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12 - P2.4
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peripheral file map
PERIPHERALS WITH WORD ACCESS
Timer_A
Reserved
Reserved
Reserved
Reserved
Capture/compare register
Capture/compare register
Capture/compare register
Timer_A register
Reserved
Reserved
Reserved
Reserved
Capture/compare control
Capture/compare control
Capture/compare control
Timer_A control
Timer_A interrupt vector
TACCTL2
TACCTL1
TACCTL0
TACTL
TAIV
017Eh
017Ch
017Ah
0178h
0176h
0174h
0172h
0170h
016Eh
016Ch
016Ah
0168h
0166h
0164h
0162h
0160h
012Eh
TACCR2
TACCR1
TACCR0
TAR
Flash Memory
Flash control 3
Flash control 2
Flash control 1
FCTL3
FCTL2
FCTL1
012Ch
012Ah
0128h
Watchdog
Watchdog/timer control
WDTCTL
0120h
PERIPHERALS WITH BYTE ACCESS
Basic Clock
Basic clock sys. control2
Basic clock sys. control1
DCO clock freq. control
BCSCTL2
BCSCTL1
DCOCTL
058h
057h
056h
Port P2
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
Port P2 input
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Port P1
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
Port P1 input
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
026h
025h
024h
023h
022h
021h
020h
Special Function
SFR interrupt flag2
SFR interrupt flag1
SFR interrupt enable2
SFR interrupt enable1
IFG2
IFG1
IE2
IE1
003h
002h
001h
000h
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absolute maximum ratings†
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V
Voltage applied to any pin (referenced to VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC+0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature, Tstg (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Storage temperature, Tstg (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to VSS.
recommended operating conditions
MIN
Supply voltage during program execution, VCC (see Note 1)
1.8
Supply voltage during program/erase flash memory, VCC
2.7
Supply voltage, VSS
MAX
−40
LF mode selected, XTS=0
Watch crystal
V
3.6
V
85
°C
XT1 mode selected, XTS=1
Hz
450
8000
1000
8000
VCC = 1.8 V
dc
2
MHz
VCC = 2.2 V
dc
5
MHz
Crystal
Processor frequency f(system) (MCLK signal)
V
32 768
Ceramic resonator
UNITS
3.6
0
Operating free-air temperature range, TA
LFXT1 crystal frequency,
f(LFXT1) (see Note 2)
NOM
kHz
VCC = 3.6 V
dc
8
MHz
NOTES: 1. The LFXT1 oscillator in LF-mode requires a resistor of 5.1 MΩ from XOUT to VSS when VCC <2.5 V.
The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal frequency of 4 MHz at VCC ≥ 2.2 V.
The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or a crystal frequency of 8 MHz at VCC ≥ 2.8 V.
2. The LFXT1 oscillator in LF-mode requires a watch crystal. The LFXT1 oscillator in XT1-mode accepts a ceramic resonator or crystal.
f(system) − Maximum Processor Frequency − MHz
MSP430F11x Devices
9
8 MHz at
3.6 V
8
7
6
5 MHz at
2.2 V
5
4
3
2 MHz at
1.8 V
2
1
0
0
1
2
3
VCC − Supply Voltage − V
4
NOTE: Minimum processor frequency is defined by system clock. Flash
program or erase operations require a minimum VCC of 2.7 V.
Figure 1. Frequency vs Supply Voltage
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
supply current (into VCC) excluding external current
PARAMETER
I(AM)
Active mode
I(CPUOff)
Low-power mode, (LPM0)
I(LPM2)
Low-power mode, (LPM2)
TEST CONDITIONS
Low-power mode, (LPM3)
Low-power mode, (LPM4)
MAX
VCC = 2.2 V
200
250
VCC = 3 V
300
350
TA = −40
−40°C
C +85
+85°C,
C,
f(MCLK) = f(SMCLK) = f(ACLK) = 4096 Hz
VCC = 2.2 V
VCC = 3 V
1.6
3
3
4.3
TA = −40°C +85°C,
f(MCLK) = 0, f(SMCLK) = 1 MHz,
f(ACLK) = 32,768 Hz
TA = −40°C +85°C,
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32,768 Hz, SCG0 = 0
VCC = 2.2 V
32
45
VCC = 3 V
55
70
VCC = 2.2 V
11
14
VCC = 3 V
17
22
0.8
1.2
0.7
1
1.6
2.3
1.8
2.2
1.6
1.9
2.3
3.4
0.1
0.5
0.1
0.5
0.8
1.9
VCC = 2.2 V
TA = 85°C
TA = −40°C
TA = 25°C
TA = 85°C
I(LPM4)
TYP
TA = −40°C +85°C,
f(MCLK) = f(SMCLK) = 1 MHz,
f(ACLK) = 32,768 Hz
TA = −40°C
TA = 25°C
I(LPM3)
MIN
TA = −40°C
TA = 25°C
VCC = 3 V
f(MCLK) = 0 MHz
f(SMCLK) = 0 MHz,
f(ACLK) = 0 Hz, SCG0 = 1
VCC = 2.2 V/3 V
TA = 85°C
NOTE: All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
UNIT
µA
µA
µA
µA
µA
µA
µA
current consumption of active mode versus system frequency, F version
IAM = IAM[1 MHz] × fsystem [MHz]
current consumption of active mode versus supply voltage, F version
IAM = IAM[3 V] + 120 µA/V × (VCC−3 V)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
Schmitt-trigger inputs Port 1 to Port P2; P1.0 to P1.7, P2.0 to P2.5
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT−
Negative-going input threshold voltage
Vhys
Input voltage hysteresis, (VIT+ − VIT−)
MIN
TYP
MAX
VCC = 2.2 V
VCC = 3 V
1.1
1.3
1.5
1.8
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
0.4
0.9
.90
1.2
0.3
1
VCC = 3 V
0.5
1.4
UNIT
V
V
V
standard inputs − RST/NMI; TCK, TMS, TDI
PARAMETER
VIL
VIH
TEST CONDITIONS
Low-level input voltage
VCC = 2.2 V / 3 V
High-level input voltage
MIN
TYP
VSS
0.8×VCC
MAX
VSS+0.6
VCC
UNIT
V
V
inputs Px.x, TAx
PARAMETER
t(int)
t(cap)
External interrupt timing
Timer_A, capture timing
TEST CONDITIONS
VCC
2.2 V/3 V
Port P1, P2: P1.x to P2.x, External trigger signal
for the interrupt flag, (see Note 1)
TA0, TA1, TA2 (see Note 2)
f(TAext)
Timer_A clock frequency
externally applied to pin
TACLK, INCLK t(H) = t(L)
f(TAint)
Timer_A clock frequency
SMCLK or ACLK signal selected
MIN
TYP
MAX
1.5
2.2 V
62
3V
50
2.2 V/3 V
1.5
2.2 V
62
3V
50
UNIT
cycle
ns
cycle
ns
2.2 V
8
3V
10
2.2 V
8
3V
10
MHz
MHz
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with
trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in
MCLK cycles.
2. The external capture signal triggers the capture event every time the mimimum t(cap) cycle and time parameters are met. A capture
may be triggered with capture signals even shorter than t(cap). Both the cycle and timing specifications must be met to ensure a
correct capture of the 16-bit timer value and to ensure the flag is set.
leakage current
PARAMETER
Ilkg(Px.x)
High-impedance leakage current
TEST CONDITIONS
MIN
TYP
MAX
Port P1: P1.x, 0 ≤ × ≤ 7
(see Notes 1 and 2)
VCC = 2.2 V/3 V,
±50
Port P2: P2.x, 0 ≤ × ≤ 5
(see Notes 1 and 2)
VCC = 2.2 V/3 V,
±50
UNIT
nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional
pullup or pulldown resistor.
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
outputs Port 1 to Port 2; P1.0 to P1.7, P2.0 to P2.5
PARAMETER
VOH
VOH
VOL
High-level output voltage
Port 1
High-level output voltage
Port 2
Low-level output voltage
Port 1 and Port 2
TEST CONDITIONS
I(OHmax) = −1.5 mA
I(OHmax) = −6 mA
VCC = 2.2 V
I(OHmax) = −1.5 mA
I(OHmax) = −6 mA
VCC = 3 V
I(OHmax) = −1 mA
I(OHmax) = −3.4 mA
VCC = 2.2 V
I(OHmax) = −1 mA
I(OHmax) = −3.4 mA
VCC = 3 V
I(OLmax) = 1.5 mA
I(OLmax) = 6 mA
VCC = 2.2 V
I(OLmax) = 1.5 mA
MIN
See Note 1
TYP
MAX
VCC−0.25
VCC−0.6
VCC
VCC
VCC−0.25
VCC−0.6
VCC
VCC
VCC−0.25
VCC−0.6
VCC
VCC
VCC−0.25
VCC−0.6
VCC
VCC
See Note 2
VSS
VSS
VSS+0.25
VSS+0.6
See Note 1
VSS
VSS+0.25
See Note 2
See Note 1
See Note 2
See Note 3
See Note 3
See Note 3
See Note 3
See Note 1
VCC = 3 V
UNIT
V
V
V
I(OLmax) = 6 mA
See Note 2
VSS
VSS+0.6
NOTES: 1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum voltage
drop specified.
2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage
drop specified.
3. One output loaded at a time.
outputs P1.x, P2.x, TAx
PARAMETER
TEST CONDITIONS
f(P20)
P2.0/ACLK, CL = 20 pF
f(TAx)
TA0, TA1, TA2, CL = 20 pF
Internal clock source, SMCLK signal applied
(See Note 1)
Output frequency
fSMCLK = fLFXT1 = fXT1
fSMCLK = fLFXT1 = fLF
P1.4/SMCLK, CL = 20 pF
t(Xdc)
Duty cycle of O/P
frequency
MIN
2.2 V/3 V
dc
fSystem
40%
60%
2.2 V/3 V
fSMCLK = fLFXT1/n
fSMCLK = fDCOCLK
P2.0/ACLK, CL = 20 pF
VCC
2.2 V/3 V
fP20 = fLFXT1 = fXT1
fP20 = fLFXT1 = fLF
fP20 = fLFXT1/n
TA0, TA1, TA2, CL = 20 pF, Duty cycle = 50%
2.2 V/3 V
35%
65%
50%−
15 ns
50%
50%+
15 ns
50%−
15 ns
50%
50%+
15 ns
40%
2.2 V/3 V
• DALLAS, TEXAS 75265
MAX
UNIT
fSystem
MHz
60%
30%
t(TAdc)
2.2 V/3 V
NOTE 1: The limits of the system clock MCLK have to be met. MCLK and SMCLK can have different frequencies.
POST OFFICE BOX 655303
TYP
70%
50%
0
±50
ns
15
SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
PUC/POR
PARAMETER
TEST CONDITIONS
MIN
VPOR
POR
VCC = 2.2 V/3 V
TA = 85°C
V(min)
t(reset)
PUC/POR
Reset is accepted internally
MAX
UNIT
150
250
µs
1.4
1.8
V
1.1
1.5
V
0.8
1.2
V
0
0.4
V
t(POR_Delay)
TA = −40°C
TA = 25°C
TYP
µs
2
V
VCC
V
POR
No POR
POR
V
(min)
POR
t
Figure 2. Power-On Reset (POR) vs Supply Voltage
2.0
1.8
1.8
V POR [V]
1.6
1.4
1.2
1.5
Max
1.2
1.4
Min
1.0
1.1
0.8
0.8
0.6
0.4
0.2
25°C
0
−40
−20
0
20
40
Temperature [°C]
Figure 3. VPOR vs Temperature
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
60
80
SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
wake-up from lower power modes (LPMx)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
t(LPM0)
t(LPM2)
VCC = 2.2 V/3 V
VCC = 2.2 V/3 V
f(MCLK) = 1 MHz,
f(MCLK) = 2 MHz,
VCC = 2.2 V/3 V
VCC = 2.2 V/3 V
6
t(LPM3)
f(MCLK) = 3 MHz,
VCC = 2.2 V/3 V
6
f(MCLK) = 1 MHz,
f(MCLK) = 2 MHz,
VCC = 2.2 V/3 V
VCC = 2.2 V/3 V
6
f(MCLK) = 3 MHz,
NOTE 1: Parameter applicable only if DCOCLK is used for MCLK.
VCC = 2.2 V/3 V
6
Delay time (see Note 1)
t(LPM4)
UNIT
100
ns
100
6
6
µs
µs
RAM
PARAMETER
MIN
TYP
MAX
UNIT
V(RAMh)
CPU halted (see Note 1)
1.6
V
NOTE 1: This parameter defines the minimum supply voltage VCC when the data in the program memory RAM remains unchanged. No program
execution should happen during this supply voltage condition.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
DCO
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.12
0.15
Rsel = 0, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 2.2 V
VCC = 3 V
0.08
f(DCO03)
0.08
0.13
0.16
0.19
0.23
Rsel = 1, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 2.2 V
VCC = 3 V
0.14
f(DCO13)
0.14
0.18
0.22
f(DCO23)
Rsel = 2, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 2.2 V
VCC = 3 V
0.22
0.30
0.36
0.22
0.28
0.34
f(DCO33)
Rsel = 3, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 2.2 V
VCC = 3 V
0.37
0.49
0.59
0.37
0.47
0.56
f(DCO43)
Rsel = 4, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 2.2 V
VCC = 3 V
0.61
0.77
0.93
0.61
0.75
0.9
f(DCO53)
Rsel = 5, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 2.2 V
VCC = 3 V
1
1.2
1.5
1
1.3
1.5
f(DCO63)
Rsel = 6, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
VCC = 2.2 V
VCC = 3 V
f(DCO73)
Rsel = 7, DCO = 3, MOD = 0, DCOR = 0,
TA = 25°C
f(DCO77)
Rsel = 7, DCO = 7, MOD = 0, DCOR = 0,
TA = 25°C
f(DCO47)
Rsel = 4, DCO = 7, MOD = 0, DCOR = 0,
TA = 25°C
S(Rsel)
SR = fRsel+1/fRsel
VCC = 2.2 V/3 V
1.35
1.65
2
S(DCO)
SDCO = fDCO+1/fDCO
VCC = 2.2 V/3 V
1.07
1.12
1.16
Temperature drift, Rsel = 4, DCO = 3, MOD = 0
(see Note 1)
VCC = 2.2 V
−0.31
−0.36
−0.40
Dt
VCC = 3 V
−0.33
−0.38
−0.43
DV
Drift with VCC variation, Rsel = 4, DCO = 3, MOD = 0
(see Note 1)
0
5
10
1.6
1.9
2.2
1.69
2.0
2.29
VCC = 2.2 V
VCC = 3 V
2.4
2.9
3.4
2.7
3.2
3.65
VCC = 2.2 V
4
4.5
4.9
4.4
4.9
5.4
VCC = 3 V
FDCO40 FDCO40 FDCO40
x1.7
x2.1
x2.5
VCC = 2.2 V/3 V
VCC = 2.2 V/3 V
f(DCOx7)
f(DCOx0)
Max
Min
Max
Min
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
2.2 V
1
f DCOCLK
Frequency Variance
NOTE 1: These parameters are not production tested.
3V
0
1
VCC
3
4
5
6
DCO Steps
Figure 4. DCO Characteristics
18
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ratio
%/°C
%/V
SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
main DCO characteristics
D Individual devices have a minimum and maximum operation frequency. The specified parameters for
f(DCOx0) to f(DCOx7) are valid for all devices.
D All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps Rsel1, ... Rsel6 overlaps Rsel7.
D DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter SDCO.
D Modulation control bits MOD0 to MOD4 select how often f(DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency f(DCO) is used for the remaining cycles. The frequency is an average equal to:
f average +
MOD
32 f (DCO) f (DCO)1)
f (DCO))(32*MOD) f (DCO)1)
crystal oscillator, LFXT1
PARAMETER
CXIN
CXOUT
VIL
VIH
Input capacitance
Output capacitance
TEST CONDITIONS
XTS=0; LF mode selected.
VCC = 2.2 V / 3 V
XTS=1; XT1 mode selected.
VCC = 2.2 V / 3 V (Note 1)
XTS=0; LF mode selected.
VCC = 2.2 V / 3 V
XTS=1; XT1 mode selected.
VCC = 2.2 V / 3 V (Note 1)
MIN
TYP
MAX
12
pF
2
12
pF
2
VSS
0.2×VCC
0.8×VCC
VCC
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
Input levels at XIN
VCC = 2.2 V/3 V (see Note 2)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
V
19
SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Flash Memory
TEST
CONDITIONS
PARAMETER
VCC(PGM/
ERASE)
VCC
MIN
NOM
MAX
UNIT
Program and Erase supply voltage
2.7
3.6
V
fFTG
IPGM
Flash Timing Generator frequency
257
476
kHz
Supply current from DVCC during program
2.7 V/ 3.6 V
3
5
mA
IERASE
tCPT
Supply current from DVCC during erase
2.7 V/ 3.6 V
3
5
mA
Cumulative program time
see Note 1
2.7 V/ 3.6 V
4
ms
tCMErase
Cumulative mass erase time
see Note 2
2.7 V/ 3.6 V
Program/Erase endurance
TJ = 25°C
200
104
ms
105
tRetention
Data retention duration
tWord
tBlock, 0
Word or byte program time
Block program time for 1st byte or word
tBlock, 1-63
tBlock, End
Block program time for each additional byte or word
tMass Erase
tSeg Erase
Mass erase time
5297
Segment erase time
4819
Block program end-sequence wait time
cycles
100
years
35
30
21
see Note 3
tFTG
6
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To
achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
JTAG Interface
TEST
CONDITIONS
PARAMETER
fTCK
TCK input frequency
see Note 1
RInternal
Internal pull-up resistance on TMS, TCK, TDI/TCLK
see Note 2
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC
MIN
2.2 V
0
3V
0
2.2 V/ 3 V
25
NOM
60
MAX
UNIT
5
MHz
10
MHz
90
kΩ
SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic
Port P1, P1.0 to P1.3, input/output with Schmitt-trigger
P1SEL.x
0
P1DIR.x
1
Direction Control
From Module
0
P1OUT.x
Pad Logic
P1.0 − P1.3
1
Module X OUT
P1IN.x
EN
Module X IN
P1IRQ.x
D
P1IE.x
P1IFG.x
Q
EN
Set
Interrupt
Flag
Interrupt
Edge
Select
P1IES.x
P1SEL.x
NOTE: x = Bit/identifier, 0 to 3 for port P1
PnSel.x
PnDIR.x
Direction
control from
module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
P1Sel.0
P1DIR.0
P1DIR.0
P1OUT.0
P1IN.0
P1IFG.0
P1IES.0
P1DIR.1
P1DIR.1
P1OUT.1
TACLK†
CCI0A†
P1IE.0
P1Sel.1
P1IE.1
P1IFG.1
P1IES.1
P1Sel.2
P1DIR.2
P1DIR.2
P1OUT.2
VSS
Out0 signal†
Out1 signal†
P1IE.2
P1IFG.2
P1IES.2
P1OUT.3
Out2 signal†
P1IN.3
CCI1A†
CCI2A†
P1IE.3
P1IFG.3
P1IES.3
P1Sel.3
P1DIR.3
P1DIR.3
† Signal from or to Timer_A
POST OFFICE BOX 655303
P1IN.1
P1IN.2
• DALLAS, TEXAS 75265
21
SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features
P1SEL.x
0
P1DIR.x
1
Direction Control
From Module
0
P1OUT.x
Pad Logic
P1.4−P1.7
1
Module X OUT
TST
Bus Keeper
P1IN.x
EN
Module X IN
D
TEST
TST
P1IRQ.x
P1IE.x
P1IFG.x
Q
EN
Set
Interrupt
Edge
Select
60 kΩ
Typical
Fuse
GND
Interrupt
Flag
Control By JTAG
P1IES.x
P1SEL.x
Fuse
Blow
TSTControl
NOTE: Fuse not implemented
in F11x
P1.x
TDO
Controlled By JTAG
P1.7/TDI/TDO
Controlled by JTAG
TDI
TST
P1.x
P1.6/TDI/TCLK
NOTE: The test pin should be protected from potential EMI
and ESD voltage spikes. This may require a smaller
external pulldown resistor in some applications.
TST
P1.x
TMS
P1.5/TMS
x = Bit identifier, 4 to 7 for port P1
During programming activity and during blowing
the fuse, the pin TDO/TDI is used to apply the test
input for JTAG circuitry.
TST
P1.x
TCK
P1.4/TCK
PnSel.x
PnDIR.x
Direction
control from
module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
P1Sel.4
P1DIR.4
P1DIR.4
P1OUT.4
unused
P1IE.4
P1IFG.4
P1IES.4
P1DIR.5
P1DIR.5
P1OUT.5
P1IN.5
unused
P1IE.5
P1IFG.5
P1IES.5
P1Sel.6
P1DIR.6
P1DIR.6
P1OUT.6
SMCLK
Out0 signal†
Out1 signal†
P1IN.4
P1Sel.5
P1IN.6
unused
P1IE.6
P1IFG.6
P1IES.6
P1OUT.7
Out2 signal†
P1IN.7
unused
P1IE.7
P1IFG.7
P1IES.7
P1Sel.7
P1DIR.7
P1DIR.7
† Signal from or to Timer_A
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
Port P2, P2.0 to P2.4, input/output with Schmitt-trigger
P2SEL.x
0
P2DIR.x
0: Input
1
Direction Control
From Module
1: Output
Pad Logic
0
P2OUT.x
P2.0 − P2.4
1
Module X OUT
P2IN.x
EN
D
Module X IN
P2IRQ.x
P2IE.x
P2IFG.x
Q
Interrupt
Edge
Select
EN
Set
Interrupt
Flag
P2IES.x
P2SEL.x
NOTE: x = Bit Identifier, 0 to 4 For Port P2
PnSel.x
PnDIR.x
Direction
control from
module
PnOUT.x
Module X
OUT
PnIN.x
Module X
IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.0
P2DIR.0
P2DIR.0
P2OUT.0
ACLK
P2IN.0
P2IFG.0
P1IES.0
P2DIR.1
P2DIR.1
P2OUT.1
P2IN.1
P2IE.1
P2IFG.1
P1IES.1
P2Sel.2
P2DIR.2
P2DIR.2
P2OUT.2
P2IN.2
P2IE.2
P2IFG.2
P1IES.2
P2Sel.3
P2DIR.3
P2DIR.3
P2OUT.3
VSS
Out0 signal†
Out1 signal†
unused
INCLK†
CCI0B†
P2IE.0
P2Sel.1
P2IN.3
CCI1B†
P2IE.3
P2IFG.3
P1IES.3
P2OUT.4
Out2 signal†
P2IN.4
unused
P2IE.4
P2IFG.4
P1IES.4
P2Sel.4
P2DIR.4
P2DIR.4
† Signal from or to Timer_A
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
Port P2, P2.5, input/output with Schmitt-trigger and ROSC function for the Basic Clock module
P2SEL.5
0: Input
1: Output
0
P2DIR.5
Pad Logic
1
Direction Control
From Module
0
P2OUT.5
P2.5
1
Module X OUT
Bus Keeper
P2IN.5
EN
Module X IN
P2IRQ.5
D
P2IE.5
P2IFG.5
Q
EN
Set
Interrupt
Flag
Internal to
Basic Clock
Module
0
VCC
Interrupt
Edge
Select
P2IES.5
1
DC
Generator
DCOR
P2SEL.5
CAPD.5
NOTE: DCOR: Control bit from basic clock module if it is set, P2.5 Is disconnected from P2.5 pad
PnSel.x
PnDIR.x
Direction
control from
module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.5
P2DIR.5
P2DIR.5
P2OUT.5
VSS
P2IN.5
unused
P2IE.5
P2IFG.5
P2IES.5
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
Port P2, unbonded bits P2.6 and P2.7
P2SEL.x
0: Input
1: Output
0
P2DIR.x
1
Direction Control
From Module
0
P2OUT.x
1
Module X OUT
P2IN.x
Node Is Reset With PUC
EN
Bus Keeper
Module X IN
P2IRQ.x
D
P2IE.x
P2IFG.x
EN
Q
Set
Interrupt
Flag
PUC
Interrupt
Edge
Select
P2IES.x
P2SEL.x
NOTE: x = Bit/identifier, 6 to 7 for port P2 without external pins
P2Sel.x
P2DIR.x
Direction
control from
module
P2OUT.x
Module X OUT
P2IN.x
Module X IN
P2IE.x
P2IFG.x
P2IES.x
P2Sel.6
P2DIR.6
P2DIR.6
P2OUT.6
unused
P2IE.6
P2IFG.6
P2IES.6
P2DIR.7
P2DIR.7
P2OUT.7
VSS
VSS
P2IN.6
P2Sel.7
P2IN.7
unused
P2IE.7
P2IFG.7
P2IES.7
NOTE: A good use of the unbonded bits 6 and 7 of port P2 is to use the interrupt flags. The interrupt flags can not be influenced from any signal
other than from software. They work then as a soft interrupt.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
SLAS256D − NOVEMBER 1999 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
JTAG fuse check mode
The JTAG protection fuse is not implemented in the MSP430F11x devices.
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
2-Nov-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
MSP430F110AIDW
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
MSP430F110AIDWR
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
MSP430F110AIPW
OBSOLETE
TSSOP
PW
20
TBD
Call TI
Call TI
MSP430F110AIPWR
OBSOLETE
TSSOP
PW
20
TBD
Call TI
Call TI
MSP430F110IDW
OBSOLETE
SOIC
DW
20
TBD
Call TI
Call TI
MSP430F110IDWR
OBSOLETE
SOIC
DW
20
Call TI
MSP430F110IPW
ACTIVE
TSSOP
PW
20
MSP430F110IPWR
OBSOLETE
TSSOP
PW
MSP430F112AIDW
OBSOLETE
SOIC
DW
MSP430F112AIPW
OBSOLETE
TSSOP
TBD
Call TI
Green (RoHS &
no Sb/Br)
CU NIPDAU
20
TBD
Call TI
Call TI
20
TBD
Call TI
Call TI
PW
20
TBD
Call TI
Call TI
Call TI
Call TI
MSP430F112IDW
OBSOLETE
SOIC
DW
20
MSP430F112IDWR
ACTIVE
SOIC
DW
20
MSP430F112IPW
ACTIVE
TSSOP
PW
20
MSP430F112IPWR
OBSOLETE
TSSOP
PW
20
70
TBD
2000 Green (RoHS &
no Sb/Br)
70
Level-1-260C-UNLIM
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Oct-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
MSP430F112IDWR
Package Package Pins
Type Drawing
SOIC
DW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
10.8
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.0
2.7
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Oct-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430F112IDWR
SOIC
DW
20
2000
346.0
346.0
41.0
Pack Materials-Page 2
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