Datasheet
Serial EEPROM Series Standard EEPROM
I2C BUS EEPROM (2-Wire)
BR24Gxxx-3A (128K 256K 1M)
General Description
BR24Gxxx-3A is a serial EEPROM of I2C BUS Interface Method
Features
Packages W(Typ) x D(Typ)x H(Max)
All controls available by 2 ports of serial clock(SCL) and
serial data(SDA)
Other devices than EEPROM can be connected to the
same port, saving microcontroller port
1.7V to 5.5V Single Power Source Operation most
suitable for battery use
1.7V to 5.5V wide limit of operating voltage, possible
1MHz operation
Page Write Mode useful for initial value write at factory
shipment
Self-timed Programming Cycle
Low Current Consumption
Prevention of Write Mistake
Write (Write Protect) Function added
Prevention of Write Mistake at Low Voltage
More than 1 million write cycles
More than 40 years data retention
Noise filter built in SCL / SDA terminal
Initial delivery state FFh
DIP-T8
TSSOP-B8
9.30mm x 6.50mm x 7.10mm
3.00mm x 6.40mm x 1.20mm
SOP8
TSSOP-B8J
5.00mm x 6.20mm x 1.71mm
3.00mm x 4.90mm x 1.10mm
SOP-J8
MSOP8
4.90mm x 6.00mm x 1.65mm
2.90mm x 4.00mm x 0.90mm
SSOP-B8
VSON008X2030
3.00mm x 6.40mm x 1.35mm
2.00mm x 3.00mm x 0.60mm
Figure 1.
Page Write
Number of Pages
64Byte
256Byte
Product Number
BR24G128-3A
BR24G256-3A
BR24G1M-3A
BR24G128-3A
Capacity
Bit Format
Type
Power Source
Voltage
BR24G128-3A
DIP-T8
BR24G128F-3A
SOP8
BR24G128FJ-3A
SOP-J8
BR24G128FV-3A
128kbit
Package
16k×8
SSOP-B8
1.7V to 5.5V
BR24G128FVT-3A
TSSOP-B8
BR24G128FVJ-3A
TSSOP-B8J
BR24G128FVM-3A
MSOP8
BR24G128NUX-3A
VSON008X2030
○ Product structure：Silicon monolithic integrated circuit ○This product has no designed protection against radioactive rays
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TSZ22111・14・001
BR24Gxxx-3A (128K 256K 1M)
BR24G256-3A
Capacity
Bit Format
256kbit
32k×8
Type
Power Source
Voltage
Package
BR24G256-3A
DIP-T8
BR24G256F-3A
SOP8
BR24G256FJ-3A
1.7V to 5.5V
SOP-J8
BR24G256FV-3A
SSOP-B8
BR24G256FVT-3A
TSSOP-B8
BR24G1M-3A
Capacity
Bit Format
Type
Power Source
Voltage
BR24G1M-3A
1Mbit
128k×8
BR24G1MF-3A
DIP-T8
1.7V to 5.5V
BR24G1MFJ-3A
.
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Package
SOP8
SOP-J8
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BR24Gxxx-3A (128K 256K 1M)
Absolute Maximum Ratings (Ta=25°C)
Parameter
Symbol
Rating
Unit
Vcc
-0.3 to +6.5
V
Supply Voltage
Power Dissipation
0.45 (SOP8)
Derate by 4.5mW/°C when operating above Ta=25°C
0.45 (SOP-J8)
Derate by 4.5mW/°C when operating above Ta=25°C
0.30 (SSOP-B8)
Derate by 3.0mW/°C when operating above Ta=25°C
0.33 (TSSOP-B8)
Pd
Remark
Derate by 3.3mW/°C when operating above Ta=25°C
W
0.31 (TSSOP-B8J)
Derate by 3.1mW/°C when operating above Ta=25°C
0.31 (MSOP8)
Derate by 3.1mW/°C when operating above Ta=25°C
0.30 (VSON008X2030)
Derate by 3.0mW/°C when operating above Ta=25°C
0.80 (DIP-T8)
Derate by 8.0mW/°C when operating above Ta=25°C
Storage Temperature
Tstg
-65 to +150
°C
Operating Temperature
Topr
-40 to +85
°C
‐
-0.3 to Vcc+1.0
V
The Max value of Input Voltage/Output Voltage is not over 6.5V.
When the pulse width is 50ns or less, the Min value Input
Voltage/Output Voltage is not lower than -1.0V.
Tjmax
150
°C
Junction temperature at the storage condition
VESD
-4000 to +4000
V
Input Voltage /
Output Voltage
Junction
Temperature
Electrostatic discharge
voltage
(human body model)
Memory Cell Characteristics (Ta=25°C, Vcc=1.7V to 5.5V)
Parameter
Min
1,000,000
40
Write Cycles (1)
Data Retention (1)
Limit
Typ
-
Max
-
Unit
Times
Years
(1) Not 100% TESTED
Recommended Operating Ratings
Parameter
Power Source Voltage
Input Voltage
Symbol
Vcc
VIN
Rating
1.7 to 5.5
0 to Vcc
Unit
V
DC Characteristics (Unless otherwise specified, Ta=-40°C to +85°C, Vcc =1.7V to 5.5V)
Parameter
Symbol
Limit
Min
Typ
Max
Unit
Input High Voltage 1
VIH1
0.7Vcc
-
Vcc+1.0
V
Input Low Voltage 1
VIL1
-0.3(2)
-
+0.3Vcc
V
Output Low Voltage 1
VOL1
-
-
0.4
V
Output Low Voltage 2
VOL2
-
-
0.2
V
Input Leakage Current
ILI
-1
-
+1
μA
Output Leakage Current
ILO
-1
-
+1
μA
-
-
2.5
Supply Current (Write)
Supply Current (Read)
Standby Current
ICC1
ICC2
mA
-
-
4.5
-
-
2.0
-
-
2.0
mA
μA
ISB
-
-
3.0
Conditions
IOL=3.0mA,
2.5V≦Vcc≦5.5V (SDA)
IOL=0.7mA,
1.7V≦Vcc＜2.5V (SDA)
VIN=0 to Vcc
VOUT=0 to Vcc (SDA)
VCC=5.5V, fSCL=1MHz, tWR=5ms,
Byte write, Page write
BR24G128/256-3A
VCC=5.5V, fSCL=1MHz, tWR=5ms,
Byte write, Page write
BR24G1M-3A
VCC=5.5V, fSCL=1MHz
Random read, current read,
sequential read
VCC=5.5V, SDA・SCL=Vcc
A0, A1, A2=GND, WP=GND
BR24G128/256-3A
VCC=5.5V, SDA・SCL=Vcc
A0, A1, A2=GND, WP=GND
BR24G1M-3A
(2) When the pulse width is 50ns or less, it is -1.0V.
.
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BR24Gxxx-3A (128K 256K 1M)
AC Characteristics (Unless otherwise specified, Ta=-40°C to +85°C, Vcc=1.7V to 5.5V)
Parameter
Symbol
Limit
Min
Typ
Max
Unit
Clock Frequency
fSCL
-
-
1000
kHz
Data Clock “HIGH“ Period
tHIGH
0.30
-
-
µs
Data Clock “LOW“ Period
tLOW
0.5
-
-
µs
tR
-
-
0.12
µs
tF1
-
-
0.12
µs
tF2
-
-
0.12
µs
tHD:STA
0.25
-
-
µs
Start Condition Setup Time
tSU:STA
0.20
-
-
µs
Input Data Hold Time
tHD:DAT
0
-
-
ns
Input Data Setup Time
SDA, SCL (INPUT) Rise Time (1)
SDA, SCL (INPUT) Fall Time
(1)
SDA (OUTPUT) Fall Time (1)
Start Condition Hold Time
tSU:DAT
50
-
-
ns
Output Data Delay Time
tPD
0.05
-
0.45
µs
Output Data Dold Time
tDH
0.05
-
-
µs
Stop Condition Setup Time
tSU:STO
0.25
-
-
µs
Bus Free Time
tBUF
0.5
-
-
µs
Write Cycle Time
tWR
-
-
5
ms
tI
-
-
0.05
µs
tHD:WP
1.0
-
-
µs
WP Setup Time
tSU:WP
0.1
-
-
µs
WP High Period
tHIGH:WP
1.0
-
-
µs
Noise Spike Width (SDA, SCL)
WP Hold Time
(1) Not 100% tested
AC Characteristics Condition
Parameter
Symbol
Conditions
Unit
CL
100
pF
SDA, SCL (INPUT) Rise Time
tR
20
ns
SDA, SCL (INPUT) Fall Time
tF1
20
ns
VIL1/VIH1
0.2VCC/0.8Vcc
V
-
0.3VCC/0.7Vcc
V
Load Capacitance
Input Data Level
Input/Output Data Timing Reference Level
.
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BR24Gxxx-3A (128K 256K 1M)
Serial Input / Output Timing
tR
SCL
tF1
70%
70% 70%
70%
30%
30%
tHD:DAT
tSU:DAT
70%
70%
30%
30%
tLOW
tHD:STA
70%
tHIGH
70%
70%
30%
30%
SDA
(入力)
(INPUT)
tDH
tPD
tBUF
70%
70%
SDA
30%
(出力)
(OUTPUT)
30%
30%
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
tF2
Figure 2-(a). Serial Input / Output Timing
70%
70%
70%
tSU:STA
tHD:STA
tSU:STO
70%
30%
30%
STOP CONDITION
START CONDITION
Figure 2-(b). Start-Stop Bit Timing
D0
70%
70%
ACK
write data
(n-th address)
tWR
STOP CONDITION
START CONDITION
Figure 2-(c). Write Cycle Timing
70%
DATA(n)
DATA(1)
D0
D1
70%
ACK
ACK
tWR
30%
30%
tSU:WP
tHD:WP
STOP CONDITION
Figure 2-(d). WP Timing at Write Execution
DATA(n)
DATA(1)
D1
D0
ACK
ACK
tWR
tHIGH:WP
70%
70%
70%
Figure 2-(e). WP Timing at Write Cancel
.
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BR24Gxxx-3A (128K 256K 1M)
Block Diagram
(2)
A0
1
128Kbit, 256Kbit, 1Mbit
EEPROM
Array
8
VCC
7
WP
6
SCL
5
SDA
8bit
A1
(1)14biit
Address
Decoder
2
Word
Address Register
15biit
17biit
START
A2 3
Data
Register
STOP
Control Circuit
ACK
GND 4
High Voltage
Generating Circuit
(1)
Power Source
Voltage Detection
14bit: BR24G128-3A
15bit: BR24G256-3A
17bit: BR24G1M-3A
(2)
A0= Don't use : BR24G1M-3A
Figure 3. Block Diagram
Pin Configuration
(TOP VIEW)
A0
1
8 VCC
A1
2 BR24G128-3A
1
BR24G256-3A
BR24G1M-3A
3
7
4
5 SDA
1
A2
1
1
GND
1
1
WP
6 SCL
1
1
Pin Descriptions
Descriptions
Terminal
Name
Input/
Output
A0
Input
Slave address setting(2)
A1
Input
Slave address setting(2)
A2
Input
Slave address setting(2)
GND
-
SDA
Input/
Output
SCL
Input
Serial clock input
WP
Input
Write protect terminal
VCC
-
BR24G128/256-3A
BR24G1M-3A
Don’t use(1)
Reference voltage of all input / output, 0V
Serial data input serial data output
Connect the power source.
(1) Pins not used as device address may be set to any of ‘H’, 'L', and 'Hi-Z'.
(2) A0, A1 and A2 are not allowed to use as open
.
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BR24Gxxx-3A (128K 256K 1M)
Typical Performance Curves
6
6
5
Ta=-40℃
Ta= 25℃
Input Low Voltage1 : VIL1(V)
Input High Voltage1 : VIH1(V)
5
Ta= 85℃
4
3
SPEC
2
3
2
1
1
0
0
0
1
2
3
4
5
Ta=-40℃
Ta= 25℃
Ta= 85℃
4
SPEC
0
6
1
3
4
5
6
Supply Voltage : Vcc(V)
Supply Voltage : Vcc(V)
Figure 4. Input High Voltage1 vs Supply Voltage
(A0, A1, A2, SCL, SDA, WP)
Figure 5. Input Low Voltage1 vs Supply Voltage
(A0, A1, A2, SCL, SDA, WP)
1
1
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.8
Output Low Voltage2 : VOL2(V)
Output Low Voltage1 : VOL1(V)
2
0.6
0.4
SPEC
0.2
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.8
0.6
SPEC
0.4
0.2
0
0
0
1
2
3
4
5
0
6
2
3
4
5
6
Output Low Current : IOL(mA)
Output Low Current : IOL(mA)
Figure 7. Output Low Voltage2 vs Output Low Current
(Vcc=1.7V)
Figure 6. Output Low Voltage1 vs Output Low Current
(Vcc=2.5V)
.
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BR24Gxxx-3A (128K 256K 1M)
Typical Performance Curves‐continued
1.2
SPEC
1
Output Leakage Current : ILO(µA)
Input Leakage Current : I LI (µA)
1.2
Ta=-40℃
Ta= 25℃
0.8
Ta= 85℃
0.6
0.4
0.2
0.8
Ta=-40℃
Ta= 25℃
0.6
Ta= 85℃
0.4
0.2
0
0
0
1
2
3
4
5
0
6
1
2
3
4
5
6
Supply Voltage : Vcc(V)
Supply Voltage: Vcc(V)
Figure 8. Input Leakage Current vs Supply Voltage
(A0, A1, A2, SCL, WP)
Figure 9. Output Leakage Current vs Supply Voltage
(SDA)
6
3
SPEC
2.5
Supply Current (Write) : Icc1(mA)
Supply Current (Write) : Icc1(mA)
SPEC
1
Ta=-40℃
Ta= 25℃
Ta= 85℃
2
1.5
1
0.5
0
SPEC
5
4
Ta=-40℃
Ta= 25℃
Ta= 85℃
3
2
1
0
0
1
2
3
4
5
0
6
2
3
4
5
Supply Voltage : Vcc(V)
Supply Voltage : Vcc(V)
Figure 10. Supply Current (Write) vs Supply Voltage
(fSCL=1MHz BR24G128/256-3A)
.
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Figure 11. Supply Current (Write) vs Supply Voltage
(fSCL=1MHz BR24G1M-3A)
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6
BR24Gxxx-3A (128K 256K 1M)
Typical Performance Curves‐continued
2.5
2.5
SPEC
2
2
Standby Current : I SB (µA)
Supply Current (Read) : ICC2(mA)
SPEC
Ta=-40℃
Ta= 25℃
Ta= 85℃
1.5
1
0.5
Ta=-40℃
Ta= 25℃
Ta= 85℃
1.5
1
0.5
0
0
0
1
2
3
4
5
0
6
1
2
3
4
5
6
Supply Voltage : Vcc(V)
Supply Voltage : Vcc(V)
Figure 12. Supply Current (Read) vs Supply Voltage
(fscl=1MHz)
Figure 13. Standby Current vs Supply Voltage
(BR24G128/256-3A)
10000
3.5
SPEC
2.5
Clock Frequency : fscl(kHz)
Standby Current : I SB (µA)
3
Ta=-40℃
Ta= 25℃
Ta= 85℃
2
1.5
1
1000
SPEC
100
Ta=-40℃
Ta= 25℃
Ta= 85℃
10
1
0.5
0
0.1
0
1
2
3
4
5
6
0
Supply Voltage : Vcc(V)
2
3
4
5
6
Supply Voltage : Vcc(V)
Figure 14. Standby Current vs Supply Voltage
(BR24G1M-3A)
.
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Figure 15. Clock Frequency vs Supply Voltage
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BR24Gxxx-3A (128K 256K 1M)
Typical Performance Curves‐continued
0.4
0.6
Data Clock Low Period : t LOW (µs)
Data Clock High Period : tHIGH(µs)
SPEC
SPEC
0.3
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.2
0.1
0
0.5
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
0
6
1
Supply Voltage : Vcc(V)
3
4
5
6
Supply Voltage : Vcc(V)
Figure 16. Data Clock High Period vs Supply Voltage
Figure 17. Data Clock Low Period vs Supply Voltage
0.3
0.14
Start Condition Hold Time : tHD:STA(µs)
SPEC
SDA (OUTPUT) Fall Time : tF 2(µs)
2
0.12
0.1
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.08
0.06
0.04
0.02
SPEC
0.25
0.2
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.15
0.1
0.05
0
0
0
1
2
3
4
5
6
1
2
3
4
5
6
Supply Voltage : Vcc(V)
Supply Voltage : Vcc(V)
Figure18. SDA (OUTPUT) Fall Time vs Supply Voltage
.
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Figure 19. Start Condition Hold Time vs Supply Voltage
TSZ02201-0R2R0G100020-1-2
18.Jun.2015 Rev.006
BR24Gxxx-3A (128K 256K 1M)
Typical Performance Curves‐continued
50
SPEC
Input Data Hold Time : tHD:DAT (ns)
Start Condition Setup Time : tSU:STA(µs)
0.3
0.25
0.2
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.15
0.1
0.05
SPEC
0
-50
Ta=-40℃
Ta= 25℃
Ta= 85℃
-100
-150
0
0
1
2
3
4
5
0
6
1
2
3
4
5
6
Supply Voltage : Vcc(V)
Supply Voltage : Vcc(V)
Figure 21. Input Data Hold Time vs Supply Voltage
(HIGH)
Figure 20. Start Condition Setup Time vs Supply Voltage
50
60
Input Data Setup Time : tSU:DAT(ns)
Input Data Hold Time : tHD:DAT(ns)
SPEC
SPEC
0
-50
Ta=-40℃
Ta= 25℃
Ta= 85℃
-100
-150
50
Ta=-40℃
Ta= 25℃
Ta= 85℃
40
30
20
10
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Supply Voltage : Vcc(V)
Supply Voltage : Vcc(V)
Figure 22. Input Data Hold Time vs Supply Voltage
(LOW)
Figure 23 Input Data Setup Time vs Supply Voltage
(HIGH)
.
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TSZ02201-0R2R0G100020-1-2
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BR24Gxxx-3A (128K 256K 1M)
Typical Performance Curves‐continued
0.5
60
SPEC
50
Output Data Delay Time : tPD0(µs)
Input Data Setup Time : t SU:DAT(ns)
SPEC
40
Ta=-40℃
Ta= 25℃
Ta= 85℃
30
20
10
0.4
0.3
0.2
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.1
SPEC
0
0
0
1
2
3
4
5
0
6
1
2
6
0.3
SPEC
Stop Condition Setup Time : t SU:STO(µs)
Output Data Delay Time : tPD1(µs)
5
Figure 25. Output Data Delay Time vs Supply Voltage
Figure 24. Input Data Setup Time vs Supply Voltage
(LOW)
0.4
0.3
0.2
4
Supply Voltage : Vcc(V)
Supply Voltage : Vcc(V)
0.5
3
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.1
SPEC
0
SPEC
0.25
0.2
0.15
0.1
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.05
0
0
1
2
3
4
5
6
Supply Voltage : Vcc(V)
1
2
3
4
5
6
Supply Voltage : Vcc(V)
Figure 26. Output Data Delay Time vs Supply Voltage
.
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Figure 27. Stop Condition Setup Time vs Supply Voltage
TSZ02201-0R2R0G100020-1-2
18.Jun.2015 Rev.006
BR24Gxxx-3A (128K 256K 1M)
Typical Performance Curves‐continued
6
0.6
SPEC
Write Cycle Time : tWR(ms)
Bus Free Time : t BUF(µs)
SPEC
5
0.5
0.4
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.3
0.2
4
3
2
0.1
1
0
0
0
1
2
3
4
5
6
Ta=-40℃
Ta= 25℃
Ta= 85℃
0
1
2
Supply Voltage : Vcc(v)
4
5
6
Supply Voltage : Vcc(v)
Figure 29. Write Cycle Time vs Supply Voltage
Figure 28. Bus Free Time vs Supply Voltage
0.3
0.3
Noise Spike Width(SCL LOW) : tI(µs)
Noise Spike Width(SCL HIGH) : tI(µs)
3
0.25
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.2
0.15
0.1
0.05
SPEC
0
0.25
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.2
0.15
0.1
0.05
SPEC
0
0
1
2
3
4
5
6
Supply Voltage : Vcc(V)
1
2
3
4
5
6
Supply Voltage : Vcc(V)
Figure 30. Noise Spike Width vs Supply Voltage
(SCL HIGH)
.
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Figure 31. Noise Spike Width vs Supply Voltage
(SCL LOW)
TSZ02201-0R2R0G100020-1-2
18.Jun.2015 Rev.006
BR24Gxxx-3A (128K 256K 1M)
Typical Performance Curves‐continued
0.3
Noise Spike Width(SDA LOW) : tI(µs)
Noise Spike Width(SDA HIGH) : tI(µs)
0.3
0.25
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.2
0.15
0.1
0.05
SPEC
0.25
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.2
0.15
0.1
0.05
SPEC
0
0
0
1
2
3
4
5
0
6
1
2
3
4
5
6
Supply Voltage : Vcc(V)
Supply Voltage : Vcc(V)
Figure 33. Noise Spike Width vs Supply Voltage
(SDA LOW)
Figure 32. Noise Spike Width vs Supply Voltage
(SDA HIGH)
1.2
0.2
SPEC
SPEC
WP Setup Time : t SU:WP(µs)
WP Hold Time : tHD:WP(µs)
1
0.8
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.6
0.4
0.2
0.1
Ta=-40℃
Ta= 25℃
Ta= 85℃
0
-0.1
-0.2
-0.3
0
0
1
2
3
4
5
6
1
2
3
4
5
6
Supply Voltage : Vcc(V)
Supply Voltage : Vcc(V)
Figure 35. WP Setup Time vs Supply Voltage
Figure 34. WP Hold Time vs Supply Voltage
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BR24Gxxx-3A (128K 256K 1M)
Typical Performance Curves‐continued
1.2
WP High Period : tHIGH:WP ( µs)
SPEC
1
0.8
Ta=-40℃
Ta= 25℃
Ta= 85℃
0.6
0.4
0.2
0
0
1
2
3
4
5
6
Supply Voltage : Vcc(V)
Figure 36. WP High Period vs Supply Voltage
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BR24Gxxx-3A (128K 256K 1M)
Timing Chart
1.
I2C BUS Data Communication
I2C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
and acknowledge is always required after each byte. I2C BUS data communication with several devices is possible by
connecting with 2 communication lines: serial data (SDA) and serial clock (SCL).
Among the devices, there should be a “master” that generates clock and control communication start and end. The rest
become “slave” which are controlled by an address peculiar to each device, like this EEPROM. The device that outputs
data to the bus during data communication is called “transmitter”, and the device that receives data is called “receiver”..
SDA
1-7
SCL
S
START ADDRESS
condition
1-7
8
9
R/W
ACK
8
DATA
1-7
9
ACK
8
DATA
9
ACK
Figure 37. Data Transfer Timing
P
STOP
condition
2.
Start Condition (Start Bit Recognition)
(1) Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when
SCL is 'HIGH' is necessary.
(2) This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this
condition is satisfied, any command cannot be executed.
3.
Stop Condition (Stop Bit Recognition)
(1) Each command can be ended by a stop condition (stop bit) where SDA goes from 'LOW' to 'HIGH' while SCL is
'HIGH'.
4.
Acknowledge (ACK) Signal
(1) This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not.
In master-slave communication, the device (Ex. µ-COM sends slave address input for write or read command to
this IC) at the transmitter (sending) side releases the bus after output of 8bit data.
(2) The device (Ex. This IC receives the slave address input for write or read command from the µ-COM) at the
receiver (receiving) side sets SDA 'LOW' during 9th clock cycle, and outputs acknowledge signal (ACK signal)
showing that it has received the 8bit data.
(3) This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal)
'LOW'.
(4) After receiving 8bit data (word address and write data) during each write operation, this IC outputs acknowledge
signal (ACK signal) 'LOW'.
(5) During read operation, this IC outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'.
When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (µ-COM) side,
this IC continues to output data. When acknowledge signal (ACK signal) is not detected, this IC stops data
transfer, and recognizes stop condition (stop bit), and ends read operation. Then this IC becomes ready for
another transmission.
5.
Device Addressing
(1) Slave address comes after start condition from master.
(2) The significant 4 bits of slave address are used for recognizing a device type.
The device code of this IC is fixed to '1010'.
(3) Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a
same bus according to the number of device addresses.
(4) The most insignificant bit (R/W --- READ/WRITE) of slave address is used for designating write or read action,
and is as shown below.
――
Setting R / W to 0 ------- write (setting 0 to word address setting of random read)
Setting R / W to 1 ------- read
――
Type
BR24G128-3A, BR24G256-3A,
BR24G1M-3A
Maximum number of
Connected buses
Slave address
1
1
――
0 1 0 A2 A1 A0 R/W
――
0 1 0 A2 A1 P0 R/W
8
4
P0 is page select bit.
.
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BR24Gxxx-3A (128K 256K 1M)
Write Command
1.
Write Cycle
(1) Arbitrary data can be written to EEPROM. When writing only 1 byte, Byte Write is normally used, and when
writing continuous data of 2 bytes or more, simultaneous write is possible by Page Write cycle. The maximum
number of write bytes is specified per device of each capacity.
Up to 256 arbitrary bytes can be written.（In the case of BR24G1M-3A）
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
1st WORD
ADDRESS
R A
/ C
W K
WA
0
(1)
S
T
O
P
DATA
WAWA
15 14
1 0 1 0 A2 A1 A0
Note)
2nd WORD
ADDRESS
A
C
K
D7
(1)
As for WA14, BR24G128-3A becomes don't care.
As for WA15, BR24G128/256-3A becomes don't care.
(1)
As for WA14, BR24G128-3A becomes don't care.
As for WA15, BR24G128/256-3A becomes don't care.
(2)
As for BR24G128/256-3A becomes (n+63)
As for BR24G1M-3A becomes (n+255)
D0
A
C
K
A
C
K
Figure 38. Byte Write Cycle
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
1 0 1
0
0
W
R
I
T
E
A2 A1 A0
1st WORD
ADDRESS(n)
2nd WORD
ADDRESS(n)
DATA(n)
WA WA
WA
15 14
0
D7
D0
D0
0
Note )
R A
/ C
W K
(1)
A
C
K
A
C
K
S
T
O
P
(2)
DATA(n+63)
A
C
K
A
C
K
Figure 39. Page Write Cycle
Note)
(1)
1 0 1 0 A2A1A0
(1)
In BR24G1M-3A A0 becomes P0.
Figure 40. Difference of Slave Address of Each Type
(2) During internal write execution, all input commands are ignored, therefore ACK is not returned.
(3) Data is written to the address designated by word address (n-th address)
(4) By issuing stop bit after 8bit data input, internal write to memory cell starts.
(5) When internal write is started, command is not accepted for tWR (5ms at maximum).
(6) Using page write cycle, writing in bulk is done as follows:
Up to 64Byte (BR24G128-3A, BR24G256-3A）
Up to 256Byte (BR24G1M-3A）
The bytes in excess overwrite the data already sent first.
(Refer to "Internal Address Increment")
(7) As for page write cycle of BR24G128-3A and BR24G256-3A, where 2 or more bytes of data is intended to be
written, after the 8 significant bits (BR24G128-3A) or 9 significant bits (BR24G256-3A) of word address are
designated arbitrarily, only the value of 6 least significant bits in the address is incremented internally, so that data
up to 64 bytes of memory only can be written.
(8) As for page write cycle of BR24G1M-3A, where 2 or more bytes of data is intended to be written, after the page
select bit ‘P0’ of slave, and the 8 significant bits of word address are designated arbitrarily, only the value of 8
least significant bits in the address is incremented internally, so that data up to 256 bytes of memory only can be
written
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BR24Gxxx-3A (128K 256K 1M)
2.
Notes on Write Cycle Continuous Input
List of numbers of page write
Number of
64Byte
256Byte
Pages
Product
BR24G128-3A
BR24G1M-3A
number
BR24G256-3A
The above numbers are maximum bytes for respective types.
Any bytes below these can be written.
In the case BR24G256-3A, 1 page=64bytes, but the page
write cycle time is 5ms at maximum for 64byte bulk write.
It does not stand 5ms at maximum × 64byte=320ms(Max)
3. Internal Address Increment
Page write mode (in the case of BR24G128-3A）
3Eh
0
0
0
WA7
WA6
WA5
WA4
WA3
WA2
WA1
WA0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
0
1
0
Increment
For example, when it is started from address 3Eh,
then, increment is made as below,
3Eh→3Fh→00h→01h･･･ please take note.
※3Eh･･･3E in hexadecimal, therefore, 00111110 becomes a
binary number.
Significant bit is fixed.
No digit up
4.
Write Protect (WP) Terminal
Write protect (WP) function
When WP terminal is set at Vcc (H level), data rewrite of all addresses is prohibited. When it is set GND (L level), data
rewrite of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do
not leave it open.
In case of using it as ROM, it is recommended to connect it to pull up or Vcc. At extremely low voltage at power
ON/OFF, by setting the WP terminal ‘H’, write error can be prevented.
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BR24Gxxx-3A (128K 256K 1M)
Read Command
1. Read Cycle
Read cycle is when data of EEPROM is read. Read cycle could be random read cycle or current read cycle. Random
read cycle is a command to read data by designating a specific address, and is used generally. Current read cycle is a
command to read data of internal address register without designating an address, and is used when to verify just after
write cycle. In both the read cycles, sequential read cycle is available where the next address data can be read in
succession.
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
2nd WORD
ADDRESS（ｎ）
R A
/ C
W K
A
C
K
(1)
R
E
A
D
SLAVE
ADDRESS
S
T
O
P
DATA(n)
(1)
WA
0
WAWA
15 14
1 0 1 0 A2A1A0
Note)
1st WORD
ADDRESS（ｎ）
S
T
A
R
T
1 0 1 0 A2 A1A0
A
C
K
D7
D0
R A
/ C
W K
As for WA14, BR24G128-3A become don’t care.
As for WA15, BR24G128/256-3A become don’t care.
A
C
K
Figure 41. Random Read Cycle
S
T
A
R
T
R
E
A
D
SLAVE
ADDRESS
SDA
LINE
S
T
O
P
DATA(n)
1 0 1 0 A2A1A0
D7
D0
A
C
K
R A
/ C
WK
Note)
Figure 42. Current Read Cycle
S
T
A
R
T
SDA
LINE
R
E
A
D
SLAVE
ADDRESS
1 0 1 0 A2 A1A0
DATA(n)
D7
D0
R A
/ C
W K
Note）
S
T
O
P
DATA(n+x)
D7
A
C
K
D0
A
C
K
A
C
K
Figure 43. Sequential Read Cycle (in the case of current read cycle)
(1) In random read cycle, data of designated word address can be read.
(2) When the command just before current read cycle is random read cycle, current read cycle (each including
sequential read cycle), data of incremented last read address (n)-th, i.e., data of the (n+1)-th address is output.
(3) When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (μ-COM) side, the next
address data can be read in succession.
(4) Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal goes from ‘L’ to
‘H’ while at SCL signal is ‘H’.
(5) When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. To end read command cycle, be sure to input 'H' to ACK signal
after D0, and the stop condition where SDA goes from ‘L’ to ‘H’ while SCL signal is 'H'.
(6) Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is asserted
from ‘L’ to ‘H’ while SCL signal is 'H'.
Note)
(1)
A2
A1
A0
1 0 1 0
(1)
In BR24G1M-3A, A0 becomes P0.
Figure 44. Difference of Slave Address of Each Type
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BR24Gxxx-3A (128K 256K 1M)
Software Reset
Software reset is executed to avoid malfunction after power ON, and during command input. Software reset has several
kinds, and 3 kinds of them are shown in the figure below. (Refer to Figure 45-(a), Figure 45-(b), Figure 45-(c)) Within the
dummy clock input area, the SDA bus is released ('H' by pull up) and ACK output and read data '0' (both 'L' level) may be
output from EEPROM. Therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to
instantaneous power failure of system power source or influence upon devices.
Dummy clock×14
SCL
1
2
Start×2
13
Normal command
14
SDA
Normal command
Figure 45-(a). The Case of Dummy Clock × 14 +START+START+ Command Input
SCL
Start
Dummy clock×9
Start
1
2
8
Normal command
9
SDA
Normal command
Figure 45-(b). The Case of START + Dummy Clock × 9 +START+ Command Input
Start×9
SCL
1
2
3
7
8
Normal command
9
SDA
Normal command
SD
Figure 45-(c). START×9+ Command Input
タ
ト
※Start
command from START input.
Acknowledge Polling
During internal write execution, all input commands are ignored, therefore ACK is not returned. During internal automatic
write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then
it means end of write operation, else 'H' is returned, which means writing is still in progress. By the use of acknowledge
polling, next command can be executed without waiting for tWR = 5ms.
To write continuously, R/W = 0, then to carry out current read cycle after write, slave address with R/W = 1 is sent, and if
ACK signal sends back 'L', then execute word address input and data output and so forth.
During internal write,
ACK = HIGH is returned.
First write command
S
T
A
R
T
Write command
S
T
O
P
S
T Slave
A
R address
T
A
C
K
H
tWR
S
T Slave
A
R address
T
A
C
K
H
…
Second write command
…
S
T Slave
A
R address
T
tWR
A
C
K
H
S
T Slave
A
R address
T
A
C
K
L
Word
address
A
C
K
L
Data
A
C
K
L
S
T
O
P
After completion of internal write,
ACK=LOW is returned, so input next
word address and data in succession.
Figure 46. Case to Continuous Write by Acknowledge Polling
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WP Valid Timing (Write Cancel)
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so on, pay attention to the following WP valid
timing. During write cycle execution, inside cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte
write cycle and page write cycle, the area from the first start condition of command to the rise of clock to take in D0 of data(in
page write cycle, the first byte data) is the cancel invalid area.
WP input in this area becomes ‘Don't care’. The area from the rise of SCL to take in D0 to the stop condition input is the
cancel valid area. Furthermore, after the execution of forced end by WP, the IC enters standby status..
・Rise of SDA
・Rise of D0 taken clock
SCL
SDA
SCL
D1
D0
ACK
SDA
S
T Slave
A
R address
T
A
C Word
K address
L
ACK
Enlarged view
Enlarged view
SDA
D0
A
C D7 D6 D5 D4 D3 D2 D1 D0
K
L
WP cancel invalid area
A
C
K
L
Data
A
C
K
L
S
T
O
P
WP cancel valid area
tWR
WP cancel invalid area
WP
Data is not written.
Figure 47. WP Valid Timing
Command Cancel by Start Condition and Stop Condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Figure
48.) However, within ACK output area and during data read, SDA bus may output 'L'. In this case, start condition and stop
condition cannot be input, so reset is not available. Therefore, execute software reset. When command is cancelled by
start-stop condition during random read cycle, sequential read cycle, or current read cycle, internal setting address is not
determined. Therefore, it is not possible to carry out current read cycle in succession. To carry out read cycle in succession,
carry out random read cycle.
SCL
SDA
1
0
1
0
Start condition
Stop condition
Figure 48. Case of Cancel by Start, Stop Condition during Slave Address Input
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I/O Peripheral Circuit
1.
Pull Up Resistance of SDA Terminal
SDA is NMOS open drain, so it requires a pull up resistor. As for this resistor value (RPU), select an appropriate value
from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, operating frequency is limited. The
smaller the RPU, the larger is the supply current (Read).
2.
Maximum Value of RPU
The maximum value of RPU is determined by the following factors.
(1)SDA rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA should be tR or lower.
Furthermore, AC timing should be satisfied even when SDA rise time is late.
(2)The bus electric potential A to be determined by input leak total (IL) of device connected to bus at output of 'H' to
SDA bus and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including
recommended noise margin of 0.2VCC.
VCC-ILRPU-0.2 VCC ≧ VIH
∴
Ex.) VCC =3V
From (2)
RPU ≦
0.8VCC－VIH
IL
IL=10μA VIH=0.7 VCC
Microcontroller
RPU ≦
BR24GXX
RPU
0.8×3－0.7×3
10×10-6
IL
≦ 300 [kΩ]
3.
SDA terminal
A
IL
Bus line
capacity
CBUS
Figure 49. I/O Circuit Diagram
Minimum Value of RPU
The minimum value of RPU is determined by the following factors.
(1) When IC outputs LOW, it should be satisfied that VOLMAX=0.4V and IOLMAX=3mA.
VCC－VOL
≦ IOL
RPU
∴ RPU ≧
VCC－VOL
IOL
(2) VOLMAX=0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended
noise margin 0.1VCC.
VOLMAX ≦ VIL-0.1 VCC
Ex.) VCC =3V, VOL=0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3VCC
from (1)
RPU
≧
3－0.4
3×10 -3
≧ 867 [Ω]
VOL=0.4 [V]
VIL=0.3×3
=0.9 [V]
Therefore, the condition (2) is satisfied.
And
4.
Pull Up Resistance of SCL Terminal
When SCL control is made at the CMOS output port, there is no need for a pull up resistor. But when there is a time
where SCL becomes 'Hi-Z', add a pull up resistor. As for the pull up resistor value, one of several kΩ to several ten kΩ is
recommended in consideration of drive performance of output port of microcontroller.
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Cautions on Microcontroller Connection
1.
RS
In I2C BUS, it is recommended that SDA port is of open drain input/output. However, when using CMOS input / output of
tri state to SDA port, insert a series resistance RS between the pull up resistor RPU and the SDA terminal of EEPROM.
This is to control over current that may occur when PMOS of the microcontroller and NMOS of EEPROM are turned ON
simultaneously. RS also plays the role of protecting the SDA terminal against surge. Therefore, even when SDA port is
open drain input/output, RS can be used.
ACK
SCL
RPU
RS
SDA
'H' output of microcontroller
'L' output of EEPROM
Microcontroller
Over current flows to SDA line by 'H'
output of microcontroller and 'L'
output of EEPROM.
EEPROM
Figure 50. I/O Circuit Diagram
2.
Figure 51. Input / Output Collision Timing
Maximum Value of RS
The maximum value of RS is determined by the following relations.
(1) SDA rise time to be determined by the capacitance (CBUS) of bus line and RPU of SDA should be tR or lower.
Furthermore, AC timing should be satisfied even when SDA rise time is slow.
(2) The bus electric potential A to be determined by RPU and RS the moment when EEPROM outputs 'L' to SDA bus
should sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin of 0.1VCC.
(V CC － VOL )×R S
RPU +R S
VCC
RPU A
RS
VOL
∴
RS
VOL +0.1V CC ≦ VIL
+
VIL－V OL － 0.1V CC
1.1V CC -V IL
≦
×
RPU
IOL
Ex. ）VCC =3V V IL=0.3V CC VOL =0.4V R PU =20k Ω
Bus line
capacity
CBUS
VIL
RS
EEPROM
Micro controller
Figure 52. I/O Circuit Diagram
3.
≦
0.3×3 － 0.4 － 0.1×3
1.1×3 － 0.3×3
×
20×10
3
≦ 1.67 [kΩ]
Minimum Value of RS
The minimum value of RS is determined by over current at bus collision. When over current flows, noises in power
source line and instantaneous power failure of power source may occur. When allowable over current is defined as I,
the following relation must be satisfied. Determine the allowable current in consideration of the impedance of power
source line in set and so forth. Set the over current to EEPROM to 10mA or lower.
RPU
VCC
≦
RS
'L'output
RS
∴ RS ≧
I
VCC
I
Over current I
Ex.) Vcc=3V, I=10mA
'H' output
RS
Microcontroller
3
-3
10×10
EEPROM
≧ 300 [Ω]
Figure 53. I/O Circuit Diagram
.
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© 2014 ROHM Co., Ltd. All rights reserved.
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BR24Gxxx-3A (128K 256K 1M)
I/O Equivalence Circuit
1. Input (A0, A1, A2, SCL, WP)
2.
Input / Output (SDA)
Figure 55. Input / Output Pin Circuit Diagram
Figure 54. Input Pin Circuit Diagram
Power-Up/Down Conditions
At power on, the IC’s internal circuits may go through unstable low voltage area as the Vcc rises, making the IC’s internal
logic circuit not completely reset, hence, malfunction may occur. To prevent this, the IC is equipped with POR circuit and
LVCC circuit. To assure the operation, observe the following conditions at power ON.
1. Set SDA = 'H' and SCL ='L' or 'H’
2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
tR
VCC
Recommended conditions of tR, tOFF,Vbot
tR
tOFF
Vbot
0
tOFF
Vbot
10ms or below
10ms or larger
0.3V or below
100ms or below
10ms or larger
0.2V or below
Figure 56. Rise Waveform Diagram
3. Set SDA and SCL so as not to become 'Hi-Z'.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
(1) In the case when the above condition 1 cannot be observed such that SDA becomes 'L' at power ON.
→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
VCC
tLOW
SCL
SDA
After Vcc becomes stable
After Vcc becomes stable
tDH
tSU:DAT
Figure 57. When SCL= 'H' and SDA= 'L'
tSU:DAT
Figure 58. When SCL='L' and SDA='L'
(2) In the case when the above condition 2 cannot be observed.
→After power source becomes stable, execute software reset(Page19).
(3) In the case when the above conditions 1 and 2 cannot be observed.
→Carry out (1), and then carry out (2).
Low Voltage Malfunction Prevention Function
LVCC circuit prevents data rewrite operation at low power, and prevents write error. At LVCC voltage (Typ =1.2V) or below,
data rewrite is prevented.
Noise Countermeasures
1. Bypass Capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, it is recommended to connect a
bypass capacitor (0.1μF) between the IC’s VCC and GND pins. Connect the capacitor as close to IC as possible. In
addition, it is also recommended to connect a bypass capacitor between board’s VCC and GND.
.
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BR24Gxxx-3A (128K 256K 1M)
Operational Notes
1.
Described numeric values and data are design representative values only, and the values are not guaranteed.
2.
We believe that the application circuit examples in this document are recommendable. However, in actual use, confirm
characteristics further sufficiently. If changing the fixed number of external parts is desired, make your decision with
sufficient margin in consideration of static characteristics, transient characteristics, and fluctuations of external parts
and our LSI.
3.
Absolute maximum ratings
If the absolute maximum ratings such as supply voltage, operating temperature range, and so on are exceeded, LSI
may be destroyed. Do not supply voltage or subject the IC to temperatures exceeding the absolute maximum ratings.
In case of fear of exceeding the absolute maximum ratings, take physical safety countermeasures such as adding
fuses, and see to it that conditions exceeding the absolute maximum ratings should not be supplied to the LSI.
4.
GND electric potential
Set the voltage of GND terminal lowest at any operating condition. Make sure that each terminal voltage is not lower
than that of GND terminal.
5.
Thermal design
Use a thermal design that allows for a sufficient margin by taking into account the permissible power dissipation (Pd) in
actual operating conditions.
6.
Short between pins and mounting errors
Be careful when mounting the IC on printed circuit boards. The IC may be damaged if it is mounted in a wrong
orientation or if pins are shorted together. Short circuit may be caused by conductive particles caught between the pins.
7.
Operating the IC in the presence of strong electromagnetic field may cause malfunction, therefore, evaluate design
sufficiently.
.
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BR24Gxxx-3A (128K 256K 1M)
Part Numbering
B
R
2
4
G
x
x
x
x
x
x
-
3
A
x
x
x
x
BUS type
24：I2C
Operating temperature/ Operating Voltage
-40°C to +85°C/ 1.7V to 5.5V
Capacity
128=128K 256=256K 1M=1024K
Package
Blank : DIP-T8
F
: SOP8
FV : SSOP-B8
FVJ : TSSOP-B8J
NUX : VSON008X2030
: SOP-J8
FJ
FVT : TSSOP-B8
FVM : MSOP8
Process Code
Revision
G
: Halogen free
Blank
: Not Halogen free
As an exception, VSON008X2030 package will be Halogen free with “Blank”
T
Blank
:
:
100% Sn
100% Sn
Packaging and Forming Specification
E2
: Embossed tape and reel
(SOP8,SOP-J8, SSOP-B8,TSSOP-B8, TSSOP-B8J)
TR
: Embossed tape and reel
(MSOP8, VSON008X2030)
None : Tube
(DIP-T8)
Lineup
Package
Capacity
Type
DIP-T8
SOP8
SOP-J8
128K
1M
Tube of 2000
Reel of 2500
Orderable Part Number
BR24G128
Remark
-3A
Not Halogen free
100% Sn
BR24G128F
-3AGTE2
Halogen free
100% Sn
BR24G128FJ
-3AGTE2
Halogen free
100% Sn
SSOP-B8
Reel of 2500
BR24G128FV
-3AGTE2
Halogen free
100% Sn
TSSOP-B8
Reel of 3000
BR24G128FVT
-3AGE2
Halogen free
100% Sn
TSSOP-B8J
Reel of 2500
BR24G128FVJ
-3AGTE2
Halogen free
100% Sn
MSOP8
Reel of 3000
BR24G128FVM
-3AGTTR
Halogen free
100% Sn
VSON008X2030
Reel of 4000
BR24G128NUX
-3ATTR
Halogen free
100% Sn
DIP-T8
Tube of 2000
BR24G256
-3A
Not Halogen free
100% Sn
BR24G256F
-3AGTE2
Halogen free
100% Sn
SOP8
256K
Quantity
SOP-J8
Reel of 2500
BR24G256FJ
-3AGTE2
Halogen free
100% Sn
SSOP-B8
Reel of 2500
BR24G256FV
-3AGTE2
Halogen free
100% Sn
TSSOP-B8
Reel of 3000
BR24G256FVT
-3AGE2
Halogen free
100% Sn
DIP-T8
Tube of 2000
SOP8
SOP-J8
.
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© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
Reel of 2500
BR24G1M
-3A
Not Halogen free
100% Sn
BR24G1MF
-3AGTE2
Halogen free
100% Sn
BR24G1MFJ
-3AGTE2
Halogen free
100% Sn
26/36
TSZ02201-0R2R0G100020-1-2
18.Jun.2015 Rev.006
BR24Gxxx-3A (128K 256K 1M)
Physical Dimensions Tape and Reel information
DIP-T8
.
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© 2014 ROHM Co., Ltd. All rights reserved.
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TSZ02201-0R2R0G100020-1-2
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BR24Gxxx-3A (128K 256K 1M)
SOP8
.
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BR24Gxxx-3A (128K 256K 1M)
SOP-J8
.
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BR24Gxxx-3A (128K 256K 1M)
SSOP-B8
.
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BR24Gxxx-3A (128K 256K 1M)
TSSOP-B8
.
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TSZ02201-0R2R0G100020-1-2
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BR24Gxxx-3A (128K 256K 1M)
TSSOP-B8J
.
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© 2014 ROHM Co., Ltd. All rights reserved.
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TSZ02201-0R2R0G100020-1-2
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BR24Gxxx-3A (128K 256K 1M)
MSOP-8
.
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TSZ02201-0R2R0G100020-1-2
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BR24Gxxx-3A (128K 256K 1M)
VSON008X2030
.
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TSZ02201-0R2R0G100020-1-2
18.Jun.2015 Rev.006
BR24Gxxx-3A (128K 256K 1M)
Marking Diagrams
SOP8(TOP VIEW)
DIP-T8 (TOP VIEW)
Part Number Marking
Part Number Marking
LOT Number
LOT Number
1PIN MARK
SOP-J8(TOP VIEW)
SSOP-B8(TOP VIEW)
Part Number Marking
Part Number Marking
LOT Number
LOT Number
1PIN MARK
1PIN MARK
TSSOP-B8(TOP VIEW)
TSSOP-B8J(TOP VIEW)
Part Number Marking
Part Number Marking
LOT Number
LOT Number
1PIN MARK
1PIN MARK
MSOP8(TOP VIEW)
VSON008X2030 (TOP VIEW)
Part Number Marking
Part Number Marking
LOT Number
LOT Number
1PIN MARK
1PIN MARK
.
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TSZ02201-0R2R0G100020-1-2
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BR24Gxxx-3A (128K 256K 1M)
Marking Information
Product Name
Marking
Capacity
BR24G128A
Package
DIP-T8
SOP8
4G12A
SOP-J8
4GHA
SSOP-B8
4G12A
TSSOP-B8
128K
4G1
2A3
4GH
A□3
4G1
2A3
BR24G256A
TSSOP-B8J
MSOP8
VSON008X2030
DIP-T8
SOP8
4G25A
256K
SOP-J8
4GJA
SSSOP-B8
4G25A
TSSOP-B8
BR24G1MA
1M
DIP-T8
SOP8
4G1MA
SOP-J8
Revision History
Date
Revision
12.Apr.2012
001
25.Feb.2013
002
31.May.2013
003
04.Jul.2013
004
02.May.2014
005
18.Jun.2015
006
Changes
New Release
Update some English words, sentences’ descriptions, grammar and formatting.
Update Part Numbering.
Delete Lineup.
P1 Change format of package line-up table.
P.3 Add VESD in Absolute Maximum Ratings
P.6 Add directions in Pin Descriptions
P.4 Change Start Condition Setup Time from 0.25us to 0.20us.
P.26 Update Part Numbering. Add Lineup table.
P.17,24,26 Japanese datasheet updated
P.3 Change unit of power dissipation from mW to W.
P.24 Japanese datasheet updated
.
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Datasheet
Notice
Precaution on using ROHM Products
1.
Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
(Note 1)
, transport
intend to use our Products in devices requiring extremely high reliability (such as medical equipment
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PGA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
Datasheet
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
QR code printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PGA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
Datasheet
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3.
The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.
Notice – WE
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
Datasheet
BR24G1M-3A - Web Page
Buy
Distribution Inventory
Part Number
Package
Unit Quantity
Minimum Package Quantity
Packing Type
Constitution Materials List
RoHS
BR24G1M-3A
DIP-T8
2000
50
Tube
inquiry
Yes