Mitsubishi M38B57MCH-P202FP 8-bit single-chip microcomputer Datasheet

ADVANCED AND EVER ADVANCING
MITSUBISHI ELECTRIC
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 38000 SERIES
38B5
Group
User’s Manual
MITSUBISHI
ELECTRIC
keep safety first in your circuit designs !
● Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury,
fire or property damage. Remember to give due consideration to safety when
making your circuit designs, with appropriate measures such as (i) placement
of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention
against any malfunction or mishap.
Notes regarding these materials
● These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the customer’s
application; they do not convey any license under any intellectual property rights,
or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
● Mitsubishi Electric Corporation assumes no responsibility for any damage, or
infringement of any third-party’s rights, originating in the use of any product
data, diagrams, charts or circuit application examples contained in these materials.
● All information contained in these materials, including product data, diagrams
and charts, represent information on products at the time of publication of these
materials, and are subject to change by Mitsubishi Electric Corporation without
notice due to product improvements or other reasons. It is therefore recommended
that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for the latest product information before
purchasing a product listed herein.
● Mitsubishi Electric Corporation semiconductors are not designed or manufactured
for use in a device or system that is used under circumstances in which human
life is potentially at stake. Please contact Mitsubishi Electric Corporation or an
authorized Mitsubishi Semiconductor product distributor when considering the
use of a product contained herein for any specific purposes, such as apparatus
or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea
repeater use.
● The prior written approval of Mitsubishi Electric Corporation is necessary to
reprint or reproduce in whole or in part these materials.
● If these products or technologies are subject to the Japanese export control
restrictions, they must be exported under a license from the Japanese government
and cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of
JAPAN and/or the country of destination is prohibited.
● Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or the
products contained therein.
Preface
This user’s manual describes Mitsubishi’s CMOS 8bit microcomputers 38B5 Group.
After reading this manual, the user should have a
through knowledge of the functions and features of
the 38B5 Group, and should be able to fully utilize
the product. The manual starts with specifications
and ends with application examples.
For details of software, refer to the “740 Family
Software Manual.”
For details of development support tools, refer to the
“DEVELOPMENT SUPPORT TOOLS FOR
MICROCOMPUTERS” data book.
BEFORE USING THIS USER’S MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development.
1. Organization
● CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
● CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on
setting examples of relevant registers.
● CHAPTER 3 APPENDIX
This chapter includes a list of registers, and necessary information for systems development using
the microcomputer, the mask ROM confirmation (for mask ROM version), ROM programming confirmation,
and the mark specifications which are to be submitted when ordering.
2. Structure of Register
The figure of each register structure describes its functions, contents at reset, and attributes as follows:
(Note 2)
Bit attributes
Bits
(Note 1)
Contents immediately after reset release
b7 b6 b5 b4 b3 b2 b1 b0
0
CPU mode register (CPUM) [Address : 3B 16]
b
0
Name
Processor mode bits
1
Functions
At reset
R W
b1 b0
0 0 : Single-chip mode
01:
Not available
10:
11:
0 : 0 page
1 : 1 page
0
0
2
Stack page selection bit
3
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
0
✕
4
0
✕
5
Fix this bit to “0.”
0
0
b7 b6
6
Main clock division ratio selection
bits
7
: Bit in which nothing is arranged
0 0 : φ = XIN /2 (High-speed mode)
0 1 : φ = XIN /8 (Middle-speed mode)
1 0 : φ = XIN /8 (Middle-speed mode)
1 1 : φ = XIN (Double-speed mode)
1
0
: Bit that is not used for control of the corresponding function
Notes 1: Contents immediately after reset release
0••••••“0” at reset release
1••••••“1” at reset release
Undefined••••••Undefined or reset release
✻ ••••••Contents determined by option at reset release
2: Bit attributes••••••The attributes of control register bits are classified into 3 bytes : read-only, write-only
and read and write. In the figure, these attributes are represented as follows :
R••••••Read
••••••Read enabled
✕••••••Read disabled
W••••••Write
••••••Write enabled
✕ ••••••Write disabled
Table of contents
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................ 1-2
FEATURES .................................................................................................................................... 1-2
APPLICATION ................................................................................................................................ 1-2
PIN CONFIGURATION .................................................................................................................. 1-2
FUNCTIONAL BLOCK .................................................................................................................. 1-3
PIN DESCRIPTION ........................................................................................................................ 1-4
PART NUMBERING ....................................................................................................................... 1-6
GROUP EXPANSION .................................................................................................................... 1-7
Memory Type ............................................................................................................................ 1-7
Memory Size ............................................................................................................................. 1-7
Package ..................................................................................................................................... 1-7
FUNCTIONAL DESCRIPTION ...................................................................................................... 1-8
Central Processing Unit (CPU) .............................................................................................. 1-8
Memory .................................................................................................................................... 1-12
I/O Ports .................................................................................................................................. 1-14
Interrupts ................................................................................................................................. 1-20
Timers ...................................................................................................................................... 1-23
Serial I/O ................................................................................................................................. 1-28
FLD Controller ........................................................................................................................ 1-40
A-D Converter ......................................................................................................................... 1-52
Pulse Width Modulation (PWM) ........................................................................................... 1-53
Interrupt Interval Determination Function ............................................................................ 1-56
Watchdog Timer ..................................................................................................................... 1-58
Buzzer Output Circucit .......................................................................................................... 1-59
Reset Circuit ........................................................................................................................... 1-60
Clock Generating Circuit ....................................................................................................... 1-62
NOTES ON PROGRAMMING ..................................................................................................... 1-65
NOTES ON USE .......................................................................................................................... 1-65
DATA REQUIRED FOR MASK ORDERS ................................................................................ 1-66
DATA REQUIRED FOR ROM WRITING ORDERS ................................................................. 1-66
ROM PROGRAMMING METHOD .............................................................................................. 1-66
MASK OPTION OF PULL-DOWN RESISTOR ......................................................................... 1-67
FUNCTIONAL DESCRIPTION SUPPLEMENT ......................................................................... 1-69
CHAPTER 2 APPLICATION
2.1 I/O port ..................................................................................................................................... 2-2
2.1.1 Memory assignment ....................................................................................................... 2-2
2.1.2 Relevant registers .......................................................................................................... 2-3
2.1.3 Terminate unused pins .................................................................................................. 2-6
2.1.4 Notes on use .................................................................................................................. 2-7
2.1.5 Termination of unused pins .......................................................................................... 2-8
2.2 Timer....................................................................................................................................... 2-10
2.2.1 Memory map ................................................................................................................. 2-10
2.2.2 Relevant registers ........................................................................................................ 2-11
38B5 Group User’s Manual
i
Table of contents
2.2.3 Timer application examples ........................................................................................ 2-19
2.3 Serial I/O ................................................................................................................................ 2-35
2.3.1 Memory map ................................................................................................................. 2-35
2.3.2 Relevant registers ........................................................................................................ 2-36
2.3.3 Serial I/O1 connection examples ............................................................................... 2-47
2.3.4 Serial I/O1’s modes ..................................................................................................... 2-49
2.3.5 Serial I/O1 application examples ............................................................................... 2-50
2.3.6 Serial I/O2 connection examples ............................................................................... 2-56
2.3.7 Serial I/O2’s modes ..................................................................................................... 2-58
2.3.8 Serial I/O2 application examples ............................................................................... 2-59
2.3.9 Notes on serial I/O1 .................................................................................................... 2-78
2.3.10 Notes on serial I/O2 .................................................................................................. 2-80
2.4 FLD controller ...................................................................................................................... 2-83
2.4.1 Memory assignment ..................................................................................................... 2-83
2.4.2 Relevant registers ........................................................................................................ 2-84
2.4.3 FLD controller application examples ......................................................................... 2-93
2.4.4 Notes on use .............................................................................................................. 2-124
2.5 A-D converter ..................................................................................................................... 2-125
2.5.1 Memory assignment ................................................................................................... 2-125
2.5.2 Relevant registers ...................................................................................................... 2-125
2.5.3 A-D converter application examples ........................................................................ 2-129
2.5.4 Notes on use .............................................................................................................. 2-131
2.6 PWM ...................................................................................................................................... 2-132
2.6.1 Memory assignment ................................................................................................... 2-132
2.6.2 Relevant registers ...................................................................................................... 2-132
2.6.3 PWM application example ......................................................................................... 2-134
2.6.4 Notes on use .............................................................................................................. 2-135
2.7 Interrupt interval determination function ..................................................................... 2-136
2.7.1 Memory assignment ................................................................................................... 2-136
2.7.2 Relevant registers ...................................................................................................... 2-136
2.7.3 Interrupt interval determination function application examples ............................ 2-140
2.8 Watchdog timer .................................................................................................................. 2-144
2.8.1 Memory assignment ................................................................................................... 2-144
2.8.2 Relevant register ........................................................................................................ 2-144
2.8.3 Watchdog timer application examples ..................................................................... 2-145
2.8.4 Notes on use .............................................................................................................. 2-146
2.9 Buzzer output circuit ........................................................................................................ 2-147
2.9.1 Memory assignment ................................................................................................... 2-147
2.9.2 Relevant register ........................................................................................................ 2-147
2.9.3 Buzzer output circuit application examples ............................................................ 2-148
2.10 Reset circuit ..................................................................................................................... 2-149
2.10.1 Connection example of reset IC ............................................................................ 2-149
2.10.2 Notes on use ............................................................................................................ 2-150
2.11 Clock generating circuit ................................................................................................ 2-151
2.11.1 Relevant register ...................................................................................................... 2-151
2.11.2 Clock generating circuit application examples ..................................................... 2-152
ii
38B5 Group User’s Manual
Table of contents
CHAPTER 3 APPENDIX
3.1 Electrical characteristics ..................................................................................................... 3-2
3.1.1 Absolute maximum ratings ............................................................................................ 3-2
3.1.2 Recommended operating conditions ............................................................................ 3-3
3.1.3 Electrical characteristics ................................................................................................ 3-4
3.1.4 A-D converter characteristics ....................................................................................... 3-5
3.1.5 Timing requirements and switching characteristics ................................................... 3-6
3.2 Standard characteristics ...................................................................................................... 3-8
3.2.1 Power source current standard characteristics .......................................................... 3-8
3.2.2 Port standard characteristics ........................................................................................ 3-9
3.2.3 A-D conversion standard characteristics ................................................................... 3-13
3.3 Notes on use ........................................................................................................................ 3-14
3.3.1 Notes on interrupts ...................................................................................................... 3-14
3.3.2 Notes on serial I/O1 .................................................................................................... 3-15
3.3.3 Notes on serial I/O2 .................................................................................................... 3-16
3.3.4 Notes on FLD controller .............................................................................................. 3-19
3.3.5 Notes on A-D converter .............................................................................................. 3-19
3.3.6 Notes on PWM ............................................................................................................. 3-19
3.3.7 Notes on watchdog timer ............................................................................................ 3-20
3.3.8 Notes on reset circuit .................................................................................................. 3-20
3.3.9 Notes on input and output pins ................................................................................. 3-20
3.3.10 Notes on programming .............................................................................................. 3-22
3.3.11 Programming and test of built-in PROM version................................................... 3-23
3.3.12 Notes on built-in PROM version .............................................................................. 3-24
3.3.13 Termination of unused pins ...................................................................................... 3-25
3.4 Countermeasures against noise ...................................................................................... 3-26
3.4.1 Shortest wiring length .................................................................................................. 3-26
3.4.2 Connection of bypass capacitor across VSS line and VCC line ............................... 3-28
3.4.3 Wiring to analog input pins ........................................................................................ 3-29
3.4.4 Oscillator concerns....................................................................................................... 3-29
3.4.5 Setup for I/O ports ....................................................................................................... 3-31
3.4.6 Providing of watchdog timer function by software .................................................. 3-32
3.5 Control registers .................................................................................................................. 3-33
3.6 Mask ROM confirmation form........................................................................................... 3-67
3.7 ROM programming confirmation form ............................................................................ 3-75
3.8 Mark specification form ..................................................................................................... 3-77
3.9 Package outline ................................................................................................................... 3-78
3.10 List of instruction code ................................................................................................... 3-79
3.11 Machine instructions ........................................................................................................ 3-80
3.12 M35501FP ............................................................................................................................ 3-91
3.13 SFR memory map ............................................................................................................ 3-103
3.14 Pin configuration ............................................................................................................. 3-104
38B5 Group User’s Manual
iii
List of figures
List of figures
CHAPTER 1 HARDWARE
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
1 Pin configuration of M38B5xMxH-XXXXFP ..................................................................... 1-2
2 Functional block diagram ................................................................................................... 1-3
3 Part numbering .................................................................................................................... 1-6
4 Memory expansion plan ..................................................................................................... 1-7
5 740 Family CPU register structure ................................................................................... 1-8
6 Register push and pop at interrupt generation and subroutine call ........................... 1-9
7 Structure of CPU mode register ..................................................................................... 1-11
8 Memory map diagram ...................................................................................................... 1-12
9 Memory map of special function register (SFR) .......................................................... 1-13
10 Structure of pull-up control registers (PULL1 and PULL2) ...................................... 1-14
11 Port block diagram (1) ................................................................................................... 1-17
12 Port block diagram (2) ................................................................................................... 1-18
13 Port block diagram (3) ................................................................................................... 1-19
14 Interrupt control ............................................................................................................... 1-22
15 Structure of interrupt related registers ........................................................................ 1-22
16 Structure of timer related register ................................................................................ 1-23
17 Block diagram of timer .................................................................................................. 1-24
18 Timing chart of timer 6 PWM1 mode ........................................................................... 1-25
19 Block diagram of timer X .............................................................................................. 1-27
20 Structure of timer X related registers .......................................................................... 1-27
21 Block diagram of serial I/O1 ......................................................................................... 1-28
22 Structure of serail I/O1 control registers 1, 2 ............................................................ 1-29
23 Structure of serial I/O1 control register 3 ................................................................... 1-30
24 Structure of serial I/O1 automatic transfer data pointer ........................................... 1-31
25 Automatic transfer serial I/O operation ....................................................................... 1-32
26 SSTB1 output operation .................................................................................................... 1-33
27 SBUSY1 input operation (internal synchronous clock) ................................................... 1-33
28 S BUSY1 input operation (external synchronous clock) .................................................. 1-33
29 S BUSY1 output operation (internal synchronous clock, 8-bits serial I/O) ................... 1-34
30 S BUSY1 output operation (external synchronous clock, 8-bits serial I/O) .................. 1-34
31 SBUSY1 output operation in automatic transfer serial I/O mode (internal synchronous
clock, SBUSY1 output function outputs each 1-byte) ................................................... 1-34
32 SRDY1 output operation .................................................................................................... 1-35
33 S RDY1 input operation (internal synchronous clock) .................................................... 1-35
34 Handshake operation at serial I/O1 mutual connecting (1) ...................................... 1-36
35 Handshake operation at serial I/O1 mutual connecting (2) ...................................... 1-36
36 Block diagram of clock snchronous serial I/O2 ......................................................... 1-37
37 Operation of clock synchronous serial I/O2 function ................................................ 1-37
38 Block diagram of UART serial I/O2 ............................................................................. 1-38
39 Operation of UART serial I/O2 function ...................................................................... 1-38
40 Structure of serial I/O2 related register ...................................................................... 1-39
41 Block diagram for FLD control circuit .......................................................................... 1-40
42 Structure of FLDC mode register ................................................................................. 1-41
43 Segment/Digit setting example ..................................................................................... 1-42
44 FLD automatic display RAM assignment .................................................................... 1-43
45 Example of using FLD automatic display RAM in 16-timing•ordinary mode ......... 1-44
38B5 Group User’s Manual
i
List of figures
Fig. 46 Example of using FLD automatic display RAM in 16-timing•gradation display mode
........................................................................................................................................................ 1-45
Fig. 47 Example of using FLD automatic display RAM in 32-timing mode ......................... 1-46
Fig. 48 Structure of FLDRAM write disable register ............................................................... 1-47
Fig. 49 Example of digit timing using grid scan type ............................................................. 1-48
Fig. 50 Example of using FLD automatic display RAM using grid scan type .................... 1-48
Fig. 51 FLDC timing .................................................................................................................... 1-50
Fig. 52 P84 to P87 FLD output waveform ................................................................................. 1-51
Fig. 53 Structure of port P8 FLD output control register ....................................................... 1-51
Fig. 54 Structure of A-D control register .................................................................................. 1-52
Fig. 55 Black diagram of A-D converter ................................................................................... 1-52
Fig. 56 PWM block diagram ....................................................................................................... 1-53
Fig. 57 PWM timing ..................................................................................................................... 1-54
Fig. 58 Structure of PWM control register ............................................................................... 1-55
Fig. 59 14-bit PWM timing .......................................................................................................... 1-55
Fig. 60 Interrupt interval determination circuit block diagram ............................................... 1-56
Fig. 61 Structure of itnerrupt interval determination control register .................................... 1-57
Fig. 62 Interrupt inteval determination operation example (at rising edge active) ............. 1-57
Fig. 63 Interrupt interval determination operation example (at both-sided edge active) ... 1-57
Fig. 64 Block diagram of watchdog timer ................................................................................. 1-58
Fig. 65 Structure of watchdog timer control register .............................................................. 1-58
Fig. 66 Block diagram of buzzer output circuit ........................................................................ 1-59
Fig. 67 Structure of buzzer output control register ................................................................ 1-59
Fig. 68 Reset circuit example .................................................................................................... 1-60
Fig. 69 Reset sequence .............................................................................................................. 1-60
Fig. 70 Internal status at reset .................................................................................................. 1-61
Fig. 71 Ceramic resonator circuit .............................................................................................. 1-62
Fig. 72 External clock input circuit ............................................................................................ 1-62
Fig. 73 Clock generating circuit block diagram ....................................................................... 1-63
Fig. 74 State transitions of system clock ................................................................................. 1-64
Fig. 75 Programming and testing of One Time PROM version ............................................ 1-66
Fig. 76 Digit timing waveform (1) .............................................................................................. 1-67
Fig. 77 Digit timing waveform (2) .............................................................................................. 1-68
Fig. 78 Timing chart after interrupt occurs ............................................................................... 1-70
Fig. 79 TIme up to execution of interrupt processing routine ............................................... 1-70
Fig. 80 A-D conversion equivalent circuit ................................................................................. 1-72
Fig. 81 A-D conversion timing chart.......................................................................................... 1-72
CHAPTER 2 APPLICATION
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
ii
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.1.8
2.1.9
2.2.1
Memory assignment of I/O port relevant registers .................................................. 2-2
Structure of port Pi (i = 0, 1, 2, 3, 4, 5, 7, 8) ........................................................ 2-3
Structure of port P6 ..................................................................................................... 2-3
Structure of port P9 ..................................................................................................... 2-3
Structure of port Pi (i = 0, 2, 4, 5, 7, 8) direction register ................................... 2-4
Structure of port P6 direction register ...................................................................... 2-4
Structure of port P9 direction register ...................................................................... 2-5
Structure of pull-up control register 1 ....................................................................... 2-5
Structure of pull-up control register 2 ....................................................................... 2-6
Memory map of registers relevant to timers .......................................................... 2-10
38B5 Group User’s Manual
List of figures
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
2.2.2 Structure of Timer i (i=1, 3, 4, 5, 6) ....................................................................... 2-11
2.2.3 Structure of Timer 2 .................................................................................................. 2-11
2.2.4 Structure of Timer 6 PWM register ......................................................................... 2-11
2.2.5 Structure of Timer 12 mode register ....................................................................... 2-12
2.2.6 Structure of Timer 34 mode register ....................................................................... 2-12
2.2.7 Structure of Timer 56 mode register ....................................................................... 2-13
2.2.8 Structure of Timer X (low-order, high-order) .......................................................... 2-13
2.2.9 Structure of Timer X mode register 1 ..................................................................... 2-14
2.2.10 Structure of Timer X mode register 2 ................................................................... 2-15
2.2.11 Structure of Interrupt request register 1 ............................................................... 2-16
2.2.12 Structure of Interrupt request register 2 ............................................................... 2-17
2.2.13 Structure of Interrupt control register 1 ................................................................ 2-18
2.2.14 Structure of Interrupt control register 2 ................................................................ 2-18
2.2.15 Timers connection and setting of division ratios ................................................. 2-20
2.2.16 Relevant registers setting ....................................................................................... 2-21
2.2.17 Control procedure..................................................................................................... 2-22
2.2.18 Peripheral circuit example ....................................................................................... 2-23
2.2.19 Timers connection and setting of division ratios ................................................. 2-23
2.2.20 Relevant registers setting ....................................................................................... 2-24
2.2.21 Control procedure..................................................................................................... 2-24
2.2.22 Judgment method of valid/invalid of input pulses ............................................... 2-25
2.2.23 Relevant registers setting ....................................................................................... 2-26
2.2.24 Control procedure..................................................................................................... 2-27
2.2.25 Timers connection and setting of division ratios ................................................. 2-28
2.2.26 Relevant registers setting ....................................................................................... 2-29
2.2.27 Control procedure..................................................................................................... 2-30
2.2.28 Timers connection and table example of timer X/RTP setting values ............. 2-32
2.2.29 RTP output example ................................................................................................ 2-32
2.2.30 Relevant registers setting ....................................................................................... 2-33
2.2.31 Control procedure..................................................................................................... 2-34
2.3.1 Memory map of registers relevant to Serial I/O .................................................... 2-35
2.3.2 Structure of Serial I/O1 automatic transfer data pointer ...................................... 2-36
2.3.3 Structure of Serial I/O1 control register 1 .............................................................. 2-37
2.3.4 Structure of Serial I/O1 control register 2 .............................................................. 2-38
2.3.5 Structure of Serial I/O1 register/Transfer counter ................................................. 2-39
2.3.6 Structure of Serial I/O1 control register 3 .............................................................. 2-40
2.3.7 Structure of Baud rate generator ............................................................................. 2-41
2.3.8 Structure of UART control register .......................................................................... 2-41
2.3.9 Structure of Serial I/O2 control register.................................................................. 2-42
2.3.10 Structure of Serial I/O2 status register ................................................................. 2-43
2.3.11 Structure of Serial I/O2 transmit/receive buffer register ..................................... 2-43
2.3.12 Structure of Interrupt source switch register ........................................................ 2-44
2.3.13 Structure of Interrupt request register 1 ............................................................... 2-44
2.3.14 Structure of Interrupt request register 2 ............................................................... 2-45
2.3.15 Structure of Interrupt control register 1 ................................................................ 2-46
2.3.16 Structure of Interrupt control register 2 ................................................................ 2-46
2.3.17 Serial I/O1 connection examples (1) ..................................................................... 2-47
2.3.18 Serial I/O1 connection examples (2) ..................................................................... 2-48
2.3.19 Serial I/O1’s modes ................................................................................................. 2-49
2.3.20 Connection diagram ................................................................................................. 2-50
2.3.21 Timing chart .............................................................................................................. 2-50
38B5 Group User’s Manual
iii
List of figures
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
iv
2.3.22 Registers setting relevant to transmission side ................................................... 2-51
2.3.23 Setting of transmission data ................................................................................... 2-51
2.3.24 Control procedure..................................................................................................... 2-52
2.3.25 Connection diagram ................................................................................................. 2-53
2.3.26 Timing chart of serial data transmission/reception .............................................. 2-53
2.3.27 Relevant registers setting ....................................................................................... 2-54
2.3.28 Control procedure ..................................................................................................... 2-55
2.3.29 Serial I/O2 connection examples (1) ..................................................................... 2-56
2.3.30 Serial I/O2 connection examples (2) ..................................................................... 2-57
2.3.31 Serial I/O2’s modes ................................................................................................. 2-58
2.3.32 Serial I/O2 transfer data format ............................................................................. 2-58
2.3.33 Connection diagram ................................................................................................. 2-59
2.3.34 Timing chart .............................................................................................................. 2-59
2.3.35 Registers setting relevant to transmission side ................................................... 2-60
2.3.36 Registers setting relevant to reception side......................................................... 2-61
2.3.37 Control procedure of transmission side ................................................................ 2-62
2.3.38 Control procedure of reception side ...................................................................... 2-63
2.3.39 Connection diagram ................................................................................................. 2-64
2.3.40 Timing chart .............................................................................................................. 2-64
2.3.41 Relevant registers setting ....................................................................................... 2-65
2.3.42 Setting of transmission data ................................................................................... 2-65
2.3.43 Control procedure..................................................................................................... 2-66
2.3.44 Connection diagram ................................................................................................. 2-67
2.3.45 Timing chart .............................................................................................................. 2-68
2.3.46 Relevant registers setting in master unit .............................................................. 2-68
2.3.47 Relevant registers setting in slave unit ................................................................ 2-69
2.3.48 Control procedure of master unit ........................................................................... 2-70
2.3.49 Control procedure of slave unit ............................................................................. 2-71
2.3.50 Connection diagram ................................................................................................. 2-72
2.3.51 Timing chart .............................................................................................................. 2-72
2.3.52 Registers setting relevant to transmission side ................................................... 2-74
2.3.53 Registers setting relevant to reception side......................................................... 2-75
2.3.54 Control procedure of transmission side ................................................................ 2-76
2.3.55 Control procedure of reception side ...................................................................... 2-77
2.3.56 Sequence of setting serial I/O2 control register again ....................................... 2-81
2.4.1 Memory assignment of FLD controller relevant registers ..................................... 2-83
2.4.2 Structure of P1FLDRAM write disable register ...................................................... 2-84
2.4.3 Structure of P3FLDRAM write disable register ...................................................... 2-85
2.4.4 Structure of FLD mode register ............................................................................... 2-86
2.4.5 Structure of Tdisp time set register ......................................................................... 2-87
2.4.6 Structure of Toff1 time set register ......................................................................... 2-88
2.4.7 Structure of Toff2 time set register ......................................................................... 2-88
2.4.8 Structure of FLD data pointer/FLD data pointer reload register ......................... 2-89
2.4.9 Structure of port P0FLD/port switch register .......................................................... 2-89
2.4.10 Structure of port P2FLD/port switch register ....................................................... 2-90
2.4.11 Structure of port P8FLD/port switch register ....................................................... 2-90
2.4.12 Structure of port P8FLD output control register .................................................. 2-91
2.4.13 Structure of interrupt request register 2 ............................................................... 2-91
2.4.14 Structure of interrupt control register 2 ................................................................ 2-92
2.4.15 Connection diagram ................................................................................................. 2-93
2.4.16 Timing chart of key-scan using FLD automatic display mode and segments . 2-93
38B5 Group User’s Manual
List of figures
Fig. 2.4.17 Enlarged view of FLD0 (P20) to FLD 7 (P27) Tscan .............................................. 2-93
Fig. 2.4.18 Setting of relevant registers ................................................................................... 2-94
Fig. 2.4.19 FLD digit allocation example .................................................................................. 2-97
Fig. 2.4.20 Control procedure..................................................................................................... 2-98
Fig. 2.4.21 Connection diagram ............................................................................................... 2-100
Fig. 2.4.22 Timing chart of key-scan using FLD automatic display mode and digits ...... 2-101
Fig. 2.4.23 Setting of relevant registers ................................................................................. 2-102
Fig. 2.4.24 FLD digit allocation example ................................................................................ 2-105
Fig. 2.4.25 Control procedure................................................................................................... 2-106
Fig. 2.4.26 Connection diagram ............................................................................................... 2-108
Fig. 2.4.27 Timing chart of FLD display by software ........................................................... 2-108
Fig. 2.4.28 Enlarged view of P20 to P27 key-scan ................................................................ 2-108
Fig. 2.4.29 Setting of relevant registers ................................................................................. 2-109
Fig. 2.4.30 FLD digit allocation example ................................................................................ 2-110
Fig. 2.4.31 Control procedure................................................................................................... 2-111
Fig. 2.4.32 Connection diagram ............................................................................................... 2-112
Fig. 2.4.33 Timing chart of 38B5 Group and M35501FP ..................................................... 2-113
Fig. 2.4.34 Timing chart (enlarged view) of digit and segment output .............................. 2-113
Fig. 2.4.35 Setting of relevant registers ................................................................................. 2-114
Fig. 2.4.36 FLD digit allocation example ................................................................................ 2-117
Fig. 2.4.37 Control procedure................................................................................................... 2-117
Fig. 2.4.38 Connection diagram ............................................................................................... 2-118
Fig. 2.4.39 Timing chart (at correct state) of 38B5 Group and M35501FP ...................... 2-119
Fig. 2.4.40 Timing chart (at incorrect state) of 38B5 Group and M35501FP ................... 2-119
Fig. 2.4.41 Setting of relevant registers ................................................................................. 2-120
Fig. 2.4.42 Control procedure................................................................................................... 2-122
Fig. 2.5.1 Memory assignment of A-D converter relevant registers ................................... 2-125
Fig. 2.5.2 Structure of A-D control register ............................................................................ 2-125
Fig. 2.5.3 Structure of A-D conversion register (low-order) ................................................. 2-126
Fig. 2.5.4 Structure of A-D conversion register (high-order) ............................................... 2-126
Fig. 2.5.5 Structure of interrupt request register 2 ............................................................... 2-127
Fig. 2.5.6 Structure of interrupt control register 2 ................................................................ 2-128
Fig. 2.5.7 Connection diagram ................................................................................................. 2-129
Fig. 2.5.8 Setting of relevant registers ................................................................................... 2-129
Fig. 2.5.9 Control procedure ..................................................................................................... 2-130
Fig. 2.6.1 Memory assignment of PWM relevant registers .................................................. 2-132
Fig. 2.6.2 Structure of PWM register (high-order) ................................................................. 2-132
Fig. 2.6.3 Structure of PWM register (low-order) .................................................................. 2-133
Fig. 2.6.4 Structure of PWM control register ......................................................................... 2-133
Fig. 2.6.5 Connection diagram ................................................................................................. 2-134
Fig. 2.6.6 Setting of relevant registers ................................................................................... 2-134
Fig. 2.6.7 Control procedure ..................................................................................................... 2-135
Fig. 2.6.8 PWM 0 output ............................................................................................................. 2-135
Fig. 2.7.1 Memory assignment of interrupt interval determination function relevant registers
...................................................................................................................................................... 2-136
Fig. 2.7.2 Structure of interrupt interval determination register........................................... 2-136
Fig. 2.7.3 Structure of interrupt interval determination control register ............................. 2-137
Fig. 2.7.4 Structure of interrupt edge selection register....................................................... 2-137
Fig. 2.7.5 Structure of interrupt request register 1 ............................................................... 2-138
Fig. 2.7.6 Structure of interrupt control register 1 ................................................................ 2-139
Fig. 2.7.7 Connection diagram ................................................................................................. 2-140
38B5 Group User’s Manual
v
List of figures
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
2.7.8 Function block diagram ........................................................................................... 2-140
2.7.9 Timing chart of data determination ........................................................................ 2-140
2.7.10 Setting of relevant registers ................................................................................. 2-141
2.7.11 Control procedure................................................................................................... 2-142
2.7.12 Reception of remote-control data (timer 2 interrupt) ........................................ 2-143
2.8.1 Memory assignment of watchdog timer relevant register ................................... 2-144
2.8.2 Structure of watchdog timer control register ........................................................ 2-144
2.8.3 Connection of watchdog timer and setting of division ratio ............................... 2-145
2.8.4 Setting of relevant registers ................................................................................... 2-145
2.8.5 Control procedure ..................................................................................................... 2-146
2.9.1 Memory assignment of buzzer output circuit relevant register .......................... 2-147
2.9.2 Structure of buzzer output control register ........................................................... 2-147
2.9.3 Connection of buzzer output circuit and setting of division ratio ...................... 2-148
2.9.4 Setting of relevant register ..................................................................................... 2-148
2.9.5 Control procedure ..................................................................................................... 2-148
2.10.1 Example of power-on reset circuit ....................................................................... 2-149
2.10.2 RAM backup system example .............................................................................. 2-149
2.11.1 Structure of CPU mode register .......................................................................... 2-151
2.11.2 Connection diagram ............................................................................................... 2-152
2.11.3 Status transition diagram during power failure .................................................. 2-152
2.11.4 Setting of relevant registers ................................................................................. 2-153
2.11.5 Control procedure................................................................................................... 2-154
2.11.6 Structure of clock counter ..................................................................................... 2-155
2.11.7 Initial setting of relevant registers ....................................................................... 2-156
2.11.8 Setting of relevant registers after detecting power failure ............................... 2-157
2.11.9 Control procedure................................................................................................... 2-158
CHAPTER 3 APPENDIX
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
vi
3.1.1 Circuit for measuring output switching characteristics ............................................ 3-6
3.1.2 Timing diagram ............................................................................................................. 3-7
3.2.1 Power source current standard characteristics ........................................................ 3-8
3.2.2 Power source current standard characteristics (in wait mode) ............................. 3-8
3.2.3 High-breakdown P-channel open-drain output port characteristics (25 °C) ......... 3-9
3.2.4 High-breakdown P-channel open-drain output port characteristics (90 °C) ......... 3-9
3.2.5 CMOS output port P-channel side characteristics (25 °C) .................................. 3-10
3.2.6 CMOS output port P-channel side characteristics (90 °C) .................................. 3-10
3.2.7 CMOS output port N-channel side characteristics (25 °C) .................................. 3-11
3.2.8 CMOS output port N-channel side characteristics (90 °C) .................................. 3-11
3.2.9 N-channel open-drain output port characteristics (25 °C) .................................... 3-12
3.2.10 N-channel open-drain output port characteristics (90 °C).................................. 3-12
3.2.11 A-D conversion standard characteristics............................................................... 3-13
3.3.1 Sequence of switch detection edge ......................................................................... 3-14
3.3.2 Sequence of check of interrupt request bit ............................................................ 3-14
3.3.3 Structure of interrupt control register 2 .................................................................. 3-15
3.3.4 Sequence of setting serial I/O2 control register again ......................................... 3-18
3.3.5 PWM output ................................................................................................................ 3-19
3.3.6 Initialization of processor status register ................................................................ 3-22
3.3.7 Sequence of PLP instruction execution .................................................................. 3-22
3.3.8 Stack memory contents after PHP instruction execution ..................................... 3-22
38B5 Group User’s Manual
List of figures
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
3.3.9 Status flag at decimal calculations .......................................................................... 3-23
3.3.10 Programming and testing of One Time PROM version ...................................... 3-23
3.4.1 Selection of packages ............................................................................................... 3-26
3.4.2 Wiring for the RESET pin ......................................................................................... 3-26
3.4.3 Wiring for clock I/O pins ........................................................................................... 3-27
3.4.4 Wiring for the V PP pin of the One Time PROM and the EPROM version ......... 3-28
3.4.5 Bypass capacitor across the VSS line and the VCC line ........................................ 3-28
3.4.6 Analog signal line and a resistor and a capacitor ................................................ 3-29
3.4.7 Wiring for a large current signal line ...................................................................... 3-29
3.4.8 Wiring of signal lines where potential levels change frequently ......................... 3-30
3.4.9 VSS pattern on the underside of an oscillator ........................................................ 3-30
3.4.10 Setup for I/O ports ................................................................................................... 3-31
3.4.11 Watchdog timer by software ................................................................................... 3-32
3.5.1 Structure of port Pi .................................................................................................... 3-33
3.5.2 Structure of port Pi direction register ...................................................................... 3-33
3.5.3 Structure of port P6 ................................................................................................... 3-34
3.5.4 Structure of port P6 direction register .................................................................... 3-34
3.5.5 Structure of port P9 ................................................................................................... 3-35
3.5.6 Structure of port P9 direction register .................................................................... 3-35
3.5.7 Structure of PWM register (high-order) ................................................................... 3-36
3.5.8 Structure of PWM register (low-order) .................................................................... 3-36
3.5.9 Structure of baud rate generator ............................................................................. 3-37
3.5.10 Structure of UART control register ........................................................................ 3-37
3.5.11 Structure of serial I/O1 automatic transfer data pointer ..................................... 3-38
3.5.12 Structure of serial I/O1 control register 1 ............................................................ 3-38
3.5.13 Structure of serial I/O1 control register 2 ............................................................ 3-39
3.5.14 Structure of serial I/O1 register/Transfer counter ................................................ 3-40
3.5.15 Structure of serial I/O1 control register 3 ............................................................ 3-41
3.5.16 Structure of serial I/O2 control register ................................................................ 3-42
3.5.17 Structure of serial I/O2 status register ................................................................. 3-43
3.5.18 Structure of serial I/O2 transmit/receive buffer register ..................................... 3-43
3.5.19 Structure of timer i ................................................................................................... 3-44
3.5.20 Structure of timer 2 ................................................................................................. 3-44
3.5.21 Structure of PWM control register ......................................................................... 3-44
3.5.22 Structure of timer 6 PWM register ........................................................................ 3-45
3.5.23 Structure of timer 12 mode register ...................................................................... 3-45
3.5.24 Structure of timer 34 mode register ...................................................................... 3-46
3.5.25 Structure of timer 56 mode register ...................................................................... 3-46
3.5.26 Structure of watchdog timer control register ........................................................ 3-47
3.5.27 Structure of timer X (low-order, high-order) ......................................................... 3-47
3.5.28 Structure of timer X mode register 1 .................................................................... 3-48
3.5.29 Structure of timer X mode register 2 .................................................................... 3-49
3.5.30 Structure of interrupt interval determination register .......................................... 3-49
3.5.31 Structure of interrupt interval determination control register ............................. 3-50
3.5.32 Structure of A-D control register ............................................................................ 3-50
3.5.33 Structure of A-D conversion register (low-order) ................................................. 3-51
3.5.34 Structure of A-D conversion register (high-order) ............................................... 3-51
3.5.35 Structure of interrupt source switch register ........................................................ 3-52
3.5.36 Structure of interrupt edge selection register ...................................................... 3-52
3.5.37 Structure of CPU mode register ............................................................................ 3-53
3.5.38 Structure of interrupt request register 1 ............................................................... 3-54
38B5 Group User’s Manual
vii
List of figures
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
Fig.
viii
3.5.39 Structure of interrupt request register 2 ............................................................... 3-55
3.5.40 Structure of interrupt control register 1 ................................................................ 3-56
3.5.41 Structure of interrupt control register 2 ................................................................ 3-57
3.5.42 Structure of pull-up control register 1 ................................................................... 3-58
3.5.43 Structure of pull-up control register 2 ................................................................... 3-58
3.5.44 Structure of P1FLDRAM write disable register .................................................... 3-59
3.5.45 Structure of P3FLDRAM write disable register .................................................... 3-60
3.5.46 Structure of FLDC mode register .......................................................................... 3-61
3.5.47 Structure of Tdisp time set register ...................................................................... 3-62
3.5.48 Structure of Toff1 time set register ....................................................................... 3-63
3.5.49 Structure of Toff2 time set register ....................................................................... 3-63
3.5.50 Structure of FLD data pointer/FLD data pointer reload register ....................... 3-64
3.5.51 Structure of port P0FLD/Port switch register ....................................................... 3-64
3.5.52 Structure of port P2FLD/port switch register ....................................................... 3-65
3.5.53 Structure of port P8FLD/port switch register ....................................................... 3-65
3.5.54 Structure of port P8FLD output control register .................................................. 3-66
3.5.55 Structure of buzzer output control register........................................................... 3-66
3.12.1 Pin configuration of M35501FP .............................................................................. 3-91
3.12.2 Functional block diagram ........................................................................................ 3-92
3.12.3 Port block diagram ................................................................................................... 3-93
3.12.4 Digit setting ............................................................................................................... 3-94
3.12.5 16-digit mode output waveform .............................................................................. 3-95
3.12.6 Optional digit mode output waveform ................................................................... 3-95
3.12.7 Cascade mode connection example: 17 digits or more selected ..................... 3-96
3.12.8 Cascade mode output waveform ........................................................................... 3-96
3.12.9 Connection example with 38B5 Group microcomputer (1 to 16 digits) ........... 3-97
3.12.10 Connection example with 38B5 Group microccomputer (17 to 32 digits) ..... 3-97
3.12.11 Digit output waveform when reset signal is input ............................................. 3-98
3.12.12 Power-on reset circuit ........................................................................................... 3-99
3.12.13 Timing diagram ..................................................................................................... 3-102
38B5 Group User’s Manual
List of tables
List of tables
CHAPTER 1 HARDWARE
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
1 Pin description (1) ........................................................................................................... 1-4
2 Pin description (2) ........................................................................................................... 1-5
3 List of supported products ............................................................................................. 1-7
4 Push and pop instructions of accumulator or processor status register ................. 1-9
5 Set and clear instructions of each bit of processor status register ....................... 1-10
6 List of I/O port functions (1) ........................................................................................ 1-15
7 List of I/O port functions (2) ........................................................................................ 1-16
8 Interrupt vector addresses and priority ...................................................................... 1-21
9 Pins in FLD automatic display mode .......................................................................... 1-42
10 Relationship between low-order 6-bit data and setting period of ADD bit ......... 1-54
11 Special programming adapter .................................................................................... 1-66
12 Mask option type of pull-down resistor .................................................................... 1-67
13 Interrupt sources, vector addresses and interrupt priority ..................................... 1-69
14 Relative formula for a refernece voltage VREF of A-D converter and V ref ..................... 1-71
15 Change of A-D conversion register during A-D conversion .................................. 1-71
CHAPTER 2 APPLICATION
Table 2.1.1 Termination of unused pins ..................................................................................... 2-6
Table 2.3.1 Setting examples of baud rate generator values and transfer bit rate values
........................................................................................................................................................ 2-73
Table 2.4.1 FLD automatic display RAM map ......................................................................... 2-96
Table 2.4.2 FLD automatic display RAM map example ......................................................... 2-97
Table 2.4.3 FLD automatic display RAM map ....................................................................... 2-104
Table 2.4.4 FLD automatic display RAM map example ....................................................... 2-105
Table 2.4.5 FLD automatic display RAM map example ....................................................... 2-110
Table 2.4.6 FLD automatic display RAM map ....................................................................... 2-116
CHAPTER 3 APPENDIX
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
3.1.1 Absolute maximum ratings ....................................................................................... 3-2
3.1.2 Recommended operating conditions (1) ................................................................ 3-3
3.1.3 Recommended operating conditions (2) ................................................................ 3-4
3.1.4 Electrical characteristics (1)..................................................................................... 3-4
3.1.5 Electrical characteristics (2)..................................................................................... 3-5
3.1.6 A-D converter characteristics .................................................................................. 3-5
3.1.7 Timing requirements ................................................................................................. 3-6
3.1.8 Switching characteristics .......................................................................................... 3-6
3.3.1 Programming adapter ............................................................................................. 3-24
3.3.2 PROM programmer address setting ..................................................................... 3-24
3.12.1 Pin description ....................................................................................................... 3-92
3.12.2 Absolute maximum ratings ................................................................................. 3-100
3.12.3 Recommended operating conditions ................................................................. 3-100
3.12.4 Recommended operating conditions ................................................................. 3-100
3.12.5 Electrical characteristics ..................................................................................... 3-101
3.12.6 Timing requirements ........................................................................................... 3-102
38B5 Group User’s Manual
i
CHAPTER 1
HARDWARE
DESCRIPTION
FEATURES
APPLICATION
PIN CONFIGURATION
FUNCTIONAL BLOCK
PIN DESCRIPTION
PART NUMBERING
GROUP EXPANSION
FUNCTIONAL DESCRIPTION
NOTES ON PROGRAMMING
NOTES ON USE
DATA REQUIRED FOR MASK
ORDERS
DATA REQUIRED FOR ROM WRITING
ORDERS
ROM PROGRAMMING METHOD
MASK OPTION OF PULL-DOWN
RESISTOR
FUNCTIONAL DESCRIPTION
SUPPLEMENT
HARDWARE
DESCRIPTION/FEATURES/APPLICATION/PIN CONFIGURATION
•
•
DESCRIPTION
The 38B5 group is the 8-bit microcomputer based on the 740 family
core technology.
The 38B5 group has six 8-bit timers, a 16-bit timer, a fluorescent display automatic display circuit, 12-channel 10-bit A-D converter, a serial I/O with automatic transfer function, which are available for controllin g mu sical in str um ent s and hous ehold appli a n c e s .
The 38B5 group has variations of internal memory size and packaging. For details, refer to the section on part numbering.
For details on availability of microcomputers in the 38B5 group, refer
to the section on group expansion.
Built-in pull-down resistors connected to high-breakdown voltage ports
are available by specifying with the mask option in some products. For
the details, refer to the section on the mask option of pull-down resistor.
•
•
•
•
•
•
•
FEATURES
•
•
•
•
•
•
•
•
•
Basic machine-language instructions ....................................... 71
The minimum instruction execution time .......................... 0.48 µ s
(at 4.19 MHz oscillation frequency)
Memory size
ROM ............................................. 24K to 60K bytes
RAM .......................................... 1024 to 2048 bytes
Programmable input/output ports ............................................. 55
High-breakdown-voltage output ports ...................................... 36
Software pull-up resistors ....... (Ports P5, P61 to P65, P7, P84 to P87, P9)
Interrupts .................................................. 21 sources, 16 vectors
Timers ........................................................... 8-bit ✕ 6, 16-bit ✕ 1
Serial I/O1 (Clock-synchronized) ................................... 8-bit ✕ 1
...................... (max. 256-byte automatic transfer function)
•
•
Serial I/O2 (UART or Clock-synchronized) .................... 8-bit ✕ 1
PWM ............................................................................ 14-bit ✕ 1
8-bit ✕ 1 (also functions as timer 6)
A-D converter .............................................. 10-bit ✕ 12 channels
Fluorescent display function ......................... Total 40 control pins
Interrupt interval determination function ..................................... 1
Watchdog timer ............................................................ 20-bit ✕ 1
Buzzer output ............................................................................. 1
2 Clock generating circuit
Main clock (XIN–XOUT) .......................... Internal feedback resistor
Sub-clock (XCIN–XCOUT) .......... Without internal feedback resistor
(connect to external ceramic resonator or quartz-crystal
oscillator)
Power source voltage
In high-speed mode ................................................... 4.0 to 5.5 V
(at 4.19 MHz oscillation frequency and high-speed selected)
In middle-speed mode ................................................ 2.7 to 5.5 V
(at 4.19 MHz oscillation frequency and middle-speed selected)
In low-speed mode ..................................................... 2.7 to 5.5 V
(at 32 kHz oscillation frequency)
Power dissipation
In high-speed mode .......................................................... 35 mW
(at 4.19 MHz oscillation frequency)
In low-speed mode ............................................................. 60 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
Operating temperature range ................................... –20 to 85 °C
APPLICATION
Musical instruments, VCR, household appliances, etc.
41
43
42
45
44
47
46
49
48
50
52
51
54
53
56
55
58
57
60
59
61
64
62
40
65
66
67
39
38
68
37
69
36
70
35
71
34
33
72
M38B5xMxH-XXXXFP
73
32
74
31
75
30
76
29
77
28
78
27
79
80
26
23
24
22
21
19
20
18
17
15
16
14
13
11
12
8
9
10
7
4
5
6
2
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
P61/CNTR0/CNTR2
(Note) P60/CNTR1
P47/INT2
RESET
P91/XCOUT
P90/XCIN
Vss
XIN
XOUT
Vcc
P46/T3OUT
P45/T1OUT
P44/PWM1
P43/BUZ01
(Note) P42/INT3
P41/INT1
P40/INT0
P87/PWM0/FLD39
1
25
3
P57/SRDY2/ SCLK22
P56/SCLK21
P55/TxD
P54/RxD
P53/SCLK12
P52/SCLK11
P51/SOUT1
P50/SIN1
AVSS
VREF
P65/SSTB1/AN11
P64/INT4/SBUSY1 /AN10
P63/AN9
P62/SRDY1/AN8
P77/AN7
P76/AN6
63
P20/BUZ02/FLD0
P21/FLD1
P22/FLD2
P23/FLD3
P24/FLD4
P25/FLD5
P26/FLD6
P27/FLD7
P00/FLD8
P01/FLD9
P02/FLD10
P03/FLD11
P04/FLD12
P05/FLD13
P06/FLD14
P07/FLD15
P10/FLD16
P11/FLD17
P12/FLD18
P13/FLD19
P14/FLD20
P15/FLD21
P16/FLD22
P17/FLD23
PIN CONFIGURATION (TOP VIEW)
Note: In the mask option type P, INT3 and CNTR1 cannot be used.
Package type : 80P6N-A
80-pin plastic-molded QFP
Fig. 1 Pin configuration of M38B5xMxH-XXXXFP
1-2
38B5 Group User’s Manual
P30/FLD24
P31/FLD25
P32/FLD26
P33/FLD27
P34/FLD28
P35/FLD29
P36/FLD30
P37/FLD31
P80/FLD32
P81/FLD33
P82/FLD34
P83/FLD35
VEE
P84/FLD36
P85/RTP0/FLD37
P86/RTP1/FLD38
Port P0(8)
8
A-D converter
38B5 Group User’s Manual
Port P7(8)
8
Port P6(6)
6
8
Interrupt interval
determination function
Watchdog timer
CPU core
Timer X(16-bit)
Timer 1(8-bit)
Timer 2(8-bit)
Timer 3(8-bit)
Timer 4(8-bit)
Timer 5(8-bit)
Timer 6(8-bit)
Timers
8
Port P2(8)
Port P5(8)
(36 high-breakdown voltage ports)
40 control pins
FLD display function
Buzzer output
PWM0(14-bit)
PWM1(8-bit)
Serial I/O2
(Clock-synchronized or UART)
Serial I/O1(Clock-synchronized)
(256 byte automatic transfer)
Serial I/O
(10-bit ✕ 12 channel)
8
Port P1(8)
Build-in peripheral functions
I/O ports
FUNCTIONAL BLOCK DIAGRAM (Package : 80P6N-A)
8
Port P8(8)
RAM
ROM
Memory
XIN-XOUT
(main-clock)
XCIN-XCOUT
(sub-clock)
System clock generation
Port P3(8)
8
2
Port P9(2)
Port P4(8)
1
7
HARDWARE
FUNCTIONAL BLOCK
FUNCTIONAL BLOCK
Fig. 2 Functional block diagram
1-3
HARDWARE
PIN DESCRIPTION
PIN DESCRIPTION
Table 1 Pin description (1)
Pin
Name
Function
Power source
Pull-down
power source
Reference
voltage
• Apply voltage of 4.0–5.5 V to VCC, and 0 V to V SS.
• Apply voltage supplied to pull-down resistors of ports P0, P1, and P3.
______
RESET
XIN
Analog power
source
Reset input
Clock input
• Analog power source input pin for A-D converter.
• Connect to V SS.
• Reset input pin for active “L.”
• Input and output pins for the main clock generating circuit.
• Feedback resistor is built in between XIN pin and XOUT pin.
XOUT
Clock output
P00/FLD8–
P07/FLD15
I/O port P0
VCC, VSS
VEE
VREF
AV SS
Function except a port function
• Reference voltage input pin for A-D converter.
• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the
oscillation frequency.
• When an external clock is used, connect the clock source to the XIN pin and leave the X OUT pin open.
• The clock is used as the oscillating source of system clock.
• 8-bit I/O port.
• FLD automatic display
• I/O direction register allows each pin to be individually programmed as either pins
input or output.
• At reset, this port is set to input mode.
• A pull-down resistor is built in between port P0 and the VEE pin.
• CMOS compatible input level.
• High-breakdown-voltage P-channel open-drain output structure.
P10/FLD16 – Output port P1
P17/FLD23
P20/BUZ02/ I/O port P2
FLD 0–
P27/FLD7
P30/FLD24 – Output port P3
P37/FLD31
P40/INT0,
P41/INT1,
I/O port P4
P42/INT3
P43/BUZ01
P44/PWM1
P45/T1OUT,
P46/T3OUT
P47/INT2
1-4
Input port P4
• At reset, this port is set to VEE level.
• 8-bit output port.
• A pull-down resistor is built in between port P1 and the VEE pin.
• High-breakdown-voltage P-channel open-drain output structure.
• At reset, this port is set to VEE level.
• 8-bit I/O port with the same function as port P0.
• Low-voltage input level.
• High-breakdown-voltage P-channel open-drain output structure.
• 8-bit output port.
• A pull-down resistor is built in between port P3 and the VEE pin.
• High-breakdown-voltage P-channel open-drain output structure.
• At reset, this port is set to VEE level.
• 7-bit I/O port with the same function as port P0.
• CMOS compatible input level
• FLD automatic display
pins
• FLD automatic display
pins
• Buzzer output pin (P20)
• FLD automatic display
pins
• Interrupt input pins
In the mask option type P,
• N-channel open-drain output structure.
INT3 cannot be used.
• Buzzer output pin
• PWM output pin
(Timer output pin)
• Timer output pin
• 1-bit input port.
• CMOS compatible input level.
• Interrupt input pin
38B5 Group User’s Manual
HARDWARE
PIN DESCRIPTION
Table 2 Pin description (2)
Pin
P50/SIN1,
Name
I/O port P5
Function
• 8-bit CMOS I/O port with the same function as port P0.
P51/SOUT1,
• CMOS compatible input level.
P52/SCLK11,
• CMOS 3-state output structure.
Function except a port function
• Serial I/O1 function pins
P53/SCLK12
P54/RXD,
• Serial I/O2 function pins
P55/TXD,
P56/SCLK21,
P57/SRDY2/
SCLK22
P60/CNTR1 I/O port P6
• 1-bit I/O port with the same function as port P0.
• Timer input pin
• CMOS compatible input level.
In the mask option type P,
• N-channel open-drain output structure.
CNTR1 cannot be used.
• Timer I/O pin
P61/CNTR0/
• 5-bit CMOS I/O port with the same function as port P0.
CNTR2
• CMOS compatible input level.
P62/SRDY1/
AN8
P63/AN9
• CMOS 3-state output structure.
• Serial I/O1 function pin
• A-D conversion input pin
• A-D conversion input pin
• Dimmer signal output pin
P64/INT4/
• Serial I/O1 function pin
SBUSY1/AN10,
• A-D conversion input pin
P65/SSTB1/
AN11
• Interrupt input pin (P64)
P70/AN0–
I/O port P7
• 8-bit CMOS I/O port with the same function as port P0.
P77/AN7
• CMOS compatible input level.
P80/FLD32– I/O port P8
P83/FLD35
• 4-bit I/O port with the same function as port P0.
• Low-voltage input level.
• High-breakdown-voltage P-channel open-drain output structure.
P84/FLD36
• 4-bit CMOS I/O port with the same function as port P0.
P85/RTP0/
FLD37,
P86/RTP1/
FLD38
• Low-voltage input level.
• CMOS 3-state output structure
• A-D conversion input pin
• CMOS 3-state output structure.
P87/PWM0/
FLD39
P90/XCIN,
P91/XCOUT
• FLD automatic display pins
• FLD automatic display pins
• Real time port output
• FLD automatic display pins
• 14-bit PWM output
I/O port P9
• 2-bit CMOS I/O port with the same function as port P0.
• CMOS compatible input level.
• CMOS 3-state output structure.
38B5 Group User’s Manual
• I/O pins for sub-clock generating
circuit (connect a ceramic resonator or a quarts-crystal oscillator)
1-5
HARDWARE
PART NUMBERING
PART NUMBERING
Product M38B5 7 M C H - XXXX FP
Package type
FP : 80P6N-A package
FS : 80D0 package
ROM number
Omitted in One Time PROM version shipped in
blank and EPROM version.
3 digits for M38B57M6-XXXFP and One Time
PROM version.
High-breakdown voltage pull-down option
Regarding option contents, refer to section “
MASK OPTION OF PULL-DOWN RESISTOR”.
For the M38B57M6-XXXFP, One Time PROM
version, and EPROM version, there is not the
option specification.
ROM/PROM size
1 : 4096 bytes
2 : 8192 bytes
3 : 12288 bytes
4 : 16384 bytes
5 : 20480 bytes
6 : 24576 bytes
7 : 28672 bytes
8 : 32768 bytes
9 : 36864 bytes
A : 40960 bytes
B : 45056 bytes
C : 49152 bytes
D : 53248 bytes
E : 57344 bytes
F : 61440 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used for
users.
Memory type
M : Mask ROM version
E : EPROM or One Time PROM version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
9 : 2048 bytes
Fig. 3 Part numbering
1-6
38B5 Group User’s Manual
HARDWARE
GROUP EXPANSION
GROUP EXPANSION
Mitsubishi plans to expand the 38B5 group as follows:
Memory Type
Support for Mask ROM, One Time PROM and EPROM versions.
Memory Size
ROM/PROM size .................................................. 24K to 60K bytes
RAM size ............................................................ 1024 to 2048 bytes
Package
80P6N-A ..................................... 0.8 mm-pitch plastic molded QFP
80D0 ........................ 0.8 mm-pitch ceramic LCC (EPROM version)
Mass product
M38B59EF
ROM size (bytes)
60K
M38B59MFH
56K
New product
52K
Mass product
M38B57MCH
48K
44K
40K
36K
32K
Mass product
28K
M38B57M6
24K
20K
16K
12K
8K
4K
256
512
768
1,024
1,536
2,048
RAM size (bytes)
Note : Products under development or planning : the development schedule and specifications may be revised without notice.
Fig. 4 Memory expansion plan
Currently supported products are listed below.
Table 3 List of supported products
(P) ROM size (bytes)
Product
ROM size for User ( )
24576
M38B57M6-XXXFP
(24446)
49152
M38B57MCH-XXXXFP
(49022)
61440
M38B59MFH-XXXXFP
(61310)
61440
M38B59EF-XXXFP
(61310)
61440
M38B59EFFP
(61310)
61440
M38B59EFFS
(61310)
As of Nov. 1998
RAM size (bytes)
Package
1024
80P6N-A
Mask ROM version
Corresponded to mask option
1024
80P6N-A
Mask ROM version
2048
80P6N-A
Mask ROM version
Corresponded to mask option
2048
80P6N-A
One Time PROM version
2048
80P6N-A
One Time PROM version (blank)
2048
80D0
38B5 Group User’s Manual
Remarks
EPROM version
1-7
HARDWARE
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016 ”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“01 16”.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 6.
Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine
calls.
The 38B5 group uses the standard 740 Family instruction set. Refer to the table of 740 Series addressing modes and machine
instructions or the 740 Series Software Manual for details on the
instruction set.
Machine-resident 740 Series instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PC H and PC L. It is used to indicate the address of the
next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b7
X
Index register X
b0
b7
Y
b7
Index register Y
b0
S
b15
b7
Stack pointer
b0
PCL
PCH
b7
Program counter
b0
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 5 740 Family CPU register structure
1-8
38B5 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
On-going Routine
Interrupt request
(Note)
M (S)
Execute JSR
Push return address
on stack
M (S)
(PCH)
(S)
(S) – 1
M (S)
(PCL)
(S)
(S)– 1
(S)
M (S)
(S)
M (S)
(S)
Subroutine
(S)
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
(S) – 1
(PCL)
Push return address
on stack
(S) – 1
(PS)
Push contents of processor
status register on stack
(S) – 1
Interrupt
Service Routine
Execute RTS
POP return
address from stack
(PCH)
I Flag is set from “0” to “1”
Fetch the jump vector
Execute RTI
Note: Condition for acceptance of an interrupt
(S)
(S) + 1
(PS)
M (S)
(S)
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
POP contents of
processor status
register from stack
POP return
address
from stack
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 6 Register push and pop at interrupt generation and subroutine call
Table 4 Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
Push instruction to stack
Pop instruction from stack
PHA
PHP
PLA
PLP
38B5 Group User’s Manual
1-9
HARDWARE
FUNCTIONAL DESCRIPTION
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
•Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 5 Set and clear instructions of each bit of processor status register
C flag
Set instruction
Clear instruction
1-10
SEC
CLC
Z flag
_
_
I flag
D flag
SEI
SED
CLI
CLD
38B5 Group User’s Manual
B flag
_
_
T flag
SET
V flag
_
CLT
CLV
N flag
_
_
HARDWARE
FUNCTIONAL DESCRIPTION
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit etc.
The CPU mode register is allocated at address 003B 16.
b7
b0
CPU mode register
(CPUM: address 003B16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1:
1 0 : Not available
1 1:
Stack page selection bit
0: Page 0
1: Page 1
XCOUT drivability selection bit
0: Low drive
1: High drive
Port X C switch bit
0: I/O port function
1: XCIN–XCOUT oscillating function
Main clock (X IN–XOUT ) stop bit
0: Oscillating
1: Stopped
Main clock division ratio selection bit
0: f(XIN) (high-speed mode)
1: f(XIN)/4 (middle-speed mode)
Internal system clock selection bit
0: XIN-XOUT selection (middle-/high-speed mode)
1: XCIN-XCOUT selection (low-speed mode)
Fig. 7 Structure of CPU mode register
38B5 Group User’s Manual
1-11
HARDWARE
FUNCTIONAL DESCRIPTION
Memory
Special function register (SFR) area
Zero page
The special function register (SFR) area in the zero page contains
control registers such as I/O ports and timers.
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
The 256 bytes from addresses 000016 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
ROM
Special page
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing, and the other areas are user areas for storing programs.
The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
RAM
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
RAM area
Address
XXXX16
RAM size
(byte)
192
256
384
512
640
768
896
1024
1536
2048
000016
SFR area 1
RAM
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
Zero page
004016
010016
XXXX16
Reserved area
044016
Not used (Note)
0EF016
0EFF16
0F0016
ROM area
ROM size
(byte)
Address
YYYY16
Address
ZZZZ16
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
ROM
0FFF16
YYYY16
SFR area 2
RAM area for Serial I/O automatic
transfer
RAM area for FLD automatic display
Reserved ROM area
(common ROM area,128 byte)
ZZZZ16
FF0016
FFDC16
FFFE16
FFFF16
Special page
Interrupt vector area
Reserved ROM area
Note: When 1024 bytes or more are used as RAM area, this area can be used.
Fig. 8 Memory map diagram
1-12
38B5 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
000016
Port P0 (P0)
002016
Timer 1 (T1)
000116
Port P0 direction register (P0D)
002116
Timer 2 (T2)
000216
Port P1 (P1)
002216
Timer 3 (T3)
002316
Timer 4 (T4)
000416
Port P2 (P2)
002416
Timer 5 (T5)
000516
Port P2 direction register (P2D)
002516
Timer 6 (T6)
000616
Port P3 (P3)
002616
PWM control register (PWMCON)
002716
Timer 6 PWM register (T6PWM)
000816
Port P4 (P4)
002816
Timer 12 mode register (T12M)
000916
Port P4 direction register (P4D)
002916
Timer 34 mode register (T34M)
000A16
Port P5 (P5)
002A16
Timer 56 mode register (T56M)
000B16
Port P5 direction register (P5D)
002B16
Watchdog timer control register (WDTCON)
000C16
Port P6 (P6)
002C16
Timer X (low-order) (TXL)
000D16
Port P6 direction register (P6D)
002D16
Timer X (high-order) (TXH)
000E16
Port P7 (P7)
002E16
Timer X mode register 1 (TXM1)
000F16
Port P7 direction register (P7D)
002F16
Timer X mode register 2 (TXM2)
001016
Port P8 (P8)
003016
Interrupt interval determination register (IID)
001116
Port P8 direction register (P8D)
003116
Interrupt interval determination control register (IIDCON)
001216
Port P9 (P9)
003216
A-D control register (ADCON)
001316
Port P9 direction register (P9D)
003316
A-D conversion register (low-order) (ADL)
001416
PWM register (high-order) (PWMH)
003416
A-D conversion register (high-order) (ADH)
001516
PWM register (low-order) (PWM L)
003516
001616
Baud rate generator (BRG)
003616
001716
UART control register (UARTCON)
003716
001816
Serial I/O1 automatic transfer data pointer (SIO1DP)
003816
001916
Serial I/O1 control register 1 (SIO1CON1)
003916
001A16
Serial I/O1 control register 2 (SIO1CON2)
003A16
Interrupt edge selection register (INTEDGE)
001B16
Serial I/O1 register/Transfer counter (SIO1)
003B16
CPU mode register (CPUM)
001C16
Serial I/O1 control register 3 (SIO1CON3)
003C16
Interrupt request register 1(IREQ1)
001D16
Serial I/O2 control register (SIO2CON)
003D16
Interrupt request register 2(IREQ2)
001E16
Serial I/O2 status register (SIO2STS)
003E16
Interrupt control register 1(ICON1)
001F16
Serial I/O2 transmit/receive buffer register (TB/RB)
003F16
Interrupt control register 2(ICON2)
0EF016
Pull-up control register 1 (PULL1)
0EF816
FLD data pointer (FLDDP)
0EF116
Pull-up control register 2 (PULL2)
0EF916
Port P0FLD/port switch register (P0FPR)
0EF216
P1FLDRAM write disable register (P1FLDRAM)
0EFA16
Port P2FLD/port switch register (P2FPR)
0EF316
P3FLDRAM write disable register (P3FLDRAM)
0EFB16
Port P8FLD/port switch register (P8FPR)
0EF416
FLDC mode register (FLDM)
0EFC16 Port P8FLD output control register (P8FLDCON)
0EF516
Tdisp time set register (TDISP)
0EFD16 Buzzer output control register (BUZCON)
0EF616
Toff1 time set register (TOFF1)
0EFE16
0EF716
Toff2 time set register (TOFF2)
0EFF16
000316
000716
Interrupt source switch register (IFR)
Fig. 9 Memory map of special function register (SFR)
38B5 Group User’s Manual
1-13
HARDWARE
FUNCTIONAL DESCRIPTION
I/O Ports
[Direction Registers] PiD
The 38B5 group has 55 programmable I/O pins arranged in eight
individual I/O ports (P0, P2, P40–P46, and P5–P9). The I/O ports
have direction registers which determine the input/output direction of
each individual pin. Each bit in a direction register corresponds to
one pin, and each pin can be set to be input port or output port. When
“0” is written to the bit corresponding to a pin, that pin becomes an
input pin. When “1” is written to that pin, that pin becomes an output
pin. If data is read from a pin set to output, the value of the port
output latch is read, not the value of the pin itself. Pins set to input
(the bit corresponding to that pin must be set to “0”) are floating and
the value of that pin can be read. If a pin set to input is written to, only
the port output latch is written to and the pin remains floating.
b7
b0
Pull-up control register 1
(PULL1 : address 0EF0 16)
P50, P51 pull-up control bit
P52, P53 pull-up control bit
P54, P55 pull-up control bit
P56, P57 pull-up control bit
P61 pull-up control bit
0: No pull-up
1: Pull-up
P62, P63 pull-up control bit
P64, P65 pull-up control bit
Not used
(returns “0” when read)
[High-Breakdown-Voltage Output Ports]
The 38B5 group has 5 ports with high-breakdown-voltage pins (ports
P0–P3 and P8 0–P83). The high-breakdown-voltage ports have Pchannel open-drain output with Vcc- 45 V of breakdown voltage. Each
pin in ports P0, P1, and P3 has an internal pull-down resistor connected to V EE. At reset, the P-channel output transistor of each port
latch is turned off, so that it goes to VEE level (“L”) by the pull-down
resistor.
Writing “1” (weak drivability) to bit 7 of the FLDC mode register (address 0EF416) shows the rising transition of the output transistors for
reducing transient noise. At reset, bit 7 of the FLDC mode register is
set to “0” (strong drivability).
b7
Pull-up control register 2
(PULL2 : address 0EF1 16)
P70, P71 pull-up control bit
P72, P73 pull-up control bit
P74, P75 pull-up control bit
P76, P77 pull-up control bit
P84, P85 pull-up control bit
0: No pull-up
1: Pull-up
P86, P87 pull-up control bit
P90, P91 pull-up control bit
Not used
(returns “0” when read)
[Pull-up Control Register] PULL
Ports P5, P61–P6 5, P7, P84–P87 and P9 have built-in programmable
pull-up resistors. The pull-up resistors are valid only in the case that
the each control bit is set to “1” and the corresponding port direction
registers are set to input mode.
1-14
b0
Fig. 10 Structure of pull-up control registers (PULL1 and
PULL2)
38B5 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Table 6 List of I/O port functions (1)
Pin
P00/FLD8–
P07/FLD15
Name
Input/Output
Port P0
Input/output,
individual bits
I/O Format
Non-Port Function
Related SFRs
CMOS compatible input level FLD automatic display function FLDC mode register
High-breakdown voltage PPort P0FLD/port switch register
Ref.No.
(1)
channel open-drain output
with pull-down resistor
P10/FLD16– Port P1
Output
P17/FLD23
P20/BUZ02/
High-breakdown voltage P-
FLDC mode register
(2)
FLDC mode register
(3)
channel open-drain output
Port P2
FLD0
Input/output,
with pull-down resistor
Low-voltage input level
Buzzer output (P20)
individual bits
High-breakdown voltage P-
FLD automatic display function Port P2FLD/port switch register
channel open-drain output
FLD automatic display function Buzzer output control register
P21/FLD1–
(1)
P27/FLD7
P30/FLD24– Port P3
Output
P37/FLD31
P40/INT0,
High-breakdown voltage P-
FLDC mode register
(2)
Interrupt edge selection register
(5-1)
channel open-drain output
with pull-down resistor
Port P4
P41/INT1,
Input/output,
CMOS compatible input level External interrupt input
individual bits
N-channel open-drain output In the mask option type P, INT3
(5-2)
P42/INT3
cannot be used.
P43/BUZ01
P44/PWM1
Buzzer output
PWM output
Buzzer output control register
Timer 56 mode register
(4)
(6)
P45/T1OUT
P46/T3OUT
Timer output
Timer output
Timer 12 mode register
Timer 34 mode register
(7)
(7)
Interrupt edge selection register
(8)
P47/INT2
Input
CMOS compatible input level External interrput input
Interrupt interval determination
control register
P50/SIN1
P51/SOUT1,
Port P5
Input/output,
individual bits
CMOS compatible input level Serial I/O1 function I/O
CMOS 3-state output
Serial I/O1 control register 1, 2
(9)
(10)
Serial I/O2 control register
(9)
UART control register
(10)
P52/SCLK11,
P53/SCLK12
P54/RXD,
Serial I/O2 function I/O
P55/TXD,
P56/SCLK21
P57/SRDY2/
SCLK22
(11)
P60/CNTR1 Port P6
P61/CNTR0/
CNTR2
CMOS compatible input level External count input
N-channel open-drain output In the mask option type P,
CMOS compatible input level CNTR1 cannot be used.
CMOS 3-state output
Interrupt edge selection register
(5-1)
(5-2)
(12)
P62/SRDY1/
AN8
Serial I/O1 function I/O
A-D conversion input
Serial I/O1 control register 1, 2
A-D control register
(13)
P63/AN9
A-D control register
P8FLD output control bit
Serial I/O1 control register 1, 2
(14)
P64/INT4/
A-D conversion input
Dimmer signal output
Serial I/O1 function I/O
S BUSY1/AN 10
A-D conversion input
A-D control register
P65/SSTB1/
External interrupt input
Serial I/O1 function I/O
Interrupt edge selection register
Serial I/O1 control register 1, 2
AN11
A-D conversion input
A-D control register
A-D conversion input
A-D control register
P70/AN0–
P77/AN7
Port P7
38B5 Group User’s Manual
(15)
(16)
(14)
1-15
HARDWARE
FUNCTIONAL DESCRIPTION
Table 7 List of I/O port functions (2)
Name
Input/Output
P80/FLD32– Port P8
Pin
Input/output,
Low-voltage input level
P83/FLD35
individual bits
High-breakdown voltage Pchannel open-drain output
Low-voltage input level
CMOS 3-state output
P84/FLD36
P85/RTP0/
FLD37,
P86/RTP1/
FLD38
P87/PWM0/
FLD39
P90/XCIN
P91/XCOUT
I/O Format
Non-Port Function
Related SFRs
FLD automatic display function FLDC mode register
(1)
Port P8FLD/port switch register
FLD automatic display function FLDC mode register
Real time port output
Port P8FLD/port switch register
(17)
(18)
Timer X mode register 2
Port P9
FLD automatic display function FLDC mode register
PWM output
Port P8FLD/port switch register
PWM control register
CMOS compatible input level Sub-clock generating circuit I/O CPU mode register
(20)
CMOS 3-state output
(21)
Notes 1 : How to use double-function ports as function I/O ports, refer to the applicable sections.
2 : Make sure that the input level at each pin is either 0 V or Vcc during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from Vcc to Vss through the input-stage gate.
1-16
Ref.No.
38B5 Group User’s Manual
(19)
HARDWARE
FUNCTIONAL DESCRIPTION
(1) Ports P0, P21–P27, P80–P83
(2) Ports P1, P3
FLD/Port
switch register
Dimmer signal (Note 1)
*
Port latch
Data bus
Dimmer signal (Note 1)
Local data
bus
Direction register
Local data
bus
*
Port latch
Data bus
read
VEE
(Note 2)
VEE
(3) Port P20
(4) Port P43
FLD/Port
switch register
Buzzer control signal
Buzzer signal output
Buzzer control signal
Buzzer signal output
Direction register
Dimmer signal (Note 1)
Local data
bus
Direction register
Data bus
Port latch
Data bus
Port latch
*
read
(Note 2)
VEE
(5-1) Ports P40–P42, P60
(5-2) Ports P42, P60 (in mask option type P)
Direction register
Direction register
Port latch
Data bus
Port latch
Data bus
INT0,INT1,INT3 interrupt input
CNTR1 input
Timer 4 external clock input
(6) Port P44
(7) Ports P45, P46
Timer 1 output bit
Timer 3 output bit
Timer 6 output selection bit
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Timer 1 output
Timer 3 output
Timer 6 output
(Note 3)
* High-breakdown-voltage P-channel transistor
Notes 1: The dimmer signal sets the Toff timing.
2: A pull-down resistor is not built in to ports P2 and P8.
3: In the mask option type P, the hysteresis circuit of
part is not built-in.
Fig. 11 Port block diagram (1)
38B5 Group User’s Manual
1-17
HARDWARE
FUNCTIONAL DESCRIPTION
(8) Port P47
(9) Ports P50, P54
Pull-up control
Data bus
Direction register
INT2 interrupt
input
Port latch
Data bus
Serial I/O input
(10) Ports P51–P53, P55, P56
(11) Port P57
Pull-up control
P-channel output disable signal (P5 1,P55)
Output OFF control signal
Serial I/O2 mode selection bit
Pull-up control
SRDY2 output enable bit
Direction register
Direction register
Data bus
Port latch
Data bus
TXD, SOUT or SCLK
Port latch
Serial ready output
Serial clock input
Serial clock input
P52,P53,P56
(12) Port P61
(13) Port P62
Pull-up control
Pull-up control
P62/SRDY1• P64/SBUSY1
pin control bit
Timer X operating mode bit
Direction register
Data bus
Port latch
Timer X output
Direction register
Data bus
Port latch
Serial ready output
CNTR0,CNTR2 input
Timer 2, Timer X external clock input
Serial ready input
A-D conversion input
Analog input pin selection bit
Fig. 12 Port block diagram (2)
1-18
38B5 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
(14) Ports P63, P7
(15) Port P64
Pull-up control
P62/SRDY1• P64/SBUSY1
pin control bit
Pull-up control
Dimmer output control bit (P6 3)
Direction register
Direction register
Data bus
Port latch
Port latch
Data bus
SBUSY1 output
INT4 interrupt input, S BUSY1 input
Dimmer signal output (P6 3)
A-D conversion input
Analog input pin selection bit
(16) Port P65
A-D conversion input
Analog
input
pin
selection
bit
(17) Port P84
Pull-up control
P65/SSTB1 pin control bit
Dimmer signal
(Note)
Direction register
Direction register
Port latch
Data bus
Pull-up control
FLD/Port
switch register
Local data
bus
Port latch
Data bus
SSTB1 output
A-D conversion input
(18) Ports P85, P86
(19) Port P87
Dimmer signal
(Note)
Pull-up control
Dimmer signal
(Note)
FLD/Port
switch register
FLD/Port
switch register
Real time port
control bit
Direction register
Local data
bus
Data bus
Local data
bus
Port latch
Pull-up control
P87/PWM
output enable
bit
Direction register
Port latch
Data bus
RTP output
PWM0 output
(20) Port P90
(21) Port P91
Port Xc switch bit
Pull-up control
Pull-up control
Port Xc switch bit
Direction register
Data bus
Direction register
Port latch
Data bus
Port latch
Oscillator
Port P90
Sub-clock generating circuit input
Port Xc switch bit
* High-breakdown-voltage P-channel transistor
Note: The dimmer signal sets the Toff timing.
Fig. 13 Port block diagram (3)
38B5 Group User’s Manual
1-19
HARDWARE
FUNCTIONAL DESCRIPTION
Interrupts
Interrupts occur by twenty one sources: five external, fifteen internal,
and one software.
(1) Interrupt Control
Each interrupt except the BRK instruction interrupt have both an
interrupt request bit and an interrupt enable bit, and is controlled by
the interrupt disable flag. An interrupt occurs if the corresponding
interrupt request and enable bits are “1” and the interrupt disable flag
is “0.” Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by
software. The BRK instruction interrupt and reset cannot be disabled
with any flag or bit. The I flag disables all interrupts except the BRK
instruction interrupt and reset. If several interrupts requests occurs
at the same time the interrupt with highest priority is accepted first.
(2) Interrupt Operation
Upon acceptance of an interrupt the following operations are automatically performed:
1. The contents of the program counter and processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding
interrupt request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
■Notes on Use
When the active edge of an external interrupt (INT0–INT4) is set or
when switching interrupt sources in the same vector address, the
corresponding interrupt request bit may also be set. Therefore, please
take following sequence:
(1) Disable the external interrupt which is selected.
(2) Change the active edge in interrupt edge selection register
(3) Clear the set interrupt request bit to “0.”
(4) Enable the external interrupt which is selected.
1-20
38B5 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Table 8 Interrupt vector addresses and priority
Interrupt Source Priority
Vector Addresses (Note 1)
Reset (Note 2)
INT0
1
2
High
FFFD16
FFFB16
Low
FFFC16
FFFA16
INT1
3
FFF916
FFF816
INT2
4
FFF716
5
FFF516
Non-maskable
External interrupt
(active edge selectable)
FFF616
At detection of either rising or falling edge of
INT1 input
At detection of either rising or falling edge of
INT2 input
At 8-bit counter overflow
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when interrupt interval
FFF416
At completion of data transfer
Serial I/O automatic transfer
At completion of the last data transfer
Timer X
Timer 1
Timer 2
Timer 3
Timer 4
6
7
8
9
10
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFF216
FFF016
FFEE16
FFEC16
FFEA16
At timer X underflow
At timer 1 underflow
At timer 2 underflow
At timer 3 underflow
At timer 4 underflow
Timer 5
Timer 6
Serial I/O2 receive
INT3
11
12
13
14
FFE916
FFE716
FFE516
FFE316
FFE816
FFE616
FFE416
FFE216
At timer 5 underflow
At timer 6 underflow
At completion of serial I/O2 data receive
At detection of either rising or falling edge of
INT3 input
Serial I/O2 transmit
INT4
15
FFE116
FFE016
16
FFDF16
FFDE16
A-D conversion
FLD blanking
Remarks
At reset
At detection of either rising or falling edge of
INT0 input
Remote control/
counter overflow
Serial I/O1
Interrupt Request
Generating Conditions
At completion of serial I/O2 data transmit
At detection of either rising or falling edge of
INT4 input
At completion of A-D conversion
determination is operating
Valid when serial I/O ordinary
mode is selected
Valid when serial I/O automatic
transfer mode is selected
STP release timer underflow
(Note 3)
External interrupt (Note 4)
(active edge selectable)
External interrupt
(active edge selectable)
Valid when INT4 interrupt is selected
Valid when A-D conversion is selected
At falling edge of the last timing immediately
Valid when FLD blanking
before blanking period starts
interrupt is selected
FLD digit
At rising edge of digit (each timing)
Valid when FLD digit interrupt is selected
BRK instruction
17
FFDD16
FFDC16
At BRK instruction execution
Non-maskable software interrupt
Notes 1 : Vector addresses contain interrupt jump destination addresses.
2 : Reset function in the same way as an interrupt with the highest priority.
3 : In the mask option type P, timer 4 interrupt whose count source is CNTR1 input cannot be used.
4 : In the mask option type P, INT3 interrupt cannot be used.
38B5 Group User’s Manual
1-21
HARDWARE
FUNCTIONAL DESCRIPTION
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset
Interrupt request
Fig. 14 Interrupt control
b7
b0 Interrupt source switch register
(IFR : address 003916)
INT3/serial I/O2 transmit interrupt switch bit (Note 1)
0 : INT3 interrupt
1 : Serial I/O2 transmit interrupt
INT4/AD conversion interrupt switch bit
0 : INT4 interrupt
1 : A-D conversion interrupt
Not used (return “0” when read)
(Do not write “1” to these bits.)
b7
b0 Interrupt edge selection register
(INTEDGE : address 003A16)
INT0 interrupt edge selection bit
INT1 interrupt edge selection bit
0 : Falling edge active
INT2 interrupt edge selection bit
1 : Rising edge active
INT3 interrupt edge selection bit (Note 1)
INT4 interrupt edge selection bit
Not used (return "0" when read)
0 : Rising edge count
CNTR0 pin edge switch bit
1 : Falling edge count
CNTR1 pin edge switch bit (Note 1)
b7
b0 Interrupt request register 1
(IREQ1 : address 003C16)
b7
b0 Interrupt request register 2
(IREQ2 : address 003D16)
INT0 interrupt request bit
INT1 interrupt request bit
INT2 interrupt request bit
Remote controller/counter overflow interrupt
request bit
Serial I/O1 interrupt request bit
Timer 4 interrupt request bit (Note 2)
Timer 5 interrupt request bit
Timer 6 interrupt request bit
Serial I/O2 receive interrupt request bit
INT3/serial I/O2 transmit interrupt request bit (Note 2)
INT4 interrupt request bit
AD conversion interrupt request bit
FLD blanking interrupt request bit
FLD digit interrupt request bit
Not used (returns “0” when read)
Serial I/O automatic transfer interrupt request bit
Timer X interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
b7
0 : No interrupt request issued
1 : Interrupt request issued
b0 Interrupt control register 1
(ICON1 : address 003E16)
b7
b0 Interrupt control register 2
(ICON2 : address 003F16)
INT0 interrupt enable bit
INT1 interrupt enable bit
INT2 interrupt enable bit
Remote controller/counter overflow interrupt
enable bit
Serial I/O1 interrupt enable bit
Timer 4 interrupt enable bit (Note 3)
Timer 5 interrupt enable bit
Timer 6 interrupt enable bit
Serial I/O2 receive interrupt enable bit
INT3/serial I/O2 transmit interrupt enable bit (Note 3)
INT4 interrupt enable bit
AD conversion interrupt enable bit
FLD blanking interrupt enable bit
FLD digit interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
Serial I/O automatic transfer interrupt enable bit
Timer X interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Notes 1: In the mask option type P, these bits are not available because CNTR1 function and INT3 function cannot be used.
2: In the mask option type P, if timer 4 interrupt whose count source is CNTR1 input and INT3 interrupt are selected, these bits do not become “1”.
3: In the mask option type P, timer 4 interrupt whose count source is CNTR1 input and INT3 interrupt are not available.
Fig. 15 Structure of interrupt related registers
1-22
38B5 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Timers
8-Bit Timer
The 38B5 group has six built-in timers : Timer 1, Timer 2, Timer 3,
Timer 4, Timer 5, and Timer 6.
Each timer has the 8-bit timer latch. All timers are down-counters.
When the timer reaches “00 16,” an underflow occurs with the next
count pulse. Then the contents of the timer latch is reloaded into the
timer and the timer continues down-counting. When a timer
underflows, the interrupt request bit corresponding to that timer is
set to “1.”
The count can be stopped by setting the stop bit of each timer to “1.”
The internal system clock can be set to either the high-speed mode
or low-speed mode with the CPU mode register. At the same time,
timer internal count source is switched to either f(X IN) or f(XCIN).
●Timer 1, Timer 2
The count sources of timer 1 and timer 2 can be selected by setting
the timer 12 mode register. A rectangular waveform of timer 1 underflow signal divided by 2 can be output from the P4 5/T1OUT pin. The
active edge of the external clock CNTR 0 can be switched with the bit
6 of the interrupt edge selection register.
At reset or when executing the STP instruction, all bits of the timer 12
mode register are cleared to “0,” timer 1 is set to “FF 16,” and timer 2
is set to “0116.”
b7
b0
Timer 12 mode register
(T12M: address 0028 16)
Timer 1 count stop bit
0 : Count operation
1 : Count stop
Timer 2 count stop bit
0 : Count operation
1 : Count stop
Timer 1 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : f(XCIN)
10 : f(XIN)/16 or f(X CIN)/32
11 : f(XIN)/64 or f(X CIN)/128
Timer 2 count source selection bits
00 : Underflow of Timer 1
01 : f(XCIN)
10 : External count input CNTR 0
11 : Not available
Timer 1 output selection bit (P4 5)
0 : I/O port
1 : Timer 1 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
b7
b0
Timer 34 mode register
(T34M: address 0029 16)
Timer 3 count stop bit
0 : Count operation
1 : Count stop
Timer 4 count stop bit
0 : Count operation
1 : Count stop
Timer 3 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : Underflow of Timer 2
10 : f(XIN)/16 or f(XCIN)/32
11 : f(XIN)/64 or f(XCIN)/128
Timer 4 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : Underflow of Timer 3
10 : External count input CNTR 1 (Note)
11 : Not available
Timer 3 output selection bit (P4 6)
0 : I/O port
1 : Timer 3 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
●Timer 3, Timer 4
The count sources of timer 3 and timer 4 can be selected by setting
the timer 34 mode register. A rectangular waveform of timer 3 underflow signal divided by 2 can be output from the P4 6/T3OUT pin. The
active edge of the external clock CNTR 1 (Note) can be switched with
the bit 7 of the interrupt edge selection register.
Note: In the mask option type P, CNTR 1 function cannot be used.
b7
●Timer 5, Timer 6
The count sources of timer 5 and timer 6 can be selected by setting
the timer 56 mode register. A rectangular waveform of timer 6 underflow signal divided by 2 can be output from the P4 4/PWM1 pin.
b0
Timer 56 mode register
(T56M: address 002A 16)
Timer 5 count stop bit
0 : Count operation
1 : Count stop
Timer 6 count stop bit
0 : Count operation
1 : Count stop
Timer 5 count source selection bit
0 : f(XIN)/8 or f(XCIN)/16
1 : Underflow of Timer 4
Timer 6 operation mode selection bit
0 : Timer mode
1 : PWM mode
Timer 6 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : Underflow of Timer 5
10 : Underflow of Timer 4
11 : Not available
Timer 6 (PWM) output selection bit (P4 4)
0 : I/O port
1 : Timer 6 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
●Timer 6 PWM 1 Mode
Timer 6 can output a PWM rectangular waveform with “H” duty cycle
n/(n+m) from the P44/PWM1 pin by setting the timer 56 mode register (refer to Figure 18). The n is the value set in timer 6 latch (address
0025 16) and m is the value in the timer 6 PWM register (address
0027 16). If n is “0,” the PWM output is “L,” if m is “0,” the PWM output
is “H” (n = 0 is prior than m = 0). In the PWM mode, interrupts occur
at the rising edge of the PWM output.
Note: In the mask option type P, CNTR 1 function cannot be used.
Fig. 16 Structure of timer related register
38B5 Group User’s Manual
1-23
HARDWARE
FUNCTIONAL DESCRIPTION
Data bus
XCIN
Timer 1 count source
“1”
Internal system clock
selection bit
1/8
XIN
“0”
RESET
Timer 1 latch (8)
1/2
“01” selection bits
Timer 1 (8)
“00”
1/16
FF16
“10”
STP instruction
Timer 1 interrupt request
Timer 1 count
stop bit
1/64
P45/T1OUT
“11”
P45 latch
1/2
Timer 1 output selection bit
Timer 2 latch (8)
“00”
Timer 2 count source
selection bits
0116
Timer 2 (8)
P45 direction register
Timer 2 count
stop bit
“10”
P61/CNTR0/CNTR2
Timer 2 interrupt request
“01”
Rising/Falling
active edge switch
Timer 3 latch (8)
“01”
“00”
P46/T3OUT
Timer 3 count source
selection bits
Timer 3 (8)
“10”
P46 latch
Timer 3 interrupt request
Timer 3 count
stop bit
“11”
1/2
Timer 3 output selection bit
Timer 4 latch (8)
“01”
P46 direction register
Timer 4 count source
selection bits
Timer 4 (8)
“00”
P60/CNTR1
(Note)
Timer 4 interrupt request
Timer 4 count
stop bit
“10”
Rising/Falling
active edge switch
Timer 5 latch (8)
“1”
Timer 5 count source
selection bit
Timer 5 (8)
“0”
Timer 5 count
stop bit
“01”
Timer 6 count source
selection bits
Timer 5 interrupt request
Timer 6 latch (8)
Timer 6 (8)
“00”
Timer 6 interrupt request
Timer 6 count
stop bit
“10”
Timer 6 PWM register (8)
P44/PWM1
P44 latch
“1”
“0”
PWM
1/2
Timer 6 output selection bit
Timer 6 operation
mode selection bit
P44 direction register
Note: In the mask option type P, CNTR 1 function cannot be used.
Fig. 17 Block diagram of timer
1-24
38B5 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
ts
Timer 6
count source
Timer 6 PWM
mode
n ✕ ts
m ✕ ts
(n+m) ✕ ts
Timer 6 interrupt request
Timer 6 interrupt request
Note: PWM waveform (duty : n/(n + m) and period: (n + m) ✕ ts) is output.
n : setting value of Timer 6
m: setting value of Timer 6 PWM register
ts: period of Timer 6 count source
Fig. 18 Timing chart of timer 6 PWM1 mode
38B5 Group User’s Manual
1-25
HARDWARE
FUNCTIONAL DESCRIPTION
16-Bit Timer
■ Note
Timer X is a 16-bit timer that can be selected in one of four modes by
the Timer X mode registers 1, 2 and can be controlled the timer X
write and the real time port by setting the timer X mode registers.
Read and write operation on 16-bit timer must be performed for both
high- and low-order bytes. When reading a 16-bit timer, read from
the high-order byte first. When writing to 16-bit timer, write to the loworder byte first. The 16-bit timer cannot perform the correct operation
when reading during write operation, or when writing during read
operation.
•Timer X Write Control
If the timer X write control bit is “0,” when the value is written in the
address of timer X, the value is loaded in the timer X and the latch at
the same time.
If the timer X write control bit is “1,” when the value is written in the
address of timer X, the value is loaded only in the latch. The value in
the latch is loaded in timer X after timer X underflows.
When the value is written in latch only, unexpected value may be set
in the high-order counter if the writing in high-order latch and the
underflow of timer X are performed at the same timing.
●Timer X
Timer X is a down-counter. When the timer reaches “000016,” an
underflow occurs with the next count pulse. Then the contents of the
timer latch is reloaded into the timer and the timer continues downcounting. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1.”
(1) Timer mode
A count source can be selected by setting the Timer X count source
selection bits (bits 1 and 2) of the Timer X mode register 1.
•Real Time Port Control
While the real time port function is valid, data for the real time port
are output from ports P85 and P86 each time the timer X underflows.
(However, if the real time port control bit is changed from “0” to “1,”
data are output without the timer X.) When the data for the real time
port is changed while the real time port function is valid, the changed
data are output at the next underflow of timer X.
Before using this function, set the corresponding port direction registers to output mode.
(2) Pulse output mode
Each time the timer underflows, a signal output from the CNTR2 pin
is inverted. Except for this, the operation in pulse output mode is the
same as in timer mode. When using a timer in this mode, set the port
shared with the CNTR2 pin to output.
(3) Event counter mode
The timer counts signals input through the CNTR2 pin. Except for
this, the operation in event counter mode is the same as in timer
mode. When using a timer in this mode, set the port shared with the
CNTR2 pin to input.
(4) Pulse width measurement mode
A count source can be selected by setting the Timer X count source
selection bits (bits 1 and 2) of the Timer X mode register 1. When
CNTR2 active edge switch bit is “0,” the timer counts while the input
signal of the CNTR2 pin is at “H.” When it is “1,” the timer counts
while the input signal of the CNTR2 pin is at “L.” When using a timer
in this mode, set the port shared with the CNTR2 pin to input.
1-26
38B5 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Real time port
control bit “1”
Data bus
Q D
P85
P85 data for real time port
“0”
Latch
P85 direction
register
P85 latch
Real time port
control bit “1”
Q D
Real time port
control bit (P85) “0”
“0”
Latch
P86 direction
register
P86 latch
Real time port
control bit (P86) “0”
“1”
Timer X mode register
write signal
P86 data for real time port
P86
XCIN
1/2
“1”
Timer X mode register
write signal
Internal system clock
selection bit
1/2
XIN
Count source selection bit
1/8
“0”
1/64
Timer X stop
Timer X write
control bit
control bit
Timer X operating
mode bits
CNTR2 active
Timer X latch (low-order) (8) Timer X latch (high-order) (8)
edge switch bit
“00”,“01”,“11”
“0”
P61/CNTR0/CNTR2
Timer X (low-order) (8)
Timer X (high-order) (8)
“10”
“1”
Pulse width
measurement mode
Pulse output mode
CNTR2 active
edge switch bit “0”
S
Q
T
“1”
Q
P61 direction
register
P61 latch
Divider
@“1”
Timer X
interrupt request
Pulse output mode
CNTR0
Fig. 19 Block diagram of timer X
b7
b7
b0
b0
Timer X mode register 1
(TXM1 : address 002E16)
Timer X mode register 2
(TXM2 : address 002F16)
Timer X write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer X count source selection bits
b2 b1
0 0 : f(XIN)/2 or f(XCIN)/4
0 1 : f(XIN)/8 or f(XCIN)/16
1 0 : f(XIN)/64 or f(XCIN)/128
1 1 : Not available
Not used (returns "0" when read)
Timer X operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNTR2 active edge switch bit
0 : • Event counter mode ; counts rising edges
• Pulse output mode ; output starts with “H” level
• Pulse width measurement mode ; measures “H” periods
1 : • Event counter mode ; counts falling edges
• Pulse output mode ; output starts with “L” level
• Pulse width measurement mode ; measures “L” periods
Timer X stop control bit
0 : Count operating
1 : Count stop
Real time port control bit (P85)
0 : Real time port function is invalid
1 : Real time port function is valid
Real time port control bit (P86)
0 : Real time port function is invalid
1 : Real time port function is valid
P85 data for real time port
P86 data for real time port
Not used (returns "0" when read)
Fig. 20 Structure of timer X related registers
38B5 Group User’s Manual
1-27
HARDWARE
FUNCTIONAL DESCRIPTION
Serial I/O
●Serial I/O1
FLD automatic display RAM).
The P62/SRDY1 /AN8, P64/INT4/S BUSY1/AN10, and P65/S STB1/AN11
pins each have a handshake I/O signal function and can select
either “H” active or “L” active for active logic.
Serial I/O1 is used as the clock synchronous serial I/O and has an
ordinary mode and an automatic transfer mode. In the automatic
transfer mode, serial transfer is performed through the serial I/O
automatic transfer RAM which has up to 256 bytes (addresses
0F0016 to 0FFF16 : addresses 0F6016 to 0FFF16 are also used as
Main address
bus
Local address
bus
Serial I/O automatic
transfer RAM
(0F0016—0FFF16)
Main
Local
data bus data bus
Serial I/O1
automatic transfer
data pointer
Address decoder
Serial I/O1
automatic transfer
controller
XCIN
1/2
Serial I/O1
control register 3
Internal system
clock selection bit
“1”
“0”
P65 latch
“0”
P65/SSTB1
Divider
XIN
(P65/SSTB1 pin control bit)
“1”
P62/SRDY1•P64/SBUSY1
pin control bit
P64 latch
“0”
Serial I/O1
synchronous clock
selection bit
“0”
P64/SBUSY1
“1”
P62/SRDY1•P64/SBUSY1
P62 latch
pin control bit
1/4
1/8
1/16
1/32
1/64
1/128
1/256
Internal synchronous
clock selection bits
Synchronous
circuit
“1”
SCLK1
“0”
P62/SRDY1
“1”
Serial I/O1 clock
pin selection bit
“0”
“1”
Serial transfer
status flag
P52 latch
“0”
P52/SCLK11
“0”
“1”
“1”
Serial I/O1 counter
“1”
P53/SCLK12
Serial I/O1 clock
pin selection bits
“0”
P53 latch
“0”
P51/SOUT1
P51 latch
“1” Serial transfer selection bits
P50/SIN1
Serial I/O1 register (8)
Fig. 21 Block diagram of serial I/O1
1-28
38B5 Group User’s Manual
Serial I/O1
interrupt request
HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
Serial I/O1 control register 1
(SIO1CON1 (SC11):address 0019 16)
Serial transfer selection bits
00: Serial I/O disabled (pins P6 2,P64,P65,and P50—P53 are I/O ports)
01: 8-bit serial I/O
10: Not available
11: Automatic transfer serial I/O (8-bits)
Serial I/O1 synchronous clock selection bits (P6 5/SSTB1 pin control bit)
00: Internal synchronous clock (P6 5 pin is an I/O port.)
01: External synchronous clock (P6 5 pin is an I/O port.)
10: Internal synchronous clock (P6 5 pin is an S STB1 output.)
11: Internal synchronous clock (P6 5 pin is an S STB1 output.)
Serial I/O initialization bit
0: Serial I/O initialization
1: Serial I/O enabled
Transfer mode selection bit
0: Full duplex (transmit and receive) mode (P5 0 pin is an SIN1 input.)
1: Transmit-only mode (P5 0 pin is an I/O port.)
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O1 clock pin selection bit
0:SCLK11 (P53/SCLK12 pin is an I/O port.)
1:SCLK12 (P52/SCLK11 pin is an I/O port.)
b7
b0
Serial I/O1 control register 2
(SIO1CON2 (SC12): address 001A 16)
P62/SRDY1 • P64/SBUSY1 pin control bits
0000: Pins P62 and P64 are I/O ports
0001: Not used
0010: P62 pin is an S RDY1 output, P64 pin is an I/O port.
0011: P62 pin is an S RDY1 output, P64 pin is an I/O port.
0100: P62 pin is an I/O port, P6 4 pin is an SBUSY1 input.
0101: P62 pin is an I/O port, P6 4 pin is an SBUSY1 input.
0110: P62 pin is an I/O port, P6 4 pin is an SBUSY1 output.
0111: P62 pin is an I/O port, P6 4 pin is an SBUSY1 output.
1000: P62 pin is an S RDY1 input, P6 4 pin is an S BUSY1 output.
1001: P62 pin is an S RDY1 input, P6 4 pin is an S BUSY1 output.
1010: P62 pin is an S RDY1 input, P6 4 pin is an S BUSY1 output.
1011: P62 pin is an S RDY1 input, P6 4 pin is an S BUSY1 output.
1100: P62 pin is an S RDY1 output, P64 pin is an S BUSY1 input.
1101: P62 pin is an S RDY1 output, P64 pin is an S BUSY1 input.
1110: P62 pin is an S RDY1 output, P64 pin is an S BUSY1 input.
1111: P62 pin is an S RDY1 output, P64 pin is an S BUSY1 input.
SBUSY1 output • SSTB1 output function selection bit
(Valid in automatic transfer mode)
0: Functions as each 1-byte signal
1: Functions as signal for all transfer data
Serial transfer status flag
0: Serial transfer completion
1: Serial transferring
SOUT1 pin control bit (at no-transfer serial data)
0: Output active
1: Output high-impedance
P51/SOUT1 P-channel output disable bit
0: CMOS 3-state (P-channel output is valid.)
1: N-channel open-drain (P-channel output is invalid.)
Fig. 22 Structure of serial I/O1 control registers 1, 2
38B5 Group User’s Manual
1-29
HARDWARE
FUNCTIONAL DESCRIPTION
(1) Serial I/O1 Operation
Either the internal synchronous clock or external synchronous clock
can be selected by the serial I/O1 synchronous clock selection bits
(b2 and b3 of address 001916 ) of serial I/O1 control register 1 as
synchronous clock for serial transfer.
The internal synchronous clock has a built-in dedicated divider where
7 different clocks are selected by the internal synchronous clock
selection bits (b5, b6 and b7 of address 001C16) of serial I/O1
control register 3.
The P62/SRDY1 /AN8, P64/INT4/SBUSY1/AN 10, and P65/S STB1/AN11
pins each select either I/O port or handshake I/O signal by the
serial I/O1 synchronous clock selection bits (b2 and b3 of address
001916) of serial I/O1 control register 1 as well as the P62/SRDY1 •
P64/SBUSY1 pin control bits (b0 to b3 of address 001A16 ) of serial
I/O1 control register 2.
For the SOUT1 being used as an output pin, either CMOS output or
N-channel open-drain output is selected by the P51/SOUT1 P-channel output disable bit (b7 of address 001A16 ) of serial I/O1 control
register 2.
Either output active or high-impedance can be selected as a SOUT1
pin state at serial non-transfer by the SOUT1 pin control bit (b6 of
address 001A16 ) of serial I/O1 control register 2. However, when
the external synchronous clock is selected, perform the following
setup to put the SOUT1 pin into a high-impedance state.
b7
When the SCLK1 input is “H” after completion of transfer, set the
SOUT1 pin control bit to “1.”
When the SCLK1 input goes to “L” after the start of the next serial
transfer, the SOUT1 pin control bit is automatically reset to “0” and
put into an output active state.
Regardless of whether the internal synchronous clock or external
synchronous clock is selected, the full duplex mode and the transmit-only mode are available for serial transfer, one of which is selected by the transfer mode selection bit (b5 of address 001916 ) of
serial I/O1 control register 1.
Either LSB first or MSB first is selected for the I/O sequence of the
serial transfer bit strings by the transfer direction selection bit (b6 of
address 001916) of serial I/O1 control register 1.
When using serial I/O1, first select either 8-bit serial I/O or automatic transfer serial I/O by the serial transfer selection bits (b0 and
b1 of address 001916) of serial I/O1 control register 1, after completion of the above bit setup. Next, set the serial I/O initialization bit
(b4 of address 001916) of serial I/O1 control register 1 to “1” (Serial
I/O enable) .
When stopping serial transfer while data is being transferred, regardless of whether the internal or external synchronous clock is
selected, reset the serial I/O initialization bit (b4) to “0.”
b0
Serial I/O1 control register 3
(SIO1CON3 (SC13): address 001C 16)
Automatic transfer interval set bits
00000: 2 cycles of transfer clocks
00001: 3 cycles of transfer clocks
:
11110: 32 cycles of transfer clocks
11111: 33 cycles of transfer clocks
Data is written to a latch and read from a decrement counter.
Internal synchronous clock selection bits
000: f(XIN)/4 or f(XCIN)/8
001: f(XIN)/8 or f(XCIN)/16
010: f(XIN)/16 or f(XCIN)/32
011: f(XIN)/32 or f(XCIN)/64
100: f(XIN)/64 or f(XCIN)/128
101: f(XIN)/128 or f(X CIN)/256
110: f(XIN)/256 or f(X CIN)/512
Fig. 23 Structure of serial I/O1 control register 3
1-30
38B5 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
(2) 8-bit Serial I/O Mode
Address 001B16 is assigned to the serial I/O1 register.
When the internal synchronous clock is selected, a serial transfer
of the 8-bit serial I/O is started by a write signal to the serial I/O1
register (address 001B16).
The serial transfer status flag (b5 of address 001A16) of serial I/O1
control register 2 indicates the shift register status of serial I/O1,
and is set to “1” by writing into the serial I/O1 register, which becomes a transfer start trigger and reset to “0” after completion of 8bit transfer. At the same time, a serial I/O1 interrupt request occurs.
When the external synchronous clock is selected, the contents of
the serial I/O1 register are continuously shifted while transfer clocks
are input to SCLK1. Therefore, the clock needs to be controlled externally.
(3) Automatic Transfer Serial I/O Mode
The serial I/O1 automatic transfer controller controls the write and
read operations of the serial I/O1 register, so the function of address 001B16 is used as a transfer counter (1-byte units).
When performing serial transfer through the serial I/O automatic
transfer RAM (addresses 0F0016 to 0FFF16 ), it is necessary to set
the serial I/O1 automatic transfer data pointer (address 001816)
beforehand.
Input the low-order 8 bits of the first data store address to be serially transferred to the automatic transfer data pointer set bits.
When the internal synchronous clock is selected, the transfer interval for each 1-byte data can be set by the automatic transfer interval set bits (b0 to b4 of address 001C16) of serial I/O1 control register 3 in the following cases:
1. When using no handshake signal
2. When using the SRDY1 output, SBUSY1 output, and SSTB1 output
of the handshake signal independently
3. When using a combination of SRDY1 output and SSTB1 output or a
combination of SBUSY1 output and SSTB1 output of the handshake
signal
It is possible to select one of 32 different values, namely 2 to 33
cycles of the transfer clock, as a setting value.
When using the SBUSY1 output and selecting the SBUSY1 output •
SSTB1 output function selection bit (b4 of address 001A16) of serial
I/O1 control register 2 as the signal for all transfer data, provided
b7
that the automatic transfer interval setting is valid, a transfer interval is placed before the start of transmission/reception of the first
data and after the end of transmission/reception of the last data.
For SSTB1 output, regardless of the contents of the S BUSY1 output •
SSTB1 output function selection bit (b4), the transfer interval for each
1-byte data is longer than the set value by 2 cycles.
Furthermore, when using a combination of SBUSY1 output and SSTB1
output as a signal for all transfer data, the transfer interval after the
end of transmission/reception of the last data is longer than the set
value by 2 cycles.
When the external synchronous clock is selected, automatic transfer interval setting is disabled.
After completion of the above bit setup, if the internal synchronous
clock is selected, automatic serial transfer is started by writing the
value of “number of transfer bytes - 1” into the transfer counter
(address 001B16 ).
When the external synchronous clock is selected, write the value of
“number of transfer bytes - 1” into the transfer counter and input an
internal system clock interval of 5 cycles or more. After that, input
transfer clock to SCLK1.
As a transfer interval for each 1-byte data transfer, input an internal
system clock interval of 5 cycles or more from the clock rise time of
the last bit.
Regardless of whether the internal or external synchronous clock
is selected, the automatic transfer data pointer and the transfer
counter are decremented after each 1-byte data is received and
then written into the automatic transfer RAM. The serial transfer
status flag (b5 of address 001A16 ) is set to “1” by writing data into
the transfer counter. Writing data becomes a transfer start trigger,
and the serial transfer status flag is reset to “0” after the last data is
written into the automatic transfer RAM. At the same time, a serial
I/O1 interrupt request occurs.
The values written in the automatic transfer data pointer set bits
(b0 to b7 of address 001816 ) and the automatic transfer interval set
bits (b0 to b4 of address 001C 16) are held in the latch.
When data is written into the transfer counter, the values latched in
the automatic transfer data pointer set bits (b0 to b7) and the automatic transfer interval set bits (b0 to b4) are transferred to the
decrement counter.
b0
Serial I/O1 automatic transfer data pointer
(SIO1DP: address 001816)
Automatic transfer data pointer set bits
Specify the low-order 8 bits of the first data store address on the serial I/O automatic
transfer RAM. Data is written into the latch and read from the decrement counter.
Fig. 24 Structure of serial I/O1 automatic transfer data pointer
38B5 Group User’s Manual
1-31
HARDWARE
FUNCTIONAL DESCRIPTION
Automatic transfer RAM
FFF16
Automatic transfer
data pointer
5216
F5216
F5116
F5016
F4F16
F4E16
Transfer counter
0416
F0016
SIN1
SOUT1
Serial I/O1 register
Fig. 25 Automatic transfer serial I/O operation
1-32
38B5 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
(4) Handshake Signal
1. SSTB1 output signal
The SSTB1 output is a signal to inform an end of transmission/reception to the serial transfer destination . The SSTB1 output signal
can be used only when the internal synchronous clock is selected.
In the initial status, namely, in the status in which the serial I/O
initialization bit (b4) is reset to “0,” the SSTB1 output goes to “L,” or
the SSTB1 output goes to “H.”
At the end of transmit/receive operation, when the data of the serial
I/O1 register is all output from SOUT1 , pulses are output in the period of 1 cycle of the transfer clock so as to cause the SSTB1 output
to go “H” or the SSTB1 output to go “L.” After that, each pulse is
returned to the initial status in which SSTB1 output goes to “L” or the
SSTB1 output goes to “H.”
Furthermore, after 1 cycle, the serial transfer status flag (b5) is reset to “0.”
In the automatic transfer serial I/O mode, whether the SSTB1 output
is to be active at an end of each 1-byte data or after completion of
transfer of all data can be selected by the SBUSY1 output • SSTB1
output function selection bit (b4 of address 001A16) of serial I/O1
control register 2.
SSTB1
Serial transfer
status flag
SCLK1
SBUSY1
SCLK1
SOUT1
Fig. 27 SBUSY1 input operation (internal synchronous clock)
When the external synchronous clock is selected, input an “H” level
signal into the SBUSY1 input and an “L” level signal into the SBUSY1
input in the initial status in which transfer is stopped. At this time,
the transfer clocks to be input in SCLK1 become invalid.
During serial transfer, the transfer clocks to be input in SCLK1 become valid, enabling a transmit/receive operation, while an “L” level
signal is input into the S BUSY1 input and an “H” level signal is input
into the SBUSY1 input.
When changing the input values in the SBUSY1 input and the SBUSY1
input at these operations, change them when the SCLK1 input is in a
high state.
When the high impedance of the SOUT1 output is selected by the
SOUT1 pin control bit (b6), the SOUT1 output becomes active, enabling serial transfer by inputting a transfer clock to SCLK1, while an
“L” level signal is input into the S BUSY1 input and an “H” level signal
is input into the SBUSY1 input.
SOUT1
SBUSY1
Fig. 26 S STB1 output operation
2. SBUSY1 input signal
The SBUSY1 input is a signal which receives a request for a stop of
transmission/reception from the serial transfer destination.
When the internal synchronous clock is selected, input an “H” level
signal into the SBUSY1 input and an “L” level signal into the SBUSY1
input in the initial status in which transfer is stopped.
When starting a transmit/receive operation, input an “L” level signal
into the SBUSY1 input and an “H” level signal into the SBUSY1 input in
the period of 1.5 cycles or more of the transfer clock. Then, transfer
clocks are output from the SCLK1 output.
When an “H” level signal is input into the SBUSY1 input and an “L”
level signal into the SBUSY1 input after a transmit/receive operation
is started, this transmit/receive operation are not stopped immediately and the transfer clocks from the SCLK1 output is not stopped
until the specified number of bits are transmitted and received.
The handshake unit of the 8-bit serial I/O is 8 bits and that of the
automatic transfer serial I/O is 8 bits.
SCLK1
Invalid
SOUT1
(Output high-impedance)
Fig. 28 SBUSY1 input operation (external synchronous clock)
3. S BUSY1 output signal
The S BUSY1 output is a signal which requests a stop of transmission/reception to the serial transfer destination. In the automatic
transfer serial I/O mode, regardless of the internal or external synchronous clock, whether the SBUSY1 output is to be active at transfer of each 1-byte data or during transfer of all data can be selected
by the SBUSY1 output • S STB1 output function selection bit (b4).
In the initial status, the status in which the serial I/O initialization bit
(b4) is reset to “0,” the SBUSY1 output goes to “H” and the S BUSY1
output goes to “L.”
38B5 Group User’s Manual
1-33
HARDWARE
FUNCTIONAL DESCRIPTION
When the internal synchronous clock is selected, in the 8-bit serial
I/O mode and the automatic transfer serial I/O mode (SBUSY1 output function outputs in 1-byte units), the S BUSY1 output goes to “L”
and the SBUSY1 output goes to “H” before 0.5 cycle (transfer clock)
of the timing at which the transfer clock from the SCLK1 output goes
to “L” at a start of transmit/receive operation.
In the automatic transfer serial I/O mode (the SBUSY1 output function outputs all transfer data), the SBUSY1 output goes to “L” and the
SBUSY1 output goes to “H” when the first transmit data is written into
the serial I/O1 register (address 001B16).
When the external synchronous clock is selected, the SBUSY1 output goes to “L” and the SBUSY1 output goes to “H” when transmit
data is written into the serial I/O1 register to start a transmit operation, regardless of the serial I/O transfer mode.
At termination of transmit/receive operation, the SBUSY1 output returns to “H” and the SBUSY1 output returns to “L”, the initial status,
when the serial transfer status flag is set to "0", regardless of whether
the internal or external synchronous clock is selected.
Furthermore, in the automatic transfer serial I/O mode (SBUSY1 output function outputs in 1-byte units), the SBUSY1 output goes to “H”
and the SBUSY1 output goes to “L” each time 1-byte of receive data
is written into the automatic transfer RAM.
SBUSY1
SBUSY1
Serial transfer
status flag
Serial transfer
status flag
SCLK1
SCLK1
Write to Serial
I/O1 register
SOUT1
Fig. 29 SBUSY1 output operation
(internal synchronous clock, 8-bits serial I/O)
Fig. 30 SBUSY1 output operation
(external synchronous clock, 8-bits serial I/O)
Automatic transfer
interval
SCLK1
Serial I/O1 register
→Automatic transfer RAM
Automatic transfer RAM
→Serial I/O1 register
SBUSY1
Serial transfer
status flag
SOUT1
Fig. 31 SBUSY1 output operation in automatic transfer serial I/O mode
(internal synchronous clock, SBUSY1 output function outputs each 1-byte)
1-34
38B5 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
4. SRDY1 output signal
The SRDY1 output is a transmit/receive enable signal which informs
the serial transfer destination that transmit/receive is ready. In the
initial status, when the serial I/O initialization bit (b4) is reset to “0,”
the SRDY1 output goes to “L” and the SRDY1 output goes to “H”. After
transmitted data is stored in the serial I/O1 register (address 001B16)
and a transmit/receive operation becomes ready, the SRDY1 output
goes to “H” and the S RDY1 output goes to “L”. When a transmit/
receive operation is started and the transfer clock goes to “L”, the
SRDY1 output goes to “L” and the SRDY1 output goes to “H”.
5. SRDY1 input signal
The SRDY1 input signal becomes valid only when the SRDY1 input
and the SBUSY1 output are used. The SRDY1 input is a signal for
receiving a transmit/receive ready completion signal from the serial
transfer destination.
When the internal synchronous clock is selected, input a low level
signal into the SRDY1 input and a high level signal into the SRDY1
input in the initial status in which the transfer is stopped.
When an “H” level signal is input into the SRDY1 input and an “L”
level signal is input into the SRDY1 input for a period of 1.5 cycles or
more of transfer clock, transfer clocks are output from the SCLK1
output and a transmit/receive operation is started.
After the transmit/receive operation is started and an “L” level signal is input into the SRDY1 input and an “H” level signal into the
SRDY1 input, this operation cannot be immediately stopped.
After the specified number of bits are transmitted and received, the
transfer clocks from the SCLK1 output is stopped. The handshake
unit of the 8-bit serial I/O and that of the automatic transfer serial
I/O are of 8 bits.
When the external synchronous clock is selected, the SRDY1 input
becomes one of the triggers to output the SBUSY1 signal.
To start a transmit/receive operation (SBUSY1 output: “L,” S BUSY1
output: “H”), input an “H” level signal into the SRDY1 input and an “L”
level signal into the SRDY1 input, and also write transmit data into
the serial I/O1 register.
SRDY1
SCLK1
Write to serial
I/O1 register
Fig. 32 SRDY1 output operation
SRDY1
SCLK1
SOUT1
Fig. 33 SRDY1 input operation (internal synchronous clock)
38B5 Group User’s Manual
1-35
HARDWARE
FUNCTIONAL DESCRIPTION
A:
SCLK1
SCLK1
SRDY1
SRDY1
SBUSY1
Write to serial
I/O1 register
SRDY1
SBUSY1
SBUSY1
A:
Internal synchronous
clock selection
SCLK1
B:
External synchronous
clock selection
B:
Write to serial
I/O1 register
Fig. 34 Handshake operation at serial I/O1 mutual connecting (1)
SCLK1
SCLK1
SRDY1
SRDY1
SBUSY1
A:
Write to serial
I/O1 register
SRDY1
SBUSY1
SBUSY1
A:
Internal synchronous
clock selection
SCLK1
B:
External synchronous
clock selection
B:
Write to serial
I/O1 register
Fig. 35 Handshake operation at serial I/O1 mutual connecting (2)
1-36
38B5 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
●Serial I/O2
ister (address 001D16) to “1.” For clock synchronous serial I/O, the
transmitter and the receiver must use the same clock for serial I/O2
operation. If an internal clock is used, transmit/receive is started by
a write signal to the serial I/O2 transmit/receive buffer register (TB/
RB) (address 001F16).
When P57 (S CLK22) is selected as a clock I/O pin, SRDY2 output
function is invalid, and P56 (SCLK21) is used as an I/O port.
Serial I/O2 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation during serial I/O2 operation.
(1) Clock Synchronous Serial I/O Mode
The clock synchronous serial I/O mode can be selected by setting
the serial I/O2 mode selection bit (b6) of the serial I/O2 control reg-
Data bus
Serial I/O2 control register
Address 001F 16
Receive buffer register
Shift clock
“0”
P56/SCLK21
P57/SRDY2/SCLK22
XIN
Serial I/O2 clock I/O pin selection bit
“0”
Internal system clock selection bit
Serial I/O2 synchronous clock selection bit
“0”
“1”
1/2
F/F
P57/SRDY2/SCLK22
P55/TXD
Clock control circuit
“1”
“1”
XCIN
Receive interrupt request (RI)
Receive shift register
P54/RXD
Address 001D 16
Receive buffer full flag (RBF)
BRG count source selection bit Division ratio 1/(n+1)
Baud rate generator
BRG clock
Address 0016 16
1/4
switch bit
Falling edge detector
Serial I/O2
clock I/O pin
selection bit
1/4
Clock control circuit
Transmit shift register shift
completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Shift clock
Transmit shift register
Transmit buffer register
Transmit buffer empty flag (TBE)
Serial I/O2 status register
Address 001E 16
Address 001F 16
Data bus
Fig. 36 Block diagram of clock synchronous serial I/O2
Transmit/Receive shift clock
(1/2—1/2048 of internal
clock or external clock)
Serial I/O2 output TxD
D0
D1
D2
D3
D4
D5
D6
D7
Serial I/O2 input RxD
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY2
Write-in signal to serial I/O2 transmit/receive
buffer register (address 001F 16)
TBE = 0
TBE = 1
TSC = 0
RBF = 1
TSC = 1
Overrun error (OE)
detection
Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting transmit interrupt source selection bit (TIC) of the serial I/O2
control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1.”
Fig. 37 Operation of clock synchronous serial I/O2 function
38B5 Group User’s Manual
1-37
HARDWARE
FUNCTIONAL DESCRIPTION
(2) Asynchronous Serial I/O (UART) Mode
The asynchronous serial I/O (UART) mode can be selected by clearing the serial I/O2 mode selection bit (b6) of the serial I/O2 control
register (address 001D16 ) to “0.” Eight serial data transfer formats
can be selected and the transfer formats used by the transmitter
and receiver must be identical.
The transmit and receive shift registers each have a buffer (the two
buffers have the same address in memory). Since the shift register
cannot be written to or read from directly, transmit data is written to
the transmit buffer, and receive data is read from the receive buffer.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer can receive 2-byte data continuously.
Data bus
Serial I/O2 control register Address 001D16
Address 001F 16
OE
P54/RXD
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive buffer register
Character length selection bit
7 bit
ST detector
Receive shift register
1/16
8 bit
PE FE
P56/SCLK21
P57/SRDY2/SCLK22
XIN
“0”
Clock control circuit
Serial I/O2 synchronous
clock selection bit
Serial I/O2 clock I/O pin
selection bit
“1”
Internal system clock selection bit
“0”
“1”
XCIN
UART control register
Address 0017 16
SP detector
1/2
BRG count source
selection bit
Division ratio 1/(n+1)
Baud rate generator
Address 0016 16
“1”
BRG clock
switch bit
1/4
ST/SP/PA generator
Transmit shift register shift
completion flag (TSC)
1/16
Transmit shift register
P55/TXD
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
Address 001E16
Transmit buffer register
Address 001F16
Serial I/O2 status register
Data bus
Fig. 38 Block diagram of UART serial I/O2
Transmit or receive clock
Write-in signal to
transmit buffer register
TBE=0
TSC=0
TBE=1
Serial I/O2 output TXD
TBE=0
TBE=1
ST
D0
D1
SP
TSC=1*
ST
D0
D1
Read-out signal from receive
buffer register
SP
* Generated at 2nd bit in 2-stop
bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit
RBF=0
RBF=1
Serial I/O2 input RXD
ST
D0
D1
SP
Fig. 39 Operation of UART serial I/O2 function
1-38
38B5 Group User’s Manual
RBF=1
ST
D0
D1
SP
HARDWARE
FUNCTIONAL DESCRIPTION
[Serial I/O2 Control Register] SIO2CON (001D16)
ter clears error flags OE, PE, FE, and SE (b3 to b6, respectively).
Writing “0” to the serial I/O2 enable bit (SIOE : b7 of the serial I/O2
control register) also clears all the status flags, including the error
flags.
All bits of the serial I/O2 status register are initialized to “0” at reset,
but if the transmit enable bit (b4) of the serial I/O2 control register
has been set to “1,” the transmit shift register shift completion flag
(b2) and the transmit buffer empty flag (b0) become “1.”
The serial I/O2 control register contains eight control bits for serial
I/O2 functions.
[UART Control Register] UARTCON (001716)
This is a 7 bit register containing four control bits, which are valid
when UART is selected, two control bits, which are valid when using
serial I/O2, and one control bit, which is always valid.
Data format of serial data receive/transfer and the output structure of
the P5 5/TxD pin, etc. are set by this register.
[Serial I/O2 Transmit Buffer Register/Receive
Buffer Register] TB/RB (001F16)
[Serial I/O2 Status Register] SIO2STS (001E16)
The transmit buffer and the receive buffer are located in the same
address. The transmit buffer is write-only and the receive buffer is
read-only. If a character bit length is 7 bits, the MSB of data stored in
the receive buffer is "0".
The read-only serial I/O2 status register consists of seven flags (b0
to b6) which indicate the operating status of the serial I/O2 function
and various errors. Three of the flags (b4 to b6) are only valid in the
UART mode. The receive buffer full flag (b1) is cleared to “0” when
the receive buffer is read.
The error detection is performed at the same time data is transferred
from the receive shift register to the receive buffer register, and the
receive buffer full flag is set. A writing to the serial I/O2 status regis-
b7
b0
[Baud Rate Generator] BRG (001616)
The baud rate generator determines the baud rate for serial transfer.
With the 8-bit counter having a reload register, the baud rate generator divides the frequency of the count source by 1/(n+1), where n is
the value written to the baud rate generator.
b7
Serial I/O2 status register
(SIO2STS : address 001E16)
b0
Serial I/O2 control register
(SIO2CON : address 001D16)
BRG count source selection bit (CSS)
0: f(XIN) or f(XCIN)/2 or f(XCIN)
1: f(XIN)/4 or f(XCIN)/8 or f(XCIN)/4
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
SRDY2 output enable bit (SRDY)
0: P57 pin operates as ordinary I/O pin
1: P57 pin operates as SRDY2 output pin
Overrun error flag (OE)
0: No error
1: Overrun error
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Serial I/O2 mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Not used (returns "1" when read)
b7
b0
Serial I/O2 synchronous clock selection bit (SCS)
0: BRG/ 4
(when clock synchronous serial I/O is selected)
BRG/16 (UART is selected)
1: External clock input
(when clock synchronous serial I/O is selected)
External clock input/16 (UART is selected)
UART control register
(UARTCON : address 001716)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Serial I/O2 enable bit (SIOE)
0: Serial I/O2 disabled
(pins P54 to P57 operate as ordinary I/O pins)
1: Serial I/O2 enabled
(pins P54 to P57 operate as serial I/O pins)
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P55/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
BRG clock switch bit
0: XIN or XCIN (depends on internal system clock)
1: XCIN
Serial I/O2 clock I/O pin selection bit
0: SCLK21 (P57/SCLK22 pin is used as I/O port or SRDY2 output pin.)
1: SCLK22 (P56/SCLK21 pin is used as I/O port.)
Not used (return "1" when read)
Fig. 40 Structure of serial I/O2 related register
38B5 Group User’s Manual
1-39
HARDWARE
FUNCTIONAL DESCRIPTION
FLD Controller
The 38B5 group has fluorescent display (FLD) drive and control circuits.
The FLD controller consists of the following components:
•40 pins for FLD control pins
•FLDC mode register
•FLD data pointer
•FLD data pointer reload register
•Tdisp time set register
•Toff1 time set register
•Toff2 time set register
•Port P0FLD/port switch register
•Port P2FLD/port switch register
•Port P8FLD/port switch register
•Port P8 FLD output control register
•FLD automatic display RAM (max. 160 bytes)
A gradation display mode can be used for bright/dark display as a
display function.
Main
data bus
Main address bus
Local
data bus
FLD/P P20/FLD0
FLD/P P21/FLD1
FLD/P P22/FLD2
8
FLD/P P23/FLD3
FLD/P P24/FLD4
FLD/P P25/FLD5
FLD/P P26/FLD6
FLD/P P27/FLD7
000416
0EFA16
FLD automatic display RAM
0F6016
Local address bus
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
0EF916
0FFF16
P00/FLD8
P01/FLD9
P02/FLD10
8
P03/FLD11
P04/FLD12
P05/FLD13
P06/FLD14
P07/FLD15
000016
P10/FLD16
P11/FLD17
P12/FLD18
8
P13/FLD19
P14/FLD20
P15/FLD21
P16/FLD22
P17/FLD23
000216
FLDC mode register
(0EF416)
FLD data pointer
reload register
(0EF816)
Address
decoder
FLD data pointer
(0EF816)
Timing generator
Fig. 41 Block diagram for FLD control circuit
1-40
38B5 Group User’s Manual
P30/FLD24
P31/FLD25
P32/FLD26
8
P33/FLD27
P34/FLD28
P35/FLD29
P36/FLD30
P37/FLD31
000616
FLD/P P80/FLD32
FLD/P P81/FLD33
FLD/P P82/FLD34
FLD/P P83/FLD35 8
FLD/P P84/FLD36
FLD/P P85/FLD37
FLD/P P86/FLD38
FLD/P P87/FLD39
001016
0EFB16
FLD blanking interrupt
FLD digit interrupt
HARDWARE
FUNCTIONAL DESCRIPTION
[FLDC Mode Register] FLDM
The FLDC mode register is a 8-bit register respectively which is used
to control the FLD automatic display and to set the blanking time
Tscan for key-scan.
b7
b0
FLDC mode register
(FLDM: address 0EF4 16)
Automatic display control bit (P0, P1, P2, P3, P8)
0 : General-purpose mode
1 : Automatic display mode
Display start bit
0 : Stop display
1 : Display
(start to display by switching “0” to “1”)
Tscan control bits
00 : FLD digit interrupt (at rising edge of each digit)
01 : 1 ✕ Tdisp
FLD blanking interrupt
10 : 2 ✕ Tdisp
(at falling edge of the last digit)
11 : 3 ✕ Tdisp
Timing number control bit
0 : 16 timing mode
1 : 32 timing mode
Gradation display mode selection control bit
0 : Not selecting
1 : Selecting (Note)
Tdisp counter count source selection bit
0 : f(XIN)/16 or f(XCIN)/32
1 : f(XIN)/64 or f(XCIN)/128
High-breakdown voltage port drivability selection bit
0 : Drivability strong
1 : Drivability weak
Notes 1: When a gradation display mode is selected, a number of timing is max. 16
timing. (Set the timing number control bit to “0.”)
2: When changing bit 4 (timing number control bit) or bit 5 (gradation display
mode selection control bit), set “0” to bit 1 (display start bit) to perform at
display stop state.
Fig. 42 Structure of FLDC mode register
38B5 Group User’s Manual
1-41
HARDWARE
FUNCTIONAL DESCRIPTION
FLD automatic display pins
This setting is performed by writing a value into the FLD/port switch
register (addresses 0EF916 to 0EFB16 ) of each port.
This setting can be performed in units of bit. When “0” is set, the port
is set to the general-purpose port. When “1” is set, the port is set to
the FLD pin. There is no restriction on whether the FLD pin is to be
used as a segment pin or a digit pin.
When the automatic display control bits of the FLDC mode register
(address 0EF416 ) are set to “1,” the ports of P0, P1, P2, P3 and P8
are used as FLD automatic display pins.
When using the FLD automatic display mode, set each port to the
FLD pin or the general-purpose port using the respective switch register in accordance with the number of segments and the number of
digits.
Table 9 Pins in FLD automatic display mode
Port Name
Automatic Display Pins
Setting Method
P0, P2,
P80–P83
FLD0–FLD15
FLD32–FLD35
The individual bits of the FLD/port switch register (addresses 0EF916–0EFB16 ) can be set each pin
either FLD port (“1”) or general-purpose port (“0”).
P1, P3
P84–P87
FLD16–FLD31
FLD36–FLD39
None (FLD only)
The individual bits of the FLD/port switch register (address 0EFB16) can be set each pin to either
FLD port (“1”) or general-purpose port (“0”).
The output can be reversed by the port P8 FLD output control register (address 0EFC16).
The port output format is the CMOS output format. When using the port as a display pin, a driver
must be installed externally.
Setting example 2
Setting example 1
15
8
Number of segments
Number of digits
Port P2
Port P0
0 P20
0 P21
0 P22
0 P23
1 FLD0(SEG1)
1 FLD1(SEG2)
1 FLD2(SEG3)
1 FLD3(SEG4)
0 P24
0 P25
0 P26
0 P27
1 FLD4(SEG5)
1 FLD5(SEG6)
1 FLD8(SEG1)
1
1
1
1
1
1
1
1
1 FLD6(SEG7)
1 FLD7(SEG8)
0 P01
0 P02
0 P03
0 P04
0 P05
1 FLD14(SEG2)
1 FLD15(SEG3)
Port P1
FLD16(DIG1)
FLD17(DIG2)
FLD18(DIG3)
FLD19(DIG4)
FLD20(SEG4)
FLD21(SEG5)
FLD22(SEG6)
FLD23(SEG7)
Port P3
Port P8
Setting example 3
Setting example 4
18
20
16
10
25
15
FLD11(SEG12)
FLD12(SEG13)
FLD13(SEG14)
FLD14(SEG15)
FLD15(SEG16)
P20
P21
FLD2(SEG1)
1
1
1
1
1
1
1
1
FLD8(DIG1)
FLD19(DIG4)
FLD20(DIG5)
FLD21(DIG6)
FLD22(DIG7)
FLD23(DIG8)
1
1
1
1
1
1
1
1
FLD5(SEG4)
FLD6(SEG5)
FLD7(SEG6)
FLD11(DIG4)
FLD12(DIG5)
FLD13(DIG6)
FLD14(DIG7)
FLD15(DIG8)
FLD23(DIG16)
1
1
1
1
1
1
1
1
FLD24(DIG17)
1
FLD25(DIG18)
FLD26(DIG19)
1
FLD27(DIG20)
1
FLD28(SEG7)
0
FLD29(SEG8)
FLD30(SEG9)
0
FLD19(DIG12)
FLD20(DIG13)
FLD21(DIG14)
FLD22(DIG15)
FLD39(SEG25)
1 FLD39(SEG18)
FLD34(SEG20)
FLD35(SEG21)
FLD36(SEG22)
FLD37(SEG23)
FLD33(SEG12)
FLD34(SEG13)
FLD35(SEG14)
FLD36(SEG15)
FLD37(SEG16)
FLD38(SEG17)
Value of FLD/port switch register
Fig. 43 Segment/Digit setting example
1-42
38B5 Group User’s Manual
FLD7(SEG4)
FLD8(SEG5)
FLD9(SEG6)
FLD10(SEG7)
FLD11(SEG8)
FLD12(SEG9)
FLD13(SEG10)
FLD16(DIG1)
FLD19(DIG4)
FLD20(DIG5)
FLD21(DIG6)
FLD22(DIG7)
FLD23(DIG8)
1
1
1
1
1
1
1
1
1
FLD25(DIG10) 1
FLD14(SEG11) 1
FLD24(DIG9)
1
FLD32(SEG11)
FLD38(SEG24)
FLD33(SEG19)
FLD6(SEG3)
FLD17(DIG2)
FLD18(DIG3)
FLD15(SEG12) 1
FLD26(SEG13) 0
FLD27(SEG14) 0
FLD28(SEG15) 0
FLD29(SEG16) 0
0
FLD31(SEG10) 0
1
1
1
1
1
1
1
FLD32(SEG18)
1
1
1
1
1
1
1
1
FLD9(DIG2)
FLD10(DIG3)
FLD18(DIG11)
1
FLD25(DIG10) 1
FLD26(DIG11) 1
FLD27(DIG12) 1
FLD28(DIG13) 1
FLD29(DIG14) 1
FLD30(DIG15) 1
FLD31(SEG17) 0
P20
P21
P22
P23
0 P24
0 P25
1 FLD4(SEG1)
1 FLD5(SEG2)
FLD4(SEG3)
FLD17(DIG10)
FLD24(DIG9)
0
FLD25(SEG9) 0
FLD26(SEG10) 0
FLD27(SEG11) 0
FLD28(DIG5)
1
FLD29(DIG6)
1
FLD30(DIG7)
1
FLD31(DIG8)
1
0
0
0
0
FLD3(SEG2)
FLD16(DIG9)
1
1
1
1
1
1
1
1
FLD17(DIG2)
FLD18(DIG3)
FLD24(SEG8)
0 P85
0 P86
0 P87
FLD9(SEG10)
FLD10(SEG11)
FLD16(DIG1)
1
1
1
1
0
0
0
0
1 FLD32(SEG12)
1 FLD33(SEG13)
1 FLD34(SEG14)
1 FLD35(SEG15)
0 P84
FLD8(SEG9)
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
P80
P81
P82
P83
P84
P85
P86
P87
Value of FLDRAM write disable register
If data is set to “1”, data is protected.
This setting does not decide the FLD
port function (SEG/DIG).
HARDWARE
FUNCTIONAL DESCRIPTION
FLD automatic display RAM
[FLD Data Pointer and FLD Data Pointer Reload Register]
The FLD automatic display RAM uses the 160 bytes of addresses
0F6016 to 0FFF16 . For FLD, the 3 modes of 16-timing ordinary mode,
16-timing•gradation display mode and 32-timing mode are available
depending on the number of timings and the presence/absence of
gradation display.
The automatic display RAM in each mode is as follows:
(1) 16-timing•Ordinary Mode
The 80 bytes of addresses 0FB016 to 0FFF16 are used as a FLD
display data store area. Because addresses 0F6016 to 0FAF 16
are not used as the automatic display RAM, they can be the ordinary RAM or serial I/O automatic transfer RAM.
(2) 16-timing•Gradation Display Mode
The 160 bytes of addresses 0F6016 to 0FFF16 are used. The 80
bytes of addresses 0FB016 to 0FFF 16 are used as an FLD display data store area, while the 80 bytes of addresses 0F6016 to
0FAF16 are used as a gradation display control data store area.
(3) 32-timing Mode
The 160 bytes of addresses 0F6016 to 0FFF16 are used as an
FLD display data store area.
FLDDP (0EF816)
16-timing•ordinary mode
Both the FLD data pointer and FLD data pointer reload register are
8-bit registers assigned at address 0EF816. When writing data to this
address, the data is written to the FLD data pointer reload register;
when reading data from this address, the value in the FLD data pointer
is read.
16-timing•gradation display mode
0F6016
0F6016
0F6016
Gradation display
control data stored
area
Not used
0FB016
1 to 32 timing display
data stored area
0FB016
1 to 16 timing display
data stored area
0FFF16
32-timing mode
1 to 16 timing display
data stored area
0FFF16
0FFF16
Fig. 44 FLD automatic display RAM assignment
38B5 Group User’s Manual
1-43
HARDWARE
FUNCTIONAL DESCRIPTION
Data setup
(1) 16-timing•Ordinary Mode
The area of addresses 0FB0 16 to 0FFF16 are used as a
FLD automatic display RAM.
When data is stored in the FLD automatic display RAM,
the last data of FLD port P2 is stored at address 0FB0 16 ,
the last data of FLD port P0 is stored at address 0FC0 16 ,
the last data of FLD port P1 is stored at address 0FD0 16 ,
the last data of FLD port P3 is stored at address 0FE0 16 ,
and the last data of FLD port P8 is stored at address 0FF0 16,
to assign in sequence from the last data respectively.
The first data of the FLD port P2, P0, P1, P3, and P8 is stored at
an address which adds the value of (the timing number – 1) to the
corresponding address 0FB0 16, 0FC0 16 , 0FD016 , 0FE016, and
0FF016 .
Set the FLD data pointer reload register to the value given by the
timing number – 1. “1” is always written to bits 7, 6, and 5. Note
that “0” is always read from bits 7, 6, and 5 when reading. “1” is
always set to bit 4, but this bit become written value when reading.
(2) 16-timing•Gradation Display Mode
Display data setting is performed in the same way as that of the
16-timing•ordinary mode. Gradation display control data is arranged at an address resulting from subtracting 0050 16 from
the display data store address of each timing and pin. Bright display is performed by setting “0,” and dark display is performed by
setting “1.”
Set the FLD data pointer reload register to the value given by the
timing number – 1. “1” is always written to bits 7, 6, and 5. Note
that “0” is always read from bits 7, 6, and 5 when reading. “1” is
always set to bit 4, but this bit become written value when reading.
(3) 32-timing Mode
The area of addresses 0F6016 to 0FFF16 are used as a FLD automatic display RAM. When data is stored in the FLD automatic
display RAM, the last data of FLD port P2 is stored at address
0F6016 , the last data of FLD port P0 is stored at address 0F8016 ,
the last data of FLD port P1 is stored at address 0FA0 16 ,
the last data of FLD port P3 is stored at address 0FC0 16 ,
and the last data of FLD port P8 is stored at address 0FE0 16,
to assign in sequence from the last data respectively.
The first data of the FLD port P2, P0, P1, P3, and P8 is stored
at an address which adds the value of (the timing number – 1)
to the corresponding address 0F6016 , 0F8016, 0FA016 , 0FC016,
and 0FE0 16.
Set the FLD data pointer reload register to the value given by
the timing number –1. “1” is always written to bits 7, 6, and 5.
Note that “0” is always read from bits 7, 6, and 5 when reading.
Number of FLD segments: 15
Number of timing: 8
(FLD data pointer reload register = 7)
Bit
Address
0FB016
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
0FEA16
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
0FFA16
0FFB16
0FFC16
0FFD16
0FFE16
0FFF16
Note:
7
6
5
4
3
2
1
0
The last timing
(The last data of FLDP2)
Timing for start
(The first data of FLDP2)
FLDP2 data area
The last timing
(The last data of FLDP0)
Timing for start
(The first data of FLDP0)
FLDP0 data area
The last timing
(The last data of FLDP1)
Timing for start
(The first data of FLDP1)
FLDP1 data area
The last timing
(The last data of FLDP3)
Timing for start
(The first data of FLDP3)
FLDP3 data area
The last timing
(The last data of FLDP8)
Timing for start
(The first data of FLDP8)
FLDP8 data area
shaded area is used for segment.
shaded area is used for digit.
Fig. 45 Example of using FLD automatic display RAM in
16-timing•ordinary mode
1-44
38B5 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Number of FLD segments: 25
Number of timing: 15
(FLD data pointer reload register = 14)
Bit
Address
0FB016
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
0FEA16
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
0FFA16
0FFB16
0FFC16
0FFD16
0FFE16
0FFF16
Note:
7
6
5
4
3
2
1
Bit
0
Address
The last timing
(The last data of FLDP2)
FLDP2 data area
Timing for start
(The first data of FLDP2)
The last timing
(The last data of FLDP0)
FLDP0 data area
Timing for start
(The first data of FLDP0)
The last timing
(The last data of FLDP1)
FLDP1 data area
Timing for start
(The first data of FLDP1)
The last timing
(The last data of FLDP3)
FLDP3 data area
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP8)
FLDP8 data area
Timing for start
(The first data of FLDP8)
shaded area is used for segment.
shaded area is used for digit.
0F6016
0F6116
0F6216
0F6316
0F6416
0F6516
0F6616
0F6716
0F6816
0F6916
0F6A16
0F6B16
0F6C16
0F6D16
0F6E16
0F6F16
0F7016
0F7116
0F7216
0F7316
0F7416
0F7516
0F7616
0F7716
0F7816
0F7916
0F7A16
0F7B16
0F7C16
0F7D16
0F7E16
0F7F16
0F8016
0F8116
0F8216
0F8316
0F8416
0F8516
0F8616
0F8716
0F8816
0F8916
0F8A16
0F8B16
0F8C16
0F8D16
0F8E16
0F8F16
0F9016
0F9116
0F9216
0F9316
0F9416
0F9516
0F9616
0F9716
0F9816
0F9916
0F9A16
0F9B16
0F9C16
0F9D16
0F9E16
0F9F16
0FA016
0FA116
0FA216
0FA316
0FA416
0FA516
0FA616
0FA716
0FA816
0FA916
0FAA16
0FAB16
0FAC16
0FAD16
0FAE16
0FAF16
Note:
7
6
5
4
3
2
1
0
The last timing
(The last data of FLDP2)
FLDP2 gradation
display data area
Timing for start
(The first data of FLDP2)
The last timing
(The last data of FLDP0)
FLDP0 gradation
display data area
Timing for start
(The first data of FLDP0)
The last timing
(The last data of FLDP1)
FLDP1 gradation
display data area
Timing for start
(The first data of FLDP1)
The last timing
(The last data of FLDP3)
FLDP3 gradation
display data area
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP8)
FLDP8 gradation
display data area
Timing for start
(The first data of FLDP8)
shaded area is used for gradation display data.
Fig. 46 Example of using FLD automatic display RAM in 16-timing•gradation display mode
38B5 Group User’s Manual
1-45
HARDWARE
FUNCTIONAL DESCRIPTION
Number of FLD segments: 18
Number of timing: 20
(FLD data pointer reload register = 19)
Bit
Address
0FB016
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
0FEA16
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
0FFA16
0FFB16
0FFC16
0FFD16
0FFE16
0FFF16
Note:
7
6
5
4
3
2
1
Bit
0
Address
Timing for start
(The first data of FLDP1)
The last timing
(The last data of FLDP3)
FLDP3 data area
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP8)
FLDP8 data area
Timing for start
(The first data of FLDP8)
7
6
0F6016
0F6116
0F6216
0F6316
0F6416
0F6516
0F6616
0F6716
0F6816
0F6916
0F6A16
0F6B16
0F6C16
0F6D16
0F6E16
0F6F16
0F7016
0F7116
0F7216
0F7316
0F7416
0F7516
0F7616
0F7716
0F7816
0F7916
0F7A16
0F7B16
0F7C16
0F7D16
0F7E16
0F7F16
0F8016
0F8116
0F8216
0F8316
0F8416
0F8516
0F8616
0F8716
0F8816
0F8916
0F8A16
0F8B16
0F8C16
0F8D16
0F8E16
0F8F16
0F9016
0F9116
0F9216
0F9316
0F9416
0F9516
0F9616
0F9716
0F9816
0F9916
0F9A16
0F9B16
0F9C16
0F9D16
0F9E16
0F9F16
0FA016
0FA116
0FA216
0FA316
0FA416
0FA516
0FA616
0FA716
0FA816
0FA916
0FAA16
0FAB16
0FAC16
0FAD16
0FAE16
0FAF16
shaded area is used for segment.
shaded area is used for digit.
Fig. 47 Example of using FLD automatic display RAM in 32-timing mode
1-46
38B5 Group User’s Manual
5
4
3
2
1
0
The last timing
(The last data of FLDP2)
FLDP2 data area
Timing for start
(The first data of FLDP2)
The last timing
(The last data of FLDP0)
FLDP0 data area
Timing for start
(The first data of FLDP0)
The last timing
(The last data of FLDP1)
FLDP1 data area
HARDWARE
FUNCTIONAL DESCRIPTION
Digit data protect function
The FLD automatic display RAM is provided with a data protect
function that disables the RAM area data to be rewritten as digit
data.
This function can disable data from being written in optional bits in
the RAM area corresponding to P1 to P3. A programming load can
be reduced by protecting an area that requires no change after
data such as digit data is written.
Write digit data beforehand; then set “1” in the corresponding bits.
With this, the setting is completed.
The data protect area becomes the maximum RAM area of P1 and
P3. For example, when bit 0 of P1 is protected in the 16timing•ordinary mode, bits 0 of RAM addresses 0FD016 to 0FDF16
can be protected. Likewise, in the 16-timing•gradation display mode,
bits 0 of addresses 0FD016 to 0FDF16 and 0F8016 to 0F8F16 can be
protected. In the 32-timing mode, bits 0 of addresses 0FA016 to
0FBF16 can be protected.
b7
b7
b0
P1FLDRAM write disable register
(P1FLDRAM : address 0EF216)
b0
P3FLDRAM write disable register
(P3FLDRAM : address 0EF316)
FLDRAM corresponding to P10
FLDRAM corresponding to P30
FLDRAM corresponding to P11
FLDRAM corresponding to P31
FLDRAM corresponding to P12
FLDRAM corresponding to P32
FLDRAM corresponding to P13
FLDRAM corresponding to P33
FLDRAM corresponding to P14
FLDRAM corresponding to P34
FLDRAM corresponding to P15
FLDRAM corresponding to P35
FLDRAM corresponding to P16
FLDRAM corresponding to P36
FLDRAM corresponding to P17
FLDRAM corresponding to P37
0: Operating normally
1: Write disabled
0: Operating normally
1: Write disabled
Fig. 48 Structure of FLDRAM write disable register
38B5 Group User’s Manual
1-47
HARDWARE
FUNCTIONAL DESCRIPTION
Setting method when using the grid scan type FLD
When using the grid scan type FLD, set “1” in the RAM area corresponding to the digit ports that output “1” at each timing. Set “0” in
the RAM area corresponding to the other digit ports.
Number of timing: 10
The first second
third.......................9th
10th
DIG10 (P31)
DIG9 (P30)
DIG8 (P17)
DIG2 (P11)
DIG1 (P10)
Segment output
Fig. 49 Example of digit timing using grid scan type
Number of FLD segments: 16
Number of timing: 10
(FLD data pointer reload register = 9)
Bit
Address
0FB016
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
0FEA16
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
0FFA16
0FFB16
0FFC16
0FFD16
0FFE16
0FFF16
Note:
7
6
5
4
3
2
1
0
The last timing
(The last data of FLDP2)
FLDP2 data area
Timing for start
(The first data of FLDP2)
The last timing
(The last data of FLDP0)
FLDP0 data area
Timing for start
(The first data of FLDP0)
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
The last timing
(The last data of FLDP1)
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
The last timing
(The last data of FLDP3)
FLDP1 data area
Timing for start
(The first data of FLDP1)
FLDP3 data area
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP8)
FLDP8 data area
Timing for start
(The first data of FLDP8)
shaded area is used for segment.
shaded area is used for digit.
Fig. 50 Example of using FLD automatic display RAM
using grid scan type
1-48
38B5 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Timing setting
Key-scan
Each timing is set by the FLDC mode register, Tdisp time set register, Toff1 time set register, and Toff2 time set register.
•Tdisp time setting
Set the Tdisp time by the Tdisp counter count source selection bit of
the FLDC mode register and the Tdisp time set register.
Supposing that the value of the Tdisp time set register is n, the
Tdisp time is represented as Tdisp = (n+1) ✕ t (t: count source
synchronization).
When the Tdisp counter count source selection bit of the FLDC mode
register is “0” and the value of the Tdisp time set register is 200
(C816 ), the Tdisp time is: Tdisp = (200+1) ✕ 4 (at XIN= 4 MHz) = 804
µs. When reading the Tdisp time set register, the value in the
counter is read out.
•Toff1 time setting
Set the Toff1 time by the Toff1 time set register.
Supposing that the value of the Toff1 time set register is n1, the
Toff1 time is represented as Toff1 = n1 ✕ t.
When the Tdisp counter count source selection bit of the FLDC mode
register is “0” and the value of the Toff1 time set register is 30
(1E16), Toff1 = 30 ✕ 4 (at XIN = 4 MHz) = 120 µs.
Set a value of 0316 or more to the Toff1 time set register (address
0EF616).
•Toff2 time setting
Set the Toff2 time by the Toff2 time set register.
Supposing that the value of the Toff2 time set register is n2, the
Toff2 time is represented as Toff2 = n2 ✕ t.
When the Tdisp counter count source selection bit of the FLDC mode
register is “0” and the value of the Toff2 time set register is 180
(B416), Toff2 = 180 ✕ 4 (at XIN = 4 MHz) = 720 µs.
This Toff2 time setting is valid only for FLD ports which are in the
gradation display mode and whose gradation display control RAM
value is “1.”
When setting “1” to bit 7 of the P8FLD output control register (address 0EFC16 ), set a value of 03 16 or more to the Toff2 time set
register (address 0EF716).
When a key-scan is performed with the segment during key-scan
blanking period Tscan, take the following sequence:
1. Write “0” to bit 0 of the FLDC mode register (address 0EF416).
2. Set the port corresponding to the segment for key-scan to the
output port.
3. Perform the key-scan.
4. After the key-scan is performed, write “1” to bit 0 of FLDC mode
register (address 0EF416).
■ Note
When performing a key-scan according to the above step 1 to 4, take
the following points into consideration.
1. Do not set “0” in bit 1 of the FLDC mode register (address 0EF4 16).
2. Do not set “1” in the ports corresponding to digits.
FLD automatic display start
To perform FLD automatic display, set the following registers.
•Port P0FLD/port switch register
•Port P2FLD/port switch register
•Port P8FLD/port switch register
•FLDC mode register
•Tdisp time set register
•Toff1 time set register
•Toff2 time set register
•FLD data pointer
FLD automatic display mode is selected by writing “1” to the bit 0 of
the FLDC mode register (address 0EF4 16 ), and the automatic display is started by writing “1” to bit 1. During FLD automatic display,
bit 1 of the FLDC mode register (address 0EF416) always keeps “1,”
and FLD automatic display can be interrupted by writing “0” to bit 1.
38B5 Group User’s Manual
1-49
HARDWARE
FUNCTIONAL DESCRIPTION
Repeat synchronous
Tdisp
Segment
Digit output
Tn
Tscan
Tn-1 Tn-2
T4
T3
FLD digit interrupt request occurs at the rising
edge of digit (each timing).
T2
T1
Segment setting by software
FLD blanking interrupt request occurs
at the falling edge of the last timing.
Segment
Digit
Toff1
Tdisp
Segment
Digit
When a gradation display mode is selected
Toff1
Toff2
Tdisp
n: Number of timing
Fig. 51 FLDC timing
1-50
38B5 Group User’s Manual
Pin under the condition that bit 5 of the
FLDC mode register is “1,” and the
corresponding gradation display control
data value is “1.”
HARDWARE
FUNCTIONAL DESCRIPTION
P84 to P87 FLD output reverse function
P84 to P87 are provided with a function to reverse the polarity of the
FLD output. This function is useful in adjusting the polarity when
using an externally installed driver.
The output polarity can be reversed by setting “1” to bit 0 of the port
P8 FLD output control register.
P84 to P87 FLDRAM write disable function
This function can disable writing data in the RAM area corresponding to P8 4 to P87. This function can be set by setting “1” to bit 1 of the
port P8FLD output control register (address 0EFC16 ).
Segment
Digit
At Toff2 control bit = “0” in
gradation display mode
(at gradation display
control data= “1”)
At Toff2 control bit = “1” in
gradation display mode
(at gradation display
control data= “1”)
Toff1
Toff2
Tdisp
P84 to P87 Toff invalid function
P8 4 to P87 can output waveform in which Toff is invalid, when P84 to
P87 is selected FLD ports (See Figure 52).
The function is useful when using a 4 bits →16 bits decoder. The Toff
can be invalid by setting “1” to bit 2 of the port P8FLD output control
register (address 0EFC 16).
Dimmer signal
P84–P87
Toff invalid
P84–P87
Toff invalid
Delay
P84 to P87 output delay function
P8 4 to P87 can output waveform in which is delayed for 16 µs, when
selecting FLD port and selecting Toff invalid function (See Figure
52). When using a 4 bits →16 bits decoder, the function can be useful for prevention of leak radiation caused by phase discrepancy between segment output waveform and digit output waveform. This function can be set by setting “1” to bit 3 of the port P8FLD output control
register (address 0EFC 16).
Dimmer signal output function
P63 can output the dimmer signal. When using a 4 bits →16 bits
decoder, the dimmer signal can be used as a control signal for a 4
bits →16 bits decoder. When using M35501FP, the dimmer signal
can be used as the CLK signal. The dimmer signal can be output by
setting “1” to bit 4 of the port P8FLD output control register (address
0EFC16).
b7
16 µs
Fig. 52 P84 to P87 FLD output waveform
Toff2 SET/RESET change function
The value of the Toff2 time set register is valid when gradation display mode is selected. The FLD ports output (set) the data of display
RAM at the end of the Toff1 time and output “0” (reset) at the end of
the Toff2 time, when bit 7 of the port P8FLD output control register is
“0”.
The FLD ports output (set) the data of display RAM at the end of the
Toff2 time and output “0” (reset) at the end of Tdisp time, when bit 7
of the port P8FLD output control register is “1”.
b0
Port P8FLD output control register
(P8FLDCON: address 0EFC 16)
P84–P87 FLD output reverse bit
0: Output normally
1: Reverse output
P84–P87 FLDRAM write disable bit
0: Operating normally
1: Write disabled
P84–P87 Toff invalid bit
0: Operating normally
1: Toff invalid
P84–P87 delay control bit (Note)
0: No delay
1: Delay
P63/AN9 dimmer output control bit
0: Ordinary port
1: Dimmer output
Not used (“0” at reading)
Toff2 control bit
0: Gradation display data is reset at Toff2
(set at Toff1)
1: Gradation display data is set at Toff2
(reset at Tdisp)
Note: Valid only when selecting FLD port and P8 4–P87 Toff invalid function
Fig. 53 Structure of port P8 FLD output control register
38B5 Group User’s Manual
1-51
HARDWARE
FUNCTIONAL DESCRIPTION
A-D Converter
The 38B5 group has a 10-bit A-D converter. The A-D converter performs successive approximation conversion.
conversion interrupt request bit to “1.”
Note that the comparator is constructed linked to a capacitor, so set
f(X IN) to at least 250 kHz during A-D conversion. Use a CPU system
clock dividing the main clock XIN as the internal system clock.
[A-D Conversion Register] AD
One of these registers is a high-order register, and the other is a loworder register. The high-order 8 bits of a conversion result is stored
in the A-D conversion register (high-order) (address 003416 ), and
the low-order 2 bits of the same result are stored in bit 7 and bit 6 of
the A-D conversion register (low-order) (address 003316 ).
During A-D conversion, do not read these registers.
b7
b0
A-D control register
(ADCON: address 0032 16)
Analog input pin selection bits
0000: P70/AN0
0001: P71/AN1
0010: P72/AN2
0011: P73/AN3
0100: P74/AN4
0101: P75/AN5
0110: P76/AN6
0111: P77/AN7
1000: P62/SRDY1/AN8
1001: P63/AN9
1010: P64/INT4/SBUSY1/AN10
1011: P65/SSTB1/AN11
[A-D Control Register] ADCON
This register controls A-D converter. Bits 3 to 0 are analog input pin
selection bits. Bit 4 is an AD conversion completion bit and “0” during
A-D conversion. This bit is set to “1” upon completion of A-D conversion.
A-D conversion is started by setting “0” in this bit.
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
[Comparison Voltage Generator]
Not used (returns “0” when read)
The comparison voltage generator divides the voltage between AVSS
and VREF, and outputs the divided voltages.
b7
[Channel Selector]
b0
A-D conversion register (high-order)
(ADH: address 0034 16)
The channel selector selects one of the input ports P77/AN7–P70/
AN0, and P65/SSTB1/AN11 –P62/SRDY1 /AN8 and inputs it to the comparator.
When port P64 is selected as an analog input pin, an external interrupt function (INT4) is invalid.
AD conversion result stored bits
b7
b0
A-D conversion register (low-order)
(ADL: address 0033 16)
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input
voltage with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
Not used (returns “0” when read)
AD conversion result stored bits
Fig. 54 Structure of A-D control register
Data bus
b7
b0
A-D control register
4
A-D control circuit
Channel selector
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6
P77/AN7
P62/SRDY1/AN8
P63/AN9
P64/INT4/SBUSY1/AN10
P65/SSTB1/AN11
Comparator
A-D interrupt request
A-D conversion register (H) A-D conversion register (L)
(Address 003416)
Resistor ladder
AVSS @VREF
Fig. 55 Block diagram of A-D converter
1-52
(Address 003316)
38B5 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Pulse Width Modulation (PWM)
The 38B5 group has a PWM function with a 14-bit resolution. When
the oscillation frequency XIN is 4 MHz, the minimum resolution bit
width is 250 ns and the cycle period is 4096 µs. The PWM timing
generator supplies a PWM control signal based on a signal that is
the frequency of the XIN clock.
The explanation in the rest assumes X IN = 4 MHz.
Data bus
It is set to “1”
when write.
bit7
PWM register (low-order)
(address 001516)
bit7
bit5
bit0
bit0
PWM register (high-order)
(address 001416)
PWM latch (14-bit)
MSB
LSB
14
P87 latch
P87/PWM0
14-bit PWM circuit
XCIN
XIN
(4MHz)
When an internal
1/2
system clock
selection bit is set
(64 µs cycle)
Timing
“1”
to “0”
generating
unit for PWM (4096 µs cycle)
“0”
PWM
P87/PWM output
selection bit
P87/PWM output
selection bit
P87 direction
register
Fig. 56 PWM block diagram
38B5 Group User’s Manual
1-53
HARDWARE
FUNCTIONAL DESCRIPTION
1. Data setup
The PWM output pin also function as port P87. Set port P87 to be the
PWM output pin by setting bit 0 of the PWM control register (address
002616) to “1.” The high-order 8 bits of output data are set in the
high-order PWM register PWMH (address 001416) and the low-order
6 bits are set in the low-order PWM register PWML (address 001516).
3. Transfer from register to latch
Data written to the PWML register is transferred to the PWM latch
once in each PWM period (every 4096 µs), and data written to the
PWMH register is transferred to the PWM latch once in each subperiod (every 64 µs). When the PWML register is read, the contents
of the latch are read. However, bit 7 of the PWML register indicates
whether the transfer to the PWM latch is completed; the transfer is
completed when bit 7 is “0.”
2. PWM operation
The timing of the 14-bit PWM function is shown in Figure 57.
The 14-bit PWM data is divided into the low-order 6 bits and the
high-order 8 bits in the PWM latch.
The high-order 8 bits of data determine how long an “H” level signal
is output during each sub-period. There are 64 sub-periods in each
period, and each sub-period t is 256 ✕ τ (= 64 µs) long. The signal’s
“H” has a length equal to N times τ, and its minimum resolution = 250
ns.
The last bit of the sub-period becomes the ADD bit which is specified
either “H” or “L,” by the contents of PWML. As shown in Table 10, the
ADD bit is decided either “H” or “L.”
That is, only in the sub-period tm shown in Table 10 in the PWM
cycle period T = 64t, the “H” duration is lengthened during the minimum resolution width τ period in comparison with the other period.
For example, if the high-order eight bits of the 14-bit data are “0316 ”
and the low-order six bits are “0516,” the length of the “H” level output
in sub-periods t8, t24 , t32 , t40 and t56 is 4 τ, and its length 3 τ in all
other sub-periods.
Time at the “H” level of each sub-period almost becomes equal because the time becomes length set in the high-order 8 bits or becomes the value plus τ, and this sub-period t (= 64 µs, approximate
15.6 kHz) becomes cycle period approximately.
Table 10 Relationship between low-order 6-bit data and setting
period of ADD bit
Low-order
Sub-periods tm lengthened (m = 0 to 63)
6-bit data
LSB
000000
000001
000010
None
000100
001000
010000
100000
m = 8, 24, 40, 56
m = 32
m = 16, 48
m = 4, 12, 20, 28, 36, 44, 52, 60
m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62
m = 1, 3, 5, 7, .................................................., 57, 59, 61, 63
4096 µs
64 µs
64 µs
m=0
15.75 µs
m=7
15.75 µs
15.75 µs
64 µs
m=8
16.0 µs
64 µs
64 µs
m=9
15.75 µs
m = 63
15.75 µs
15.75 µs
Pulse width modulation register H: 00111111
Pulse width modulation register L: 000101
Sub-periods where “H” pulse width is 16.0 µs: m = 8, 24, 32, 40, 56
Sub-periods where “H” pulse width is 15.75 µs: m = all other values
Fig. 57 PWM timing
1-54
38B5 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
PWM control register
(PWMCON: address 0026 16)
P87/PWM output selection bit
0: I/O port
1: PWM output
Not used (return “0” when read)
Fig. 58 Structure of PWM control register
Data 6A16 stored at address 001416
PWM register
(high-order)
5916
Data 7B16 stored at address 001416
6A16
7B16
Data 2416 stored at address 001516
PWM register
(low-order)
1316
Bit 7 cleared after transfer
A416
Data 3516 stored at address 001516
2416
3516
Transfer from register to latch
PWM latch
(14-bit)
165316
1A9316
Transfer from register to latch
B516
1AA416
1AA416
1EE416
1EF516
When bit 7 of PWML is “0,” transfer
from register to latch is disabled.
T = 4096 µs
(64 ✕ 64 µs)
t = 64 µs
6A
(Example 1)
6B
6A
6B
6A
6B
6A
6B
6A
6B
6B
5
2
5
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
PWM output
1
Low-order 6-bits
output
H = 6A16
L = 2416
5
5
5
6B16............36 times
(107)
6A
(Example 2)
5
6A
6A
6A
6B
6A
5
5
6A
6B
6A
6A
6A
5
5
5
5
5
106 ✕ 64 + 36
6A16............28 times
(106)
6B
5
6B
6A
6B
6A
6B
6A
6A
6A
6B
6A
6B
6A
6B
6A
6A
PWM output
Low-order 6 bits
output
H = 6A16
L = 1816
4
3
4
6B16............24 times
4
3
4
6A16............40 times
4
3
4
106 ✕ 64 + 24
t = 64 µs
(256 ✕ 0.25 µs)
Minimum bit width
PWM output
6B
τ = 0.25 µs
6A
69
68
67
.........
02
01
6A
69
68
67
..........
02
01
FF
FE
FD
FC
..........
97
96
2
ADD
8-bit counter
02
01
The ADD portions with
additional τ are determined
either “H” or “L” by low-order
6-bit data.
00
ADD
FF
FE
FD
FC
..........
97
96
95
..........
02
01
00
95
............
“H” period length specified by PWMH
256
τ (64 µs), fixed
Fig. 59 14-bit PWM timing
38B5 Group User’s Manual
1-55
HARDWARE
FUNCTIONAL DESCRIPTION
Interrupt Interval Determination Function
The 38B5 group has an interrupt interval determination circuit.
This interrupt interval determination circuit has an 8-bit binary up
counter. Using this counter, it determines a duration of time from the
rising edge (falling edge) of an input signal pulse on the P47/INT2 pin
to the rising edge (falling edge) of the signal pulse that is input next.
How to determine the interrupt interval is described below.
1. Enable the INT2 interrupt by setting bit 2 of the interrupt control
register 1 (address 003E16). Select the rising interval or falling
interval by setting bit 2 of the interrupt edge selection register
(address 003A16).
2. Set bit 0 of the interrupt interval determination control register
(address 003116 ) to “1” (interrupt interval determination operating).
3. Select the sampling clock of 8-bit binary up counter by setting bit
1 of the interrupt interval determination control register. When
writing “0,” f(XIN)/128 is selected (the sampling interval: 32 µs at
f(XIN) = 4.19 MHz); when “1,” f(XIN)/256 is selected (the sampling
interval: 64 µs at f(XIN) = 4.19 MHz).
4. When the signal of polarity which is set on the INT2 pin (rising or
falling edge) is input, the 8-bit binary up counter starts counting up of the selected counter sampling clock.
5. When the signal of polarity above 4 is input again, the value of the
8-bit binary up counter is transferred to the interrupt interval
determination register (address 003016 ), and the remote control
interrupt request occurs. Immediately after that, the 8-bit binary
up counter continues to count up again from “0016.”
6. When count value reaches “FF16,” the 8-bit binary up counter stops
counting up. Then, simultaneously when the next counter sampling clock is input, the counter sets value “FF16 ” to the interrupt
interval determination register to generate the counter overflow
interrupt request.
Counter sampling
clock selection bit
f(XIN)/128
f(XIN)/256
Noise filter
INT2 interrupt input
Noise filter
The P47/INT2 pin builds in the noise filter.
The noise filter operation is described below.
1. Select the sampling clock of the input signal with bits 2 and 3 of
the interrupt interval determination control register. When not
using the noise filter, set “00.”
2. The P47/INT 2 input signal is sampled in synchronization with the
selected clock. When sampling the same level signal in a series
of three sampling, the signal is recognized as the interrupt
signal, and the interrupt request occurs.
When setting bit 4 of interrupt interval determination control
register to “1,” the interrupt request can occur at both rising and
falling edges.
When using the noise filter, set the minimum pulse width of the
INT2 input signal to 3 cycles or more of the sample clock.
Note: In the low-speed mode (CM 7 = 1), the interrupt interval determination function cannot operate.
8-bit binary up
counter
Interrupt interval
determination register
address 003016
One-sided/both-sided
detection selection bit
Noise filter sampling
clock selection bit
1/128
1/32
1/64
Data bus
Divider
f(XIN)
Fig. 60 Interrupt interval determination circuit block diagram
1-56
38B5 Group User’s Manual
Counter overflow
interrupt request
or remote control
interrupt request
HARDWARE
FUNCTIONAL DESCRIPTION
b7
b0
Interrupt interval determination control register
(IIDCON: address 003116)
Interrupt interval determination circuit operating selection bit
0 : Stopped
1 : Operating
Counter sampling clock selection bit
0 : f(XIN)/128
1 : f(XIN)/256
Noise filter sampling clock selection bits (INT2)
00 : Filter stop
01 : f(XIN)/32
10 : f(XIN)/64
11 : f(XIN)/128
One-sided/both-sided edge detection selection bit
0 : One-sided edge detection
1 : Both-sided edge detection (can be used when using a noise filter)
Not used (return “0” when read)
Fig. 61 Structure of interrupt interval determination control register
(When IIDCON4 = “0”)
Noise filter
sampling clock
INT2 pin
Acceptance of
interrupt
Counter sampling
clock
N
8-bit binary up
counter value
2
1
0
3
2
1
0
FF
N
FF
6
Counter overflow
interrupt request
Remote control
interrupt request
Remote control
interrupt request
1
0
6
N
Interrupt interval
determination
register value
FF
FE
6
5
4
3
Fig. 62 Interrupt interval determination operation example (at rising edge active)
(When IIDCON4 = “1”)
Noise filter
sampling clock
INT2 pin
Acceptance of
interrupt
Counter sampling
clock
FE
N
8-bit binary up
counter value
0
1
N
Interrupt interval
determination
register value
2
0
2
N
Remote control
interrupt request
2
1
0
1
3
2
Remote control
interrupt request
3
2
0
1
2
2
Remote control
interrupt request
Remote control
interrupt request
0
1
FF
2
3
FF
FF
Counter overflow
interrupt request
Fig. 63 Interrupt interval determination operation example (at both-sided edge active)
38B5 Group User’s Manual
1-57
HARDWARE
FUNCTIONAL DESCRIPTION
Watchdog Timer
“0,” the underflow signal of watchdog timer L becomes the count
source. The detection time is set then to f(XIN ) = 2.1 s at 4 MHz
frequency and f(X CIN) = 512 s at 32 kHz frequency.
When this bit is set to “1,” the count source becomes the signal
divided by 8 for f(XIN) (or divided by 16 for f(X CIN)). The detection
time in this case is set to f(XIN) = 8.2 ms at 4 MHz frequency and
f(X CIN) = 2 s at 32 KHz frequency. This bit is cleared to “0” after
resetting.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because
of a software runaway). The watchdog timer consists of an 8-bit watchdog timer L and a 12-bit watchdog timer H.
●Standard operation of watchdog timer
When any data is not written into the watchdog timer control register
(address 002B16 ) after resetting, the watchdog timer is in the stop
state. The watchdog timer starts to count down by writing an optional
value into the watchdog timer control register (address 002B16 ) and
an internal reset occurs at an underflow of the watchdog timer H.
Accordingly, programming is usually performed so that writing to the
watchdog timer control register (address 002B16) may be started
before an underflow. When the watchdog timer control register
(address 002B16) is read, the values of the high-order 6 bits of the
watchdog timer H, STP instruction disable bit, and watchdog timer H
count source selection bit are read.
(3) Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 002B16) permits
disabling the STP instruction when the watchdog timer is in operation.
When this bit is “0,” the STP instruction is enabled.
When this bit is “1,” the STP instruction is disabled.
Once the STP instruction is executed, an internal resetting occurs.
When this bit is set to “1,” it cannot be rewritten to “0” by program.
This bit is cleared to “0” after resetting.
■ Note
(1) Initial value of watchdog timer
At reset or writing to the watchdog timer control register (address
002B16), a watchdog timer H is set to “FFF16 ” and a watchdog timer
L to “FF16.”
When releasing the stop mode, the watchdog timer performs its count
operation even in the stop release waiting time. Be careful not to
cause the watchdog timer H to underflow in the stop release waiting
time, for example, by writing data in the watchdog timer control register (address 002B16) before executing the STP instruction.
(2) Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 002B16 ) permits
selecting a watchdog timer H count source. When this bit is set to
XCIN
“FF16” is set when
watchdog timer
control register is
written to.
1/2
“0”
“1”
Internal system clock
selection bit
(Note)
Data bus
Watchdog timer L (8)
1/8
“1”
“0”
Watchdog timer H (12)
“FFF16” is set
when watchdog
timer control
register is written
to.
Watchdog timer H count
source selection bit
XIN
STP instruction disable bit
STP instruction
Reset
circuit
RESET
Internal reset
Note: Either high-speed, middle-speed or low-speed mode is selected by bit 7 of CPU mode register.
Fig. 64 Block diagram of watchdog timer
b0
b7
Watchdog timer control register
(WDTCON : address 002B16)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/8 or f(XCIN)/16
Fig. 65 Structure of watchdog timer control register
1-58
38B5 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Buzzer Output Circuit
The 38B5 group has a buzzer output circuit. One of 1 kHz, 2 kHz and
4 kHz (at XIN = 4.19 MHz) frequencies can be selected by the buzzer
output control register (address 0EFD 16). Either P43/B UZ01 or P20/
BUZ02/FLD0 can be selected as a buzzer output port by the output
port selection bits (b2 and b3 of address 0EFD16 ).
The buzzer output is controlled by the buzzer output ON/OFF bit
(b4).
Port latch
f(XIN)
Divider
1/1024
1/2048
1/4096
Buzzer output
Buzzer output ON/OFF bit
Output port control signal
Port direction register
Fig. 66 Block diagram of buzzer output circuit
b7
b0
Buzzer output control register
(BUZCON: address 0EFD16)
Output frequency selection bits (X IN = 4.19 MHz)
00 : 1 kHz (f(XIN)/4096)
01 : 2 kHz (f(XIN)/2048)
10 : 4 kHz (f(XIN)/1024)
11 : Not available
Output port selection bits
00 : P20 and P43 function as ordinary ports.
01 : P43/BUZ01 functions as a buzzer output.
10 : P20/BUZ02 /FLD0 functions as a buzzer output.
11 : Not available
Buzzer output ON/OFF bit
0 : Buzzer output OFF (“0” output)
1 : Buzzer output ON
Not used (return “0” when read)
Fig. 67 Structure of buzzer output control register
38B5 Group User’s Manual
1-59
HARDWARE
FUNCTIONAL DESCRIPTION
Reset Circuit
______
Poweron
To reset the microcomputer, RESET
pin should be held at an “L”
______
level for 2 µs or more. Then the RESET pin is returned to an “H” level
(the power source voltage should be between 2.7 V and 5.5 V, and
the oscillation should be stable), reset is released. After the reset is
completed, the program starts from the address contained in address
FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make
sure that the reset input voltage is less than 0.5 V for VCC of 2.7 V
(switching to the high-speed mode, a power source voltage must be
between 4.0 V and 5.5 V).
RESET
VCC
Power source
voltage
0V
Reset input
voltage
0V
(Note)
0.2VCC
Note : Reset release voltage ; Vcc=2.7 V
RESET
VCC
Power source
voltage detection
circuit
Fig. 68 Reset circuit example
XIN
φ
RESET
Internal
reset
Address
?
?
?
?
FFFC
FFFD
ADL
Data
ADH, ADL
ADH
SYNC
XIN: about 4000 cycles
Notes 1: The frequency relation of f(X IN) and f(φ) is f(XIN)=4 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 69 Reset sequence
1-60
38B5 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Address Register contents
Address Register contents
(1) Port P0
000016
0016
(33) Timer 34 mode register
002916
0016
(2) Port P0 direction register
000116
0016
(34) Timer 56 mode register
002A16
0016
(3) Port P1
000216
0016
(35) Watchdog timer control register
002B16
3F16
(4) Port P2
000416
0016
(36) Timer X (low-order)
002C16
FF16
(5) Port P2 direction register
000516
0016
(37) Timer X (high-order)
002D16
FF16
(6) Port P3
000616
0016
(38) Timer X mode register 1
002E16
0016
(7) Port P4
000816
0016
(39) Timer X mode register 2
002F16
0016
(8) Port P4 direction register
000916
0016
003116
0016
(9) Port P5
000A16
0016
(40) Interrupt interval determination
control register
(41) A-D control register
003216
1016
(10) Port P5 direction register
000B16
0016
(42) Interrupt source switch register
003916
0016
(11) Port P6
000C16
0016
(43) Interrupt edge selection register
003A16
0016
(12) Port P6 direction register
000D16
0016
(44) CPU mode register
003B16 0 1 0 0 1 0 0 0
(13) Port P7
000E16
0016
(45) Interrupt request register 1
003C16
0016
(14) Port P7 direction register
000F16
0016
(46) Interrupt request register 2
003D16
0016
(15) Port P8
001016
0016
(47) Interrupt control register 1
003E16
0016
(16) Port P8 direction register
001116
0016
(48) Interrupt control register 2
003F16
0016
(17) Port P9
001216
0016
(49) Pull-up control register 1
0EF016
0016
(18) Port P9 direction register
001316
0016
(50) Pull-up control register 2
0EF116
0016
(19) UART control register
001716
8016
(51) P1FLDRAM write disable register 0EF216
0016
(20) Serial I/O1 control register 1
001916
0016
(52) P3FLDRAM write disable register 0EF316
0016
(21) Serial I/O1 control register 2
001A16
0016
(53) FLDC mode register
0EF416
0016
(22) Serial I/O1 control register 3
001C16
0016
(54) Tdisp time set register
0EF516
0016
(23) Serial I/O2 control register
001D16
0016
(55) Toff1 time set register
0EF616
FF16
(24) Serial I/O2 status register
001E16
8016
(56) Toff2 time set register
0EF716
FF16
(25) Timer 1
002016
FF16
(57) Port P0FLD/port switch register
0EF916
0016
(26) Timer 2
002116
0116
(58) Port P2FLD/port switch register
0EFA16
0016
(27) Timer 3
002216
FF16
(59) Port P8FLD/port switch register
0EFB16
0016
(28) Timer 4
002316
FF16
(60) Port P8FLD output control register
0EFC16
0016
(29) Timer 5
002416
FF16
(61) Buzzer output control register
0EFD16
0016
(30) Timer 6
002516
FF16
(62) Processor status register
(31) PWM control register
002616
0016
(63) Program counter
(32) Timer 12 mode register
002816
0016
(PS) ✕ ✕ ✕ ✕ ✕ 1 ✕ ✕
(PCH)
FFFD16 contents
(PCL)
FFFC16 contents
✕: Not fixed
Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.
Fig. 70 Internal status at reset
38B5 Group User’s Manual
1-61
HARDWARE
FUNCTIONAL DESCRIPTION
Clock Generating Circuit
●Oscillation control
The 38B5 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance with
the resonator manufacturer's recommended values. No
external resistor is needed between XIN and XOUT since a feedback
resistor exists on-chip. However, an external feedback resistor is
needed between XCIN and XCOUT.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and X COUT pins function as I/O ports.
(1) Stop mode
If the STP instruction is executed, the internal system clock stops at
an “H” level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16”
and timer 2 is set to “01 16.”
Either XIN divided by 8 or XCIN divided by 16 is input to timer 1 as
count source, and the output of timer 1 is connected to timer 2. The
bits of the timer 12 mode register are cleared to “0.” Set the interrupt
enable bits of the timer 1 and timer 2 to disabled (“0”) before executing the STP instruction. Oscillator restarts when an external interrupt
is received, but the internal system clock is not supplied to the CPU
until timer 1 underflows. This allows time for the clock circuit oscillation to stabilize.
●Frequency control
(1) Middle-speed mode
The internal system clock is the frequency of XIN divided by 4. After
reset, this mode is selected.
(2) High-speed mode
The internal system clock is the frequency of XIN.
(3) Low-speed mode
The internal system clock is the frequency of XCIN divided by 2.
(2) Wait mode
If the WIT instruction is executed, the internal system clock stops at
an “H” level. The states of X IN and XCIN are the same as the state
before executing the WIT instruction. The internal system clock restarts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after the
clock is restarted.
■Note
If you switch the mode between middle/high-speed and low-speed,
stabilize both XIN and XCIN oscillations. The sufficient time is required
for the sub clock to stabilize, especially immediately after power on
and at returning from stop mode. When switching the mode between
middle/high-speed and low-speed, set the frequency on condition
that f(XIN) > 3f(XCIN).
(4) Low power consumption mode
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set bit
5 of the CPU mode register to “1.” When the main clock XIN is restarted (by setting the main clock stop bit to “0”), set enough time for
oscillation to stabilize.
By clearing furthermore the XCOUT drivability selection bit (b3) of CPU
mode register to “0,” low power consumption operation of less than
200 µA (f(XCIN) = 32 kHz) can be realized by reducing the drivability
between XCIN and X COUT. At reset or during STP instruction execution this bit is set to “1” and a strong drivability that has an easy
oscillation start is set.
XCIN
XCOUT
Rf
CCIN
XIN
Rd
CCOUT
CIN
COUT
Fig. 71 Ceramic resonator circuit
XCIN
XCOUT
open
XIN
VCC
VCC
VSS
VSS
Fig. 72 External clock input circuit
38B5 Group User’s Manual
XOUT
open
External oscillation circuit
External oscillation circuit
or external pulse
1-62
XOUT
HARDWARE
FUNCTIONAL DESCRIPTION
XCOUT
XCIN
“0”
“1”
Port XC
switch bit (Note 3)
1/2
XOUT
XIN
Timer 2 count source
selection bit (Note 2)
Timer 1 count source
selection bit (Note 2)
Internal system clock
selection bit (Notes 1, 3)
“1”
Low-speed mode
Timer 1
“1”
1/4
1/2
“0”
Timer 2
“0”
“0”
“1”
High-speed or
middle-speed
mode
Main clock division ratio
selection bits (Note 3)
Middle-speed mode
“1”
Timing φ (internal clock)
“0”
Main clock stop bit
(Note 3)
Q
High-speed or
low-speed mode
S
R
S Q
STP instruction
WIT instruction
Q S
R
R
STP instruction
Reset
Interrupt disable flag l
Interrupt request
Notes 1: When low-speed mode is selected, set the port Xc switch bit (b4) to “1.”
2: Refer to the structure of the timer 12 mode register.
3: Refer to the structure of the CPU mode register.
Fig. 73 Clock generating circuit block diagram
38B5 Group User’s Manual
1-63
HARDWARE
FUNCTIONAL DESCRIPTION
Reset
CM4
“1”
CM7=0(4 MHz selected)
CM6=0(high-speed)
CM5=0(XIN oscillating)
CM4=0(32 kHz stopped)
“0
4 “0”
CM
6
0”
”
M “
“1 C
”
“1
Middle-speed mode
(φ =1 MHz)
“0”
“1
”
” CM
4
CM
“1
6
”
“0
”
High-speed mode
(φ =4 MHz)
CM 6
“1”
“0”
CM7=0(4 MHz selected)
CM6=0(high-speed)
CM5=0(X IN oscillating)
CM4=1(32 kHz oscillating)
“1”
“1”
CM 7
CM 7
“0”
“0”
CM7=0(4 MHz selected)
CM6=1(middle-speed)
CM5=0(XIN oscillating)
CM4=1(32 kHz oscillating)
CM4
“0”
CM7=0(4 MHz selected)
CM6=1(middle-speed)
CM5=0(X IN oscillating)
CM4=0(32 kHz stopped)
High-speed mode
(φ =4 MHz)
“0”
CM 6
“1”
“1”
Middle-speed mode
(φ =1 MHz)
CM
1”
6
“1
”
”
“0
“
Low-power dissipation mode
(φ =16 kHz)
CM7=1(32 kHz selected)
CM6=1(middle-speed)
CM5=1(XIN stopped)
CM4=1(32 kHz oscillating)
Low-power dissipation mode
(φ =16 kHz)
CM 6
“1”
” CM
5
CM
“1
6
”
“0
”
b7
“0”
CM7=1(32 kHz selected)
CM6=0(high-speed)
CM5=0(XIN oscillating)
CM4=1(32 kHz oscillating)
“0
”
“0
C
M
5
CM 5
“0”
”
“1
“0”
CM 5
“1”
CM7=1(32 kHz selected)
CM6=1(middle-speed)
CM5=0(X IN oscillating)
CM4=1(32 kHz oscillating)
“1”
Low-speed mode
(φ =16 kHz)
CM 6
“1”
Low-speed mode
(φ =16 kHz)
“0”
CM7=1(32 kHz selected)
CM6=0(high-speed)
CM5=1(X IN stopped)
CM4=1(32 kHz oscillating)
b4
CPU mode register
(CPUM : address 003B 16)
CM4 : Port Xc switch bit
0: I/O port function
1: X CIN-XCOUT oscillating function
CM5 : Main clock (X IN- XOUT) stop bit
0: Oscillating
1: Stopped
CM6: Main clock division ratio selection bit
0: f(X IN) (High-speed mode)
1: f(X IN)/4 (Middle-speed mode)
CM7: Internal system clock selection bit
0: X IN–XOUT selected (Middle-/High-speed mode)
1: X CIN–XCOUT selected (Low-speed mode)
Notes 1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2: The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait
mode is ended.
3: Timer operates in the wait mode.
4: When the stop mode is ended, a delay of approximately 1 ms occurs by Timer 1 in middle-/high-speed mode.
5: When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 in low-speed mode.
6: The example assumes that 4 MHz is being applied to the X IN pin and 32 kHz to the X CIN pin. φ indicates the internal system clock.
Fig. 74 State transitions of system clock
1-64
38B5 Group User’s Manual
HARDWARE
NOTES ON PROGRAMMING/NOTES ON USE
NOTES ON PROGRAMMING
Processor Status Register
A-D Converter
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” After a
reset, initialize flags which affect program execution. In particular, it
is essential to initialize the index X mode (T) and the decimal mode
(D) flags because of their effect on calculations.
The comparator uses internal capacitors whose charge will be lost if
the clock frequency is too low.
Therefore, make sure that f(XIN) is at least on 250 kHz during an A-D
conversion.
Do not execute the STP or WIT instruction during an A-D conversion.
Interrupts
Instruction Execution Time
The contents of the interrupt request bits do not change immediately
after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or
BBS instruction.
The instruction execution time is obtained by multiplying the frequency
of the internal system clock by the number of cycles needed to execute an instruction.
The number of cycles required to execute an instruction is shown in
the list of machine instructions.
The frequency of the internal system clock is the same of the XIN
frequency in high-speed mode.
Decimal Calculations
•To calculate in decimal notation, set the decimal mode flag (D) to
“1,” then execute an ADC or SBC instruction. Only the ADC and
SBC instructions yield proper decimal results. After executing an
ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction.
•In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
At STP Instruction Release
At the STP instruction release, all bits of the timer 12 mode register
are cleared.
The XCOUT drivability selection bit (the CPU mode register) is set to
“1” (high drive) in order to start oscillating.
Timers
NOTES ON USE
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
Notes on Built-in EPROM Version
Multiplication and Division Instructions
•The index X mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
•The execution of these instructions does not change the contents of
the processor status register.
The P47 pin of the One Time PROM version or the EPROM version
functions as the power source input pin of the internal EPROM.
Therefore, this pin is set at low input impedance, thereby being affected easily by noise.
To prevent a malfunction due to noise, insert a resistor (approx. 5
kΩ) in series with the P47 pin.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
•The data transfer instruction (LDA, etc.)
•The operation instruction when the index X mode flag (T) is “1”
•The addressing mode which uses the value of a direction register
as an index
•The bit-test instruction (BBC or BBS, etc.) to a direction register
•The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a
direction register.
Use instructions such as LDM and STA, etc., to set the port direction
registers.
Serial I/O
•Using an external clock
When using an external clock, input “H” to the external clock input
pin and clear the serial I/O interrupt request bit before executing
serial I/O transfer and serial I/O automatic transfer.
•Using an internal clock
When using an internal clock, set the synchronous clock to the internal clock, then clear the serial I/O interrupt request bit before executing a serial I/O transfer and serial I/O automatic transfer.
38B5 Group User’s Manual
1-65
HARDWARE
DATA REQUIRED FOR MASK ORDERS/DATA REQUIRED FOR ROM WRITING ORDERS/ROM PROGRAMMING METHOD
DATA REQUIRED FOR MASK ORDERS
ROM PROGRAMMING METHOD
The following are necessary when ordering a mask ROM production:
(1) Mask ROM Order Confirmation Form
(2) Mark Specification Form
(3) Data to be written to ROM, in EPROM form (three identical copies)
The built-in PROM of the blank One Time PROM version and the
EPROM version can be read or programmed with a general purpose
PROM programmer using a special programming adapter. Set the
address of PROM programmer in the user ROM area.
DATA REQUIRED FOR ROM WRITING ORDERS
The following are necessary when ordering a ROM writing:
(1) ROM Writing Confirmation Form
(2) Mark Specification Form
(3) Data to be written to ROM, in EPROM form (three identical copies)
Table 11 Special programming adapter
Package
80P6N-A
80D0
Name of Programming Adapter
PCA7438F-80A
PCA7438L-80A
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in
Figure 75 is recommended to verify programming.
Programming with PROM
programmer
Screening (Note)
(150°C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
Note: The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Fig. 75 Programming and testing of One Time PROM version
1-66
38B5 Group User’s Manual
HARDWARE
MASK OPTION OF PULL-DOWN RESISTOR
MASK OPTION OF PULL-DOWN RESISTOR
(object product: M38B5XMXH-XXXFP)
Power Dissipation Calculating example 1
Whether built-in pull-down resistors are connected or not to highbreakdown voltage ports P20 to P27 and P80 to P83 can be specified
in ordering mask ROM. The option type can be specified from among
8 types; A to G, P as shown Table 12.
● Fixed number depending on microcomputer’s standard
• VOH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value 43 V / 900 µA = 48 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V ✕
15 mA = 75 mW
Table 12 Mask option type of pull-down resistor
Option
type
Connective port of pull-down resistor
Restriction
(connected at “1” writing)
P20 P21 P22 P23 P24 P25 P26 P27 P80 P81 P82 P83
A ($41)
B ($42)
C ($43)
D ($44)
E ($45) 1
F ($46) 1
G ($47) 1
P ($50) 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(Note 4)
Notes 1: The electrical characteristics of high-breakdown voltage ports
P20 to P27 and P80 to P83’s built-in pull-down resistors are the
same as that of high-breakdown voltage ports P00 to P07.
2: The absolute maximum ratings of power dissipation may be
exceed owing to the number of built-in pull-down resistor. After
calculating the power dissipation, specify the option type.
3: One time PROM version and EPROM version cannot be
specified whether built-in pull-down resistors are connected or not
likewise option type A.
4: INT3 function and CNTR1 function cannot be used in the option
type P.
Power Dissipation Calculating Method
● Fixed number depending on microcomputer’s standard
• VOH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value 43 V / 900 µA = 48 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V ✕
15 mA = 75 mW
● Fixed number depending on use condition
• Apply voltage to VEE pin: Vcc – 45 V
• Timing number 17; digit number 16; segment number 20
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: 31
• All segment number during repeat cycle: 340 (= 17 ✕ 20)
• Total number of built-in resistor: for digit; 16, for segment; 20
• Digit pin current value: 18 (mA)
• Segment pin current value: 3 (mA)
(1) Digit pin power dissipation
{18 ✕ 16 ✕ (1–1/16) ✕ 2} / 17 = 31.77 mW
(2) Segment pin power dissipation
{3 ✕ 31 ✕ (1–1/16) ✕ 2} / 17 = 10.26 mW
(3) Pull-down resistor power dissipation (digit)
(45 – 2)2 /48 ✕ (16 ✕ 16/16) ✕ (1 – 1/16) / 17 = 33.99 mW
(4) Pull-down resistor power dissipation (segment)
(45 – 2)2 /48 ✕ (31 ✕ 20/20) ✕ (1 – 1/16) / 17 = 65.86 mW
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 75 mW
(1) + (2)+ (3) + (4) + (5) = 217 mW
DIG0
DIG1
DIG2
● Fixed number depending on use condition
• Apply voltage to VEE pin: Vcc – 45 V
• Timing number a; digit number b; segment number c
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: d
• All segment number during repeat cycle: c (= a ✕ c)
• Total number of built-in resistor: for digit; f, for segment; g
• Digit pin current value h (mA)
• Segment pin current value i (mA)
DIG3
DIG14
DIG15
DIG16
Timing number
(1) Digit pin power dissipation
{h ✕ b ✕ (1–Toff/Tdisp) ✕ voltage} / a
(2) Segment pin power dissipation
{i ✕ d ✕ (1–Toff/Tdisp) ✕ voltage} / a
(3) Pull-down resistor power dissipation (digit)
{power dissipation per 1 digit ✕ (b ✕ f / b) ✕ (1–Toff/Tdisp) } / a
(4) Pull-down resistor power dissipation (segment)
{power dissipation per 1 segment ✕ (d ✕ g / c) ✕ (1–Toff/Tdisp) } / a
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 75 mW
1
2
3
14
15
16
17
Repeat cycle
Tscan
Fig. 76 Digit timing waveform (1)
(1) + (2)+ (3) + (4) + (5) = X mW
38B5 Group User’s Manual
1-67
HARDWARE
MASK OPTION OF PULL-DOWN RESISTOR
Power Dissipation Calculating example 2
(when 2 or more digit is turned ON at same
time)
● Fixed number depending on microcomputer’s standard
• VOH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value 43 V / 900 µA = 48 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V ✕
15 mA = 75 mW
● Fixed number depending on use condition
• Apply voltage to VEE pin: Vcc – 45 V
• Timing number 11; digit number 12; segment number 24
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: 114
• All segment number during repeat cycle: 264 (= 11 ✕ 24)
• Total number of built-in resistor: for digit; 10, for segment; 22
• Digit pin current value: 18 (mA)
• Segment pin current value: 3 (mA)
(1) Digit pin power dissipation
{18 ✕ 12 ✕ (1–1/16) ✕ 2} / 11 = 36.82 mW
(2) Segment pin power dissipation
{3 ✕ 114 ✕ (1–1/16) ✕ 2} / 11 = 58.30 mW
(3) Pull-down resistor power dissipation (digit)
(45 – 2)2 /48 ✕ (12 ✕ 10/12) ✕ (1 – 1/16) / 11 = 32.84 mW
(4) Pull-down resistor power dissipation (segment)
(45 – 2)2 /48 ✕ (114 ✕ 22/24) ✕ (1 – 1/16) / 11 = 343.08 mW
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 75 mW
(1) + (2)+ (3) + (4) + (5) = 547 mW
DIG0
DIG1
DIG2
DIG3
DIG4
DIG5
DIG6
DIG7
DIG8
DIG9
Timing number
1
2
3
4
5
6
7
8
9
10
11
Repeat cycle
Tscan
Fig. 77 Digit timing waveform (2)
1-68
38B5 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
FUNCTIONAL DESCRIPTION SUPPLEMENT
higher-priority interrupt is accepted first. This priority is determined
by hardware, but various priority processing can be performed by
software, using an interrupt enable bit and an interrupt disable flag.
For interrupt sources, vector addresses and interrupt priority, refer to
Table 13.
Interrupt
38B5 group permits interrupts on the basis of 21 sources.
It is vector interrupts with a fixed priority system. Accordingly, when
two or more interrupt requests occur during the same sampling, the
Table 13 Interrupt sources, vector addresses and interrupt priority
Interrupt source
Reset (Note 2)
INT0
INT1
INT2
Remote control/counter overflow
Serial I/O1
Serial I/O1 automatic transfer
Timer X
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
Serial I/O2 receive
INT3
Serial I/O2 transmit
INT4
A-D conversion
FLD blanking
FLD digit
BRK instruction
Priority
1
2
3
4
Vector Addresses (Note 1)
High
Low
FFFD16
FFFC16
FFFB 16
FFF916
FFF716
FFFA16
FFF816
FFF616
5
FFF516
FFF416
6
7
8
9
10
11
12
13
14
FFF316
FFF116
FFEF 16
FFED 16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFF216
FFF016
FFEE16
FFEC 16
FFEA16
FFE816
FFE616
FFE416
FFE216
15
FFE116
FFE016
16
FFDF16
FFDE 16
Remarks
Non-maskable
External interrupt (active edge selectable)
External interrupt (active edge selectable)
External interrupt (active edge selectable)
Valid when interrupt interval determination is operating
Valid when serial I/O1 ordinary mode is selected
Valid when serial I/O1 automatic transfer mode is selected
STP release timer underflow
(Note 3)
External interrupt (active edge selectable) (Note 4)
External interrupt (active edge selectable)
Valid when INT4 interrupt is selected
Valid when A-D conversion is selected
Valid when FLD blanking interrupt is selected
Valid when FLD digit interrupt is selected
Non-maskable software interrupt
17
FFDD16
FFDC16
Notes 1 : Vector addresses contain interrupt jump destination addresses.
2 : Reset function in the same way as an interrupt with the highest priority.
3 : In the mask option type P, timer 4 interrupt whose count source is CNTR1 input cannot be used.
4 : In the mask option type P, INT3 interrupt cannot be used.
38B5 Group User’s Manual
1-69
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Timing After Interrupt
The interrupt processing routine begins with the machine cycle following the completion of the instruction that is currently in execution.
Figure 78 shows a timing chart after an interrupt occurs, and Figure
79 shows the time up to execution of the interrupt processing routine.
φ
SYNC
RD
WR
Address bus
Data bus
PC
Not used
S, SPS
BL
S-1, SPS S-2, SPS
PCH
P CL
PS
BH
AL
AL, AH
AH
SYNC : CPU operation code fetch cycle
(This is an internal signal which cannot be observed from the external unit.)
BL, BH : Vector address of each interrupt
AL, AH : Jump destination address of each interrupt
SPS : “0016” or “0116”
Fig. 78 Timing chart after interrupt occurs
Interrupt request occurs
Interrupt operation starts
Waiting time for
pipeline postprocessing
Main routine
0 to 16 cycles
2 cycles
Push onto
stack vector
fetch
5 cycles
7 to 23 cycles (4 MHz, 1.75 µs to 5.75 µs)
Fig. 79 Time up to execution of interrupt processing routine
1-70
38B5 Group User’s Manual
Interrupt processing routine
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
A-D Converter
By repeating the above operations up to the lowest-order bit of the
A-D conversion register, an analog value converts into a digital value.
A-D conversion completes at 61 clock cycles (15.25 µs at f(XIN) = 8
MHz) after it is started, and the result of the conversion is stored into
the A-D conversion register.
Concurrently with the completion of A-D conversion, A-D conversion
interrupt request occurs, so that the AD conversion interrupt request
bit is set to “1.”
A-D conversion is started by setting AD conversion completion bit to
“0.” During A-D conversion, internal operations are performed as follows.
1. After the start of A-D conversion, A-D conversion register goes to
“00 16 .”
2. The highest-order bit of A-D conversion register is set to “1,” and
the comparison voltage Vref is input to the comparator. Then, Vref
is compared with analog input voltage V IN.
3. As a result of comparison, when Vref < VIN, the highest-order bit of
A-D conversion register becomes “1.” When Vref > VIN , the highest-order bit becomes “0.”
Table 14 Relative formula for a reference voltage VREF of A-D
converter and Vref
When n = 0
Vref = 0
VREF
When n = 1 to 1023
Vref =
✕n
1024
n: Value of A-D converter (decimal numeral)
Table 15 Change of A-D conversion register during A-D conversion
Change of A-D conversion register
Value of comparison voltage (Vref )
At start of conversion
0
0
0
0
0
0
0
0
0
0
First comparison
1
0
0
0
0
0
0
0
0
0
Second comparison
✽1
1
0
0
0
0
0
0
0
0
Third comparison
✽1 ✽2
1
0
0
0
0
0
0
0
After completion of tenth
comparison
A result of A-D conversion
✽1 ✽2
✽3 ✽ 4 ✽ 5 ✽6
✽ 7 ✽8 ✽ 9 ✽10
0
VREF
2
VREF
±
2
VREF
4
VREF
±
2
VREF
4
±
VREF
8
VREF
±
2
VREF
4
±
••••
±
VREF
1024
✽1–✽10: A result of the first comparison to the tenth comparison
38B5 Group User’s Manual
1-71
HARDWARE
FUNCTIONAL DESCRIPTION SUPPLEMENT
Figures 80 shows the A-D conversion equivalent circuit, and Figure
81 shows the A-D conversion timing chart.
VCC
VSS
About 2 kΩ
VCC
VSS
V IN
AN0
Sampling
clock
AN1
C
AN2
Chopper
amplifier
AN3
AN4
A-D conversion register (high-order)
AN5
AN6
AN7
A-D conversion register
(low-order)
AN8
AN9
AD conversion interrupt request
AN10
AN11
b3 b2 b1 b0
A-D control
register
VREF
Built-in
D-A converter
Vref
Reference
clock
VSS
Fig. 80 A-D conversion equivalent circuit
φ
Write signal for A-D
control register
61 cycles
AD conversion
completion bit
Sampling clock
Fig. 81 A-D conversion timing chart
1-72
38B5 Group User’s Manual
CHAPTER 2
APPLICATION
2.1
2.2
2.3
2.4
2.5
2.6
2.7
I/O port
Timer
Serial I/O
FLD controller
A-D converter
PWM
Interrupt interval determination
function
2.8 Watchdog timer
2.9 Buzzer output circuit
2.10 Reset circuit
2.11 Clock generating circuit
APPLICATION
2.1 I/O port
2.1 I/O port
This paragraph describes the setting method of I/O port relevant registers, notes etc.
2.1.1 Memory assignment
Address
000016
Port P0 (P0)
000116
Port P0 direction register (P0D)
000216
Port P1 (P1)
000316
000416
Port P2 (P2)
000516
Port P2 direction register (P2D)
000616
Port P3 (P3)
000716
000816
Port P4 (P4)
000916
Port P4 direction register (P4D)
000A16
000B16
Port P5 (P5)
Port P5 direction register (P5D)
000C16
Port P6 (P6)
000D16
Port P6 direction register (P6D)
000E16
Port P7 (P7)
000F16
Port P7 direction register (P7D)
001016
Port P8 (P8)
001116
Port P8 direction register (P8D)
001216
001316
Port P9 (P9)
0EF016
Pull-up control register 1 (PULL1)
0EF116
Pull-up control register 2 (PULL2)
Port P9 direction register (P9D)
Fig. 2.1.1 Memory assignment of I/O port relevant registers
2-2
38B5 Group User’s Manual
APPLICATION
2.1 I/O port
2.1.2 Relevant registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (i = 0, 1, 2, 3, 4, 5, 7, 8)
(Pi: addresses 0016, 0216, 0416, 0616, 0816, 0A16, 0E16, 1016)
b
0
1
2
3
4
5
6
7
Name
Port Pi0
Port Pi1
Port Pi2
Port Pi3
Port Pi4
Port Pi5
Port Pi6
Port Pi7
Functions
●In output mode
Write •••••••• Port latch
Read •••••••• Port latch
●In input mode
Write •••••••• Port latch
Read •••••••• Value of pin
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.1.2 Structure of port Pi (i = 0, 1, 2, 3, 4, 5, 7, 8)
Port P6
b7 b6 b5 b4 b3 b2 b1 b0
Port P6
(P6: address 0C16)
b
0
1
2
3
4
5
6
7
Name
Functions
Port P60
●In output mode
Port P61
Write •••••••• Port latch
Port P62
Read •••••••• Port latch
●In input mode
Port P63
Write •••••••• Port latch
Port P64
Read •••••••• Value of pin
Port P65
Nothing is arranged for these bits. When these
bits are read out, the contents are undefined.
At reset R W
0
0
0
0
0
0
0
0
✕ ✕
✕ ✕
Fig. 2.1.3 Structure of port P6
Port P9
b7 b6 b5 b4 b3 b2 b1 b0
Port P9
(P9: address 1216)
b
Name
0 Port P90
1 Port P91
Functions
●In output mode
Write •••••••• Port latch
Read •••••••• Port latch
●In input mode
Write •••••••• Port latch
Read •••••••• Value of pin
2 Nothing is arranged for these bits. When these
3 bits are read out, the contents are undefined.
4
5
6
7
At reset R W
0
0
0
0
0
0
0
0
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
Fig. 2.1.4 Structure of port P9
38B5 Group User’s Manual
2-3
APPLICATION
2.1 I/O port
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (i = 0, 2, 4, 5, 7, 8)
(PiD: addresses 0116, 0516, 0916, 0B16, 0F16, 1116)
b
Name
0 Port Pi direction
register
1
2
3
4
5
6
7
Functions
0 : Port Pi0 input mode
1 : Port Pi0 output mode
0 : Port Pi1 input mode
1 : Port Pi1 output mode
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0 : Port Pi3 input mode
1 : Port Pi3 output mode
0 : Port Pi4 input mode
1 : Port Pi4 output mode
0 : Port Pi5 input mode
1 : Port Pi5 output mode
0 : Port Pi6 input mode
1 : Port Pi6 output mode
0 : Port Pi7 input mode
1 : Port Pi7 output mode
(Note)
At reset R W
0
0
0
0
0
0
0
0
Note: Bit 7 of the port P4 direction register (address 0916) does not have
direction register function because P47 is input port. When writing to bit 7
of the port P4 direction register, write “0” to the bit.
Fig. 2.1.5 Structure of port Pi (i = 0, 2, 4, 5, 7, 8) direction register
Port P6 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P6 direction register
(P6D: address 0D16)
b
Name
Functions
0 Port P6 direction
register
1
0
2
0
3
4
5
6
7
0 : Port P60 input mode
1 : Port P60 output mode
0 : Port P61 input mode
1 : Port P61 output mode
0 : Port P62 input mode
1 : Port P62 output mode
0 : Port P63 input mode
1 : Port P63 output mode
0 : Port P64 input mode
1 : Port P64 output mode
0 : Port P65 input mode
1 : Port P65 output mode
Nothing is arranged for these bits. When these
bits are read out, the contents are undefined.
Fig. 2.1.6 Structure of port P6 direction register
2-4
At reset R W
38B5 Group User’s Manual
0
0
0
0
0
0
✕ ✕
✕ ✕
APPLICATION
2.1 I/O port
Port P9 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P9 direction register
(P9D: address 1316)
b
Name
Functions
0 Port P9 direction
register
1
0 : Port P90 input mode
1 : Port P90 output mode
0 : Port P91 input mode
1 : Port P91 output mode
2 Nothing is arranged for these bits. When these
3 bits are read out, the contents are undefined.
4
5
6
7
At reset R W
0
0
0
0
0
0
0
0
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
Fig. 2.1.7 Structure of port P9 direction register
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register 1
(PULL1: address 0EF016)
b
Name
0
Ports P50, P51 pullup control
Ports P52, P53 pullup control
Ports P54, P55 pullup control
Ports P56, P57 pullup control
1
2
3
4
5
6
7
Functions
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
Port P61 pull-up
1: Pull-up
control
Ports P62, P63 pull- 0: No pull-up
1: Pull-up
up control
Ports P64, P65 pull- 0: No pull-up
up control
1: Pull-up
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
At reset R W
0
0
0
0
0
0
0
0
Note: The pin set to output port is cut off from pull-up control.
Fig. 2.1.8 Structure of pull-up control register 1
38B5 Group User’s Manual
2-5
APPLICATION
2.1 I/O port
Pull-up control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register 2
(PULL2: address 0EF116)
b
Name
Functions
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
Nothing
is
arranged
for
this bit. This is a write
7
disabled bit. When this bit is read out, the
contents are “0”.
0 Ports P70, P71 pullup control
1 Ports P72, P73 pullup control
2 Ports P74, P75 pullup control
3 Ports P76, P77 pullup control
4 Ports P84, P85 pullup control
5 Ports P86, P87 pullup control
6 Ports P90, P91 pullup control
At reset R W
0
0
0
0
0
0
0
0
Note: The pin set to output port is cut off from pull-up control.
Fig. 2.1.9 Structure of pull-up control register 2
2.1.3 Terminate unused pins
Table 2.1.1 Termination of unused pins
Pins
Termination
P1, P3
Open at “H” output state.
P5, P6 1–P6 5, P7, • Set to the input mode and connect each to VCC or V SS through a resistor of 1 kΩ to
P8 4–P87, P9
10 kΩ.
P4 0–P46, P60
P0, P2, P8 0–P83
P4 7
V REF
X OUT
AV SS , VEE
2-6
• Set to the
• Set to the
10 kΩ.
• Set to the
• Set to the
10 kΩ.
• Set to the
output mode and open at “L” or “H” output state.
input mode and connect each to VCC or V SS through a resistor of 1 kΩ to
output mode and open at “L” output state.
input mode and connect each to VCC or V SS through a resistor of 1 kΩ to
output mode and open at “H” output state.
Disable INT2 interrupt and connect to V CC or V SS through a resistor of 1 KΩ to 10 kΩ.
Open
Open (only when using external clock)
Connect to V SS (GND).
38B5 Group User’s Manual
APPLICATION
2.1 I/O port
2.1.4 Notes on use
(1)
Notes in standby state
In standby state✽1 for low-power dissipation, do not make input levels of an input port and an I/O port
“undefined”, especially for I/O ports of the P-channel open-drain and the N-channel open-drain.
Pull-up (connect the port to V CC) or pull-down (connect the port to V SS ) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using built-in pull-up resistor, note on varied current values:
• When setting as an input port : Fix its input level
• When setting as an output port : Prevent current from flowing out to external
● Reason
Even when setting as an output port with its direction register, in the following state :
• P-channel......when the content of the port latch is “0”
• N-channel......when the content of the port latch is “1”
the transistor becomes the OFF state, which causes the ports to be the high-impedance state.
Note that the level becomes “undefined” depending on external circuits.
Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the
state that input levels of a input port and an I/O port are “undefined”. This may cause power source
current.
✽1 standby state: stop mode by executing STP instruction
wait mode by executing WIT instruction
(2)
N-channel open-drain port
P4 0–P4 2, P45, P46, P60 of N-channel open-drain output ports have the built-in hysteresis circuit for
input. In standby state for low-power dissipation, do not make these pins floating state.
● Reason
When power sources for pull-up of these pins are cut off in standby state, these ports become
floating. Accordingly, a current may flow from Vcc to Vss through the built-in hysteresis circuit.
38B5 Group User’s Manual
2-7
APPLICATION
2.1 I/O port
(3)
Modifying port latch of I/O port with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction ✽2, the value of the
unspecified bit may be changed.
● Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
•As for bit which is set for input port:
The pin state is read in the CPU, and is written to this bit after bit managing.
•As for bit which is set for output port:
The bit value is read in the CPU, and is written to this bit after bit managing.
Note the following:
•Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
•As for a bit of which is set for an input port, its value may be changed even when not specified
with a bit managing instruction in case where the pin state differs from its port latch contents.
✽2 Bit managing instructions: SEB and CLB instructions
(4)
Pull-up control
When each port which has built-in pull-up resistor (P5, P6 1–P65, P7, P8 4–P8 7, P9) is set to output
port, pull-up control of corresponding port become invalid. (Pull-up cannot be set.)
● Reason
Pull-up control is valid only when each direction register is set to the input mode.
2.1.5 Termination of unused pins
(1)
Terminate unused pins
➀ Output ports : Open
➁ Input ports :
Connect each pin to VCC or V SS through each resistor of 1 kΩ to 10 kΩ.
As for pins whose potential affects to operation modes such as pin INT or others, select the V CC
pin or the V SS pin according to their operation mode.
➂ I/O ports :
• Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of
1 kΩ to 10 kΩ.
Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the
I/O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the
mode of the ports is switched over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source current may increase in the input
mode. With regard to an effects on the system, thoroughly perform system evaluation on the user
side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
2-8
38B5 Group User’s Manual
APPLICATION
2.1 I/O port
(2) Termination remarks
➀ Input ports and I/O ports :
Do not open in the input mode.
● Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➁ and
➂ shown on the above.
➁ I/O ports :
When setting for the input mode, do not connect to VCC or VSS directly.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and V CC (or VSS).
➂ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to V CC or VSS through
a resistor.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
38B5 Group User’s Manual
2-9
APPLICATION
2.2 Timer
2.2 Timer
This paragraph explains the registers setting method and the notes relevant to the timers.
2.2.1 Memory map
002016
Timer 1 (T1)
002116
Timer 2 (T2)
002216
Timer 3 (T3)
002316
Timer 4 (T4)
002416
Timer 5 (T5)
002516
Timer 6 (T6)
002716
Timer 6 PWM register (T6PWM)
002816
Timer 12 mode register (T12M)
002916
Timer 34 mode register (T34M)
002A16
Timer 56 mode register (T56M)
002C16
Timer X (low-order) (TXL)
002D16
Timer X (high-order) (TXH)
002E16
Timer X mode register 1 (TXM1)
002F16
Timer X mode register 2 (TXM2)
003C16
Interrupt request register 1 (IREQ1)
003D16
Interrupt request register 2 (IREQ2)
003E16
Interrupt control register 1 (ICON1)
003F16
Interrupt control register 2 (ICON2)
Fig. 2.2.1 Memory map of registers relevant to timers
2-10
38B5 Group User’s Manual
APPLICATION
2.2 Timer
2.2.2 Relevant registers
(1) 8-bit timer
Timer i
b7 b6 b5 b4 b3 b2 b1 b0
Timer i (i = 1, 3, 4, 5, 6)
(Ti: addresses 2016, 2216, 2316, 2416, 2516)
b
Functions
0 • Set timer i count value.
1 • The value set in this register is written to both
2 the timer i and the timer i latch at one time.
3 • When the timer i is read out, the count value
4 of the timer i is read out.
5
6
7
At reset R W
1
1
1
1
1
1
1
1
Fig. 2.2.2 Structure of Timer i (i=1, 3, 4, 5, 6)
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2
(T2: address 2116)
b
Functions
0 • Set timer 2 count value.
1 • The value set in this register is written to both
2 the timer 2 and the timer 2 latch at one time.
3 • When the timer 2 is read out, the count value
4 of the timer 2 is read out.
5
6
7
At reset R W
1
0
0
0
0
0
0
0
Fig. 2.2.3 Structure of Timer 2
Timer 6 PWM register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 6 PWM register
(T6PWM: address 2716)
b
0
1
2
3
4
5
6
Functions
• In timer 6 PWM1 mode
“L” level width of PWM rectangular waveform is set.
• Duty of PWM rectangular waveform: n/(n + m)
Period: (n + m) × ts
n = timer 6 set value
m = timer 6 PWM register set value
ts = timer 6 count source period
At n = 0, all PWM output “L”.
At m = 0, all PWM output “H”.
(However, n = 0 has priority.)
• Selection of timer 6 PWM1 mode
Set “1” to the timer 6 operation mode selection bit.
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
7
Fig. 2.2.4 Structure of Timer 6 PWM register
38B5 Group User’s Manual
2-11
APPLICATION
2.2 Timer
Timer 12 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 12 mode register
(T12M: address 2816)
b
Name
0
Timer 1 count stop
bit
Timer 2 count stop
bit
Timer 1 count
source selection
bits
1
2
3
4 Timer 2 count
source selection
bits
5
Functions
At reset R W
0: Count operation
1: Count stop
0: Count operation
1: Count stop
0
b3 b2
0
b5 b4
0
0 0: f(XIN)/8 or f(XCIN)/16
0 1: f(XCIN)
1 0: f(XIN)/16 or f(XCIN)/32
1 1: f(XIN)/64 or f(XCIN)/128
0 0: Timer 1 underflow
0 1: f(XCIN)
1 0: External count input
CNTR0
1 1: Not available
0: I/O port
6 Timer 1 output
selection bit (P45) 1: Timer 1 output
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
0
0
0
Fig. 2.2.5 Structure of Timer 12 mode register
Timer 34 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 34 mode register
(T34M: address 2916)
b
Name
0 Timer 3 count stop
bit
1 Timer 4 count stop
bit
Timer
3 count
2
source selection
3 bits
4 Timer 4 count
source selection
bits
5
Functions
At reset R W
0: Count operation
1: Count stop
0: Count operation
1: Count stop
0
b3 b2
0
b5 b4
0
0 0: f(XIN)/8 or f(XCIN)/16
0 1: Timer 2 underflow
1 0: f(XIN)/16 or f(XCIN)/32
1 1: f(XIN)/64 or f(XCIN)/128
0 0: f(XIN)/8 or f(XCIN)/16
0 1: Timer 3 underflow
1 0: External count input
CNTR1 (Note)
1 1: Not available
0: I/O port
6 Timer 3 output
selection bit (P46) 1: Timer 3 output
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
0
0
0
Note: In the mask option type P, CNTR1 function cannot be used.
Fig. 2.2.6 Structure of Timer 34 mode register
2-12
38B5 Group User’s Manual
APPLICATION
2.2 Timer
Timer 56 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 56 mode register
(T56M: address 2A16)
b
Name
Functions
0 Timer 5 count stop
bit
1 Timer 6 count stop
bit
2 Timer 5 count
source selection bit
3 Timer 6 operation
mode selection bit
4 Timer 6 count
source selection
5 bits
0: Count operation
1: Count stop
0: Count operation
1: Count stop
0: f(XIN)/8 or f(XCIN)/16
1: Timer 4 underflow
0: Timer mode
1: PWM mode
b5 b4
0 0: f(XIN)/8 or f(XCIN)/16
0 1: Timer 5 underflow
1 0: Timer 4 underflow
1 1: Not available
0: I/O port
1: Timer 6 output
6 Timer 6 (PWM)
output selection bit
(P44)
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.2.7 Structure of Timer 56 mode register
(2) 16-bit timer
Timer X (low-order, high-order)
b7 b6 b5 b4 b3 b2 b1 b0
Timer X (low-order, high-order)
(TXL, TXH: addresses 2C16, 2D16)
b
Functions
0 • Set timer X count value.
1 • When the timer X write control bit of the timer
X mode register 1 is “0”, the value is written to
2
timer X and the latch at one time.
3
When the timer X write control bit of the timer
X mode register 1 is “1”, the value is written
4
only to the latch.
5
• The timer X count value is read out by reading
6
this register.
7
At reset R W
1
1
1
1
1
1
1
1
Notes 1: When reading and writing, perform them to both the highorder and low-order bytes.
2: Read both registers in order of TXH and TXL following.
3: Write both registers in order of TXL and TXH following.
4: Do not read both registers during a write, and do not write to
both registers during a read.
Fig. 2.2.8 Structure of Timer X (low-order, high-order)
38B5 Group User’s Manual
2-13
APPLICATION
2.2 Timer
Timer X mode register 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register 1
(TXM1: address 2E16)
b
Name
0 Timer X write
control bit
Functions
0 : Write value in latch and
counter
1 : Write value in latch only
0
b2 b1
1 Timer X count
0 0: f(XIN)/2 or f(XCIN)/4
source selection bits 0 1: f(XIN)/8 or f(XCIN)/16
1 0: f(XIN)/64 or f(XCIN)/128
2
1 1: Not available
3 Nothing is arranged for this bit. This is write
disabled bit. When this bit is read out, the
contents are “0”.
0
4 Timer X operating
mode bits
5
b5 b4
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width
measurement mode
6 CNTR2 active edge 0 : •Count at rising edge in
event counter mode
switch bit
•Start from “H” output in
pulse output mode
•Measure “H” pulse
width in pulse width
measurement mode
1 : •Count at falling edge in
event counter mode
•Start from “L” output in
pulse output mode
•Measure “L” pulse
width in pulse width
measurement mode
7 Timer X stop
control bit
0 : Count operating
1 : Count stop
Fig. 2.2.9 Structure of Timer X mode register 1
2-14
At reset R W
38B5 Group User’s Manual
0
0
0
0
0
0
APPLICATION
2.2 Timer
Timer X mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register 2
(TXM2: address 2F16)
b
Name
0 Real time port control
bit (P85)
1 Real time port control
bit (P86)
2 P85 data for real time
port
3 P86 data for real time
port
Functions
At reset R W
0: Real time port function is
invalid
1: Real time port function is
valid
0
0: Real time port function is
invalid
1: Real time port function is
valid
0
0: “L” output
1: “H” output
0
0: “L” output
1: “H” output
0
4 Nothing is arranged for these bits. These are
5 write disabled bits. When these bits are read
6 out, the contents are “0”.
7
0
0
0
0
0
Fig. 2.2.10 Structure of Timer X mode register 2
38B5 Group User’s Manual
2-15
APPLICATION
2.2 Timer
(3) 8-bit timer, 16-bit timer
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16)
b
Name
Functions
0 INT0 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
1 INT1 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
2 INT2 interrupt
0 : No interrupt request
request bit
issued
Remote controller
1 : Interrupt request issued
/counter overflow
interrupt request bit
0
✽
3 Serial I/O1 interrupt 0 : No interrupt request
issued
request bit
Serial I/O automatic 1 : Interrupt request issued
transfer interrupt
request bit
0
✽
4 Timer X interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
5 Timer 1 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
6 Timer 2 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
7 Timer 3 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.2.11 Structure of Interrupt request register 1
2-16
At reset R W
38B5 Group User’s Manual
APPLICATION
2.2 Timer
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16)
b
Name
Functions
0 Timer 4 interrupt
0 : No interrupt request issued
request bit (Note)
1 : Interrupt request issued
1 Timer 5 interrupt
0 : No interrupt request issued
request bit
1 : Interrupt request issued
0 : No interrupt request issued
2 Timer 6 interrupt
1 : Interrupt request issued
request bit
3 Serial I/O2 receive 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
0 : No interrupt request issued
4 INT3/Serial I/O2
1 : Interrupt request issued
transmit interrupt
request bit (Note)
0 : No interrupt request issued
5 INT4 interrupt
1 : Interrupt request issued
request bit
A-D converter
interrupt request bit
0 : No interrupt request issued
6 FLD blanking
interrupt request bit 1 : Interrupt request issued
FLD digit interrupt
request bit
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
At reset R W
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽: “0” can be set by software, but “1” cannot be set.
Note: In the mask option type P, if timer 4 interrupt whose count source is
CNTR1 input and INT3 interrupt are selected, these bits do not
become “1”.
Fig. 2.2.12 Structure of Interrupt request register 2
38B5 Group User’s Manual
2-17
APPLICATION
2.2 Timer
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 3E16)
b
Name
Functions
At reset R W
0 INT0 interrupt
enable bit
1 INT1 interrupt
enable bit
2 INT2 interrupt
enable bit
Remote controller
/counter overflow
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
3 Serial I/O1 interrupt
enable bit
Serial I/O automatic
transfer interrupt
enable bit
Timer
X interrupt
4
enable bit
5 Timer 1 interrupt
enable bit
6 Timer 2 interrupt
enable bit
7 Timer 3 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
0
0
Fig. 2.2.13 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2
(ICON2 : address 3F16)
b
Name
Functions
At reset R W
0
0 Timer 4 interrupt
0 : interrupt disabled
enable bit (Note)
1 : Interrupt enabled
0
1 Timer 5 interrupt
0 : interrupt disabled
enable bit
1 : Interrupt enabled
0
2 Timer 6 interrupt
0 : interrupt disabled
enable bit
1 : Interrupt enabled
0
3 Serial I/O2 receive 0 : interrupt disabled
interrupt enable bit 1 : Interrupt enabled
0
0 : interrupt disabled
4 INT3/Serial I/O2
1 : Interrupt enabled
transmit interrupt
enable bit (Note)
0
5 INT4 interrupt
0 : interrupt disabled
1 : Interrupt enabled
enable bit
A-D converter
interrupt enable bit
0
6 FLD blanking
0 : interrupt disabled
interrupt enable bit 1 : Interrupt enabled
FLD digit interrupt
enable bit
7 Fix “0” to this bit.
0
Note: In the mask option type P, timer 4 interrupt whose count source
is CNTR1 input and INT3 interrupt are not available.
Fig. 2.2.14 Structure of Interrupt control register 2
2-18
38B5 Group User’s Manual
APPLICATION
2.2 Timer
2.2.3 Timer application examples
(1) Basic functions and uses
[Function 1] Control of event interval (Timer 1 to Timer 6, Timer X: timer mode)
When a certain time, by setting a count value to each timer, has passed, the timer interrupt request occurs.
<Use>
•Generating of an output signal timing
•Generating of a wait time
[Function 2] Control of cyclic operation (Timer 1 to Timer 6, Timer X: timer mode)
The value of the timer latch is automatically written to the corresponding timer each time the timer
underflows, and each timer interrupt request occurs in cycles.
<Use>
•Generating of cyclic interrupts
•Clock function (measurement of 1 s); see “(2) Timer application example 1”
•Control of a main routine cycle
[Function 3] Output of rectangular waveform
(Timer 1, Timer 3, Timer 6, Timer X: pulse output mode)
The output level of the T1OUT pin, T 3OUT pin, PWM1 pin or CNTR2 pin is inverted each time the timer
underflows.
<Use>
•Piezoelectric buzzer output; see “(3) Timer application example 2”
•Generating of the remote control carrier waveforms
[Function 4] Count of external pulses (Timer 2, Timer 4, Timer X: event counter mode)
External pulses input to the CNTR0 pin, CNTR 1 pin, CNTR 2 pin are counted as the timer count
source (in the event counter mode).
<Use>
•Frequency measurement; see “(4) Timer application example 3”
•Division of external pulses
•Generating of interrupts due to a cycle using external pulses as the count source; count of a reel pulse
[Function 5] Output of PWM signal (Timer 6)
“H” interval and “L” interval are specified, respectively, and the output of pulses from P44/PWM 1
pin is repeated.
<Use>
•Control of electric volume
[Function 6] Measurement of external pulse width (Timer X: pulse width measurement mode)
The “H” or “L” level width of external pulses input to CNTR2 pin is measured.
<Use>
•Measurement of external pulse frequency (measurement of pulse width of FG pulse ✽ for a motor);
see “(5) Timer application example 4”
•Measurement of external pulse duty (when the frequency is fixed)
FG pulse ✽: Pulse used for detecting the motor speed to control the motor speed.
[Function 7] Control of real time port (Timer X: real time port function)
The data for real time is output from the P8 5 pin or P86 pin each time the timer underflows.
<Use>
•Stepping motor control; see “(6) Timer application example 5”
38B5 Group User’s Manual
2-19
APPLICATION
2.2 Timer
(2) Timer application example 1: Clock function (measurement of 1 s)
Outline: The input clock is divided by the timer so that the clock can count up at 1 s intervals.
Specifications: •The clock f(X IN) = 4.19 MHz (2 22 Hz) is divided by the timer.
•The timer 3 interrupt request bit is checked in main routine, and if the interrupt
request is issued, the clock is counted up.
• The timer 1 interrupt occurs every 244 µs to execute processing of other interrupts.
Figure 2.2.15 shows the timers connection and setting of division ratios; Figure 2.2.16 shows the
relevant registers setting; Figure 2.2.17 shows the control procedure.
f(XIN)
4.19 MHz
1/16
Timer 1
Timer 2
Timer 3
1/64
1/256
1/16
Timer 3 interrupt request bit
0/1
1 second
0/1
244 µs
Timer 1 interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
Fig. 2.2.15 Timers connection and setting of division ratios
2-20
38B5 Group User’s Manual
APPLICATION
2.2 Timer
Timer 12 mode register (address 2816)
b7
T12M
b0
0 0 0 0 1 0 0 1
Timer 1 count: Stop; Clear to “0” when starting count.
Timer 2 count: In progress
Timer 1 count source: f(XIN)/16
Timer 2 count source: Timer 1’s underflow
Timer 1 output selection: I/O port
Timer 34 mode register (address 2916)
b7
T34M
0 0
b0
0 1
0
Timer 3 count: In progress
Timer 3 count source: Timer 2’s underflow
Timer 3 output selection: I/O port
Timer 1 (address 2016)
b7
T1
b0
3 F1 6
Timer 2 (address 2116)
b7
T2
b0
Set “division ratio – 1”.
[ T1 = 63 (3F16), T2 = 255 (FF16), T3 = 15 (0F16) ]
FF16
Timer 3 (address 2216)
b7
b0
0 F1 6
T3
Interrupt control register 1 (address 3E16)
b7
ICON1
b0
0 0 1
Timer 1 interrupt: Enabled
Timer 2 interrupt: Disabled
Timer 3 interrupt: Disabled
Interrupt request register 1 (address 3C16)
b7
b0
IREQ1
Timer 1 interrupt request (becomes “1” at 244 µs intervals)
Timer 2 interrupt request
Timer 3 interrupt request (becomes “1” at 1 s intervals)
Fig. 2.2.16 Relevant registers setting
38B5 Group User’s Manual
2-21
APPLICATION
2.2 Timer
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
SEI
.....
•All interrupts disabled
T12M
T34M
IREQ1
ICON1
(address 2816)
(address 2916)
(address 3C16)
(address 3E16)
000010012
00XX01X02
000XXXXX2
001XXXXX2
•Connection of Timers 1 to 3
(address 2016)
(address 2116)
(address 2216)
3 F1 6
FF16
0 F1 6
•Setting “Division ratio – 1” to Timers 1 to 3
•Setting of Interrupt request bits of Timers 1 to 3 to “0”
•Timer 1 interrupt enabled, Timers 2 and 3 interrupts disabled
.....
T1
T2
T3
.....
T12M
(address 2816), bit0
0
•Timer count start
.....
CLI
•Interrupts enabled
Y
Clock is stopped ?
•Judgment whether time is not set or time is being set
N
0
IREQ1 (address 3C16), bit7 ?
•Confirmation that 1 sec. has passed
(Check of Timer 3 interrupt request bit)
1
IREQ1 (address 3C16), bit7
•Interrupt request bit cleared
(Clear it by software when not using the interrupt.)
0
✽
Clock count up
Second to Year
•Clock count up
Main processing
.....
•Adjust the main processing so that all processing in the loop ✽ will
be processed within 1 second interval.
<Procedure for end of clock setting> (Note)
T2
T3
IREQ1
(address 2116)
(address 2216)
(address 3C16), bit7
FF16
0 F1 6
0
•Set Timers again when starting clock from 0 second after
end of clcok setting.
The procedure is Timer 2 setting followed by Timer 3 setting.
•Do not set Timer 1 again because Timer 1 is used to
generate the interrupt at 244 µs intervals.
Note : Perform proc edure f or end o f clock sett ing o nly when end of
clock sett ing.
Fig. 2.2.17 Control procedure
2-22
38B5 Group User’s Manual
APPLICATION
2.2 Timer
(3) Timer application example 2: Piezoelectric buzzer output
Outline: The rectangular waveform output function of the timer is applied for a piezoelectric buzzer
output.
Specifications: •The rectangular waveform, dividing the clock f(XIN) = 4.19 MHz (2 22 Hz) into about
2 kHz (2048 Hz), is output from the P4 6/T3OUT pin.
•The level of the P46/T 3OUT pin is fixed to “H” while a piezoelectric buzzer output
stops.
Figure 2.2.18 shows a peripheral circuit example, and Figure 2.2.19 shows the timers connection and
setting of division ratios. Figures 2.2.20 shows the relevant registers setting, and Figure 2.2.21
shows the control procedure.
The “H” level is output while a piezoelectric buzzer output stops.
T3OUT output
T3OUT
PiPiPi.....
244 µs 244 µs
Set a division ratio so that the underflow
output period of the timer 3 can be 244 µs. 38B5 Group
Fig. 2.2.18 Peripheral circuit example
f(XIN)
4.19 MHz
1/16
Timer 3
Fixed
1/64
1/2
T3OUT
Fig. 2.2.19 Timers connection and setting of division ratios
38B5 Group User’s Manual
2-23
APPLICATION
2.2 Timer
Timer 34 mode register (address 2916)
b7
T34M
b0
0 1
1 0
0
Timer 3 count: In progress
Timer 3 count source: f(XIN)/16
Timer 3 output selection: Buzzer output in progress = “1”
Buzzer output stopped = “0”
Timer 3 (address 2216)
b7
b0
Set “division ratio – 1”; 63 (3F16).
3F16
T3
Interrupt control register 1 (address 3E16)
b7
ICON1
b0
0
Timer 3 interrupt: Disabled
Fig. 2.2.20 Relevant registers setting
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
SEI
•All interrupts disabled
.....
P4D
P4
(address 0916), bit6
(address 0816), bit6
•Port stat e setting at buzzer output stopped; “H” level output
1
1
.....
ICON1 (address 3E16), bit7
T34M (address 2916)
T3
(address 2216)
0
00XX10X02
3 F1 6
•Timer 3 interrupt disabled
•T3OUT output stopped; Buzzer output stopped
.....
•Interrupts enabled
CLI
Main processing
.....
•Processing buzzer request, generated during main
processing, in output unit
Output unit
Piezoelectric buzzer request ?
Yes
No
T34M
T3
(address 2916), bit6
(address 2216)
0
3F16
T34M (address 2916), bit6
Start of piezoelectric buzzer output
Stop of piezoelectric buzzer
output
Fig. 2.2.21 Control procedure
2-24
1
38B5 Group User’s Manual
APPLICATION
2.2 Timer
(4) Timer application example 3: Frequency measurement
Outline: The following two values are compared to judge whether the frequency is within a valid
range.
•A value by counting pulses input to P6 0/CNTR 1 pin with the timer.
•A reference value
Specifications: •The pulse is input to the P60/CNTR 1 pin and counted by the timer 4. (Note 1)
•A count value of timer 4 is read out at about 2 ms intervals, the timer 1 interrupt
interval. When the count value is 28 to 40, it is judged that the input pulse is valid.
•Because the timer is a down-counter, the count value is compared with 227 to 215
(Note 2).
Notes 1: In the mask option type P, use the CNTR0 pin and timer 2.
2: 227 to 215 = {255 (initial value of counter) – 28} to {255 – 40}; 28 to 40 means the number
of valid value.
Figure 2.2.22 shows the judgment method of valid/invalid of input pulses; Figure 2.2.23 shows the
relevant registers setting; Figure 2.2.24 shows the control procedure.
Input pulse
@
@
@
@
71.4 µs or more
(14 kHz or less)
@
@
@
@
71.4 µs
(14 kHz)
@
50 µs
(20 kHz)
Valid
Invalid
2 ms = 28 counts
71.4 µs
@
@
@
50 µs or less
(20 kHz or more)
Invalid
2 ms
50 µs
= 40 counts
Fig. 2.2.22 Judgment method of valid/invalid of input pulses
38B5 Group User’s Manual
2-25
APPLICATION
2.2 Timer
Timer 12 mode register (address 2816)
b7
T12M
b0
0 0
1 0
1
Timer 1 count: Stop; Clear to “0” when starting count.
Timer 1 count source: f(XIN)/16
Timer 1 output selection: I/O port
Timer 34 mode register (address 2916)
b7
T34M
0
b0
1 0
0
Timer 4 count: In progress
Timer 4 count source: External count input CNTR1
Timer 1 (address 2016)
b7
b0
T1
Set “division ratio – 1”; 63 (3F16).
3 F1 6
Timer 4 (address 2316)
b7
b0
T4
Set 255 (FF16) just before counting pulses.
(After a certain time has passed, the number of
input pulses is decreased from this value.)
FF16
Interrupt control register 1 (address 3E16)
b7
ICON1
b0
1
Timer 1 interrupt: Enabled
Interrupt control register 2 (address 3F16)
b7
b0
0
ICON2
Timer 4 interrupt: Disabled
Interrupt request register 2 (address 3D16)
b7
IREQ2
b0
0
Timer 4 interrupt request
( “1” of this bit when reading the count value
indicates the 256 or more pulses input in the
condition of Timer 4 = 255)
Fig. 2.2.23 Relevant registers setting
2-26
38B5 Group User’s Manual
APPLICATION
2.2 Timer
● X: This bit is not used here. Set it to “0” or “1” arbitrary.
RESET
Initialization
•All interrupts disabled
SEI
.....
T12M (address 2816)
(address 2016)
T1
T34M (address 2916)
(address 2316)
T4
ICON1 (address 3E16),bit5
ICON2 (address 3F16),bit0
•Set div ision rat io s o that Timer 1 inte rrupt will oc cur at 244 µs interv als .
•External pulses input from CNTR1 pin selected as Timer 4’s count source
•Setting Timer 4 count value
•Timer 1 interrupt enabled
•Timer 4 interrupt disabled
0
•Timer 1 count start
.....
00XX10X12
3F16
0X10XX0X2
FF16
1
0
T12M (address 2816), bit0
.....
•Interrupts enabled
CLI
Timer 1 interrupt process routine
1/8
CLT (Note 1)
CLD (Note 2)
Push registers to stack
Note 1: When using Index X mode flag (T)
Note 2: When using Decimal mode flag (D)
•Pus hing regis ters u sed in in terrupt process routine
1
•Processing as out of range when the count value is 256 or more
IREQ2 (address 3D16), bit0 ?
(A)
•Set so that pulse judgment process will be performed once each time
Timer 1 interrupt occurs 8 times, at 2 ms intervals.
T4 (address 2316)
•Count value read
•Storing count value into Accumulator (A)
In range
214 < (A) < 228
•Compare the read value with
reference value.
•Store the comparison result to flag Fpulse.
Out of range
Fpulse
Fpulse
0
T4
(address 2316)
IREQ2 (address 3D16), bit0
FF16
0
1
•Initialization of counter value
•Timer 4 interrupt request bit cleared
Process judgment result
Pop registers
•Popping registers pushed to stack
RTI
Fig. 2.2.24 Control procedure
38B5 Group User’s Manual
2-27
APPLICATION
2.2 Timer
(5) Timer application example 4: Measurement of FG pulse width for motor
Outline: The timer X counts the “H” level width of the pulses input to the P6 1/CNTR 0/CNTR 2 pin. An
underflow is detected by the timer X interrupt and an end of the input pulse “H” level is
detected by the timer 2 interrupt of which count source is the input to P61/CNTR0/CNTR2
pin.
Specifications: •The timer X counts the “H” level width of the FG pulse input to the P6 1/CNTR 0/
CNTR2 pin.
<Example>
When f(X IN) = 4.19 MHz, the count source is 15.2 µs, which is obtained by dividing the clock
frequency by 64. Measurement can be made up to 1 s in the range of FFFF 16 to 0000 16 .
Figure 2.2.25 shows the timers connection and setting of division ratio; Figure 2.2.26 shows the
relevant registers setting; Figure 2.2.27 shows the control procedure.
Timer X count source
selection bit
f(XIN) = 4.19 MHz
1/64
Timer X
1/65536
Timer X interrupt
request bit
0/1
1 second
Fig. 2.2.25 Timers connection and setting of division ratios
2-28
38B5 Group User’s Manual
APPLICATION
2.2 Timer
Port P6 direction register (address 0D16)
b7
b0
P6D
0
P61/CNTR0/CNTR2: Input mode
Timer X mode register 1 (address 2E16)
b7
TXM1
b0
1 0 1 1
1 0 0
Write value in latch and counter
Timer X count source: f(XIN)/64
Timer X operating mode: Pulse width measurement mode
CNTR2 active edge: Measuring “H” pulse width in pulse width measurement mode
Timer X count: Stop; Clear to “0” when starting count.
Timer X mode register 2 (address 2F16)
b7
b0
TXM2
0 0
Real time port function (P85): Invalid
Real time port function (P86): Invalid
Timer X (low-order) (address 2C16)
b7
b0
FF16
TXL
Timer X (high-order) (address 2D16)
b7
b0
TXH
Set “65535 (FFFF16)” before stat of pulse width
measurement.
FF16
Interrupt edge selection register (address 3A16)
b7
INTEDGE
b0
1
CNTR0 pin edge: Falling edge count
Timer 12 mode register (address 2816)
b7
T12M
b0
0
1 0
0
Timer 2 count: Stop
Timer 2 count source: External count input CNTR0
Timer 2 (address 2116)
b7
T2
b0
Set “0”.
Timer 2 interrupt request occurs due to falling edge input to CNTR0 pin.
Interrupt control register 1 (address 3E16)
0
b7
ICON1
b0
1
1
Timer X interrupt: Enabled
Timer 2 interrupt: Enabled
Interrupt request register 1 (address 3C16)
b7
b0
IREQ1
Timer X interrupt request (becomes “1” when Timer X underflows)
Timer 2 interrupt request (becomes “1” when “H” level input ends)
Fig. 2.2.26 Relevant registers setting
38B5 Group User’s Manual
2-29
APPLICATION
2.2 Timer
RESET
● X: This bit is not used here. Set it to “0” or “1” arbitrary.
Initialization
SEI
•All interrupts disabled
.....
P6D
(address 0D16),bit1
TXM1
(address 2E16)
TXM2
(address 2F16)
TXL
(address 2C16)
TXH
(address 2D16)
INTEDGE (address 3A16),bit6
T12M
(address 2816)
T2
(address 2116)
ICON1 (address 3E16)
0
1011X1002
XXXXXX002
FF16
FF16
1
0X10XX1X2
0
XXXX1X1X2
•Set ting P61/CNTR0/CNTR2 pin to input mode
•Timer X: Pulse width measurement mode
(Measuring “H” pulse width of input pulses from CNTR2 pin)
•Setting Timer X count value
•CNTR0 pin edge: Falling edge count
•External pulses input from CNTR0 pin selected as Timer 2’s count source
•Setting “0” to Timer 2
•Timers X and 2 interrupts: Enabled
.....
TXM1
T12M
(address 2E16),bit7
(address 2816),bit1
0
0
•Timers X and 2 count start
.....
•Interrupts enabled
CLI
Timer X interrupt process routine (Note 1)
CLT (Note 2)
CLD (Note 3)
Push registers to stack
Notes 1: Timer X interrupt also occurs owing to factors other than
measurement level.(CNTR2 input = “L” in this application)
Process it by software as error proccesing is performed for
measurement level as necessary . CNTR2 input level can be
checked by reading the contents of sharing port P61 register.
2: When using Index X mode flag (T)
3: When using Decimal mode flag (D)
•Pus hing regis ters u sed in in terrupt process routine
Error processing
Pop registers
•Popping registers pushed to stack
RTI
Fig. 2.2.27 Control procedure
2-30
38B5 Group User’s Manual
APPLICATION
2.2 Timer
Timer 2 interrupt process routine (Note 1)
Notes 2: When using Index X mode flag (T)
3: When using Decimal mo de f la g (D)
•Pus hin g r eg is t ers u s ed in in te rru pt p ro ce ss r ou tine
CLT (Note 2)
CLD (Note 3)
Push registers to stack
(A)
Measurement result (high-order 8 bits)
(A)
Measurement result (low-order 8 bits)
TXL
(address 2C16)
TXH
(address 2D16)
TXH
(A)
TXL
(A)
FF16
FF16
Pop registers
•Count value read and storing it to RAM
•Popping registers pushed to stack
RTI
Note 1: The f irst value bec omes invalid depending on start timing of Time X co unt
sho wn by the following f ig ur e.
Pro ce ss it b y s of twar e a s ne ce ss ar y.
[ Example 1] • Start Timer X count when CNTR2 input level is “L”.
(CNTR2 input level can be checked by reading the contents of sharing port P61 register.
FFFF16
T1
T2
000016
T1 value: Valid
T2 value: Valid
CNTR2
Count start of
Timer X
Timer 2 interrupt
Timer 2 interrupt
[ Example 2] • Start Timer X count when CNTR2 input level is “H”.
Invalidate the first Timer 2 interrupt after start of Timer X count.
FFFF16
T1
T2
000016
T1 value: Invalid
T2 value: Valid
CNTR2
Count start of
Timer 2 interrupt
Timer X
Timer 2 interrupt
38B5 Group User’s Manual
2-31
APPLICATION
2.2 Timer
(6) Timer application example 5: Control of stepping motor
Outline: The rotating of stepping motor is controlled by using real time output ports.
Specifications: •The motor is controlled by using 2 real time output ports.
•The count source is f(X IN) = 4.19 MHz divided by 8.
•Values of Timer X and real time output are updated in the timer X interrupt routine
Figure 2.2.28 shows the timers connection and the table example of timer X/RTP setting values;
Figure 29 shows the RTP output example; Figure 2.2.30 shows the relevant registers setting; Figure
2.2.31 shows the control procedure.
RTP P85
TXL
TXH
TXM2
Timer X
table
RTP
table
Motor
RTP P86
38B5 group
Timer X setting table example
RTP
output time Timer X value
T1
2FD016
T2
2B7116
T3
208116
T4
186916
T5
13C916
T6
13A916
T7
122116
T8
11C116
RTP setting table example
RTP value
RTP output
pattern
TXM2,b2 TXM2,b3
(1)
0
0
(2)
0
1
(3)
1
0
(4)
1
1
RTP: Real Time Port
Fig. 2.2.28 Timers connection and table example of timer X/RTP setting values
T1
T2
T3
T4
T5
T6
T7
T8
RTP
output
pattern
( 1)
RTP
output
pattern
( 2)
RTP
output
pattern
( 3)
RTP
output
pattern
( 4)
(1)
(2)
(3)
(4)
RTP output time
RTP P85
RTP P86
RTP: Real Time Port
Fig. 2.2.29 RTP output example
2-32
38B5 Group User’s Manual
APPLICATION
2.2 Timer
Timer X mode register 1 (address 2E16)
b7
TXM1
1
b0
0 0
0 1 0
Write value in latch and counter
Timer X count source: f(XIN)/8
Timer X operating mode: Timer mode
Timer X count: Stop; Clear to “0” when starting count.
Timer X mode register 2 (address 2F16)
b7
b0
TXM2
1 1
Real time port function (P85): Valid
Real time port function (P86): Valid
P85 data for real time port
P86 data for real time port
Timer X (low-order) (address 2C16)
b7
b0
TXL
Timer X (high-order) (address 2D16)
b7
b0
Update the value from the table each time Timer X underflows.
(When accelerating or reducing speed.)
TXH
Interrupt control register 1 (address 3E16)
b7
ICON1
b0
1
Timer X interrupt: Enabled
Fig. 2.2.30 Relevant registers setting
38B5 Group User’s Manual
2-33
APPLICATION
2.2 Timer
● X: This bit is not used here. Set it to “0” or “1” arbitrary.
RESET
Initialization
SEI
•All interrupts disabled
.....
TXM1
TXM2
TXL
TXH
IREQ1
ICON1
(address 2E16)
(address 2F16)
(address 2C16)
(address 2D16)
(address 3C16),bit4
(address 3E16),bit4
1X00X0102
XXXX00112
D016
2F16
0
1
•Setting Timer X
•Setting RTP function, “002” data from table
•Setting Timer X initial value, “2FD02” data from table
0
•Timer X count start
•Timer X interrupt request cleared
•Timer X interrupt enabled
.....
TXM1 (address 2E16), bit7
.....
•Interrupts enabled
CLI
Main processing
.....
RTP: Real Time Port
Timer X interrupt process routine
CLT (Note 1)
CLD (Note 2)
Push registers to stack
Notes 1: When using Index X mode flag (T)
2: When using Decimal mode flag (D)
•Pus hing regis ters u sed in in terrupt process routine
Transfer the next underflow time of Timer X
from internal ROM table and store it to TXL
(address 2C16) and TXH (address 2D16)
Transfer RTP output data from internal
ROM table next underflow of Timer X and
store it to bits 2 and 3 of TXM2 (address
2F16) and TXH (address 2D16)
Pop registers
•Popping registers pushed to stack
RTI
Fig. 2.2.31 Control procedure
2-34
38B5 Group User’s Manual
APPLICATION
2.3 Serial I/O
2.3 Serial I/O
This paragraph explains the registers setting method and the notes relevant to the serial I/O.
2.3.1 Memory map
001616 Baud rate generator (BRG)
001716 UART control register (UARTCON)
001816 Serial I/O1 automatic transfer data pointer (SIO1DP)
001916 Serial I/O1 control register 1 (SIO1CON1,SC11)
001A1 6 Serial I/O1 control register 2 (SIO1CON2,SC12)
001B1 6 Serial I/O1 register/Transfer counter (SIO1)
001C16 Serial I/O1 control register 3 (SIO1CON3,SC13)
001D16 Serial I/O2 control register (SIO2CON)
001E1 6 Serial I/O2 status register (SIO2STS)
001F16 Serial I/O2 transmit/receive buffer register (TB/RB)
003916 Interrupt source switch register (IFR)
003C16 Interrupt request register 1 (IREQ1)
003D16 Interrupt request register 2 (IREQ2)
003E1 6 Interrupt control register 1 (ICON1)
003F16 Interrupt control register 2 (ICON2)
Fig. 2.3.1 Memory map of registers relevant to Serial I/O
38B5 Group User’s Manual
2-35
APPLICATION
2.3 Serial I/O
2.3.2 Relevant registers
(1) Serial I/O1
Serial I/O1 automatic transfer data pointer
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 automatic transfer data pointer
(SIO1DP: address 1816)
b
Functions
0 • Indicates the low-order 8 bits of the address
1 storing the start data on the serial I/O.
2 automatic transfer RAM.
3 • Data is written into the latch and read from the
4 decrement counter.
5
6
7
Fig. 2.3.2 Structure of Serial I/O1 automatic transfer data pointer
2-36
38B5 Group User’s Manual
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
APPLICATION
2.3 Serial I/O
Serial I/O1 control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 1
(SIO1CON1•SC11: address 1916)
b
Name
0 Serial transfer
selection bits
1
2 Serial I/O1
synchronous clock
selection bits
(P65/SSTB1 pin
control bits)
3
Functions
b1b0
0 0: Serial I/O disabled
(Pins P62, P64, P65,
P50–P53 pins are I/O
ports.)
0 1: 8-bit serial I/O
1 0: Not available
1 1: Automatic transfer
serial I/O (8 bits)
b3b2
0 0: Internal synchronous
clock (P65 pin is I/O
port.)
0 1: External synchronous
clock (P65 pin is I/O
port.)
1 0: Internal synchronous
clock (P65 pin is
SSTB1 output.)
1 1: Internal synchronous
clock (P65 pin is
SSTB1 output.)
At reset R W
0
0
0
0
4 Serial I/O
initialization bit
5 Transfer mode
selection bit
0: Serial I/O initialization
1: Serial I/O enabled
0: Full-duplex
(transmit/receive) mode
(P50 pin is SIN1 input.)
1: Transmit-only mode
(P50 pin is I/O port.)
0
6 Transfer direction
selection bit
0: LSB first
1: MSB first
0
7 Serial I/O1 clock pin 0: SCLK11 (P53/SCLK12 pin
selection bit
is I/O port.)
1: SCLK12 (P52/SCLK11 pin
is I/O port.)
0
0
Fig. 2.3.3 Structure of Serial I/O1 control register 1
38B5 Group User’s Manual
2-37
APPLICATION
2.3 Serial I/O
Serial I/O1 control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 2
(SIO1CON2 • SC12: address 1A16)
b
Name
Functions
0 P62/SRDY1 •
P64/SBUSY1 pin
control bits
At reset R W
0
b3b2b1b0
1
2
3
4
5
0 0 0 0: P62, P64 pins are I/O ports.
0 0 0 1: Not used
0 0 1 0: P62 pin is SRDY1 output; P64 pin is
I/O port.
0 0 1 1: P62 pin is SRDY1 output; P64 pin is
I/O port.
0 1 0 0: P62 pin is I/O port; P64 pin is
SBUSY1 input.
0 1 0 1: P62 pin is I/O port; P64 pin is
SBUSY1 input.
0 1 1 0: P62 pin is I/O port; P64 pin is
SBUSY1 output.
0 1 1 1: P62 pin is I/O port; P64 pin is
SBUSY1 output.
1 0 0 0: P62 pin is SRDY1 input; P64 pin is
SBUSY1 output.
1 0 0 1: P62 pin is SRDY1 input; P64 pin is
SBUSY1 output.
1 0 1 0: P62 pin is SRDY1 input; P64 pin is
SBUSY1 output.
1 0 1 1: P62 pin is SRDY1 input; P64 pin is
SBUSY1 output.
1 1 0 0: P62 pin is SRDY1 output; P64 pin is
SBUSY1 input.
1 1 0 1: P62 pin is SRDY1 output; P64 pin is
SBUSY1 input.
1 1 1 0: P62 pin is SRDY1 output; P64 pin is
SBUSY1 input.
1 1 1 1: P62 pin is SRDY1 output; P64 pin is
SBUSY1 input.
SBUSY1 output •
0: Functions as signal for
SSTB1 output
each 1-byte
function selection bit 1: Functions as signal for
(Valid in serial I/O1
each transfer data set
automatic transfer
mode)
Serial transfer
0: Serial transfer
status flag
completed
1: Serial transfer inprogress
0
0
0
0
6 SOUT1 pin control
0: Output active
bit (when serial data 1: Output high-impedance
is not transferred)
0
7 P51/SOUT1 P-channel 0: CMOS 3 state (Poutput disable bit
channel output is valid.)
1: N-channel open-drain
output (P-channel output
is invalid.)
0
Fig. 2.3.4 Structure of Serial I/O1 control register 2
2-38
0
38B5 Group User’s Manual
APPLICATION
2.3 Serial I/O
Serial I/O1 register/Transfer counter
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 register/Transfer counter
(SIO1: address 1B16)
b
Name
Functions
At reset R W
•At function as serial I/O1
Undefined
register:
This register becomes the
shift register to perform
Undefined
serial transmit/reception.
•In automatic transfer
Set transmit data to this
serial I/O mode:
register.
Transfer counter
Undefined
The serial transfer is started
by writing the transmit data.
0 •In 8-bit serial I/O
mode:
Serial I/O1 register
1
2
3
4
5
6
7
•At function as transfer
counter:
Set (transfer byte number –
1) to this register.
When selecting an internal
clock, the automatic
transfer is started by writing
the transmit data.
(When selecting an external
clock, after writing a value
to this register, wait for 5 or
more cycles of the internal
system clock before
inputting the transfer clock
to the SCLK1 pin.)
Undefined
Undefined
Undefined
Undefined
Undefined
Fig. 2.3.5 Structure of Serial I/O1 register/Transfer counter
38B5 Group User’s Manual
2-39
APPLICATION
2.3 Serial I/O
Serial I/O1 control register 3
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 3
(SIO1CON3 • SC13: address 1C16)
b
Name
Functions
0 Automatic transfer b4b3b2b1b0
0 0 0 0 0: 2 cycles of
interval set bits
transfer clock
(valid only when
0 0 0 0 1: 3 cycles of
1 selecting internal
transfer clock
synchronous clock)
to
1
1
1
1
0:
32
cycles of
2
transfer clock
1 1 1 1 1: 33 cycles of
3
transfer clock
4
5 Internal
synchronous clock
selection bits
6
7
0
0
0
0
Data is written into the
latch and read from the
decrement counter.
0
b7b6b5
0
0 0 0 : f(XIN)/4 or f(XCIN)/8
0 0 1 : f(XIN)/8 or
f(XCIN)/16
0 1 0 : f(XIN)/16 or
f(XCIN)/32
0 1 1 : f(XIN)/32 or
f(XCIN)/64
1 0 0 : f(XIN)/64 or
f(XCIN)/128
1 0 1 : f(XIN)/128 or
f(XCIN)/256
1 1 0 : f(XIN)/256 or
f(XCIN)/512
1 1 1 : Not used
Fig. 2.3.6 Structure of Serial I/O1 control register 3
2-40
At reset R W
38B5 Group User’s Manual
0
0
APPLICATION
2.3 Serial I/O
(2)
Serial I/O2
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator
(BRG: address 1616)
b
Functions
At reset R W
0 • Bit rate of the serial transfer is determined.
• This is the 8-bit counter and has the reload
1
register.
The count source is divided by n+1 owing to
2
specifying a value n.
3
Undefined
4
Undefined
5
Undefined
6
Undefined
7
Undefined
Undefined
Undefined
Undefined
Fig. 2.3.7 Structure of Baud rate generator
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register
(UARTCON: address 1716)
b
Name
Functions
0
Character length
selection bit (CHAS)
Parity enable bit
(PARE)
Parity selection bit
(PARS)
Stop bit length
selection bit (STPS)
P55/TxD P-channel
output disable bit
(POFF)
0: 8 bits
1: 7 bits
0: Parity checking disabled
1: Parity checking enabled
0: Even parity
1: Odd parity
0: 1 stop bit
1: 2 stop bits
0
0: CMOS output (in output
mode)
1: N-channel open-drain
output (in output mode)
0
1
2
3
4
At reset R W
0
0
0
5 BRG clock switch bit 0: XIN or XCIN/2 (depending
on internal system clock)
1: XCIN
6 Serial I/O2 clock
0: SCLK21 (P57/SCLK22 pin is
used as I/O port or SRDY2
I/O pin selection bit
output pin.)
1: SCLK22 (P56/SCLK21 pin is
used as I/O port.)
0
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “1”.
1
0
Fig. 2.3.8 Structure of UART control register
38B5 Group User’s Manual
2-41
APPLICATION
2.3 Serial I/O
Serial I/O2 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register
(SIO2CON: address 1D16)
b
Name
Functions
0: f(XIN) or f(XCIN)/2 or
f(XCIN)
1: f(XIN)/4 or f(XCIN)/8 or
f(XCIN)/4
0
1 Serial I/O2
synchronous clock
selection bit
(SCS)
•In clock synchronous
mode
0: BRG output/4
1: External clock input
•In UART mode
0: BRG output/16
1: External clock input/16
0
2 SRDY2 output
enable bit (SRDY)
0: P57 pin operates as
normal I/O pin
1: P57 pin operates as
SRDY2 output pin
0
0: When transmit buffer
3 Transmit interrupt
has emptied
source selection bit
1: When transmit shift
(TIC)
operation is completed
0
4 Transmit enable bit
(TE)
5 Receive enable bit
(RE)
6 Serial I/O2 mode
selection bit (SIOM)
0: Transmit disabled
1: Transmit enabled
0: Receive disabled
1: Receive enabled
0: Clock asynchronous
serial I/O (UART) mode
1: Clock synchronous
serial I/O mode
0
7 Serial I/O2 enable
bit (SIOE)
0: Serial I/O2 disabled
(pins P54–P57 operate
as normal I/O pins)
1: Serial I/O2 enabled
(pins P54–P57 operate
as serial I/O pins)
0
Fig. 2.3.9 Structure of Serial I/O2 control register
2-42
At reset R W
0 BRG count source
selection bit (CSS)
38B5 Group User’s Manual
0
0
APPLICATION
2.3 Serial I/O
Serial I/O2 status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 status register
(SIO2STS: address 1E16)
b
Name
Functions
0 Transmit buffer
empty flag (TBE)
1 Receive buffer full
flag (RBF)
2 Transmit shift
register shift
completion flag
(TSC)
0: Buffer full
1: Buffer empty
0: Buffer empty
1: Buffer full
0: Transmit shift in progress
1: Transmit shift completed
3 Overrun error flag
(OE)
Parity
error flag
4
(PE)
0: No error
1: Overrun error
0: No error
1: Parity error
5 Framing error flag 0: No error
1: Framing error
(FE)
6 Summing error flag 0: (OE) U (PE) U (FE) = 0
(SE)
1: (OE) U (PE) U (FE) = 1
Nothing
is
arranged
for
this bit. This is a write
7
disabled bit. When this bit is read out, the
contents are “1”.
At reset R W
0
0
0
0
0
0
0
1
Fig. 2.3.10 Structure of Serial I/O2 status register
Serial I/O2 transmit/receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 transmit/receive buffer register
(TB/RB: address 1F16)
b
Functions
0 This is the buffer register which is used to write
transmit data or to read receive data.
1
• At write : The value is written to the transmit
buffer register. The value cannot be
2
written to the receive buffer register.
3 • At read : The contents of the receive buffer
register is read out. When a
4
character bit length is 7 bits, the
5
MSB of data stored in the receive
buffer is “0”. The contents of the
6
transmit buffer register cannot be
7
read out.
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Fig. 2.3.11 Structure of Serial I/O2 transmit/receive buffer register
38B5 Group User’s Manual
2-43
APPLICATION
2.3 Serial I/O
(3) Serial I/O1 and Serial I/O2
Interrupt source switch register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt source switch register
(IFR: address 3916)
b
Name
Functions
0 INT3/serial I/O2
transmit interrupt
switch bit (Note)
0: INT3 intrrupt
1: Serial I/O2 transmit
interrupt
0: INT4 interrupt
1 INT4/A-D
conversion interrupt 1: A-D conversion intrerrupt
switch bit
At reset R W
0
0
0
2 Nothing is arranged for these bits. These are
0
3 write disabled bits. When these bits are read
4 out, the contents are “0”.
0
5
0
6
0
0
7
Note: In the mask option type P, this bit is not available because INT3
funciton is not used.
Fig. 2.3.12 Structure of Interrupt source switch register
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16)
b
Name
Functions
0 INT0 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
1 INT1 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
2 INT2 interrupt
0 : No interrupt request
request bit
issued
Remote controller
1 : Interrupt request issued
/counter overflow
interrupt request bit
0
✽
3 Serial I/O1 interrupt 0 : No interrupt request
issued
request bit
Serial I/O automatic 1 : Interrupt request issued
transfer interrupt
request bit
0
✽
4 Timer X interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
5 Timer 1 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
6 Timer 2 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
7 Timer 3 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.3.13 Structure of Interrupt request register 1
2-44
At reset R W
38B5 Group User’s Manual
APPLICATION
2.3 Serial I/O
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16)
b
Name
Functions
0 : No interrupt request issued
0 Timer 4 interrupt
1 : Interrupt request issued
request bit (Note)
0 : No interrupt request issued
1 Timer 5 interrupt
1 : Interrupt request issued
request bit
0 : No interrupt request issued
2 Timer 6 interrupt
1 : Interrupt request issued
request bit
3 Serial I/O2 receive 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
0 : No interrupt request issued
4 INT3/Serial I/O2
1 : Interrupt request issued
transmit interrupt
request bit (Note)
0 : No interrupt request issued
5 INT4 interrupt
1 : Interrupt request issued
request bit
A-D converter
interrupt request bit
0 : No interrupt request issued
6 FLD blanking
interrupt request bit 1 : Interrupt request issued
FLD digit interrupt
request bit
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
At reset R W
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽: “0” can be set by software, but “1” cannot be set.
Note: In the mask option type P, if timer 4 interrupt whose count source is
CNTR1 input and INT3 interrupt are selected, these bits do not
become “1”.
Fig. 2.3.14 Structure of Interrupt request register 2
38B5 Group User’s Manual
2-45
APPLICATION
2.3 Serial I/O
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 3E16)
b
Name
Functions
At reset R W
0 INT0 interrupt
enable bit
1 INT1 interrupt
enable bit
2 INT2 interrupt
enable bit
Remote controller
/counter overflow
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
3 Serial I/O1 interrupt
enable bit
Serial I/O automatic
transfer interrupt
enable bit
Timer
X interrupt
4
enable bit
5 Timer 1 interrupt
enable bit
6 Timer 2 interrupt
enable bit
7 Timer 3 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
0
0
Fig. 2.3.15 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2
(ICON2 : address 3F16)
b
Name
Functions
At reset R W
0
0 Timer 4 interrupt
0 : interrupt disabled
enable bit (Note)
1 : Interrupt enabled
0
1 Timer 5 interrupt
0 : interrupt disabled
enable bit
1 : Interrupt enabled
0
2 Timer 6 interrupt
0 : interrupt disabled
enable bit
1 : Interrupt enabled
0
3 Serial I/O2 receive 0 : interrupt disabled
interrupt enable bit 1 : Interrupt enabled
0
0 : interrupt disabled
4 INT3/Serial I/O2
1 : Interrupt enabled
transmit interrupt
enable bit (Note)
0
5 INT4 interrupt
0 : interrupt disabled
1 : Interrupt enabled
enable bit
A-D converter
interrupt enable bit
0
6 FLD blanking
0 : interrupt disabled
interrupt enable bit 1 : Interrupt enabled
FLD digit interrupt
enable bit
7 Fix “0” to this bit.
0
Note: In the mask option type P, timer 4 interrupt whose count source
is CNTR1 input and INT3 interrupt are not available.
Fig. 2.3.16 Structure of Interrupt control register 2
2-46
38B5 Group User’s Manual
APPLICATION
2.3 Serial I/O
2.3.3 Serial I/O1 connection examples
(1) Control of peripheral IC equipped with CS pin
Figure 2.3.17 shows connection examples with peripheral ICs equipped with the CS pin.
All examples can use the automatic transfer function.
(1) Only transmission
(Using SIN1 pin as I/O port)
SBUSY1
SCLK11
SOUT1
38B5 group
(2) Transmission and reception
CS
CLK
DATA
SBUSY1
SCLK11
SOUT1
SIN1
Peripheral IC
(OSD controller etc.)
38B5 group
(3) Transmission and reception
(When connecting SIN1 with SOUT1)
(When connecting IN with OUT in
peripheral IC)
SBUSY1
SCLK11
SOUT1
SIN1
38B5 group✽1
CS
CLK
IN
OUT
Peripheral IC
(EEPROM etc.)
(4) Connection of plural IC
Port
CS
CLK
IN
OUT
SCLK11
CL K
SOUT1
IN
SIN1
Port
Peripheral IC ✽2
(EEPROM etc.)
CS
O UT
Peripheral IC 1
38B5 group
✽1: Select an N-channel open-drain output for SOUT1 pin
output control.
✽2: Use the OUT pin of peripheral IC which is an Nchannel open-drain output and becomes high impedance during receiving data.
CS
CLK
IN
OUT
Peripheral IC 2
Note: “Port” means an output port controlled by software.
Fig. 2.3.17 Serial I/O1 connection examples (1)
38B5 Group User’s Manual
2-47
APPLICATION
2.3 Serial I/O
(2)
Connection with microcomputer
Figure 2.3.18 shows connection examples with another microcomputer.
(1) Selecting internal clock
(2) Selecting external clock
SCLK11
CLK
SCLK11
CLK
SOUT1
IN
SOUT1
IN
SIN1
38B5 group
OUT
SIN1
Microcomputer
38B5 group
(3) Using SRDY1 signal output function
(Selecting external clock)
SRDY1
SCLK11
SOUT1
SIN1
38B5 group
OUT
Microcomputer
(4) Using switch function of CLK signal output
pins, SCLK12 (Selecting internal clock)
RDY
SCLK11
CLK
CLK
SOUT1
IN
SIN1
IN
OUT
SCLK12
OUT
Port
Microcomputer
Microcomputer
38B5 group
CLK
IN
OUT
CS
Peripheral IC
Fig. 2.3.18 Serial I/O1 connection examples (2)
2-48
38B5 Group User’s Manual
APPLICATION
2.3 Serial I/O
2.3.4 Serial I/O1’s modes
Figure 2.3.19 shows the serial I/O1’s modes.
Output SRDY1 ✽ signal
Input SRDY1 ✽ signal (Note)
Used
handshake
signal
Output SBUSY1 ✽ signal
Input SBUSY1 ✽ signal
Internal
clock
Full duplex
mode
8-bit serial
I/O
Transmit
only mode
Automatic
transfer
serial I/O
Output SSTB1 ✽ signal
Not used
handshake
signal
Serial I/O1
Output SRDY1 ✽ signal
Used
handshake
signal
External
clock
Input SRDY1 ✽ signal (Note)
Output SBUSY1 ✽ signal
Input SBUSY1 ✽ signal
Not used
handshake
signal
Note: This is only valid when outputting the SBUSY1 signal.
✽ Active logic can apply to each signal of SRDY1, SBUSY1, SSTB1.
Fig. 2.3.19 Serial I/O1’s modes
38B5 Group User’s Manual
2-49
APPLICATION
2.3 Serial I/O
2.3.5 Serial I/O1 application examples
(1) Output of serial data (control of peripheral IC)
Outline : Serial communication is performed, connecting ports with the CS pin of a peripheral IC.
Figure 2.3.20 shows a connection diagram, and Figure 2.3.21 shows a timing chart.
CS
P62
CS
CLK
P52/SCLK11
CLK
DATA
P51/SOUT1
DATA
38B5 group
Peripheral IC
Fig. 2.3.20 Connection diagram
Specifications : • Use of serial I/O1 (Not using automatic transfer function)
• Synchronous clock frequency : 131 kHz (f(XIN ) = 4.19 MHz is divided by 32)
• Transfer direction : LSB first
• Not use of serial I/O1 interrupt
• Port P62 is connected to the CS pin (“L” active) of the peripheral IC for transmission
control; the output level of port P6 2 is controlled by software.
CS
CLK
DATA
D O0
D O1
D O2
Fig. 2.3.21 Timing chart
2-50
38B5 Group User’s Manual
D O3
APPLICATION
2.3 Serial I/O
Figure 2.3.22 shows the registers setting relevant to the transmission side, and Figure 2.3.23 shows
the setting of transmission data.
Serial I/O1 control register 1 (address 001916)
SIO1CON1 0 0 1 0 0 0 0 1
(SC11)
8-bit serial I/O
Internal synchronous clock (P65 pin is an I/O port.)
Serial I/O initialization
Transmit-only mode
LSB first
Serial I/O1 clock pin: SCLK11
Serial I/O1 control register 2 (address 001A16)
SIO1CON2 0 0
(SC12)
0 0 0 0
Pins P62 and P64 of I/O ports
SOUT1 pin: Output active
P51/SOUT1: CMOS 3-state (P-channel output is valid.)
Serial I/O1 control register 3 (address 001C16)
SIO1CON3 0 1
(SC13)
1
Internal synchronous clock: f(XIN)/32
Port P6 (address 000C16)
P6
1
Set P62 output level to “H”
Port P6 direction register (address 000D16)
P6D
1
Set P62 to output mode
Fig. 2.3.22 Registers setting relevant to transmission side
Serial I/O1 register (001B16)
Set a transmission data.
Confirm that transmission of the previous
data is completed, where bit 5, the serial
transfer status flag of the serial I/O1 control
register 2, is “0”; before writing data.
SIO1
Fig. 2.3.23 Setting of transmission data
38B5 Group User’s Manual
2-51
APPLICATION
2.3 Serial I/O
Control procedure: When the registers are set as shown in Figure 2.3.22, the serial I/O1 can transmit
1-byte data by writing data to the serial I/O1 register.
Thus, after setting the CS signal to “L”, write the transmission data to the serial
I/O1 register by each 1 byte; and return the CS signal to “H” when the target
number of bytes has been transmitted.
Figure 2.3.24 shows a control procedure.
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
.....
SC11 (address 001916)
SC12 (address 001A16)
SC13 (address 001C16)
P6 (address 000C16), bit2
P6D (address 000D16), bit2
SC11 (address 001916), bit4
001000012
00XX00002
011XXXXX2
1
1
1
Serial I/O1 setting
CS signal output level to “H” setting
CS signal output port setting
Enabled serial I/O1
.....
P6 (address 000C16), bit2
SIO1 (address 001B16)
0
CS signal output level to “L” setting
Transmission data
Transmission data write
(Start of 1-byte data transmission)
SIO1CON2 (address 001A16), bit5 ?
1
Judgment of completion of transmitting 1-byte
data
0
N
All data have been transmitted ?
Use any of RAM area as a counter for counting
the number of transmitted bytes.
Judgment of completion of transmitting the target
number of bytes
Y
P6 (address 000C16), bit2
1
Returning CS signal output level to “H” when
transmission of the target number of bytes is
completed
Fig. 2.3.24 Control procedure
2-52
38B5 Group User’s Manual
APPLICATION
2.3 Serial I/O
(2)
Transmission/Reception using automatic transfer
Outline: Serial transmission/reception control is performed, using the serial automatic transfer function.
Figure 2.3.25 shows a connection diagram, and Figure 2.3.26 shows a timing chart of serial data
transmission/reception.
P52/SCLK11
CLK
P51/SOUT1
IN
P50/SIN1
OUT
Sub microcomputer
38B5 group
Fig. 2.3.25 Connection diagram
Specifications: •
•
•
•
•
•
Use of serial I/O1 using automatic transfer function
Synchronous clock frequency: 131 kHz (f(X IN ) = 4.19 MHz is divided by 32.)
Transfer direction: LSB first
Transmission/reception byte number: 8 bytes/block each
Transfer interval for 1-byte: 244 µs (32 cycles of transfer clock)
Not use of serial I/O1 automatic transfer interrupt
Figure 2.3.27 shows the relevant registers setting, and Figure 2.3.28 shows the control procedure.
1 block
CLK
OUT
IN
D O0
D O1
D O2
D O7
D O0
D O1
D I0
D I1
D I2
D I7
D I0
D I1
Block period is controlled by software.
(Synchronize it with the main routine.)
Fig. 2.3.26 Timing chart of serial data transmission/reception
38B5 Group User’s Manual
2-53
APPLICATION
2.3 Serial I/O
Serial I/O1 control register 1 (address 001916)
SIO1CON1
(SC11)
0 0 0 0 0 0 1 1
Automatic transfer serial I/O (8 bits)
Internal synchronous clock (P65 pin is an I/O port.)
Serial I/O initialization
Full duplex mode
LSB first
Serial I/O1 clock pin: SCLK11
Serial I/O1 control register 2 (address 001A16)
SIO1CON2 0 0
(SC12)
0 0 0 0
Pins P62 and P64 of I/O ports
SOUT1 pin: Output active
P51/SOUT1: CMOS 3-state
Serial I/O1 control register 3 (address 001C16)
SIO1CON3 0 1 1 1 1 1 1 0
(SC13)
Automatic transfer interval set bits: 32 cycles of transfer clock
Internal synchronous clock: f(XIN)/32
Serial I/O1 automatic transfer data pointer (address 001816)
0716
SIO1DP
Set low-order 8 bits of address 0F0716 (=0716)
Transfer counter (address 001B16)
Set the number of transfer bytes – 1 = 7
(Automatic transfer stars by writing to this register
when selecting an internal synchronous clock.)
0716
SIO1
Automatic transfer RAM of serial I/O (addresses 0F0016 to 0FFF16, its addresses 0F6016 to 0FFF16
shared by FLD automatic display RAM
SIORAM
0F0016
0F0116
D O7
D O6
0F0016
0F0116
D I7
DI6
0F0616
0F0716
DI1
DI0
Transfer counter
Serial I/O1
automatic transfer
data pointer
0F0616
0F0716
0716
0716
D O1
D O0
Automatic transfer executed
The area of addresses 0F0816 to 0FFF16, which is not used as automatic transfer,
can be used as normal RAM; the area of addresses 0F6016 to 0FFF16 can be
used as FLD automatic display RAM.
Fig. 2.3.27 Relevant registers setting
2-54
38B5 Group User’s Manual
APPLICATION
2.3 Serial I/O
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
.....
SC11 (address 001916)
SC12 (address 001A16)
SC13 (address 001C16)
SIO1DP (address 001816)
SC11 (address 001916), bit4
000000112
00XX00002
011111102
0716
1
Serial I/O1 initial setting
Setting of automatic transfer function
Enabled serial I/O1
.....
The time to control main routine
period has passed ?
N
Generating certain period timing using timer’s functions
(Control so that main routine will be executed at certain
period.)
Y
Automatic transfer RAM of
serial I/O (addresses 0F0016
to 0F0716)
SIO1 (address 001B16)
Transmitted
data RAM
1-block data, 8 bytes, to be transmitted set in RAM
Number of transferred count set causing automatic
transfer start
(Set the number of transfer bytes – 1.)
8–1
Possible to process others during automatic transfer
(Perform part of main processing.)
SIO1CON2 (address 001A16), bit5 ?
1
Judgment of completion of automatic transfer
0
Received data
RAM
Automatic transfer RAM of
serial I/O (addresses 0F0016
to 0F0716)
Main processing
Taking received data into RAM for processing
Processing data taken into received data
RAM and preparing next transmission data in
main routine
Fig. 2.3.28 Control procedure
38B5 Group User’s Manual
2-55
APPLICATION
2.3 Serial I/O
2.3.6 Serial I/O2 connection examples
(1) Control of peripheral IC equipped with CS pin
Figure 2.3.29 shows connection examples with peripheral ICs equipped with the CS pin.
(1) Only transmission
(Using RxD pin as I/O port)
Port
SCLK21
TxD
38B5 group
(2) Transmission and reception
CS
CLK
DATA
Port
SCLK21
TxD
RxD
Peripheral IC
(OSD controller etc.)
38B5 group
(3) Transmission and reception
(When connecting RxD with TxD)
(When connecting IN with OUT in
peripheral IC)
Port
SCLK21
TxD
RxD
38B5 group ✽1
CS
CLK
IN
OUT
Peripheral IC
(EEPROM etc.)
(4) Connection of plural IC
CS
CLK
IN
OUT
Port
SCLK21
CL K
TxD
IN
RxD
O UT
Port
Peripheral IC ✽2
(EEPROM etc.)
CS
Peripheral IC 1
38B5 group
✽1: Select an N-channel open-drain output for TxD pin
output control.
✽2: Use the OUT pin of peripheral IC which is an Nchannel open-drain output and becomes high impedance during receiving data.
CS
CLK
IN
OUT
Peripheral IC 2
Note: “Port” means an output port controlled by software.
Fig. 2.3.29 Serial I/O2 connection examples (1)
2-56
38B5 Group User’s Manual
APPLICATION
2.3 Serial I/O
(2)
Connection with microcomputer
Figure 2.3.30 shows connection examples with another microcomputer.
(1) Selecting internal clock
SCLK21
(2) Selecting external clock
CLK
SCLK21
CLK
TxD
IN
TxD
IN
RxD
OUT
RxD
OUT
38B5 group
Microcomputer
38B5 group
(3) Using SRDY2 signal output function
(Selecting external clock)
SRDY2
SCLK21
TxD
RxD
38B5 group
Microcomputer
(4) Using switch function of CLK signal output
pins, SCLK22, (Selecting internal clock)
RDY
SCLK21
CLK
TxD
IN
IN
RxD
OUT
CLK
SCLK22
OUT
Port
Microcomputer
Microcomputer
38B5 group
CLK
IN
OUT
CS
(5) In UART
Peripheral IC
TxD
RxD
RxD
TxD
38B5 group
Microcomputer
Fig. 2.3.30 Serial I/O2 connection examples (2)
38B5 Group User’s Manual
2-57
APPLICATION
2.3 Serial I/O
2.3.7 Serial I/O2’s modes
A clock synchronous or clock asynchronous (UART) can be selected for the serial I/O2.
Figure 2.3.31 shows the serial I/O2’s modes, and Figure 2.3.32 shows the serial I/O2 transfer data format.
Internal clock
Output SRDY2 signal
Clock synchronous serial I/O
External clock
Serial I/O2
Not output SRDY2 signal
Clock asynchronous serial I/O
(UART)
Fig. 2.3.31 Serial I/O2’s modes
Clock synchronous serial I/O
1ST-8DATA-1SP
ST
LSB
MSB SP
1ST-7DATA-1SP
Serial I/O2
ST
LSB
MSB SP
1ST-8DATA-1PAR-1SP
ST
LSB
MSB PAR SP
1ST-7DATA-1PAR-1SP
ST
LSB
MSB PAR SP
UART
1ST-8DATA-2SP
ST
LSB
MSB 2SP
1ST-7DATA-2SP
ST
LSB
MSB 2SP
1ST-8DATA-1PAR-2SP
ST
LSB
MSB PAR 2SP
1ST-7DATA-1PAR-2SP
ST
LSB
Fig. 2.3.32 Serial I/O2 transfer data format
2-58
38B5 Group User’s Manual
MSB PAR 2SP
APPLICATION
2.3 Serial I/O
2.3.8 Serial I/O2 application examples
(1) Communication (transmission/reception) using clock synchronous serial I/O
Outline : 2-byte data is transmitted and received, using the clock synchronous serial I/O.
The S RDY2 signal is used for communication control.
Figure 2.3.33 shows a connection diagram, and Figure 2.3.34 shows a timing chart.
P40/INT0
SRDY2
SCLK21
SCLK21
TxD
RxD
38B5 group
38B5 group
Fig. 2.3.33 Connection diagram
Specifications : •
•
•
•
Use of serial I/O2 in clock synchronous serial I/O
Synchronous clock frequency : 125 kHz (f(X IN) = 4 MHz is divided by 32)
Use of SRDY2 (receivable signal)
The reception side outputs the SRDY2 signal at intervals of 2 ms (generated by the
timer), and 2-byte data is transferred from the transmission side to the reception
side.
SRDY2
...
SCLK21
...
TxD
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1
...
2 ms
Fig. 2.3.34 Timing chart
38B5 Group User’s Manual
2-59
APPLICATION
2.3 Serial I/O
Figure 2.3.35 shows the registers setting relevant to the transmission side, and Figure 2.3.36 shows
the registers setting relevant to the reception side.
Transmission side
Serial I/O2 status register (address 001E16)
SIO2STS
Transmit buffer empty flag
• Confirm that the data has been transferred from Transmit buffer
register to Transmit shift register.
• When this flag is “1”, it is possible to write the next transmission
data in to Transmit buffer register.
Transmit shift register shift completion flag
Confirm completion of transmitting 1-byte data with this flag.
“1” : Transmit shift completed
Serial I/O2 control register (address 001D16)
SIO2CON
1 1 0 1
0 0 0
BRG count source: f(XIN)
Synchronous clock: BRG/4
SRDY2 output not used
Transmit enabled
Receive disabled
Clock synchronous serial I/O
Serial I/O2 enabled
UART control register (address 001716)
UARTCON
0 0 0
P55/TxD pin: CMOS output
BRG clock: f(XIN)
Serial I/O2 clock: SCLK21
Baud rate generator (address 001616)
B RG
Set “division ratio – 1”
0716
Interrupt edge selection register (address 003A16)
INTEDGE
0
INT0 falling edge active
Fig. 2.3.35 Registers setting relevant to transmission side
2-60
38B5 Group User’s Manual
APPLICATION
2.3 Serial I/O
Reception side
Serial I/O2 status register (address 001E16)
SIO2STS
Receive buffer full flag
Confirm completion of receiving 1-byte data with this flag.
“1” : at completing reception
“0” : at reading out contents of Receive buffer register
Overrun error flag
“1” : When data is ready in Receive shift register while Receive buffer
register contains the data.
Serial I/O2 control register (address 001D16)
SIO2CON
1 1 1 1
1 1
Synchronous clock: External clock input
SRDY2 output enabled
Transmit enabled
When using SRDY2 output, set this bit to “1”.
Receive disabled
Clock synchronous serial I/O
Serial I/O2 enabled
UART control register (address 001716)
UARTCON
0
Serial I/O2 clock: SCLK21
Fig. 2.3.36 Registers setting relevant to reception side
38B5 Group User’s Manual
2-61
APPLICATION
2.3 Serial I/O
Figure 2.3.37 shows a control procedure of the transmission side, and Figure 2.3.38 shows a control
procedure of the reception side.
RESET
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
.....
SIO2CON (address 001D16)
UARTCON (address 001716)
BRG (address 001616)
INTEDGE (address 003A16), bit0
• Serial I/O2 setting
1101X0002
X000XXXX2
8–1
0
.....
IREQ1 (address 003C16), bit0 ?
0
• Detection of INT0 falling edge
1
IREQ1 (address 003C16), bit0
0
• Transmission data write
Transmit buffer empty flag is set to “0” by this writing.
The first byte of a
transmission data
TB/RB (address 001F16)
SIO2STS (address 001E16), bit0 ?
0
• Judgment of transferring from Transmit buffer
register to Transmit shift register
(Transmit buffer empty flag)
1
• Transmission data write
Transmit buffer empty flag is set to “0” by this writing.
The second byte of
a transmission data
TB/RB (address 001F16)
SIO2STS (address 001E16), bit0 ?
0
• Judgment of transferring from Transmit buffer
register to Transmit shift register
(Transmit buffer empty flag)
1
SIO2STS (address 001E16), bit2 ?
0
• Judgment of shift completion of Transmit shift register
(Transmit shift register shift completion flag)
1
Fig. 2.3.37 Control procedure of transmission side
2-62
38B5 Group User’s Manual
APPLICATION
2.3 Serial I/O
RESET
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
.....
SIO2CON (address 001D16)
UARTCON (address 001716), bit6
1111X11X2
0
• Serial I/O2 setting
.....
0
2ms has passed ?
1
TB/RB (address 001F16)
• SRDY2 output
SRDY2 signal is output by writing data to
the TB/RB.
When using SRDY2, set Transmit enable
bit (bit4) of SIO2CON to “1.”
Dummy data
SIO2STS (address 001E16), bit1 ?
• An interval of 2 ms generated by Timer.
0
• Judgment of completion of receiving
(Receive buffer full flag)
1
• Reception of the first byte data.
Receive buffer full flag is set to “0” by reading
data.
Read out reception data from
TB/RB (address 001F16)
SIO2STS (address 001E16), bit1 ?
0
• Judgment of completion of receiving
(Receive buffer full flag)
1
Read out reception data from
TB/RB (address 001F16)
• Reception of the second byte data.
Receive buffer full flag is set to “0” by reading data.
Fig. 2.3.38 Control procedure of reception side
38B5 Group User’s Manual
2-63
APPLICATION
2.3 Serial I/O
(2)
Output of serial data (control of peripheral IC)
Outline : Serial communication is performed, connecting port P5 7 with the CS pin of a peripheral IC.
Figure 2.3.39 shows a connection diagram, and Figure 2.3.40 shows a timing chart.
CS
P57
CS
CLK
SCLK21
CLK
DATA
TxD
DATA
38B5 group
Peripheral IC
Fig. 2.3.39 Connection diagram
Specifications : • Use of serial I/O2 in clock synchronous serial I/O
• Synchronous clock frequency : 125 kHz (f(X IN) = 4 MHz is divided by 32)
• Transfer direction : LSB first
• Not use of receive/transmit interrupts of serial I/O2
• Port P57 is connected with the CS pin (“L” active) of the peripheral IC for transmission
control; the output level of port P5 7 is controlled by software.
CS
CLK
DATA
D O0
D O1
D O2
D O3
Fig. 2.3.40 Timing chart
2-64
38B5 Group User’s Manual
APPLICATION
2.3 Serial I/O
Figure 2.3.41 shows the relevant registers setting and Figure 2.3.42 shows the setting of transmission
data.
Serial I/O2 control register (address 001D16)
SIO2CON
1 1 0 1 1 0 0 0
BRG count source: f(XIN)
Synchronous clock: BRG/4
SRDY2 output not used
Transmit interrupt source: When transmit shift operation is completed
Transmit enabled
Receive disabled
Clock synchronous serial I/O
Serial I/O2 enabled
UART control register (address 001716)
UARTCON
0 0 0
P55/TxD pin: CMOS output
BRG clock: f(XIN)
Serial I/O2 clock: SCLK21
Baud rate generator (address 001616)
B RG
Set “division ratio – 1”
0716
Interrupt control register 2 (address 003F16)
ICON2 0
0
INT3/Serial I/O2 transmit interrupt: Disabled
Interrupt request register 2 (address 003D16)
IREQ2
0
INT3/serial I/O2 transmit interrupt request cleared
Confirm transmission completion of 1-byte unit.
Fig. 2.3.41 Relevant registers setting
Serial I/O2 transmit/receive buffer register (001F16)
Set a transmission data.
Confirm that transmission of the previous data is
completed, where bit 4, the INT3/serial I/O2
transmit interrupt request bit of the interrupt
request register 2, is “1”; before writing data.
TB/RB
Fig. 2.3.42 Setting of transmission data
38B5 Group User’s Manual
2-65
APPLICATION
2.3 Serial I/O
Figure 2.3.43 shows a control procedure.
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
.....
SIO2CON (address 001D16)
UARTCON (address 001716)
BRG (address 00161)
ICON2 (address 003F16), bit4
P5 (address 000A16), bit7
P5D (address 000B16), bit7
Serial I/O2 setting
110110002
X000XXXX2
8– 1
0
1
1
INT3/Serial I/O2 transmit interrupt: Disabled
CS signal output level to “H” setting
CS signal output port setting
.....
P5 (address 000A1 6), bit7
CS signal output level to “L” setting
0
IR EQ2 (address 003D16), bit4
0
INT3/Serial I/O2 transmit interrupt request bit to “0” setting
Transmission data write
(Start of 1-byte data transmission)
Transmission data
TB/RB (address 001F16)
IREQ2 (address 003D16), bit4 ?
0
Judgment of completion of transmitting 1-byte
data
1
N
All data has been transmitted ?
Use any of RAM area as a counter for counting
the number of transmitted bytes.
Judgment of completion of transmitting the target
number of bytes
Y
P5 (address000A16), bit7
1
Returning CS signal output level to “H” when
transmission of the target number of bytes is
completed
Fig. 2.3.43 Control procedure
2-66
38B5 Group User’s Manual
APPLICATION
2.3 Serial I/O
(3)
Cyclic transmission or reception of block data (data of specified number of bytes) between
two microcomputers
Outline : When the clock synchronous serial I/O is used for communication, synchronization of the
clock and the data between the transmitting and receiving sides may be lost because of
noise included in the synchronous clock. It is necessary to correct that constantly, using
“heading adjustment”.
This “heading adjustment” is carried out by using the interval between blocks in this
example.
Figure 2.3.44 shows a connection diagram.
SCLK21
SCLK21
RXD
TXD
TXD
RXD
38B5 group
Master unit
38B5 group
Slave unit
Fig. 2.3.44 Connection diagram
Specifications: •
•
•
•
•
•
•
•
•
Use of serial I/O2 in clock synchronous serial I/O
Synchronous clock frequency : 131 kHz (f(X IN) = 4.19 MHz is divided by 32.)
Byte cycle: 488 µs
Number of bytes for transmission or reception : 8 bytes/block each
Block transfer cycle : 16 ms
Block transfer term : 3.5 ms
Interval between blocks : 12.5 ms
Heading adjustment time : 8 ms
Transfer direction : LSB first
Limitations of the specifications:
• Reading of the reception data and setting of the next transmission data must be
completed within the time obtained from “byte cycle – time for transferring 1-byte
data” (in this example, the time taken from generating of the serial I/O2 receive
interrupt request to input of the next synchronous clock is 431 µs).
• “Heading adjustment time < interval between blocks” must be satisfied.
38B5 Group User’s Manual
2-67
APPLICATION
2.3 Serial I/O
The communication is performed according to the timing shown in Figure 2.3.45. In the slave unit,
when a synchronous clock is not input within a certain time (heading adjusment time), the next clock
input is processed as the beginning (heading) of a block.
When a clock is input again after one block (8 bytes) is received, the clock is ignored.
Figure 2.3.46 shows the relevant registers setting in the master unit and Figure 2.3.47 shows the
relevant registers setting in the slave unit.
D0
D1
D2
D7
D0
Byte cycle
Interval between blocks
Block transfer term
Block transfer cycle
Heading adjustment time
Processing for heading adjustment
Fig. 2.3.45 Timing chart
Master unit
Serial I/O2 control register (address 001D16)
SIO2CON
1 1 1 1 1 0 0 0
BRG count source : f(XIN)
Synchronous clock : BRG/4
SRDY2 output disabled
Transmit interrupt source : Transmit shift operating completion
Transmit enabled
Receive enabled
Clock synchronous serial I/O
Serial I/O2 enabled
UART control register (address 001716)
UARTCON
0 0 0
P55/TxD pin: CMOS output
BRG clock: f(XIN)
Serial I/O2 clock: SCLK21
Baud rate generator (address 001616)
B RG
0716
Set “division ratio – 1”
Fig. 2.3.46 Relevant registers setting in master unit
2-68
38B5 Group User’s Manual
APPLICATION
2.3 Serial I/O
Slave unit
Serial I/O2 control register (address 001D16)
SIO2CON
1 1 1 1
0 1
Synchronous clock : External clock
SRDY2 output disabled
Transmit enabled
Receive enabled
Clock synchronous serial I/O
Serial I/O2 enabled
UART control register (address 001716)
UARTCON
0
0
P55/TxD pin: CMOS output
Serial I/O2 clock: SCLK21
Fig. 2.3.47 Relevant registers setting in slave unit
38B5 Group User’s Manual
2-69
APPLICATION
2.3 Serial I/O
Control procedure by software:
● Control in the master unit
After setting the relevant registers shown in Figure 2.3.46, the master unit starts transmission or
reception of 1-byte data by writing transmission data to the serial I/O2 transmit buffer register.
To perform the communication in the timing shown in Figure 2.3.45, take the timing into account
and write transmission data. Additionally, read out the reception data when the serial I/O2 transmit
interrupt request bit is set to “1,” or before the next transmission data is written to the serial I/O2
transmit buffer register.
Figure 2.3.48 shows a control procedure of the master unit using timer interrupts.
Interrupt processing routine
executed every 500 µs
CLT (Note 1)
CLD (Note 2)
Push register to stack
●
Note 1: When using the Index X mode flag (T).
Note 2: When using the Decimal mode flag (D).
Pushing the register used in the interrupt
processing routine into the stack
●
Within a block transfer
period?
N
Generating a certain block interval by
using a timer or other functions
Y
●
Count a block interval counter
Read a reception data
Complete to transfer
a block?
Y
Start a block transfer?
Write the first transmission data
(first byte) in a block
Write a transmission data
●
Popping registers which is pushed to stack
RTI
Fig. 2.3.48 Control procedure of master unit
2-70
N
Y
N
Pop registers
Check of the block interval counter and
determination to start a block transfer
38B5 Group User’s Manual
APPLICATION
2.3 Serial I/O
● Control in the slave unit
After setting the relevant registers as shown in Figure 2.3.47, the slave unit becomes the state
where a synchronous clock can be received at any time, and the serial I/O2 receive interrupt
request bit is set to “1” each time an 8-bit synchronous clock is received.
In the serial I/O2 receive interrupt processing routine, the data to be transmitted next is written to
the transmit buffer register after the received data is read out.
However, if no serial I/O2 receive interrupt occurs for a certain time (heading adjustment time or
more), the following processing will be performed.
1. The first 1-byte data of the transmission data in the block is written into the transmit buffer register.
2. The data to be received next is processed as the first 1 byte of the received data in the block.
Figure 2.3.49 shows a control procedure of the slave unit using the serial I/O2 receive interrupt
and any timer interrupt (for heading adjustment).
Serial I/O2 receive interrupt
processing routine
Timer interrupt processing
routine
CLT (Note 1)
CLD (Note 2)
Push register to stack
●
●
Within a block transfer
term?
N
Pushing the register used in
the interrupt processing
routine into the stack
Confirmation of the received
byte counter to judge the
block transfer term
CLT (Note 1)
CLD (Note 2)
Push register to stack
●
Heading adjustment
counter – 1
Y
N
Heading adjustment
counter = 0?
Read a reception data
Pushing the register used
in the interrupt processing
routine into the stack.
Y
Write the first transmission
data (first byte) in a block
A received byte counter +1
A received byte
counter ≥ 8?
A received byte counter
N
0
Y
Pop registers
Write a transmission data
Write dummy data (FF 16)
●
Popping registers which is
pushed to stack
RTI
Initial
value
(Note 3)
Heading
adjustment
counter
Pop registers
RTI
●
Popping registers which is
pushed to stack
Notes 1: When using the Index X mode flag (T).
2: When using the Decimal mode flag (D).
3: In this example, set the value which is equal to the
heading adjustment time divided by the timer interrupt
cycle as the initial value of the heading adjustment
counter.
For example: When the heading adjustment time is 8 ms
and the timer interrupt cycle is 1 ms, set
8 as the initial value.
Fig. 2.3.49 Control procedure of slave unit
38B5 Group User’s Manual
2-71
APPLICATION
2.3 Serial I/O
(4)
Communication (transmission/reception) using asynchronous serial I/O (UART)
Outline : 2-byte data is transmitted and received, using the asynchronous serial I/O.
Port P56 is used for communication control.
Figure 2.3.50 shows a connection diagram, and Figure 2.3.51 shows a timing chart.
Transmission side
Reception side
P56
P56
TXD
RX D
38B5 group
38B5 group
Fig. 2.3.50 Connection diagram
Specifications : • Use of serial I/O2 in UART
• Transfer bit rate : 9600 bps (f(X IN) = 3.6864 MHz is divided by 384)
• Data format : 1ST-8DADA-2ST
• Communication control using port P5 6
(The output level of port P5 6 is controlled by softoware.)
• 2-byte data is transferred from the transmission side to the receiption side at
intervals of 10 ms generated by the timer.
P56
TXD
....
ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2) ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2)
10 ms
Fig. 2.3.51 Timing chart
2-72
38B5 Group User’s Manual
ST D0
....
APPLICATION
2.3 Serial I/O
Table 2.3.1 shows setting examples of the baud rate generator (BRG) values and transfer bit rate
values.
Table 2.3.1 Setting examples of baud rate generator values and transfer bit rate values
Transfer bit rate
(Note 1)
600
f(X IN) = 3.6864 MHz
BRG count BRG setting
source (Note 2)
value
f(XIN)/4
95(5F 16)
f(XIN ) = 4 MHz
Actual rate
600.00
BRG count
BRG setting
source (Note 2)
value
f(XIN)/4
103(67 16)
Actual rate
600.96
1200
f(XIN)/4
47(2F 16)
1200.00
f(XIN)/4
51(33 16)
1201.92
2400
f(XIN)/4
23(17 16)
2400.00
f(XIN)/4
25(19 16)
2403.85
4800
f(XIN)/4
11(0B 16)
4800.00
f(XIN)/4
12(0C16)
4807.69
9600
f(XIN)/4
5(05 16)
9600.00
f(XIN)
25(19 16)
9615.38
19200
f(XIN)/4
2(02 16)
19200.00
f(XIN)
12(0C16)
19230.77
38400
f(XIN)
5(05 16)
38400.00
f(XIN)
5(0516)
41666.67
76800
f(XIN)
2(02 16)
76800.00
f(XIN)
2(0216)
83333.33
31250
—
—
—
f(XIN)
7(0716)
31250.00
62500
—
—
—
f(XIN)
3(0316)
62500.00
Notes 1: Equation of transfer bit rate:
Transfer bit rate (bps) =
f(XIN)
(BRG setting value + 1) ✕ 16 ✕ m✽
✽m: When bit 0 of the serial I/O2 control register (address 001D 16 ) is set to “0”, a value of m
is 1.
When bit 0 of the serial I/O2 control register is set to “1”, a value of m is 4.
2: Select the BRG count source with bit 0 of the serial I/O2 control register (address 001D 16 ).
38B5 Group User’s Manual
2-73
APPLICATION
2.3 Serial I/O
Figure 2.3.52 shows the registers setting relevant to the transmission side; Figure 2.3.53 shows the
registers setting relevant to the reception side.
Transmission side
Serial I/O2 status register (address 001E 16)
b7
b0
SIO2STS
Transmit buffer empty flag
• Confirm that tha data has been transferred from Transmit buffer
register to Transmit shift register.
• When this flag is “1”, it is possible to write the next transmission
data in to Transmit buffer register.
Transmit shift register shift completion flag
Confirm completion of transmitting 1-byte data with this flag.
“1” : Transmit shift completed
Serial I/O2 control register (address 001D
b7
SIO2CON
16)
b0
1 0 0 1
0 0 1
BRG count source : f(XIN)/4
Serial I/O2 synchronous clock : BRG/16
SRDY2 output disabled
Transmit enabled
Receive disabled
Asynchronous serial I/O (UART)
Serial I/O2 enabled
UART control register (address 0017 16)
b7
UARTCON
b0
0 0 1
0 0
Character length : 8 bits
Parity checking disabled
Stop bit length : 2 stop bits
P55/TXD pin : CMOS output
BRG clock : f(X IN)
Baud rate generator (address 0016 16)
b7
BRG
b0
0516
Set
f(XIN)
Transfer bit rate ✕ 16 ✕ m ✽
–1
✽ When bit 0 of SIO2CON (address 001D 16) is set to “0”,
a value of m is 1.
When bit 0 of SIO2CON is set to “1”, a value of m is 4.
Fig. 2.3.52 Registers setting relevant to transmission side
2-74
38B5 Group User’s Manual
APPLICATION
2.3 Serial I/O
Reception side
Serial I/O2 status register (address 001E
b7
16)
b0
SIO2STS
Receive buffer full flag
Confirm completion of receiving 1-byte data with this flag.
“1” : at completing reception
“0” : at reading out contents of Receive buffer register
Overrun error flag
“1” : When data is ready in Receive shift register while Receive buffer
register contains the data.
Parity error flag
“1” : When a parity error occurs in enabled parity.
Framing error flag
“1” : When stop bits cannot be detected at the specified timing
Summing error flag
“1” : when any one of the following errors occurs.
• Overrun error
• Parity error
• Framing error
Serial I/O2 control register (address 001D
b7
SIO2CON
16)
b0
1 0 1 0
0 0 1
BRG count source : f(X IN)/4
Serial I/O synchronous clock : BRG/16
SRDY output disabled
Transmit disabled
Receive enabled
Asynchronous serial I/O (UART)
Serial I/O2 enabled
UART control register (address 0017 16)
b7
UARTCON
b0
0
1
0 0
Character length : 8 bits
Parity checking disabled
Stop bit length : 2 stop bits
BRG clock: f(X IN)
Baud rate generator (address 0016 16)
b7
BRG
b0
0516
Set
f(XIN)
Transfer bit rate ✕ 16 ✕ m ✽
–1
✽ When bit 0 of SIO2CON (address 001D 16) is set to “0”,
a value of m is 1.
When bit 0 of SIO2CON is set to “1”, a value of m is 4.
Fig. 2.3.53 Registers setting relevant to reception side
38B5 Group User’s Manual
2-75
APPLICATION
2.3 Serial I/O
Figure 2.3.54 shows a control procedure of the transmission side, and Figure 2.3.55 shows a control
procedure of the reception side.
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
.....
• Serial I/O2 setting
1001X001 2
SIO2CON (address 001D 16)
XX001X00 2
UARTCON (address 0017 16)
6–1
(address 0016 16)
BRG
0
(address 000A 16), bit6
P5
(address 000B 16), bit6
P5D
1
• Port P5 6 set for communication control
.....
N
10 ms has passed ?
• An interval of 10 ms generated by Timer
Y
P5 (address 000A 16), bit6
TB/RB (address 001F 16)
1
• Communication start
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
The first byte of a
transmission data
0
SIO2STS (address 001E 16), bit0?
• Judgment of transferring data from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
1
The second byte of
TB/RB (address 001F 16) a transmission data
SIO2STS (address 001E 16), bit0?
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
0
• Judgment of transferring data from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
0
• Judgment of shift completion of Transmit shift register
(Transmit shift register shift completion flag)
1
SIO2STS (address 001E 16), bit2?
1
P5 (address 000A 16), bit6
0
• Communication completion
Fig. 2.3.54 Control procedure of transmission side
2-76
38B5 Group User’s Manual
APPLICATION
2.3 Serial I/O
RESET
● X: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
.....
SIO2CON
UARTCON
BRG
P5D
(address 001D 16) 1010X001 2
XX0X1X00 2
(address 0017 16)
6–1
(address 0016 16)
0
(address 000B 16), bit6
0
SIO2STS (address 001E 16), bit1?
• Serial I/O2 setting
• Port P5 6 setting for communication control
• Judgment of completion of receiving
(Receive buffer full flag)
1
• Reception of the first byte data
Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from TB/RB (address 001F 16)
SIO2STS (address 001E 16), bit6?
1
• Judgment of an error flag
0
• Judgment of completion of
receiving
(Receive buffer full flag)
0
SIO2STS (address 001E 16), bit1?
1
• Reception of the second byte data
Receive buffer full flag is set
to “0” by reading data.
Read out a reception data
from TB/RB (address 001F 16)
SIO2STS (address 001E 16), bit0?
1
• Judgment of an error flag
Processing for error
0
1
P5 (address 000A 16), bit0?
0
SIO2CON (address 001D 16)
SIO2CON (address 001D 16)
0000X001 2
1010X001 2
• Countermeasure for a bit slippage
Fig. 2.3.55 Control procedure of reception side
38B5 Group User’s Manual
2-77
APPLICATION
2.3 Serial I/O
2.3.9 Notes on serial I/O1
(1) Clock
■ Using internal clock
After setting the synchronous clock to an internal clock, clear the serial I/O interrupt request bit
before perform the normal serial I/O transfer or the serial I/O automatic transfer.
■ Using external clock
After inputting “H” level to the external clock input pin, clear the serial I/O interrupt request bit
before performing the normal serial I/O transfer or the serial I/O automatic transfer.
(2) Using serial I/O1 interrupt
Clear bit 3 of the interrupt request register 1 to “0” by software.
(3)
State of SOUT1 pin
The SOUT1 pin control bit of the serial I/O1 control register 2 can be used to select the state of the
S OUT1 pin when serial data is not transferred; either output active or high-impedance. However, when
selecting an external synchronous clock; the SOUT1 pin can become the high-impedance state by
setting the SOUT1 pin control bit to “1” when the serial I/O1 clock input is at “H” after transfer completion.
(4)
Serial I/O initialization bit
● Set “0” to the serial I/O initialization bit of the serial I/O1 control register 1 when terminating a
serial transfer during transferring.
● When writing “1” to the serial I/O initialization bit, the serial I/O1 is enabled, but each register is
not initialized. Set the value of each register by program.
(5)
Handshake signal
■ S BUSY1 input signal
Input an “H” level to the SBUSY1 input and an “L” level signal to the S BUSY1 input in the initial state.
When the external synchronous clock is selected, switch the input level to the SBUSY1 input and
the SBUSY1 input while the serial I/O1 clock input is in “H” state.
■ S RDY1 input•output signal
When selecting the internal synchronous clock, input an “L” level to the SRDY1 input and an “H”
level signal to the SRDY1 input in the initial state.
(6)
8-bit serial I/O mode
■ When selecting external synchronous clock
When an external synchronous clock is selected, the contents of the serial I/O1 register are being
shifted continually while the transfer clock is input to the serial I/O1 clock pin. In this case, control
the clock externally.
(7)
In automatic transfer serial I/O mode
■ Set of automatic transfer interval
● When the SBUSY1 output is used, and the S BUSY1 output and the SSTB1 output function as signals
for each transfer data set by the SBUSY1 output•SSTB1 output function selection bit of serial I/O1
control register 2; the transfer interval is inserted before the first data is transmitted/received,
and after the last data is transmitted/received. Accordingly, regardless of the contents of the
SBUSY1 output•SSTB1 output function selection bit, this transfer interval for each 1-byte data becomes
2 cycles longer than the value set by the automatic transfer interval set bits of serial I/O1 control
register 3.
2-78
38B5 Group User’s Manual
APPLICATION
2.3 Serial I/O
● When using the SSTB1 output, regardless of the contents of the S BUSY1 output•S STB1 output function
selection bit, this transfer interval for each 1-byte data becomes 2 cycles longer than the value
set by the automatic transfer interval set bits of serial I/O1 control register 3.
● When using the combined output of S BUSY1 and SSTB1 as the signal for each of all transfer data
set, the transfer interval after completion of transmission/reception of the last data becomes 2
cycles longer than the value set by the automatic transfer interval set bits.
● Set the transfer interval of each 1-byte data transfer to 5 or more cycles of the internal clock
φ after the rising edge of the last bit of a 1-byte data.
● When selecting an external clock, the set of automatic transfer interval becomes invalid.
■ Set of serial I/O1 transfer counter
● Write the value decreased by 1 from the number of transfer data bytes to the serial I/O1 transfer
counter.
● When selecting an external clock, after writing a value to the serial I/O1 register/transfer counter,
wait for 5 or more cycles of internal clock φ before inputting the transfer clock to the serial I/
O1 clock pin.
■ Serial I/O initialization bit
A serial I/O1 automatic transfer interrupt request occurs when “0” is written to the serial I/O
initialization bit during an operation. Disable it with the interrupt enable bit as necessary by program.
38B5 Group User’s Manual
2-79
APPLICATION
2.3 Serial I/O
2.3.10 Notes on serial I/O2
(1)
Notes when selecting clock synchronous serial I/O
➀ Stop of transmission operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O2 enable bit is cleared to “0” (serial I/O2 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, S CLK21, S CLK22 and S RDY2 function as I/O ports, the transmission
data is not output). When data is written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O2 enable bit is set to “1” at this time,
the data during internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the receive enable bit to “0” (receive disabled), or clear the serial I/O2 enable bit
to “0” (serial I/O2 disabled).
➂ Stop of transmit/receive operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, simultaneously clear both the transmit enable bit and receive enable bit to “0” (transmit
and receive disabled).
(when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
● Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.
If any one of transmission and reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,
the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clearing the serial I/O2 enable bit to
“0” (serial I/O2 disabled) (refer to (1), ➀).
2-80
38B5 Group User’s Manual
APPLICATION
2.3 Serial I/O
(2)
Notes when selecting clock asynchronous serial I/O
➀ Stop of transmission operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O2 enable bit is cleared to “0” (serial I/O2 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, S CLK21, S CLK22 and S RDY2 function as I/O ports, the transmission
data is not output). When data is written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O2 enable bit is set to “1” at this time,
the data during internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the receive enable bit to “0” (receive disabled).
➂ Stop of transmit/receive operation
Only transmission operation is stopped.
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O2 enable bit is cleared to “0” (serial I/O2 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, S CLK21, S CLK22 and S RDY2 function as I/O ports, the transmission
data is not output). When data is written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O2 enable bit is set to “1” at this time,
the data during internally shifting is output to the TxD pin and an operation failure occurs.
Only receive operation is stopped.
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the receive enable bit to “0” (receive disabled).
(3)
S RDY2 output of reception side
When signals are output from the SRDY2 pin on the reception side by using an external clock in the
clock synchronous serial I/O mode, set all of the receive enable bit, the SRDY2 output enable bit, and
the transmit enable bit to “1” (transmit enabled).
(4)
Setting serial I/O2 control register again
Set the serial I/O2 control register again after the transmission and the reception circuits are reset
by clearing both the transmit enable bit and the receive enable bit to “0.”
Clear both the transmit enable
bit (TE) and the receive enable
bit (RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O2 control register
↓
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to “1”
Can be set with the
LDM instruction at
the same time
Fig. 2.3.56 Sequence of setting serial I/O2 control register again
38B5 Group User’s Manual
2-81
APPLICATION
2.3 Serial I/O
(5)
Data transmission control with referring to transmit shift register completion flag
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks. When data transmission is controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(6)
Transmission control when external clock is selected
When an external clock is used as the synchronous clock for data transmission, set the transmit
enable bit to “1” at “H” of the serial I/O2 clock input level. Also, write the transmit data to the transmit
buffer register (serial I/O shift register) at “H” of the serial I/O2 clock input level.
(7)
Transmit interrupt request when transmit enable bit is set
The transmission interrupt request bit is set and the interruption request is generated even when
selecting timing that either of the following flags is set to “1” as timing where the transmission
interruption is generated.
• Transmit buffer empty flag is set to “1”
• Transmit shift register completion flag is set to “1”
Therefore, when the transmit interrupt is used, set the transmit interrupt enable bit to transmit
enabled as the following sequence.
➀ Transmit enable bit is set to “1”
➁ Transmit interrupt request bit is set to “0”
● Reason
When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift
register completion flag are set to “1”.
(8)
2-82
Using TxD pin
The P55/TxD P-channel output disable bit of UART control register is valid in both cases: using as
a normal I/O port and as the TxD pin. Do not supply Vcc + 0.3 V or more even when using the P55/
TxD pin as an N-channel open-drain output.
Additionally, in the serial I/O2, the TxD pin latches the last bit and continues to output it after
completing transmission.
38B5 Group User’s Manual
APPLICATION
2.4 FLD controller
2.4 FLD controller
This paragraph describes the setting method of FLD controller relevant registers, notes etc.
2.4.1 Memory assignment
Address
003D16
Interrupt request register 2 (IREQ2)
003F16
Interrupt control register 2 (ICON2)
0EF216
P1FLDRAM write disable register (P1FLDRAM)
0EF316
P3FLDRAM write disable register (P3FLDRAM)
0EF416
FLDC mode register (FLDM)
0EF516
0EF616
Tdisp time set register (TDISP)
Toff1 time set register (TOFF1)
0EF716
Toff2 time set register (TOFF2)
0EF816
FLD data pointer (FLDDP)
0EF916
Port P0FLD/port switch register (P0FPR)
0EFA16
Port P2FLD/port switch register (P2FPR)
0EFB16
Port P8FLD/port switch register (P8FPR)
0EFC16
Port P8FLD output control register (P8FLDCON)
Fig. 2.4.1 Memory assignment of FLD controller relevant registers
38B5 Group User’s Manual
2-83
APPLICATION
2.4 FLD controller
2.4.2 Relevant registers
P1FLDRAM write disable register
b7 b6 b5 b4 b3 b2 b1 b0
P1FLDRAM write disable register
(P1FLDRAM: address 0EF216)
b
Name
Functions
0
1 FLDRAM corre0: Operating normally
sponding to port
1: Write disabled
P11 write disable bit
0
2 FLDRAM corre0: Operating normally
sponding to port
1: Write disabled
P12 write disable bit
0
3 FLDRAM corre0: Operating normally
sponding to port
1: Write disabled
P13 write disable bit
0
4 FLDRAM corresponding to port
P14 write disable bit
5 FLDRAM corresponding to port
P15 write disable bit
6 FLDRAM corresponding to port
P16 write disable bit
7 FLDRAM corresponding to port
P17 write disable bit
0: Operating normally
1: Write disabled
0
0: Operating normally
1: Write disabled
0
0: Operating normally
1: Write disabled
0
0: Operating normally
1: Write disabled
0
Fig. 2.4.2 Structure of P1FLDRAM write disable register
2-84
At reset R W
0 FLDRAM corre0: Operating normally
sponding to port
1: Write disabled
P10 write disable bit
38B5 Group User’s Manual
APPLICATION
2.4 FLD controller
P3FLDRAM write disable register
b7 b6 b5 b4 b3 b2 b1 b0
P3FLDRAM write disable register
(P3FLDRAM: address 0EF316)
b
Name
Functions
At reset R W
0 FLDRAM corre0: Operating normally
sponding to port
1: Write disabled
P30 write disable bit
0
1 FLDRAM corre0: Operating normally
sponding to port
1: Write disabled
P31 write disable bit
0
2 FLDRAM corre0: Operating normally
sponding to port
1: Write disabled
P32 write disable bit
0
3 FLDRAM corre0: Operating normally
sponding to port
1: Write disabled
P33 write disable bit
0
4 FLDRAM corresponding to port
P34 write disable bit
5 FLDRAM corresponding to port
P35 write disable bit
6 FLDRAM corresponding to port
P36 write disable bit
7 FLDRAM corresponding to port
P37 write disable bit
0: Operating normally
1: Write disabled
0
0: Operating normally
1: Write disabled
0
0: Operating normally
1: Write disabled
0
0: Operating normally
1: Write disabled
0
Fig. 2.4.3 Structure of P3FLDRAM write disable register
38B5 Group User’s Manual
2-85
APPLICATION
2.4 FLD controller
FLDC mode register
b7 b6 b5 b4 b3 b2 b1 b0
FLDC mode register
(FLDM: address 0EF416)
b
Name
Functions
At reset R W
0 Automatic display
control bit (P0, P1,
P2, P3, P8)
0 : General-purpose mode
1 : Automatic display
mode
0
1 Display start bit
0 : Display stopped
1 : Display in progress (display
starts by writing “1”)
0
2 Tscan control bits
b3 b2
0
3
0 0 : 0 FLD digit interrupt
(at rising edge of each
digit)
0 1 : 1 ✕ Tdisp
1 0 : 2 ✕ Tdisp
1 1 : 3 ✕ Tdisp
FLD blanking interrupt (at
falling edge of last digit)
0
4 Timing number
control bit
0 : 16 timing mode
1 : 32 timing mode (Note 2)
0
5 Gradation display
mode selection
control bit
6 Tdisp counter count
source selection bit
0 : Not selected
1 : Selected (Notes 1, 2)
0
0 : f(XIN)/16 or f(XCIN)/32
1 : f(XIN)/64 or f(XCIN)/128
0
0 : Drivability strong
1 : Drivability weak
0
7 High-breakdown
voltage port drivability selection bit
Notes 1: When the gradation display mode is selected, the number of
timing is max. 16 timing. (Set “0” to the timing number control
bit (b4).)
2: When switching the timing number control bit (b4) or the
gradation display mode selection control bit (b5), set “0” to
the display start bit (b1) (display stop state) before that.
Fig. 2.4.4 Structure of FLD mode register
2-86
38B5 Group User’s Manual
APPLICATION
2.4 FLD controller
Tdisp time set register
b7 b6 b5 b4 b3 b2 b1 b0
Tdisp time set register
(TDISP: address 0EF516)
b
Functions
0
•Set the Tdisp time.
•When a value n is written to this register, Tdisp
time is expressed as Tdisp = (n + 1) ✕ count
source.
•When reading this register, the value in the
counter is read out.
0
(Example)
When the following condition is satisfied, Tdisp
becomes 804 µs {(200 + 1) ✕ 4 µs};
•f(XIN) = 4 MHz
•bit 6 of FLDC mode register = 0
(f(XIN)/16 is selected as Tdisp counter count
source. )
•Tdisp time set register = 200 (C816).
0
1
2
3
4
At reset R W
0
0
0
5
0
6
0
7
0
Fig. 2.4.5 Structure of Tdisp time set register
38B5 Group User’s Manual
2-87
APPLICATION
2.4 FLD controller
Toff1 time set register
b7 b6 b5 b4 b3 b2 b1 b0
Toff1 time set register
(TOFF1: address 0EF616)
b
0
1
2
3
4
5
Functions
•Set the Toff1 time.
•When a value n1 is written to this register,
Toff1 time is expressed as Toff1 = n1 ✕ count
source.
(Example)
When the following condition is satisfied, Toff1
becomes 120 µs (= 30 ✕ 4 µs);
•f(XIN) = 4 MHz
•bit 6 of FLDC mode register = 0
(f(XIN)/16 is selected as Tdisp counter count
source.)
•Toff1 time set register = 30 (1E16).
At reset R W
1
1
1
1
1
1
6
1
7
1
Note: Set value of 0316 or more.
Fig. 2.4.6 Structure of Toff1 time set register
Toff2 time set register
b7 b6 b5 b4 b3 b2 b1 b0
Toff2 time set register
(TOFF2: address 0EF716)
b
Functions
0
•Set the Toff2 time.
•When a value n2 is written to this register,
Toff2 time is expressed as Toff2 = n2 ✕ count
source.
However, setting of Toff2 time is valid only for
the FLD port which is satisfied the following;
•gradation display mode
•value of FLD automatic display RAM (in
gradation display mode) = “1” (dark display).
1
(Example)
When the following condition is satisfied, Toff2
becomes 720 µs (= 180 ✕ 4 µs);
•f(XIN) = 4 MHz
•bit 6 of FLDC mode register = 0
(f(XIN)/16 is selected as Tdisp counter count
source.)
•Toff2 time set register = 180 (B416).
1
1
2
3
4
5
6
7
At reset R W
1
1
1
1
1
1
Note: When the Toff2 control bit (b7) of the port P8FLD output control
register (address 0EFC16) is set to “1”, set value of 0316 or
more to the Toff2 control register.
Fig. 2.4.7 Structure of Toff2 time set register
2-88
38B5 Group User’s Manual
APPLICATION
2.4 FLD controller
FLD data pointer/FLD data pointer reload register
b7 b6 b5 b4 b3 b2 b1 b0
FLD data pointer/FLD data pointer reload register
(FLDDP: address 0EF816)
b
Functions
0
The start address of each data of FLD ports P0,
P1, P2, P3, and P8, which is transferred from
FLD automatic display RAM, is set to this
register.
The start address becomes the address adding
the value set to this register into the last data
address of each FLD port.
Set a value of (timing number – 1) to this
register.
1
2
3
4
5
6
7
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
The value which is set to this address is written
to the FLD data pointer reload register.
Undefined
When reading data from this address, the value
in the FLD data pointer is read.
Undefined
When bits 5 to 7 of this register is read, “0” is
always read.
Undefined
Fig. 2.4.8 Structure of FLD data pointer/FLD data pointer reload register
Port P0FLD/port switch register
b7 b6 b5 b4 b3 b2 b1 b0
Port P0FLD/port switch register
(P0FPR: address 0EF916)
b
0
1
2
3
4
5
6
7
Name
Port P00FLD/port
switch bit
Port P01FLD/port
switch bit
Port P02FLD/port
switch bit
Port P03FLD/port
switch bit
Port P04FLD/port
switch bit
Port P05FLD/port
switch bit
Port P06FLD/port
switch bit
Port P07FLD/port
switch bit
Functions
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.4.9 Structure of port P0FLD/port switch register
38B5 Group User’s Manual
2-89
APPLICATION
2.4 FLD controller
Port P2FLD/port switch register
b7 b6 b5 b4 b3 b2 b1 b0
Port P2FLD/port switch register
(P2FPR: address 0EFA16)
b
Name
0 Port P20FLD/port
switch bit
1 Port P21FLD/port
switch bit
2 Port P22FLD/port
switch bit
3 Port P23FLD/port
switch bit
4 Port P24FLD/port
switch bit
5 Port P25FLD/port
switch bit
6 Port P26FLD/port
switch bit
7 Port P27FLD/port
switch bit
Functions
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.4.10 Structure of port P2FLD/port switch register
Port P8FLD/port switch register
b7 b6 b5 b4 b3 b2 b1 b0
Port P8FLD/port switch register
(P8FPR: address 0EFB16)
b
Name
0 Port P80FLD/port
switch bit
Port
P81FLD/port
1
switch bit
2 Port P82FLD/port
switch bit
3 Port P83FLD/port
switch bit
4 Port P84FLD/port
switch bit
5 Port P85FLD/port
switch bit
6 Port P86FLD/port
switch bit
7 Port P87FLD/port
switch bit
Functions
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
Fig. 2.4.11 Structure of port P8FLD/port switch register
2-90
38B5 Group User’s Manual
At reset R W
0
0
0
0
0
0
0
0
APPLICATION
2.4 FLD controller
Port P8FLD output control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P8FLD output control register
(P8FLDCON : address 0EFC16)
b
0
1
2
3
4
5
6
7
Name
Functions
P84–P87 FLD
0 : Output normally
1 : Reverse output
output reverse bit
P84–P87/FLDRAM 0 : Operating normally
1 : Write disabled
write disable bit
0 : Operating normally
P84–P87 Toff
1 : Toff invalid
invalid bit
P84–P87 delay
0 : No delay
control bit (Note)
1 : Delay
P63/AN9 dimmer
0 : Ordinary port
output control bit
1 : Dimmer output
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
0 : Operating normally
Toff2 control bit
(falling operation)
1 : Rising operation
At reset R W
0
0
0
0
0
0
0
0
Note: Valid only when selecting FLD port and P84–P87 Toff invalid function
Fig. 2.4.12 Structure of port P8FLD output control register
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16)
b
0
1
2
3
4
5
6
7
Name
Functions
Timer 4 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
request bit (Note)
0 : No interrupt request issued
Timer 5 interrupt
1 : Interrupt request issued
request bit
0 : No interrupt request issued
Timer 6 interrupt
1 : Interrupt request issued
request bit
Serial I/O2 receive 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
0 : No interrupt request issued
INT3/serial I/O2
1 : Interrupt request issued
transmit interrupt
request bit (Note)
0 : No interrupt request issued
INT4 interrupt
1 : Interrupt request issued
request bit
A-D converter
interrupt request bit
0 : No interrupt request issued
FLD blanking
interrupt request bit 1 : Interrupt request issued
FLD digit interrupt
request bit
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
At reset R W
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽: “0” can be set by software, but “1” cannot be set.
Note: In the mask option type P, if timer 4 interrupt whose count source is
CNTR1 input and INT3 interrupt are selected, these bits do not
become “1”.
Fig. 2.4.13 Structure of interrupt request register 2
38B5 Group User’s Manual
2-91
APPLICATION
2.4 FLD controller
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2
(ICON2 : address 3F16)
b
Name
0 Timer 4 interrupt
enable bit (Note)
1 Timer 5 interrupt
enable bit
2 Timer 6 interrupt
enable bit
3 Serial I/O2 receive
interrupt enable bit
4 INT3/serial I/O2
transmit interrupt
enable bit (Note)
5 INT4 interrupt
enable bit
A-D converter
interrupt enable bit
6 FLD blanking
interrupt enable bit
FLD digit interrupt
enable bit
7 Fix “0” to this bit.
Functions
At reset R W
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0
0 : interrupt disabled
1 : Interrupt enabled
0
0 : interrupt disabled
1 : Interrupt enabled
0
0
0
0
0
0
Note: In the mask option type P, timer 4 interrupt whose count source
is CNTR1 input and INT3 interrupt are not available.
Fig. 2.4.14 Structure of interrupt control register 2
2-92
38B5 Group User’s Manual
APPLICATION
2.4 FLD controller
2.4.3 FLD controller application examples
(1) Key-scan using FLD automatic display and segments
Outline: Key read-in with segment pins is performed by software using the FLD automatic display
mode.
SUN MON TUE WED THU FRI SAT
P10–P17 Digit
P30, P31
P00, P01
P20–P27
Segment
SP EP
RE C
■
Segment
LEVEL
P04–P07
●
●
●
●
AM
PM
CH
L
R
Panel with fluorescent display (FLD)
38B5 Group
Key-matrix
Fig. 2.4.15 Connection diagram
Specifications: •Use of total 20 FLD ports (10 digits; 10 segments (8 key-scan included))
•Use of FLD automatic display mode
•Display in gradation display mode and 16 timing mode
•Toff1 = 40 µs, Toff2 = 64 µs, Tdisp = 204 µs, Tscan = 3 ✕ Tdisp = 720 µs,
f(X IN) = 4 MHz
•Use of FLD blanking interrupt
Figure 2.4.16 shows the timing chart of key-scan, and Figure 2.4.17 shows the enlarged view of
Tscan. After switching the segment pin to an output port, generate the waveform shown Figure 2.4.17
by software and perform key-scan.
Tdisp
Tscan
FLD16 (P10)
Toff1
Toff2
FLD17 (P11)
FLD18 (P12)
•••
•••
FLD25 (P31)
FLD blanking interrupt request occur
FLD0–FLD9
(P20–P27,
P00, P01)
•••
Key-scan
Fig. 2.4.16 Timing chart of key-scan using FLD automatic display mode and segments
FLD0 (P20)
FLD1 (P21)
FLD2 (P22)
•••
•••
FLD7 (P27)
Fig. 2.4.17 Enlarged view of FLD 0 (P2 0) to FLD7 (P27) Tscan
38B5 Group User’s Manual
2-93
APPLICATION
2.4 FLD controller
Figure 2.4.18 shows the setting of relevant registers.
Port P0 direction register (address 000116)
P0D
0 0 0 0
Set P04 to P07 to input ports for key-scan input
Port P2 direction register (address 000516)
P2D
1 1 1 1 1 1 1 1
Set P20 to P27 to output ports for key-scan output
Port P0FLD/port switch register (address 0EF916)
P0FPR
0 0 0 0 0 0 1 1
Set P00, P01 to FLD ports (FLD8, FLD9)
Set P02–P07 to general-purpose I/O ports
Port P2FLD/port switch register (address 0EFA16)
P2FPR
1 1 1 1 1 1 1 1
Set P20–P27 to FLD ports (FLD0–FLD7)
FLDC mode register (address 0EF416)
FLDM
1 0 1 0 1 1 0 1
Automatic display mode
Display stopped
Tscan = 3 ✕ Tdisp FLD blanking interrupt
16 timing mode
Gradation display mode selected
Tdisp counter count source : f(XIN)/16
High-breakdown voltage port drivability weak
Fig. 2.4.18 Setting of relevant registers
2-94
38B5 Group User’s Manual
APPLICATION
2.4 FLD controller
Tdisp time set register (address 0EF516)
TDISP
50 (3216) set; (50 + 1) ✕ count source = 204 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
3216
Toff1 time set register (address 0EF616)
TOFF1
10 (A16) set; 10 ✕ count source = 40 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
A16
Toff2 time set register (address 0EF716)
TOFF2
16 (1016) set; 16 ✕ count source = 64 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
1016
Note: Perform this setting when the gradation display mode is selected.
FLD data pointer (address 0EF816)
FLDDP
0 0 0 0 1 0 0 1
Set {(digit number) – 1} = 9
P1FLDRAM write disable register (address 0EF216)
P1FLDRAM
1 1 1 1 1 1 1 1
Disable writing to FLDRAM corresponding to P10 to P17
P3FLDRAM write disable register (address 0EF316)
P3FLDRAM
1 1
Disable writing to FLDRAM corresponding to P30, P31
Interrupt request register 2 (address 003D16)
IREQ2
0
Clear FLD blanking interrupt request bit
Interrupt control register 2 (address 003F16)
ICON2
0 1
FLD blanking interrupt: Enabled
FLDC mode register (address 0EF416)
FLDM
1 0 1 0 1 1 1 1
Display start
38B5 Group User’s Manual
2-95
APPLICATION
2.4 FLD controller
Setting of FLD automatic display RAM:
Table 2.4.1 FLD automatic display RAM map
1 to 16 timing display data stored area
Address
0FB016
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
Bit 7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
Bit 6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
Bit 5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
Bit 4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
Bit 3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
Bit 2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
Gradation display control data stored area
Bit 1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
Bit 0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
Address
0F6016
0F6116
0F6216
0F6316
0F6416
0F6516
0F6616
0F6716
0F6816
0F6916
0F6A16
0F6B16
0F6C16
0F6D16
0F6E16
0F6F16
0F7016
0F7116
0F7216
0F7316
0F7416
0F7516
0F7616
0F7716
0F7816
0F7916
0F7A16
0F7B16
0F7C16
0F7D16
0F7E16
0F7F16
0F8016
0F8116
0F8216
0F8316
0F8416
0F8516
0F8616
0F8716
0F8816
0F8916
0F8A16
0F8B16
0F8C16
0F8D16
0F8E16
0F8F16
0F9016
0F9116
0F9216
0F9316
0F9416
0F9516
0F9616
0F9716
0F9816
0F9916
Bit 7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
Bit 6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
Bit 4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
Bit 3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
Bit 2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
: Area which is used to set digit data
: Area which is available as ordinary RAM
38B5 Group User’s Manual
Corresponding
digit pin
Bit 1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
Bit 0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
→ FLD25 (P31)
→ FLD24 (P30)
→ FLD23 (P17)
→ FLD22 (P16)
→ FLD21 (P15)
→ FLD20 (P14)
→ FLD19 (P13)
→ FLD18 (P12)
→ FLD17 (P11)
→ FLD16 (P10)
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
→ FLD25 (P31)
→ FLD24 (P30)
→ FLD23 (P17)
→ FLD22 (P16)
→ FLD21 (P15)
→ FLD20 (P14)
→ FLD19 (P13)
→ FLD18 (P12)
→ FLD17 (P11)
→ FLD16 (P10)
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
: Area which is used to set segment data
2-96
Bit 5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
APPLICATION
2.4 FLD controller
FLD18
FLD19
FLD20
FLD21
SUN MON
SP EP
RE C
■
LEVEL
FLD22 FLD23
FLD24
FLD25
a
TUE WED THU FRI SAT
•
•
•
•
AM
PM
f g b
e
CH
FLD17
L
R
c
d
FLD16
Fig. 2.4.19 FLD digit allocation example
Table 2.4.2 FLD automatic display RAM map example
Gradation display control data stored area
1 to 16 timing display data stored area
Address
0FB016
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
g
f
e
d
c
b
a
CH
g
f
e
d
c
b
a
SAT
g
FRI
f
e
d
c
b
a
WED g
f
e
d
c
b
a
MON g
f
e
d
c
b
a
SUN g
f
e
d
c
b
a
g
–
f
e
d
c
b
a
■
REC SP
EP
PM
AM
THU
TUE
•
•
•
•
L
R
LEVEL
Address
0F6016
0F6116
0F6216
0F6316
0F6416
0F6516
0F6616
0F6716
0F6816
0F6916
0F6A16
0F6B16
0F6C16
0F6D16
0F6E16
0F6F16
0F7016
0F7116
0F7216
0F7316
0F7416
0F7516
0F7616
0F7716
0F7816
0F7916
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
g
f
e
d
c
b
a
CH
g
f
e
d
c
b
a
SAT
g
FRI
f
e
d
c
b
a
WED g
f
e
d
c
b
a
MON g
f
e
d
c
b
a
SUN g
f
e
d
c
b
a
g
–
f
e
d
c
b
a
■
REC SP
EP
PM
AM
THU
TUE
•
•
•
•
L
R
LEVEL
Corresponding
digit pin
→ FLD25 (P31)
→ FLD24 (P30)
→ FLD23 (P17)
→ FLD22 (P16)
→ FLD21 (P15)
→ FLD20 (P14)
→ FLD19 (P13)
→ FLD18 (P12)
→ FLD17 (P11)
→ FLD16 (P10)
→ FLD25 (P31)
→ FLD24 (P30)
→ FLD23 (P17)
→ FLD22 (P16)
→ FLD21 (P15)
→ FLD20 (P14)
→ FLD19 (P13)
→ FLD18 (P12)
→ FLD17 (P11)
→ FLD16 (P10)
: Unused
38B5 Group User’s Manual
2-97
APPLICATION
2.4 FLD controller
Control procedure:
RESET
Initialization
••••
P0D (address 000116), bit 4–bit 7
P2D (address 000516)
P0FPR (address 0EF916)
P2FPR (address 0EFA16)
FLDM (address 0EF416)
TDISP (address 0EF516)
TOFF1 (address 0EF616)
TOFF2 (address 0EF716)
FLDDP (address 0EF816)
00002
111111112
000000112
111111112
101011012
3216
A16
1016 (Note 1)
000010012
Port direction registers setting
FLD port setting
FLD automatic display function setting
••••
FLD automatic display RAM
(addresses 0FB016–0FE916)
Gradation display control
RAM
(addresses 0F6016–0F9916)
P1FLDRAM (address 0EF216)
P3FLDRAM (address 0EF316)
Data to be
display
Gradation display
control data (Note 1)
111111112
000000112
(Note 3)
IREQ2 (address 003D16), bit 6
0
Gradation display control data setting
Set “1” for dark display
Set “0” for bright display (Note 2)
Writing data to digit pin disabled
FLD blanking interrupt request bit cleared
Wait until writing to FLD blanking interrupt request
bit is completed
1 cycle or more wait
ICON2 (address 003F16), bit 6
FLDM (address 0EF4 16), bit 1
Digit data and segment data setting
1
1
FLD blanking interrupt enabled
FLD automatic display start
Main processing
Notes 1: When selecting the gradation display, set these
registers, too.
2: The display data can be rewritten at arbitrary
timing.
3: Set these registers according to necessity.
Fig. 2.4.20 Control procedure
2-98
38B5 Group User’s Manual
APPLICATION
2.4 FLD controller
FLD blanking interrupt routine
Segment key-scan
Push registers to stack, etc.
••••
•
FLDM (address 0EF416), bit 0
P1 (address 000216)
P3 (address 000616), bit 0, bit 1
P2FPR (address 0EFA16)
P2 (address 000416)
0
0016
002
000000002
0016
Switching from automatic display mode to general-purpose mode
Setting of “L” level to port corresponding to digit
Setting of port to be used for key-scan to general-purpose port
Output of “L” level from all ports for key-scan
••••
Set data table for key-scan to P2 (address
000416)
Wait for key-scan
Wait until “H” level output of P2 is stabilized
Transfer the contents of P04 to P07 (address
000016) to RAM
Update the data table pointer for key-scan
N
Keys read-in
(Set the port P0 direction register (P0D) (address
000116) to the input mode in the initialization, etc.)
Data table reference pointer for the next key-scan updated
Key-scan is completed ? (Note)
Y
Setting of flag which judge whether key-scan is completed or not
Set key-scan completion flag
Initialize data table pointer for key-scan
P2 (address 000416)
P2FPR (address 0EFA16)
FLDM (address 0EF416), bit 0
R TI
0016
111111112
1
Output of “L” level from all key-scan ports
Setting of general-purpose ports to FLD ports
Switching from general-purpose mode to the automatic
display mode
Note: If key-scan is not completed within Tscan set
time, perform key-scan separately.
38B5 Group User’s Manual
2-99
APPLICATION
2.4 FLD controller
(2) Key-scan using FLD automatic display and digits
Outline: Key read-in with digit output waveforms is performed by software using the FLD automatic
display mode.
P00, P01 Segment
P20–P27
P30, P31 Digit
SUN MON TUE WED THU FRI SAT
SP EP
RE C
■
P10–P17 Digit
LEVEL
P04–P07
●
●
●
●
AM
PM
CH
L
R
Panel with fluorescent display (FLD)
38B5 Group
Key-matrix
Fig. 2.4.21 Connection diagram
Specifications: •Use of total 20 FLD ports (10 digits, 8 key-scan included; 10 segments)
•Use of FLD automatic display mode
•Display in gradation display mode and 16 timing mode
•Toff1 = 40 ms, Toff2 = 64 ms, Tdisp = 204 ms, Tscan = 0 ms, f(XIN) = 4 MHz
•Use of FLD digit interrupt
2-100
38B5 Group User’s Manual
APPLICATION
2.4 FLD controller
Figure 2.4.22 shows the timing chart of key-scan.
Tscan = 0 µs
Tdisp
FLD16 (P10)Toff1
FLD digit interrupt request occur
Toff2
FLD17 (P11)
FLD digit interrupt request occur
FLD18 (P12)
•
•
•
FLD25 (P31)
FLD digit interrupt request occur
•
•
•
•
•
FLD digit interrupt request occur
FLD0–FLD9
(P20–P27,
P00, P01)
Fig. 2.4.22 Timing chart of key-scan using FLD automatic display mode and digits
38B5 Group User’s Manual
2-101
APPLICATION
2.4 FLD controller
Figure 2.4.23 shows the setting of relevant registers.
Port P0 direction register (address 000116)
P0D
0 0 0 0
Set P04 to P07 to input ports for key-scan input
Port P0FLD/port switch register (address 0EF916)
P0FPR
0 0 0 0 0 0 1 1
Set P00, P01 to FLD ports (FLD8, FLD9)
Set P02–P07 to general-purpose I/O ports
Port P2FLD/port switch register (address 0EFA16)
P2FPR
1 1 1 1 1 1 1 1
Set P20–P27 to FLD ports (FLD0–FLD7)
FLDC mode register (address 0EF416)
FLDM
1 0 1 0 0 0 0 1
Automatic display mode
Display stopped
0 FLD digit interrupt
16 timing mode
Gradation display mode selected
Tdisp counter count source : f(XIN)/16
High-breakdown voltage port drivability weak
Fig. 2.4.23 Setting of relevant registers
2-102
38B5 Group User’s Manual
APPLICATION
2.4 FLD controller
Tdisp time set register (address 0EF516)
TDISP
50 (3216) set; (50 + 1) ✕ count source = 204 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
3216
Toff1 time set register (address 0EF616)
TOFF1
10 (A16) set; 10 ✕ count source = 40 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
A16
Toff2 time set register (address 0EF716)
TOFF2
16 (1016) set; 16 ✕ count source = 64 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
1016
Note: Perform this setting when the gradation display mode is selected.
FLD data pointer (address 0EF816)
FLDDP
0 0 0 0 1 0 0 1
Set {(digit number) – 1} = 9
P1FLDRAM write disable register (address 0EF216)
P1FLDRAM
1 1 1 1 1 1 1 1
Disable writing to FLDRAM corresponding to P10 to P17.
P3FLDRAM write disable register (address 0EF316)
P3FLDRAM
1 1
Disable writing to FLDRAM corresponding to P30, P31.
Interrupt request register 2 (address 003D16)
IREQ2
0
Clear FLD digit interrupt request bit
Interrupt control register 2 (address 003F16)
ICON2
0 1
FLD digit interrupt: Enabled
FLDC mode register (address 0EF416)
FLDM
1 0 1 0 0 0 1 1
Display start
38B5 Group User’s Manual
2-103
APPLICATION
2.4 FLD controller
Setting of FLD automatic display RAM:
Table 2.4.3 FLD automatic display RAM map
1 to 16 timing display data stored area
Address
0FB016
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
Bit 7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
Bit 6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
Bit 5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
Bit 4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
Bit 3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
Bit 2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
Gradation display control data stored area
Bit 1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
Bit 0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
Address
0F6016
0F6116
0F6216
0F6316
0F6416
0F6516
0F6616
0F6716
0F6816
0F6916
0F6A16
0F6B16
0F6C16
0F6D16
0F6E16
0F6F16
0F7016
0F7116
0F7216
0F7316
0F7416
0F7516
0F7616
0F7716
0F7816
0F7916
0F7A16
0F7B16
0F7C16
0F7D16
0F7E16
0F7F16
0F8016
0F8116
0F8216
0F8316
0F8416
0F8516
0F8616
0F8716
0F8816
0F8916
0F8A16
0F8B16
0F8C16
0F8D16
0F8E16
0F8F16
0F9016
0F9116
0F9216
0F9316
0F9416
0F9516
0F9616
0F9716
0F9816
0F9916
Bit 7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
FLD7
Bit 6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
FLD6
Bit 4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
FLD4
Bit 3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
FLD3
Bit 2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
FLD2
: Area which is used to set digit data
: Area which is available as ordinary RAM
38B5 Group User’s Manual
Corresponding
digit pin
Bit 1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
FLD1
Bit 0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
FLD0
→ FLD25 (P31)
→ FLD24 (P30)
→ FLD23 (P17)
→ FLD22 (P16)
→ FLD21 (P15)
→ FLD20 (P14)
→ FLD19 (P13)
→ FLD18 (P12)
→ FLD17 (P11)
→ FLD16 (P10)
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD9
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
FLD8
→ FLD25 (P31)
→ FLD24 (P30)
→ FLD23 (P17)
→ FLD22 (P16)
→ FLD21 (P15)
→ FLD20 (P14)
→ FLD19 (P13)
→ FLD18 (P12)
→ FLD17 (P11)
→ FLD16 (P10)
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
: Area which is used to set segment data
2-104
Bit 5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD5
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
FLD25 FLD24
APPLICATION
2.4 FLD controller
FLD18
FLD19
FLD20
FLD21
SUN MON
SP EP
RE C
■
LEVEL
FLD22 FLD23
FLD24
FLD25
a
TUE WED THU FRI SAT
•
•
•
•
AM
PM
f g b
e
CH
FLD17
L
R
c
d
FLD16
Fig. 2.4.24 FLD digit allocation example
Table 2.4.4 FLD automatic display RAM map example
Gradation display control data stored area
1 to 16 timing display data stored area
Address
0FB016
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
g
f
e
d
c
b
a
CH
g
f
e
d
c
b
a
SAT
g
FRI
f
e
d
c
b
a
WED g
f
e
d
c
b
a
MON g
f
e
d
c
b
a
SUN g
f
e
d
c
b
a
g
–
f
e
d
c
b
a
■
REC SP
EP
PM
AM
THU
TUE
•
•
•
•
L
R
LEVEL
Address
0F6016
0F6116
0F6216
0F6316
0F6416
0F6516
0F6616
0F6716
0F6816
0F6916
0F6A16
0F6B16
0F6C16
0F6D16
0F6E16
0F6F16
0F7016
0F7116
0F7216
0F7316
0F7416
0F7516
0F7616
0F7716
0F7816
0F7916
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
g
f
e
d
c
b
a
CH
g
f
e
d
c
b
a
SAT
g
FRI
f
e
d
c
b
a
WED g
f
e
d
c
b
a
MON g
f
e
d
c
b
a
SUN g
f
e
d
c
b
a
g
–
f
e
d
c
b
a
■
REC SP
EP
PM
AM
THU
TUE
•
•
•
•
L
R
LEVEL
Corresponding
digit pin
→ FLD25 (P31)
→ FLD24 (P30)
→ FLD23 (P17)
→ FLD22 (P16)
→ FLD21 (P15)
→ FLD20 (P14)
→ FLD19 (P13)
→ FLD18 (P12)
→ FLD17 (P11)
→ FLD16 (P10)
→ FLD25 (P31)
→ FLD24 (P30)
→ FLD23 (P17)
→ FLD22 (P16)
→ FLD21 (P15)
→ FLD20 (P14)
→ FLD19 (P13)
→ FLD18 (P12)
→ FLD17 (P11)
→ FLD16 (P10)
: Unused
38B5 Group User’s Manual
2-105
APPLICATION
2.4 FLD controller
Control procedure:
RESET
Initialization
••••
00002
000000112
111111112
101000012
3216
A16
1016 (Note 1)
000010012
P0D (address 000116), bit 4–bit 7
P0FPR (address 0EF916)
P2FPR (address 0EFA16)
FLDM (address 0EF416)
TDISP (address 0EF516)
TOFF1 (address 0EF616)
TOFF2 (address 0EF716)
FLDDP (address 0EF816)
Port direction register setting
FLD port setting
FLD automatic display function setting
••••
FLD automatic display RAM
(addresses 0FB016–0FE916)
Gradation display control
RAM
(addresses 0F6016–0F9916)
P1FLDRAM (address 0EF216)
P3FLDRAM (address 0EF316)
Data to be
display
Gradation display
control data (Note 1)
111111112
000000112
(Note 3)
IREQ2 (address 003D16), bit 6
0
Setting of gradation display control data
Set “1” for dark display
Set “0” for bright display (Note 2)
Writing data to digit pin disabled
FLD digit interrupt request bit cleared
Wait until writing to the FLD digit interrupt request
bit is completed
1 cycle or more wait
I CON2 (address 003F16), bit 6
FLDM (address 0EF4 16), bit 1
Digit data and segment data setting (Note 2)
1
1
FLD digit interrupt enabled
FLD automatic display start
Main processing
Notes 1: When selecting the gradation display, set these
registers, too.
2: The display data can be rewritten at arbitrary
timing.
3: Set these registers according to necessity.
Fig. 2.4.25 Control procedure
2-106
38B5 Group User’s Manual
APPLICATION
2.4 FLD controller
FLD digit interrupt routine
Digit key-scan
Push registers to stack, etc.
••••
Wait until the digit output is stabilized since the digit
output waveform may become dull depending on the
PCB pattern wiring length etc.
Wait for key-scan
Transfer the contents of P04 to P07
(address 000016) to RAM
Keys read-in
(Set the port P0 direction register (P0D) (address
000116) to the input mode in the initialization, etc.)
Store the contents of RAM to the buffer
R TI
38B5 Group User’s Manual
2-107
APPLICATION
2.4 FLD controller
(3) FLD display by software (example of not used FLD controller)
Outline: FLD display and key read-in is performed, using a timer interrupt.
SUN MON TUE WED THU FRI SAT
P10–P17 Digit
P30, P31
P00, P01
P20–P27
Segment
SP EP
RE C
■
Segment
P04–P07
LEVEL
●
●
●
●
AM
PM
CH
L
R
Panel with fluorescent display (FLD)
38B5 Group
Key-matrix
Fig. 2.4.26 Connection diagram
Specifications: •Use of 10 digits and 10 segments (8 key-scan included)
•Display controlled by software
•Use of timer 1 interrupt
Figure 2.4.27 shows the timing chart of FLD display by software, and Figure 2.4.28 shows the
enlarged view of P20 to P27 key-scan. Generate the waveform shown Figure 2.4.28 by software and
perform key-scan.
P10
P11
P12
•••
•••
P31
Key-scan
P20–P27,
P00, P01
•••
Fig. 2.4.27 Timing chart of FLD display by software
P20
P21
P22
•••
•••
P27
Fig. 2.4.28 Enlarged view of P20 to P2 7 key-scan
2-108
38B5 Group User’s Manual
APPLICATION
2.4 FLD controller
Figure 2.4.29 shows the setting of relevant registers.
Port P0 direction register (address 000116)
P0D
0 0 0 0
Set P04 to P07 to input ports for key scan input
Port P2 direction register (address 000516)
P2D
1 1 1 1 1 1 1 1
Set P20 to P27 to output ports for key scan output
FLDC mode register (address 0EF416)
FLDM
1
0 0
General-purpose mode
Display stopped
High-breakdown voltage port drivability weak
Interrupt request register 1 (address 003C16)
IREQ1
0
Clear timer 1 interrupt request bit
Interrupt control register 1 (address 003E16)
ICON1
1
Timer 1 interrupt: Enabled
Timer 12 mode register (address 002816)
T12M
0
Timer 1 count start
Fig. 2.4.29 Setting of relevant registers
38B5 Group User’s Manual
2-109
APPLICATION
2.4 FLD controller
P12
P13
P14
P15
P16
SUN MON
SP EP
RE C
■
LEVEL
P17
•
•
•
•
a
AM
PM
f g b
e
CH
P11
L
R
P10
Table 2.4.5 FLD automatic display RAM map example
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
g
f
e
d
c
b
a
CH
g
f
e
d
c
b
a
SAT
g
FRI
f
e
d
c
b
a
WED g
f
e
d
c
b
a
MON g
f
e
d
c
b
a
f
e
d
c
b
a
SUN g
g
–
f
e
d
c
b
a
■
REC SP
EP
PM
AM
THU
TUE
•
•
•
•
L
R
LEVEL
Corresponding
digit pin
→ P31
→ P30
→ P17
→ P16
→ P15
→ P14
→ P13
→ P12
→ P11
→ P10
→ P31
→ P30
→ P17
→ P16
→ P15
→ P14
→ P13
→ P12
→ P11
→ P10
: Unused
(The automatic display is not performed because FLD controller is not used.)
2-110
P31
TUE WEDTHU FRI SAT
Fig. 2.4.30 FLD digit allocation example
Address
0FB016
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
P30
38B5 Group User’s Manual
c
d
APPLICATION
2.4 FLD controller
Control procedure:
●X: This bit is not used for this application.
Set “0” or “1” to this bit arbitrarily.
RESET
Initialization
.....
P0D (address 000116), bit 4–bit 7
P2D (address 000516)
FLDM (address 0EF416)
IREQ1 (address 003C16), bit 5
00002
111111112
1XXXXX002
0
Port direction registers setting
1
0
Timer 1 interrupt: Enabled
Timer 1 count start
.....
Timer 1 interrupt request bit cleared
Wait until completion of writing to timer 1 interrupt request bit
ICON1 (address 003E16), bit 5
T12M (address 002816), bit 0
.....
Timer 1 interrupt routine
Segment key-scan
Push registers to stack, etc.
P0 (address 000016), bit 0, bit 1
P1 (address 000216)
P2 (address 000416)
P3 (address 000616), bit 0, bit 1
FLD display turned off
002
0016
0016
002
.....
All column display is completed ?
Y
Set data table for key-scan to P2 (address 000416)
N
P0 (address 000016), bit 0, bit 1
P2 (address 000416)
Segment
data
P1 (address 000216)
P3 (address 000616), bit 0, bit 1
Digit data
Wait until “H” level output of P2
is stabilized.
Wait for key-scan
Transfer the contents of P04 to P07
(address 000016) to RAM
Keys read-in
(Set the port P0 direction register (P0D) (address
000116) to the input mode on initialization, etc.)
Update the data table pointer for key-scan
N
Key-scan is completed ?
Y
R TI
Fig. 2.4.31 Control procedure
38B5 Group User’s Manual
2-111
APPLICATION
2.4 FLD controller
(4) Display by combination with digit expander (M35501FP*) (basic combination example)
* For M35501FP, refer to section “3.12 M35501FP”.
Outline: The fluorescent display which has many display numbers (36 segments ✕ 16 digits) is
displayed by using the digit expander (M35501FP).
38B5 Group
M35501FP
P50
RESET
SEL
P51
P87
CLK
P20–P27
P00–P07
P10–P17
P30–P37
P80–P83
OVFIN
DIG0–DIG15
Digit (16)
REC
SLEEP
DISC
TRACK
Fluorescent display (FLD)
DATE
CLOCK
Y
M
D
m
s
Segment (36)
1
2
3
4 5
6
7 8
9
h
10 11 12 13 14 15 16 17 18
19 20 21 22 23 24 25 26 27
28 29 30 31 32 33 34 35 36
RE C
Fig. 2.4.32 Connection diagram
Specifications: •Use of M35501FP (M35501FP: 16 digits, 38B5 Group: 36
segments)
_____________
Ports P5 0 and P51 of 38B5 Group supply signals to the RESET and SEL pins of
M35501FP respectively.
The P87 pin (FLD port vacant pin) supply signals to the CLK pin of M35501FP.
•Use of FLD automatic display mode of 38B5 Group
•Display in gradation display mode and 16 timing mode
•Toff1 = 40 µs, Toff2 = 64 µs, Tdisp = 204 µs, f(XIN) = 4 MHz
Figure 2.4.33 shows the timing chart of 38B5 Group and M35501FP, and Figure 2.4.34 shows the
timing chart (enlarged view) of digit and segment output.
2-112
38B5 Group User’s Manual
APPLICATION
2.4 FLD controller
M35501FP
RESET
SEL
OVFIN
OVFOUT
CLK
DIG0
DIG1
DIG2
DIG3
•••
•••
DIG12
DIG13
DIG14
DIG15
38B5 Group
FLD0–FLD35
(P20–P27, P00–P07,
P10–P17, P30–P37,
P80–P83)
Fig. 2.4.33 Timing chart of 38B5 Group and M35501FP
M35501FP
CLK
Tdisp
DIG0
DIG1
Toff1
DIG2
Toff2
•••
DIG15
38B5 Group
FLD0–FLD35
(P20–P27, P00–P07,
P10–P17, P30–P37,
P80–P83)
•••
Fig. 2.4.34 Timing chart (enlarged view) of digit and segment output
38B5 Group User’s Manual
2-113
APPLICATION
2.4 FLD controller
Figure 2.4.35 shows the setting of relevant registers.
Port P0FLD/port switch register (address 0EF916)
P0FPR
1 1 1 1 1 1 1 1
Set P00–P07 to FLD output ports (FLD8–FLD15)
Port P2FLD/port switch register (address 0EFA16)
P2FPR
1 1 1 1 1 1 1 1
Set P20–P27 to FLD output ports (FLD0–FLD7)
Port P8FLD/port switch register (address 0EFB16)
P8FPR
1 0 0 0 1 1 1 1
Set P80–P83 to FLD output ports (FLD32–FLD35)
Set P84–P86 to general-purpose I/O ports
Set P87 to FLD output port (FLD39)
Port P5 direction register (address 000B16)
P5D
0 0 0 0 0 0 1 1
Set P50 to output port (for M35501 RESET signal)
Set P51 to output port (for M35501 SEL signal)
Port P5 (address 000A16)
P5
0 0 0 0 0 0 0 0
M35501 RESET signal output (Note 1)
M35501 SEL signal “L” output
Note 1: After retain RESET signal output “L” for 2 µs or more, release reset by outputting “H” level
from RESET signal output at CLK signal = “L” .
Fig. 2.4.35 Setting of relevant registers
2-114
38B5 Group User’s Manual
APPLICATION
2.4 FLD controller
FLDC mode register (address 0EF416)
FLDM
1 0 1 0 0 0 0 1
Automatic display mode
Display stopped
Tscan = 0 FLD digit interrupt
16 timing mode
Gradation display mode selected
Tdisp counter count source : f(XIN)/16
High-breakdown voltage port drivability weak
Tdisp time set register (address 0EF516)
TDISP
50 (3216) set; (50 + 1) ✕ count source = 204 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
3216
Toff1 time set register (address 0EF616)
TOFF1
10 (A16) set; 10 ✕ count source = 40 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
A16
Toff2 time set register (address 0EF716) (Note 2)
16 (1016) set; 16 ✕ count source = 64 µs
1016
TOFF2
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
Note 2: Perform this setting when the gradation display mode is selected.
FLD data pointer (address 0EF816)
FLDDP
0 0 0 0 1
1 1 1
Set {(digit number) – 1} = 15
FLDC mode register (address 0EF416)
FLDM
1 0 1 0 0 0 1 1
Display start
38B5 Group User’s Manual
2-115
APPLICATION
2.4 FLD controller
Setting of FLD automatic display RAM:
Table 2.4.6 FLD automatic display RAM map
1 to 16 timing display data stored area
Address
0FB016
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
0FEA16
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
0FFA16
0FFB16
0FFC16
0FFD16
0FFE16
0FFF16
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
FLD15 FLD14 FLD13 FLD12 FLD11 FLD10 FLD9 FLD8
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD31 FLD30 FLD29 FLD28 FLD27 FLD26 FLD25 FLD24
FLD35 FLD34 FLD33 FLD32
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Gradation display control data stored area
Address
0F6016
0F6116
0F6216
0F6316
0F6416
0F6516
0F6616
0F6716
0F6816
0F6916
0F6A16
0F6B16
0F6C16
0F6D16
0F6E16
0F6F16
0F7016
0F7116
0F7216
0F7316
0F7416
0F7516
0F7616
0F7716
0F7816
0F7916
0F7A16
0F7B16
0F7C16
0F7D16
0F7E16
0F7F16
0F8016
0F8116
0F8216
0F8316
0F8416
0F8516
0F8616
0F8716
0F8816
0F8916
0F8A16
0F8B16
0F8C16
0F8D16
0F8E16
0F8F16
0F9016
0F9116
0F9216
0F9316
0F9416
0F9516
0F9616
0F9716
0F9816
0F9916
0F9A16
0F9B16
0F9C16
0F9D16
0F9E16
0F9F16
0FA016
0FA116
0FA216
0FA316
0FA416
0FA516
0FA616
0FA716
0FA816
0FA916
0FAA16
0FAB16
0FAC16
0FAD16
0FAE16
0FAF16
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
FLD15 FLD14 FLD13 FLD12 FLD11 FLD10 FLD9 FLD8
FLD23 FLD22 FLD21 FLD20 FLD19 FLD18 FLD17 FLD16
FLD31 FLD30 FLD29 FLD28FLD27 FLD26 FLD25 FLD24
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FLD35 FLD34 FLD33 FLD32
: CLK signal set area to M35501FP
: Unused
2-116
38B5 Group User’s Manual
Corresponding
digit pin of
M35501FP
→ DIG15
→ DIG14
→ DIG13
→ DIG12
→ DIG11
→ DIG10
→ DIG9
→ DIG8
→ DIG7
→ DIG6
→ DIG5
→ DIG4
→ DIG3
→ DIG2
→ DIG1
→ DIG0
→ DIG15
→ DIG14
→ DIG13
→ DIG12
→ DIG11
→ DIG10
→ DIG9
→ DIG8
→ DIG7
→ DIG6
→ DIG5
→ DIG4
→ DIG3
→ DIG2
→ DIG1
→ DIG0
→ DIG15
→ DIG14
→ DIG13
→ DIG12
→ DIG11
→ DIG10
→ DIG9
→ DIG8
→ DIG7
→ DIG6
→ DIG5
→ DIG4
→ DIG3
→ DIG2
→ DIG1
→ DIG0
→ DIG15
→ DIG14
→ DIG13
→ DIG12
→ DIG11
→ DIG10
→ DIG9
→ DIG8
→ DIG7
→ DIG6
→ DIG5
→ DIG4
→ DIG3
→ DIG2
→ DIG1
→ DIG0
→ DIG15
→ DIG14
→ DIG13
→ DIG12
→ DIG11
→ DIG10
→ DIG9
→ DIG8
→ DIG7
→ DIG6
→ DIG5
→ DIG4
→ DIG3
→ DIG2
→ DIG1
→ DIG0
APPLICATION
2.4 FLD controller
DIG0
DIG1 DIG2 DIG3
DIG4 DIG5 DIG6 DIG7
DIG8 DIG9 DIG10 DIG11
FLD26
FLD0
FLD1
FLD2
FLD27
FLD20 FLD22 FLD18
FLD5
FLD6
FLD7 FLD8
FLD9
1
2
REC
SLEEP
3 4
5
6
FLD15 FLD16 FLD17FLD18 FLD19
DATE
CLOCK
7 8
Y
D
FLD21 FLD23 FLD19
FLD17
FLD12 FLD14
FLD2
FLD8
FLD20 FLD21FLD22 FLD23FLD24
FLD6
FLD4
FLD25
FLD13 FLD15
FLD10
FLD3 FLD7
FLD9
FLD11
FLD5
FLD0
FLD29
FLD1
FLD25 FLD26FLD27 FLD28 FLD29
9
10 11 12 13 14 15 16 17 18
M
FLD24
FLD16
FLD10 FLD11 FLD12 FLD13FLD14
DISC
TRACK
FLD28
FLD3 FLD4
m
h
DIG13
s
FLD30 FLD31FLD32 FLD33 FLD34
DIG14
FLD30
FLD31 FLD32
FLD33 FLD34
RE
35C
F LD
FLD35
19 20 21 22 23 24 25 26 27
28 29 30 31 32 33 34 35 36
RE C
DIG12
DIG15
LD
F LD
F LD
10 F21LD F32LD F43LD F54LD F65LD F7
8
98
6
7
F LD
D
1F9L0D 1F1L1
1FL2D 1FL3D 1FL4D 1FL5D 1FL6D 1FL7D 1FL8D
0 11 12 13 14 15 16 17
F LD
F LD
F LD
F LD
F LD
F LD
2FL5D 2FL6D 2FL7D
1
189 2
10
9 2
201 222
1 2
23
2 2
24
3 24 25 26
D
F LD
F LD
F LD
F LD
F LD
F LD
2F2L78D 2F2L89D 3F2L0
6
9 331
0 332
1 333
2 3
34
3 3
35
4 3
35
Fig. 2.4.36 FLD digit allocation example
Control procedure:
Figure 2.4.37 shows the control procedure.
RESET
Initialization
•••
111111112
111111112
100011112
101000012
3216
A16
1016 (Note 1)
000011112
000000112
000000002
FLD port setting
P5 (address 000A16)
000000012
RESET of M35501FP released (Note 2)
FLD automatic display RAM
(address 0FB016–0FFF16)
Data to be
display
Setting of CLK data to M35501FP and
segment data (Note 3)
Gradation
display control
data (Note 1)
Gradation display control data setting
Set “1” for dark display
Set “0” for bright display (Note 3)
P0FPR (address 0EF916)
P2FPR (address 0EFA16)
P8FPR (address 0EFB16)
FLDM (address 0EF416)
TDISP (address 0EF516)
TOFF1 (address 0EF616)
TOFF2 (address 0EF716)
FLDDP (address 0EF816)
P5D (address 000B16)
P5 (address 000A16)
•••
Gradation display control
RAM
(addresses 0F6016–0FAF16)
FLDM (address 0EF416), bit 1
1
FLD automatic display function setting
Port direction registers setting
RESET to M35501FP = “ L ” ,
SEL = “L ” signal output set
FLD automatic display start
Main processing
Notes 1: When selecting the gradation display, set these registers,
too.
2: After retaining RESET signal output “L” for 2 µs or more,
release reset while CLK signal is “L”.
3: The display data can be rewritten at arbitrary timing.
Fig. 2.4.37 Control procedure
38B5 Group User’s Manual
2-117
APPLICATION
2.4 FLD controller
(5) Display by combination with digit expander (M35501FP*) (example considering column discrepancy
prevention)
* For M35501FP, refer to section “3.12 M35501FP”.
Outline: In the case of (4), which is displayed by using the digit expander (M35501FP), if a noise
enters signals between 38B5 Group and M35501FP, a column discrepancy of display may
occur. Prevent the column discrepancy by using the OVF OUT output of M35501FP.
The OVF OUT pin of M35501FP outputs an overflow signal. The overflow signal is the
signal which outputs “H” synchronizing to the last digit output signal of M35501FP, and
the signal is output at definite intervals in the correct state. Incorrect state is detected by
measuring the output period of this signal, and a column discrepancy is prevented.
38B5 Group
M35501FP
P50
P51
RESET
SEL
P87
CLK
CNTR 1
OVFOUT
P20–P27
P00–P07
P10–P17
P30–P37
P80–P83
OVFIN
DIG0–DIG15
Digit (16)
REC
SLEEP
DISC
TRACK
Fluorescent display (FLD)
DATE
CLOCK
Y
M
D
h
m
s
Segment (36)
1
2
3
4 5
6
7 8
9
10 11 12 13 14 15 16 17 18
19 20 21 22 23 24 25 26 27
28 29 30 31 32 33 34 35 36
RE C
Fig. 2.4.38 Connection diagram
Specifications: •Use of M35501FP (M35501: 16 digits, 38B5 Group: 36 segments)
_____________
Ports P5 0 and P5 1 of 38B5 Group supply signal to the RESET and SEL pins of
M35501FP respectively.
The P87 pin (FLD port vacant pin) supply signals to the CLK pin of M35501FP.
•Use of FLD automatic display mode of 38B5 Group
•Display in gradation display mode and 16 timing mode
•Toff1 = 40 µs, Toff2 = 64 µs, Tdisp = 204 µs, f(XIN ) = 4 MHz
Countermeasures against
→ •OVFOUT output of M35501FP input to CNTR1 pin of 38B5 Group
column discrepancycolumn
Input signal to CNTR1 pin is counted as a count source by timer
discrepancy
4 of 38B5 Group
The timer 6 interrupt is generated each time FLD display period
(Tdisp (204 µs) ✕ 16 column = 3.264 ms), and a value of timer
4 is confirmed. M35501FP is reset at incorrect state.
Figure 2.4.39 shows the timing chart (at correct state) of 38B5 Group and M35501FP, and Figure
2.4.40 shows the timing chart (at incorrect state) of 38B5 Group and M35501FP.
2-118
38B5 Group User’s Manual
APPLICATION
2.4 FLD controller
M35501FP
RESET
SEL
OVFIN
OVFOUT
CLK
DIG0
DIG1
•••
•••
DIG14
DIG15
38B5 Group
FLD0–FLD35
(P20–P27, P00–P07,
P10–P17, P30–P37,
P80–P83)
Fig. 2.4.39 Timing chart (at correct state) of 38B5 Group and M35501FP
M35501FP
RESET
SEL
OVFIN
Noise
OVFOUT
CLK
DIG0
DIG1
•••
•••
DIG14
DIG15
38B5 Group
FLD0–FLD35
(P20–P27, P00–P07,
P10–P17, P30–P37,
P80–P83)
Column discrepancy occur
Fig. 2.4.40 Timing chart (at incorrect state) of 38B5 Group and M35501FP
38B5 Group User’s Manual
2-119
APPLICATION
2.4 FLD controller
Figure 2.4.41 shows the setting of relevant registers.
g
P0FPR
1 1 1 1 1 1 1 1
Set P00–P07 to FLD output ports (FLD8–FLD15)
Port P2FLD/port switch register (address 0EFA16)
P2FPR
1 1 1 1 1 1 1 1
Set P20–P27 to FLD output ports (FLD0–FLD7)
Port P8FLD/port switch register (address 0EFB16)
P8FPR
1 0 0 0 1 1 1 1
Set P80–P83 to FLD output ports (FLD32–FLD35)
Set P84–P86 to general-purpose I/O ports
Set P87 to FLD output port (FLD39)
Port P5 direction register (address 000B16)
P5D
1 1
Set P50 to general-purpose output port (for M35501 RESET signal)
Set P51 to general-purpose output port (for M35501 SEL signal)
Port P5 (address 000A16)
P5
0 0
M35501 RESET signal output (Note 1)
M35501 SEL signal “L” output
Note 1: After retain RESET signal output “L” for 2 µs or more, release reset by
outputting “ H” level from RESET signal output at CLK signal = “L” .
FLDC mode register (address 0EF416)
FLDM
1 0 1 0 0 0 0 1
Automatic display mode
Display stopped
Tscan = 0 FLD digit interrupt
16 timing mode
Gradation display mode selected
Tdisp counter count source : f(XIN)/16
High-breakdown voltage port drivability weak
Tdisp time set register (address 0EF516)
TDISP
3216
50 (3216) set; (50 + 1) ✕ count source = 204 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
Toff1 time set register (address 0EF616)
TOFF1
0A16
10 (A16) set; 10 ✕ count source = 40 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
Tof f 2 t im e set reg ist er ( addr ess 0 EF7 1 6 ) (Note 2)
TOFF2
1 0 16
16 (1016) set; 16 ✕ count source = 64 µs
Count source = f(XIN)/16 = 4 µs, at f(XIN) = 4 MHz
Note 2: Perform this setting when the gradation display mode is selected.
Fig. 2.4.41 Setting of relevant registers
2-120
38B5 Group User’s Manual
APPLICATION
2.4 FLD controller
FLD data pointer (address 0EF816)
FLDDP
0 0 0 0 1 1 1 1
Set {(digit number) – 1} = 15
Interrupt edge selection register (address 003A16)
INTEDGE 0
CNTR1 pin rising edge active
Timer 34 mode register (address 002916)
T34M 0
1 0
1
Timer 4 count stop, count start at FLD display started
Timer 4 count source: External count input CNTR1
Timer 4 (address 002316)
T4
Check value of T4 each time timer 6 interrupt occurrence
When the value is FE16, it is judged as correct state
FF16
Timer 56 mode register (address 002A16)
T56M 0 0 0 1 0 0 1 1
Timer 5 count stop, count start at FLD display started
Timer 6 count stop, count start at FLD display started
Timer 5 count source: f(XIN)/8
Timer 6: Timer mode
Timer 6 count source: Timer 5 underflow
P44 I/O port
Timer 5 (address 002416)
T5
0716
Timer 6 (address 002516)
T6
Timer 6 interrupt occurs at 3.264 ms intervals
CB16
Interrupt request register 2 (address 003D16)
IREQ2
0
Clear timer 6 interrupt request
Interrupt control register 2 (address 003F16)
ICON2 0
1
Timer 6 interrupt enabled
FLDC mode register (address 0EF416)
FLDM
1 0 1 0 0 0 1 1
Display start
38B5 Group User’s Manual
2-121
APPLICATION
2.4 FLD controller
Control procedure:
Figure 2.4.42 shows the control procedure.
●X: This bit is not used for this application.
Set “0” or “1” to this bit arbitrarily.
RESET
Initialization
•••
111111112
111111112
1XXX11112
101000012
3216
A16
1016 (Note 1)
XXXX11112
XXXXXX112
XXXXXX002
0X10XX1X2
0
FF16
000100112
716
CB16
XXXXXX012
P0FPR (address 0EF916)
P2FPR (address 0EFA16)
P8FPR (address 0EFB16)
FLDM (address 0EF416)
TDISP (address 0EF516)
TOFF1 (address 0EF616)
TOFF2 (address 0EF716)
FLDDP (address 0EF816)
P5D (address 000B16)
P5 (address 000A16)
T34M (address 002916)
INTEDGE (address 003A16), bit 7
T4 (address 002316)
T56M (address 002A16)
T5 (address 002416)
T6 (address 002516)
P5 (address 000A16)
FLD port setting
FLD automatic display function setting
Port direction register setting
RESET to M35501FP = “ L ” , SEL = “ L ” signal output setting
Timer 4 setting
Timer 5, timer 6 setting
RESET of M35501FP released (Note 2)
•••
FLD automatic display RAM
(addresses 0FB016–0FFF16)
Data to be
display
Gradation display control
RAM
(addresses 0F6016–0FAF16)
Gradation
display control
data (Note 1)
IREQ2 (address 003D16), bit 2
ICON2 (address 003F16), bit 2
T34M (address 002916), bit 0
T56M (address 002A16), bit 0, 1
FLDM (address 0EF416), bit 1
0
1
0
002
1
Setting of CLK data to M35501FP and
segment data (Note 3)
Setting of gradation display control data
Set “1” for dark display
Set “0” for bright display (Note 3)
Timer 6 interrupt enabled
Timer 4, timer 5, timer 6 count start (Note 4)
FLD automatic display start (Note 4)
Main processing
Fig. 2.4.42 Control procedure
2-122
38B5 Group User’s Manual
APPLICATION
2.4 FLD controller
Interrupt occurs each time FLD display cycle = 3.264 ms
Timer 6 interrupt routine
Push registers to stack, etc.
Correct
data (FE16)
Check timer 4 data ?
Check of OVFOUT output number during FLD display cycle
Only 1 time (=FE16) is correct.
Incorrect data (except FE16)
Error processing
FLDM (address 0EF416), bit 1
FLD turned off
0
Transfer present display contents to work RAM
P5 (address 000A16)
XXXXXX002
Setting of RESET to M35501FP = “L”,
SEL = “L” signal output
XXXXXX012
Releasing RESET of M35501FP (Note 2)
••
P5 (address 000A16)
Display data is retained as backup.
FLD automatic display RAM
(addresses 0FB016–0FFF16)
Data to be
display
Setting of CLK data to M35501FP
Setting of segment data by display data
of backup
(Note 5)
Gradation display control
RAM
(addresses 0F6016–0FAF16)
Gradation
display control
data (Note 1)
T56M (address 002A16), bit 0, 1
FLDM (address 0EF416), bit 1
T4 (address 002316)
FF16
002
1
Setting of gradation display control data
Set “1” for dark display
Set “0” for bright display
Timer 5, timer 6 count start (Note 4)
FLD turned on, automatic display start (Note 4)
Setting of timer 4 again
••
Pop registers
R TI
Notes 1: When selecting the gradation display, set these registers,
too.
2: After retaining RESET signal output “L” for 2 µs or more,
release reset while CLK signal is “L”.
3: The display data can be rewritten at arbitrary timing.
4: Synchronize count start timing of timer 5 and timer 6 with
FLD automatic display start timing as possible.
5: Set segment data of M35501FP at reset and others
according to necessity.
38B5 Group User’s Manual
2-123
APPLICATION
2.4 FLD controller
2.4.4 Notes on use
● Set a value of 0316 or more to the Toff1 time set register.
● When displaying in the gradation display mode, select the 16 timing mode by the timing number control
bit (bit 4 of FLDC mode register (address 0EF4 16 ) = “0”).
2-124
38B5 Group User’s Manual
APPLICATION
2.5 A-D converter
2.5 A-D converter
This paragraph describes the setting method of A-D converter relevant registers, notes etc.
2.5.1 Memory assignment
Address
003216
A-D control register (ADCON)
003316 A-D conversion register (low-order) (ADL)
003416 A-D conversion register (high-order) (ADH)
003D16
Interrupt request register 2 (IREQ2)
003F16
Interrupt control register 2 (ICON2)
Fig. 2.5.1 Memory assignment of A-D converter relevant registers
2.5.2 Relevant registers
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register
(ADCON: address 3216)
b
Name
0 Analog input pin
selection bits
1
2
3
Functions
b3 b2 b1 b0
0 0 0 0: P70/AN0
0 0 0 1: P71/AN1
0 0 1 0: P72/AN2
0 0 1 1: P73/AN3
0 1 0 0: P74/AN4
0 1 0 1: P75/AN5
0 1 1 0: P76/AN6
0 1 1 1: P77/AN7
1 0 0 0: P62/SRDY1/AN8
1 0 0 1: P63/AN9
1 0 1 0: P64/INT4/SBUSY1/AN10
1 0 1 1: P65/SSTB1/AN11
4 AD conversion
0: Conversion in progress
1: Conversion completed
completion bit
5 Nothing is arranged for these bits. These are
6 write disabled bits. When these bits are read
7 out, the contents are “0”.
At reset R W
0
0
0
0
1
0
0
0
Fig. 2.5.2 Structure of A-D control register
38B5 Group User’s Manual
2-125
APPLICATION
2.5 A-D converter
A-D conversion register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (low-order)
(ADL: address 3316)
b
0
1
2
3
4
5
6
7
Functions
Nothing is arranged for these bits. These are write
disabled bits. When these bits are read out, the
contents are “0”.
These are A-D conversion result (low-order 2 bits)
stored bits. This is read exclusive register.
At reset R W
Undefined
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Note: Do not read this register during A-D conversion.
Fig. 2.5.3 Structure of A-D conversion register (low-order)
A-D conversion register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (high-order)
(ADH: address 3416)
b
0
1
2
3
4
5
6
7
Functions
Note: Do not read this register during A-D conversion.
Fig. 2.5.4 Structure of A-D conversion register (high-order)
2-126
At reset R W
This is A-D conversion result (high-order 8 bits) stored Undefined
bits. This is read exclusive register.
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
38B5 Group User’s Manual
APPLICATION
2.5 A-D converter
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16)
b
0
1
2
3
4
5
6
7
Name
Functions
Timer 4 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
request bit (Note)
Timer 5 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
request bit
Timer 6 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
request bit
Serial I/O2 receive 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
INT3/Serial I/O2
0 : No interrupt request issued
1 : Interrupt request issued
transmit interrupt
request bit (Note)
0 : No interrupt request issued
INT4 interrupt
1 : Interrupt request issued
request bit
A-D converter
interrupt request bit
FLD blanking
0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
FLD digit interrupt
request bit
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
At reset R W
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽: “0” can be set by software, but “1” cannot be set.
Note: In the mask option type P, if timer 4 interrupt whose count source is
CNTR1 input and INT3 interrupt are selected, these bits do not
become “1”.
Fig. 2.5.5 Structure of interrupt request register 2
38B5 Group User’s Manual
2-127
APPLICATION
2.5 A-D converter
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2
(ICON2 : address 3F16)
b
Name
Functions
At reset R W
0
0 Timer 4 interrupt
0 : interrupt disabled
enable bit (Note)
1 : Interrupt enabled
0
1 Timer 5 interrupt
0 : interrupt disabled
enable bit
1 : Interrupt enabled
0
2 Timer 6 interrupt
0 : interrupt disabled
enable bit
1 : Interrupt enabled
0
3 Serial I/O2 receive 0 : interrupt disabled
interrupt enable bit 1 : Interrupt enabled
0
0 : interrupt disabled
4 INT3/Serial I/O2
1 : Interrupt enabled
transmit interrupt
enable bit (Note)
0
5 INT4 interrupt
0 : interrupt disabled
1 : Interrupt enabled
enable bit
A-D converter
interrupt enable bit
0
6 FLD blanking
0 : interrupt disabled
interrupt enable bit 1 : Interrupt enabled
FLD digit interrupt
enable bit
7 Fix “0” to this bit.
0
Note: In the mask option type P, timer 4 interrupt whose count source
is CNTR1 input and INT3 interrupt are not available.
Fig. 2.5.6 Structure of interrupt control register 2
2-128
38B5 Group User’s Manual
APPLICATION
2.5 A-D converter
2.5.3 A-D converter application examples
(1) Read-in of analog signal
Outline: The analog input voltage input from a sensor is converted to digital values.
Figure 2.5.7 shows a connection diagram, and Figure 2.5.8 shows the setting of relevant registers.
Sensor
P70/AN0
38B5 Group
Fig. 2.5.7 Connection diagram
Specifications: •Conversion of analog input voltage input from sensor to digital values
•Use of P7 0/AN0 pin as analog input pin
A-D control register (address 003216)
ADCON
0 0 0 0 0
Analog input pin : P70/AN0 selected
A-D conversion start
A-D conversion register (high-order) (address 003416)
ADH
(Read-only)
A result of A-D conversion is stored (Note).
A-D conversion register (low-order) (address 003316)
A DL
(Read-only)
A result of A-D conversion is stored (Note).
Note: After bit 4 of ADCON is set to “1”, read out both registers in order of ADH (address
003416) and ADL (address 003316) following.
Fig. 2.5.8 Setting of relevant registers
38B5 Group User’s Manual
2-129
APPLICATION
2.5 A-D converter
Control procedure: A-D converter is started by performing register setting shown Figure 2.5.8.
Figure 2.5.9 shows the control procedure.
ADCON (address 003216), bit 0–bit 3 ← 00002
←0
ADCON (address 003216), bit 4
• P70/AN0 pin selected as analog input pin
• A-D conversion start
0
ADCON (address 003216), bit 4 ?
• Judgment of A-D conversion completion
1
Read out ADH (address 003416)
• Read out of high-order (b9–b2) conversion result
Read out ADL (address 003316)
• Read out of low-order (b1, b0) conversion result
Fig. 2.5.9 Control procedure
2-130
38B5 Group User’s Manual
APPLICATION
2.5 A-D converter
2.5.4 Notes on use
(1)
Analog input pin
■ Make the signal source impedance for analog input low, or equip an analog input pin with an
external capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application
products on the user side.
● Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A-D conversion precision to be worse.
■ When the P64/INT4/S BUSY1/AN 10 pin is selected as analog input pin, external interrupt function (INT4)
becomes invalid.
(2)
A-D converter power source pin
The AVSS pin is A-D converter power source pin. Regardless of using the A-D conversion function
or not, connect it as following :
• AVSS : Connect to the VSS line
● Reason
If the AV SS pin is opened, the microcomputer may have a failure because of noise or others.
(3)
Clock frequency during A-D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A-D conversion.
• f(X IN) is 250 kHz or more
• Use clock divided by main clock (f(X IN)) as internal system clock.
• Do not execute the STP instruction and WIT instruction
38B5 Group User’s Manual
2-131
APPLICATION
2.6 PWM
2.6 PWM
This paragraph describes the setting method of PWM relevant registers, notes etc.
2.6.1 Memory assignment
Address
001416
PWM register (high-order) (PWMH)
001516
PWM register (low-order) (PWML)
002616
PWM control register (PWMCON)
Fig. 2.6.1 Memory assignment of PWM relevant registers
2.6.2 Relevant registers
PWM register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
PWM register (high-order)
(PWMH: address 1416)
b
Functions
0 • High-order 8 bits of PWM0 output data is set.
• The values set in this register is transferred to
1
the PWM latch each sub-period cycle (64 µs).
(At f(XIN) = 4 MHz)
2
• When this register is read out, the value of the
3
PWM register (high-order) is read out.
Undefined
4
Undefined
5
Undefined
6
Undefined
7
Undefined
Fig. 2.6.2 Structure of PWM register (high-order)
2-132
At reset R W
38B5 Group User’s Manual
Undefined
Undefined
Undefined
APPLICATION
2.6 PWM
PWM register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
PWM register (low-order)
(PWML: address 1516)
b
Functions
At reset R W
0 • Low-order 6 bits of PWM0 output data is set.
• The values set in this register is transferred to
1
the PWM latch at each PWM cycle period
(4096 µs).
2
(At f(XIN) = 4 MHz)
3 • When this register is read out, the value of the
PWM latch (low-order 6 bits) is read out.
4
Undefined
5
Undefined
6 Nothing is arranged for this bit. This bit is a
write disabled bit. When this bit is read out, the
contents are “0”.
7 • This bit indicates whether the transfer to the
PWM latch is completed.
0: Transfer is completed
1: Transfer is not completed
• This bit is set to “1” at writing.
Undefined
Undefined
Undefined
Undefined
Undefined
✕
Undefined
✕
Fig. 2.6.3 Structure of PWM register (low-order)
PWM control register
b7 b6 b5 b4 b3 b2 b1 b0
PWM control register
(PWMCON: address 2616)
b
Name
Functions
0: I/O port
0 P87/PWM output
selection bit
1: PWM output
1 Nothing is arranged for these bits. These are
2 write disabled bits. When these bits are read out,
3 the contents are “0”.
4
5
6
7
At reset R W
0
0
0
0
0
0
0
0
Fig. 2.6.4 Structure of PWM control register
38B5 Group User’s Manual
2-133
APPLICATION
2.6 PWM
2.6.3 PWM application example
(1) Control of VS tuner
Figure 2.6.5 shows a connection diagram, and Figure 2.6.6 shows the setting of relevant registers.
VS tuner
A NT
Filter
P87/PWM0/FLD39
0–32 V
VT
38B5 Group
Fig. 2.6.5 Connection diagram
Outline: • Control of VS tuner by using the 14-bit resolution PWM 0 output function
• f(X IN ) = 4 MHz
PWM control register (address 002616)
PWMCON
1
Select PWM output
Note: The PWM output function has priority even when the
bit corresponded to the P87 pin of the port P8 direction
register is set to the input mode.
PWM register (high-order) (address 001416)
PWMH
Set high-order 8 bits (N) of a 14-bit data to be output
Note: Depending on data (N) of the high-order 8 bits, the period (250
✕ N) of the “H” level during the sub period (64 µs) is
determined.
PWM register (low-order) (address 001516)
PWML
Set low-order 6 bits (m) of a 14-bit data to be output
Note: Depending on data (m) of the low-order 6 bits, the number of
sub period to which the ADD bit is to be added within the
repetitive cycle consisting of 64 sub periods is determined.
When output data is written to the PWM register (low-order),
bit 7 of this register becomes “1”. When completing to transfer
data from the PWM register (low-order) to the PWM latch, bit 7
becomes “0”.
Fig. 2.6.6 Setting of relevant registers
2-134
38B5 Group User’s Manual
APPLICATION
2.6 PWM
Control procedure: PWM waveform is output to the external by setting relevant registers shown
Figure 2.6.6. This PWM 0 output is integrated through the low pass filter and
converted into DC signals for control of the VS tuner.
Figure 2.6.7 shows the control procedure.
PWMCON (address 002616), bit 0
PWMH (address 001416)
PWML (address 001516)
1
Data to be
output
The P87/PWM0/FLD39 pin is set to the PWM
output pin.
After setting data, PWM waveform
corresponding to the new data is output from
the next repetitive cycle.
Fig. 2.6.7 Control procedure
2.6.4 Notes on use
● For PWM 0 output, “L” level is output first.
● After data is set to the PWM register (low-order) and the PWM register (high-order), PWM waveform
corresponding to new data is output from next repetitive cycle.
PWM0 output data
change
Modified data is output from next
repetitive cycle.
Fig. 2.6.8 PWM 0 output
38B5 Group User’s Manual
2-135
APPLICATION
2.7 Interrupt interval determination function
2.7 Interrupt interval determination function
This paragraph describes the setting method of interrupt interval determination function relevant registers,
notes etc.
2.7.1 Memory assignment
Address
003016 Interrupt interval determination register (IID)
003116
Interrupt interval determination control register (IIDCON)
003A16 Interrupt edge selection register (INTEDGE)
003C16
Interrupt request register 1 (IREQ1)
003E16
Interrupt control register 1 (ICON1)
Fig. 2.7.1 Memory assignment of interrupt interval determination function relevant registers
2.7.2 Relevant registers
Interrupt interval determination register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt interval determination register
(IID: address 3016)
b
Functions
0 • This register stores a value which is obtained
by counting a following interval with the
1
counter sampling clock.
2
Rising interval
3
Falling interval
Both edges interval (Note)
4
(Selected by interrupt edge selection register)
5
• Read exclusive register
6
7
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Note: When the noise filter sampling clock selection bits (bits 2, 3) of
the interrupt interval determination control register is “00”, the
both-sided edge detection function cannot be used.
Fig. 2.7.2 Structure of interrupt interval determination register
2-136
38B5 Group User’s Manual
APPLICATION
2.7 Interrupt interval determination function
Interrupt interval determination control register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt interval determination control register
(IIDCON: address 3116)
b
Name
Functions
At reset R W
0: Stopped
0 Interrupt interval
determination circuit 1: Operating
operating selection
bit
0
1 Counter sampling
clock selection bit
2 Noise filter
sampling clock
3 selection bits (INT2)
0: f(XIN)/128
1: f(XIN)/256
0
b3 b2
0
4 One-sided/bothsided edge
detection selection
bit
0 0: Filter is not used.
0 1: f(XIN)/32
1 0: f(XIN)/64
1 1: f(XIN)/128
0: One-sided edge
detection
1: Both-sided edge
detection (Note)
5 Nothing is arranged for these bits. These are
6 write disabled bits. When these bits are read
7 out, the contents are “0”.
0
0
0
0
0
Note: When the noise filter sampling clock selection bits (bits 2, 3) is
“00”, the both-sided edge detection function cannot be used.
Fig. 2.7.3 Structure of interrupt interval determination control register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register
(INTEDGE : address 3A16)
b
Name
Functions
At reset R W
0
0 INT0 interrupt edge 0 : Falling edge active
selection bit
1 : Rising edge active
0
1 INT1 interrupt edge 0 : Falling edge active
selection bit
1 : Rising edge active
0
2 INT2 interrupt edge 0 : Falling edge active
1 : Rising edge active
selection bit
0
3 INT3 interrupt edge 0 : Falling edge active
selection bit (Note) 1 : Rising edge active
0
4 INT4 interrupt edge 0 : Falling edge active
1 : Rising edge active
selection bit
0
5 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
0 : Rising edge count
6 CNTR0 pin edge
switch bit
1 : Falling edge count
0
0 : Rising edge count
7 CNTR1 pin edge
1 : Falling edge count
switch bit (Note)
Note: In the mask option type P, these bits are not available because
CNTR1 function and INT3 function cannot be used.
Fig. 2.7.4 Structure of interrupt edge selection register
38B5 Group User’s Manual
2-137
APPLICATION
2.7 Interrupt interval determination function
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16)
b
Name
Functions
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
1 INT1 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
2 INT2 interrupt
0 : No interrupt request
request bit
issued
Remote controller
1 : Interrupt request issued
/counter overflow
interrupt request bit
0
✽
3 Serial I/O1 interrupt 0 : No interrupt request
issued
request bit
Serial I/O automatic 1 : Interrupt request issued
transfer interrupt
request bit
0
✽
4 Timer X interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
5 Timer 1 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
6 Timer 2 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
7 Timer 3 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
✽: “0” can be set by software, but “1” cannot be set.
Fig. 2.7.5 Structure of interrupt request register 1
2-138
At reset R W
0 INT0 interrupt
request bit
38B5 Group User’s Manual
APPLICATION
2.7 Interrupt interval determination function
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 3E16)
b
Name
Functions
At reset R W
0 INT0 interrupt
enable bit
1 INT1 interrupt
enable bit
2 INT2 interrupt
enable bit
Remote controller
/counter overflow
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
3 Serial I/O1 interrupt
enable bit
Serial I/O automatic
transfer interrupt
enable bit
Timer
X interrupt
4
enable bit
5 Timer 1 interrupt
enable bit
6 Timer 2 interrupt
enable bit
Timer
3 interrupt
7
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
0
0
0
Fig. 2.7.6 Structure of interrupt control register 1
38B5 Group User’s Manual
2-139
APPLICATION
2.7 Interrupt interval determination function
2.7.3 Interrupt interval determination function application examples
(1) Reception of remote-control signal
Outline: Remote-control signal is read in by both of the interrupt interval determination function using
a noise filter and a timer interrupt.
Receiver
unit
P47/INT2
Remote controller
38B5 Group
Fig. 2.7.7 Connection diagram
Specifications: • Measurement of one-sided edge interval
• Use of noise filter
• Check of remote control interrupt request within the timer 2 interrupt (488 µs
period) processing routine
• Operation at f(XIN ) = 4 MHz in high-speed mode
Figure 2.7.8 shows the function block diagram, and Figure 2.7.9 shows a timing chart of data
determination.
Microcomputer hardware
Receiver
unit
Microcomputer software
Noise filter
Interrupt interval
determination
register
• Noise elimination
• One-sided edge
detection
• One-sided edge
interval
judgment
Determination
of header or
0 /1
Data
check
1-byte
reception
• Read out register
• Comparison of
read out value with
reference value
• Recognition bit
number of each
code
Fig. 2.7.8 Function block diagram
Input (INT2)
(Overflow)
Interrupt request
Timer 2 interrupt
(488 µs)
Interrupt interval
determination
register read-in
Data determination
Ignore
Header
0
1
•••
1-byte reception
Fig. 2.7.9 Timing chart of data determination
2-140
38B5 Group User’s Manual
1
Ignore Ignore
Check of excess bit
APPLICATION
2.7 Interrupt interval determination function
Figure 2.7.10 shows the setting of relevant registers.
CPU mode register (address 003B16)
CP UM
0
High-speed (f(XIN)) mode operation (Note)
Interrupt edge selection register (address 003A16)
INTEDGE
0
INT2 pin: Falling edge active
Interrupt interval determination control register (address 003116)
IIDCON
0 1 0 1 1
Interrupt interval determination circuit: Operating
Counter sampling clock: f(XIN)/256
Noise filter sampling clock: f(XIN)/64
One-sided edge detection
Interrupt request register 1 (address 003C16)
IREQ1
Determination of remote controller/counter overflow interrupt request bit
Interrupt control register 1 (address 003E16)
ICON1
0
Remote controller/counter overflow interrupt: Disabled
Interrupt interval determination register (address 003016)
IID
Determination of header/data (0/1) with this value
Note: The interrupt interval determination
function cannot be used in the lowspeed mode.
Fig. 2.7.10 Setting of relevant registers
38B5 Group User’s Manual
2-141
APPLICATION
2.7 Interrupt interval determination function
Control procedure: When the registers are set as shown Figure 2.7.10, remote-control signals are
receivable. Figure 2.7.11 shows the control procedure, and Figure 2.7.12 shows
the reception of remote-control data (timer 2 interrupt).
●X: This bit is not used here. Set it to “0” or “1”
arbitrarily.
RESET
Initialization
SEI
.....
CPUM (address 003B1 6), bit 6
0
.....
INTEDGE (address 003A1 6), bit 2
IIDCON (address 0031 16)
IREQ1 (address 003C16)
NOP
ICON1 (address 003E1 6)
0
XXX10111 2
0
0
.....
CLI
Fig. 2.7.11 Control procedure
2-142
38B5 Group User’s Manual
APPLICATION
2.7 Interrupt interval determination function
Timer 2 interrupt
Push registers to stack etc.
Input edge ?
(IREQ1, bit 2 = ?)
N
Y
During checking excess
bit ?
Clear edge (IREQ1, bit 2 = 0)
N
Y
Y
Number of bits error
(Excess bit is found)
Excess bit
determined counter
over ?
Y
During checking
excess bit ?
N
Read IID (address 003016)
N
Fixed data
R TI
Y
Time error
R TI
R TI
IID (address 003016)
= FF16 ?
N
In range of header ?
Y
Start receiving data etc.
N
R TI
Out of range of 0 or 1
In range of data, 0 or 1 ?
In range of 0
In range of 1
Time error
R TI
CY ← 1
CY ← 0
Shift reception data
Complete to
receive ?
N
Y
Start checking excess bit
R TI
Fig. 2.7.12 Reception of remote-control data (timer 2 interrupt)
38B5 Group User’s Manual
2-143
APPLICATION
2.8 Watchdog timer
2.8 Watchdog timer
The watchdog timer is a 20-bit down-count counter consisting of a low-order 8 bits and a high-order 12 bits.
“1” is subtracted from the watchdog timer each time a count source inputs.
This paragraph describes the setting method of watchdog timer relevant register, notes etc.
2.8.1 Memory assignment
Address
002B16
Watchdog timer contort register (WDTCON)
Fig. 2.8.1 Memory assignment of watchdog timer relevant register
2.8.2 Relevant register
The watchdog timer starts counting by writing an arbitrary value to the watchdog timer control register.
Figure 2.8.2 shows the structure of the watchdog timer control register.
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Watchdog timer control register
(WDTCON: address 2B16)
b
Name
Functions
0 Watchdog timer H
1 (high-order 6 bits of reading exclusive)
2
3
4
5
6 STP instruction
0: STP instruction enabled
disable bit
1: STP instruction disabled
7 Watchdog timer H
0: Watchdog timer L
count source
underflow
selection bit
1: f(XIN)/16 or f(XCIN)/16
Fig. 2.8.2 Structure of watchdog timer control register
2-144
38B5 Group User’s Manual
At reset R W
1
1
1
1
1
1
0
0
APPLICATION
2.8 Watchdog timer
2.8.3 Watchdog timer application examples
Outline: When a program runs away, the watchdog timer makes the microcomputer return to the
reset state.
Specifications: •When the watchdog timer H underflows, it is judged as incorrect program, and the
microcomputer is returned to the reset state.
•Bit 7 of the watchdog timer control register is set to “0” at 1-cycle intervals in the
main routine before underflow of the watchdog timer H. (Initialization of watchdog
timer value)
•Use of watchdog timer L underflow as count source of watchdog timer H
•Setting of main clock division ratio to f(X IN) (high-speed mode)
Figure 2.8.3 shows the connection of watchdog timer and the setting of the division ratio.
Figure 2.8.4 shows the setting of relevant registers.
Watchdog timer L
Fixed
f(XIN) = 4 MHz
1/8
1/256
Watchdog timer H
1/4096
Reset
circuit
Internal reset
RESET
STP instruction disable bit
STP instruction
Fig. 2.8.3 Connection of watchdog timer and setting of division ratio
CPU mode register (address 003B16)
CP UM
0 0 0
0 0
Single-chip mode
Main clock (XIN-XOUT): Oscillating
High-speed (f(XIN)) mode operation
Internal system clock: XIN-XOUT
Watchdog timer control register (address 002B16)
WDTCON
0 0
STP instruction: Enabled
Watchdog timer H count source:
Underflow of watchdog timer L
Fig. 2.8.4 Setting of relevant registers
38B5 Group User’s Manual
2-145
APPLICATION
2.8 Watchdog timer
Figure 2.8.5 shows the control procedure.
RESET
●X: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SEI
CLT
CLD
••••
CPUM (address 003B16)
CPU mode register setting
(single-chip mode, main clock oscillating, high-speed mode)
00XXXXXX2
Count of watchdog timer start
(STP instruction enabled, WDTH count source)
••••
000XXX002
CLI
WDTCON (address 002B16)
Main processing
Fig. 2.8.5 Control procedure
2.8.4 Notes on use
● The watchdog timer continues to count even while waiting for stop release. Accordingly, make sure that
watchdog timer does not underflow during this term by writing to the watchdog timer control register
(address 002B 16 ) once before executing the STP instruction, etc.
● Once a “1” is written to the STP instruction disable bit (bit 6) of the watchdog timer control register
(address 002B 16 ), it cannot be programmed to “0” again. This bit becomes “0” after reset.
2-146
38B5 Group User’s Manual
APPLICATION
2.9 Buzzer output circuit
2.9 Buzzer output circuit
The output frequency can be selected from 1 kHz, 2 kHz, or 4 kHz (at f(XIN) = 4.19 MHz), and the output
port can be selected between either the B UZ01 pin or the B UZ02 pin.
This paragraph describes the setting method of buzzer output circuit relevant register, notes etc.
2.9.1 Memory assignment
Address
0EFD16
Buzzer output control register (BUZCON)
Fig. 2.9.1 Memory assignment of buzzer output circuit relevant register
2.9.2 Relevant register
The buzzer output circuit starts outputting a buzzer by setting the buzzer output ON/OFF bit (bit 4) of the
buzzer output control register.
Figure 2.9.2 shows the structure of the buzzer output control register.
Buzzer output control register
b7 b6 b5 b4 b3 b2 b1 b0
Buzzer output control register
(BUZCON: address 0EFD16)
b
Name
0 Output frequency
selection bits
1
2 Output port
selection bits
3
Functions
At reset R W
b1b0
0
0 0: 1 kHz (f(XIN)/4096)
0 1: 2 kHz (f(XIN)/2048)
1 0: 4 kHz (f(XIN)/1024)
1 1: Not available
0
b3b2
0
0 0: P20 and P43 function
as ordinary ports.
0 1: P43/BUZ01 functions as
a buzzer output.
1 0: P20/BUZ02/FLD0
functions as a buzzer
output.
1 1: Not available
4 Buzzer output
ON/OFF bit
0: Buzzer output OFF (“0”
output)
1: Buzzer output ON
5 Nothing is arranged for these bits. These are
6 write disabled bits. When these bits are read
7 out, the contents are “0”.
0
0
0
0
0
Fig. 2.9.2 Structure of buzzer output control register
38B5 Group User’s Manual
2-147
APPLICATION
2.9 Buzzer output circuit
2.9.3 Buzzer output circuit application examples
Outline: A buzzer output is performed by using the buzzer output circuit.
Specifications: •f(XIN ) = 4.19 MHz, buzzer output frequency = 4 kHz
•Buzzer output from B UZ01 pin
Figure 2.9.3 shows the connection of buzzer output circuit and the setting of the division ratio.
Figure 2.9.4 shows the setting of relevant register. Figure 2.9.5 shows the control procedure.
Port latch
f(XIN) = 4.19 MHz
1/1024
Buzzer output
(4 kHz)
Buzzer output ON/OFF bit
Output port control signal
Port direction register
Fig. 2.9.3 Connection of buzzer output circuit and setting of division ratio
Buzzer output control register (address 0EFD16)
BUZCON
0 0 1 1 0
Output frequency: 4 kHz (f(XIN)/1024)
P43/Buz01: Buzzer output
Buzzer output: OFF
Fig. 2.9.4 Setting of relevant register
●X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
SEI
CLT
CLD
••••
BUZCON (address 0EFD16)
XXX001102
••••
CLI
BUZCON (address 0EFD16), bit 4
1
Fig. 2.9.5 Control procedure
2-148
38B5 Group User’s Manual
Buzzer output control register setting
(output frequency = 4 kHz, Buz01 output,
buzzer output OFF)
Buzzer output ON
APPLICATION
2.10 Reset circuit
2.10 Reset circuit
____________
The reset state is caused by applying
an “L” level to the RESET pin. After that, the reset state is released
____________
by applying an “H” level to the RESET pin, so that the program is executed in the middle-speed mode from
the contents of the reset vector address.
2.10.1 Connection example of reset IC
Figure 2.10.1 shows the example of power-on reset circuit. Figure 2.10.2 shows the system example which
switches to the RAM backup mode by detecting a drop of the system power source voltage with the INT
interrupt.
VCC
Power source
M62022L
GND
Output
RESET
Delay capacity
0.1µF
VSS
38B5 Group
Fig. 2.10.1 Example of power-on reset circuit
System power
source voltage
+5V
VCC
VCC1
RESET
VCC2
INT
RESET
INT
VSS
V1 GND
Cd
38B5 Group
M62009L, M62009P, M62009FP
Fig. 2.10.2 RAM backup system example
38B5 Group User’s Manual
2-149
APPLICATION
2.10 Reset circuit
2.10.2 Notes on use
(1) Reset input voltage control
Make sure that the reset input voltage is 0.5 V or less for Vcc of 2.7 V.
Perform switch to the high-speed mode when power source voltage is within 4.0 to 5.5 V.
(2) Countermeasure when RESET signal rise time is long
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the V SS pin. And use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
● Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
2-150
38B5 Group User’s Manual
APPLICATION
2.11 Clock generating circuit
2.11 Clock generating circuit
2.11.1 Relevant register
Figure 2.11.1 shows the structure of the CPU mode register.
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register
(CPUM, CM: address 3B16)
b
Name
0 Processor mode
bits
1
2 Stack page
selection bit
3 XCOUT drivability
selection bit
4 Port Xc switch bit
5 Main clock (XINXOUT) stop bit
6 Main clock division
ratio selection bit
7 Internal system
clock selection bit
Functions
b1 b0
At reset R W
00 : Single-chip mode
01 :
10 :
Not available
11 :
0 : Page 0
1 : Page 1
0: Low drive
1: High drive
0
0: I/O port function
1: XCIN-XCOUT oscillation
function
0: Oscillating
1: Stopped
0
0: f(XIN) (high-speed mode)
1: f(XIN)/4 (middle-speed
mode)
0: XIN–XOUT selection
(middle-/high-speed
mode)
1: XCIN–XCOUT selection
(low-speed mode)
1
0
0
1
0
0
Fig. 2.11.1 Structure of CPU mode register
38B5 Group User’s Manual
2-151
APPLICATION
2.11 Clock generating circuit
2.11.2 Clock generating circuit application examples
(1) Status transition during power failure
Outline: The clock is counted up every one second by using the timer interrupt during a power
failure.
Power failure detection signal
Input port
( N o t e)
38B5 Group
Note: Signal is detected by inputting to each input port,
interrupt input pin, and analog input pin.
Fig. 2.11.2 Connection diagram
Specifications: •Reducing power dissipation as low as possible while maintaining clock function
•Clock: f(XIN ) = 4.19 MHz, f(XCIN ) = 32.768 kHz
•Port processing
Input port: Fixed to “H” or “L” level on the external
Output port: Fixed to output level that does not cause current flow to the external
(Example) When a circuit turns on LED at “L” output level, fix the
output level to “H”.
I/O port: Input port → Fixed to “H” or “L” level on the external
Output port → Output of data that does not consume current
V REF: Stop to supply to reference voltage input pin by external circuit
Figure 2.11.3 shows the status transition diagram during power failure and Figure 2.11.4 shows the
setting of relevant registers.
Reset released
Power failure detected
XIN
XCIN
Internal
system clock
Middle-speed
mode
High-speed mode
Change internal system
clock to high-speed
mode
Low-speed mode
After detecting, change internal system clock to
low-speed mode and stop oscillating XIN-XOUT
XCIN-XCOUT oscillation function selected
Fig. 2.11.3 Status transition diagram during power failure
2-152
38B5 Group User’s Manual
APPLICATION
2.11 Clock generating circuit
CPU mode register (address 003B16)
CP UM
0 0 0 0
0 0
Main clock: High-speed mode (f(XIN)) (Note 1)
CPU mode register (address 003B16)
CP UM
0 0 0 1
0 0
(Note 2)
Port XC: XCIN-XCOUT oscillation function
CPU mode register (address 003B16)
CP UM
1 0 0 1
0 0
(Note 2)
Internal system clock: Low-speed mode (f(XCIN))
CPU mode register (address 003B16)
CP UM
1 0 1 1
0 0
(Note 2)
Main clock f(XIN): Stopped
Notes 1: This setting is necessary only when selecting the highspeed mode.
2: When selecting the middle-speed mode, bit 6 is “1”.
Fig. 2.11.4 Setting of relevant registers
38B5 Group User’s Manual
2-153
APPLICATION
2.11 Clock generating circuit
Control procedure: Set the relevant registers in the order shown below to prepare for a power
failure.
●X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
••••
CPUM (address 003B16), bit 6
CPUM (address 003B16), bit 4
0
1
When selecting main clock f(XIN) (high-speed mode)
Port XC: XCIN-XCOUT oscillation function
••••
N
Detect power failure ?
≈
Y
CPUM (address 003B16), bit 7
CPUM (address 003B16), bit 5
1 (Note)
1 (Note)
Set so that timer interrupt occurs every one
second
Execute WIT instruction
N
Internal system clock: f(XCIN) (low-speed mode)
Main clock f(XIN) oscillation stopped
At a power failure, clock count is performed during
timer interrupt processing (every second).
Return condition from power failure
concluded ?
Y
Return processing from power failure
Note: Do not switch at one time.
≈
Fig. 2.11.5 Control procedure
2-154
38B5 Group User’s Manual
APPLICATION
2.11 Clock generating circuit
(2) Counting without clock error during power failure
Outline: It keeps counting without clock error during a power failure.
Specifications: •Reducing power consumption as low as possible while maintaining clock function
•Clock: f(XIN) = 4.19 MHz
•Sub clock: f(XCIN) = 32.768 kHz
•Use of Timer 3 interrupt
For the peripheral circuit and the status transition during a power failure, refer to “Figures 2.11.2
and 2.11.3”.
Figure 2.11.6 shows the structure of clock counter, Figures 2.11.7 and 2.11.8 show the setting of
relevant registers.
Timer 1 interrupt
Timer 1
f(XIN) = 4.19 MHz
1/16
1/64
Base counter
244 µs
1 second counter
1/256
1/16
When the system returns from a
power failure, add the time taken
for the switching processing for the
return.
Timer 1
<At power failure>
f(XCIN) = 32.768 kHz
1/8
244 µs
Timer 2
Timer 3
1/256
1/16
Timer 3 interrupt
1 minute counter
1 second
1/60
Minute/Time/Day/
Month/Year
: Software timer
: Hardware timer
Fig. 2.11.6 Structure of clock counter
38B5 Group User’s Manual
2-155
APPLICATION
2.11 Clock generating circuit
CPU mode register (address 003B16)
CP UM
0 0 0 1
0 0
Port XC: XCIN-XCOUT oscillation function
CPU mode register (address 003B16)
CP UM
1
0 0 1
0 0
Internal system clock: f(XIN) (high-speed mode)
Timer 1 (address 002016)
T1
Set (Division ratio -1); 63 (3F16)
3F16
Timer 12 mode register (address 002816)
T12M
0
0 0 0 1 0 0 0
Timer 1 count: Operating
Timer 2 count: Operating
Timer 1 count source: f(XIN)/16
Timer 2 count source: Timer 1 underflow
P45 I/O port
Timer 34 mode register (address 002916)
T34M
0
0
0 1
0
Timer 3 count: Operating
Timer 3 count source: Timer 2 underflow
P46 I/O port
Interrupt request register 1 (address 003C16)
IREQ1
0
0
Set “0” to timer 1 interrupt request bit
Set “0” to timer 3 interrupt request bit
Interrupt control register 1 (address 003E16)
ICON1
1
Timer 1 interrupt: Enabled
Fig. 2.11.7 Initial setting of relevant registers
2-156
38B5 Group User’s Manual
APPLICATION
2.11 Clock generating circuit
Timer 12 mode register (address 002816)
T12M
0 1
Timer 1 count source: f(XCIN)
CPU mode register (address 003B16)
CP UM
1 0 0 1
0 0
Internal system clock: f(XCIN) (low-speed mode)
CPU mode register (address 003B16)
CP UM
1 0 1 1
0 0
Main clock f(XIN): Stopped
Interrupt control register 1 (address 003E16)
ICON1
1
0
Timer 1 interrupt: Disabled
Timer 3 interrupt: Enabled
Timer 1 (address 002016)
T1
0716
Timer 2 (address 002116)
T2
FF16
Set (Division ratio – 1)
(T1 = 7 (0716), T2 = 255 (FF16), T3 = 15 (0F16))
Timer 3 (address 002216)
T3
0F16
Fig. 2.11.8 Setting of relevant registers after detecting power failure
38B5 Group User’s Manual
2-157
APPLICATION
2.11 Clock generating circuit
Control procedure: Set the relevant registers in the order shown below to prepare for a power
failure.
●X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
••••
CPUM (address 003B16), bit 4
CPUM (address 003B16), bit 6
T1 (address 002016)
T12M (address 002816)
T34M (address 002916)
IREQ1 (address 003C16), bit 7, bit 5
Base counter (internal RAM)
1 second counter (internal RAM)
ICON1 (address 003E16), bit 5
1
0
3F16
000010002
00XX01X02
0,0
FF16
0F16
1
Port XC: XCIN-XCOUT oscillation function
When selecting main clock f(XIN) (high-speed mode)
Setting for making base and one second counters activate during
timer 1 interrupt
In the normal power state, these software counters generate one
second.
••••
N
Detect power failure ?
≈
Y
T12M (address 002816), bit 3, bit 2
ICON1 (address 003E16), bit 5
CPUM (address 003B16), bit 7
CPUM (address 003B16), bit 5
IREQ1 (address 003C16), bit 7, bit 5
T1 (address 002016)
T2 (address 002116)
T3 (address 002216)
ICON1 (address 003E16), bit 7
0, 1
0
1 (Note)
1 (Note)
0, 0
0716
3F16
0F16
1
Timer 3 interrupt: Enabled
Timer 3 interrupt occurs every second
(return from wait mode)
Execute WIT instruction
N
Timer 1 count source: f(XCIN)
Timer 1 interrupt: Disabled
Internal system clock: f(XCIN) (low-speed mode)
Main clock f(XIN): Oscillation stopped
Setting for generating timer 3 interrupt every second
Generation of one second by hardware timer during
power failure
Return condition for power failure is
satisfied ?
Y
Return processing from power failure
Note: Do not switch at one time.
≈
Fig. 2.11.9 Control procedure
2-158
38B5 Group User’s Manual
APPLICATION
2.11 Clock generating circuit
Timer 3 interrupt routine
Push registers to stack etc.
••••
Count 1 minute (internal RAM) counter
1 minute counter overflow ?
N
Y
Modify time, day, month, year
≈
R TI
38B5 Group User’s Manual
2-159
APPLICATION
2.11 Clock generating circuit
MEMORANDUM
2-160
38B5 Group User’s Manual
CHAPTER 3
APPENDIX
3.1 Electrical characteristics
3.2 Standard characteristics
3.3 Notes on use
3.4 Countermeasures against noise
3.5 Control registers
3.6 Mask ROM confirmation form
3.7 ROM programming confirmation form
3.8 Mark specification form
3.9 Package outline
3.10 List of instruction code
3.11 Machine instructions
3.12 M35501FP
3.13 SFR memory map
3.14 Pin configuration
APPENDIX
3.1 Electrical characteristics
3.1 Electrical characteristics
3.1.1 Absolute maximum ratings
Table 3.1.1 Absolute maximum ratings
Parameter
Symbol
Conditions
VCC
Power source voltage
VEE
Pull-down power source voltage
VI
Input voltage
P47, P5 0–P57, P6 1–P65 , P70–
P77, P8 4–P87, P9 0, P91
VI
Input voltage
P40–P4 6, P60
VI
Input voltage
P00–P0 7, P20–P2 7, P80 –P83
VI
Input voltage
RESET, XIN
VI
Input voltage
XCIN
VO
Output voltage
P00–P0 7, P10–P1 7, P20 –P27,
P30–P3 7, P80–P8 3
VO
Output voltage
P50–P5 7, P61–P6 5, P70 –P77,
P84–P8 7, P90, P9 1, XOUT,
XCOUT
VO
Output voltage
P40–P4 6, P60
Pd
Power dissipation
All voltages are
based on VSS.
Output transistors
are cut off.
Ratings
Unit
–0.3 to 7.0
V
VCC – 45 to VCC +0.3
V
–0.3 to VCC +0.3
V
–0.3 to 13
V
VCC – 45 to VCC +0.3
V
–0.3 to VCC +0.3
V
–0.3 to VCC +0.3
V
VCC – 45 to VCC +0.3
V
–0.3 to VCC +0.3
V
–0.3 to 13
V
Ta = –20 to 65 °C
800
mW
Ta = 65 to 85 °C
800 – 12.5 ✕ (Ta – 65)
mW
Topr
Operating temperature
–20 to 85
°C
Tstg
Storage temperature
–40 to 125
°C
3-2
38B5 Group User’s Manual
APPENDIX
3.1 Electrical characteristics
3.1.2 Recommended operating conditions
Table 3.1.2 Recommended operating conditions (1)
(Vcc = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
VCC
Power source voltage
VSS
VEE
VREF
AVSS
VIA
VIH
Power source voltage
Pull-down power source voltage
Analog reference voltage (when A-D converter is used)
Analog power source voltage
Analog input voltage
AN0–AN11
“H” input voltage
P40 –P47, P50–P57 , P60–P65, P70–P77 ,
P90 , P91
“H” input voltage
P84 –P87
“H” input voltage
P00 –P07
“H” input voltage
P20 –P27, P80–P83
“H” input voltage
RESET
“H” input voltage
XIN, X CIN
“L” input voltage
P40 –P47, P50–P57 , P60–P65, P70–P77 ,
P90 , P91
“L” input voltage
P84 –P87
“L” input voltage
P00 –P07, P20–P27, P8 0–P83
“L” input voltage
RESET
“L” input voltage
XIN, X CIN
H” total peak output current (Note 1)
P00–P07, P10 –P17, P20–P27, P3 0–P37, P80–P83
“H” total peak output current (Note 1)
P50–P57, P61 –P65, P70–P77, P9 0, P91
“L” total peak output current (Note 1)
P50–P57, P60 –P65, P70–P77, P9 0, P91
“L” total peak output current (Note 1)
P40–P46, P84 –P87
“H” total average output current (Note 1)
P00–P07, P10 –P17, P20–P27, P3 0–P37, P80–P87
“H” total average output current (Note 1)
P50–P57, P61 –P65, P70–P77, P9 0, P91
“L” total average output current (Note 1)
P50–P57, P60 –P65, P70–P77, P9 0, P91
“L” total average output current (Note 1)
P40–P46, P84 –P87
“H” peak output current (Note 2)
P00–P07, P10 –P17, P20–P27, P3 0–P37, P80–P83
“H” peak output current (Note 2)
P50–P57, P61 –P65, P70–P77, P8 4–P87, P90, P9 1
“L” peak output current (Note 2)
P50–P57, P61 –P65, P70–P77, P8 4–P87, P90, P9 1
“L” peak output current (Note 2)
P40–P46, P60
“H” average output current (Note 3)
P00–P07, P10 –P17, P20–P27, P3 0–P37, P80–P83
“H” average output current (Note 3)
P50–P57, P60 –P65, P70–P77, P8 4–P87, P90, P9 1
“L” average output current (Note 3)
P50–P57, P61 –P65, P70–P77, P8 4–P87, P90, P9 1
“L” average output current (Note 3)
P40–P46, P60
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
I OH(peak)
I OH(peak)
I OL(peak)
I OL(peak)
I OH(avg)
I OH(avg)
I OL(avg)
I OL(avg)
In high-speed mode
In middle-/low-speed mode
Min.
4.0
2.7
Limits
Typ.
5.0
5.0
0
Max.
5.5
5.5
Unit
0
0.75V CC
VCC
VCC
V
V
V
V
V
V
V
V
0.4VCC
0.8VCC
0.52V CC
0.8VCC
0.8VCC
0
VCC
VCC
VCC
VCC
VCC
0.25V CC
V
V
V
V
V
V
0
0
0
0
0.16V CC
0.2V CC
0.2V CC
0.2V CC
–240
V
V
V
V
mA
–60
mA
100
mA
60
mA
–120
mA
–30
mA
50
mA
30
mA
–40
mA
–10
mA
10
mA
30
mA
–18
mA
–5
mA
5
mA
15
mA
VCC–43
2.0
VCC
VCC
0
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an
average value measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current I OL (avg), IOH(avg) in an average value measured over 100 ms.
38B5 Group User’s Manual
3-3
APPENDIX
3.1 Electrical characteristics
Table 3.1.3 Recommended operating conditions (2)
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Limits
Parameter
Min.
f(CNTR0)
f(CNTR1)
Clock input frequency for timers 2, 4, and X (duty cycle 50 %)
f(XIN)
Main clock input oscillation frequency (Note 1)
f(XCIN)
Sub-clock input oscillation frequency (Notes 1, 2)
Typ.
32.768
Max.
Unit
250
kHz
4.2
MHz
50
kHz
Notes 1: When the oscillation frequency has a duty cycle of 50%.
2: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
3.1.3 Electrical characteristics
Table 3.1.4 Electrical characteristics (1)
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Test conditions
Parameter
Limits
Min.
Typ.
Max.
Unit
VOH
“H” output voltage P00–P07 , P10–P1 7, P20–P2 7,
P30–P37 , P80–P8 3
I OH = –18 mA
VCC –2.0
V
VOH
“H” output voltage P50–P57 , P60–P6 5, P70–P7 7,
P84–P87 , P90, P91
I OH = –10 mA
VCC –2.0
V
VOL
“L” output voltage P50–P57 , P61–P6 5, P84–P8 7,
P90, P91
VOL
“L” output voltage P40–P46 , P60
VT+–VT–
Hysteresis
P40–P42 , P45–P4 7, P5, P60,
P61, P64 (Note 1)
0.4
V
VT+–VT–
Hysteresis
RESET, XIN
0.5
V
VT+–VT–
Hysteresis
XCIN
0.5
V
IIH
“H” input current
P47, P50 –P57, P6 1–P65,
P70–P77 , P84–P8 7
VI = VCC
5.0
µA
IIH
I OL = 10 mA
I OL = 15 mA
0.6
2.0
V
2.0
V
“H” input current
P40–P46 , P60
VI = 12 V
10.0
µA
IIH
“H” input current
P00–P07, P2 0–P27, P80–P83 (Note 2) VI = VCC
5.0
µA
IIH
“H” input current
RESET, XCIN
VI = VCC
5.0
µA
IIH
“H” input current
XIN
VI = VCC
IIL
“L” input current
P40–P47 , P60
VI = VSS
–5.0
µA
P50–P57 , P61–P6 5, P70–P7 7,
P84–P87 , P90, P9 1
VI = VSS
Pull-up “off”
–5.0
µA
IIL
“L” input current
µA
4.0
VCC = 5 V , VI = VSS
Pull-up “on”
–30
–70
–140
µA
VCC = 3 V , VI = VSS
Pull-up “on”
–6.0
–25
–45
µA
IIL
“L” input current
P00–P0 7, P2 0–P2 7, P8 0–P8 3 (Note 2) VI = VSS
–5.0
µA
IIL
“L” input current
RESET, XCIN
VI = VSS
–5.0
µA
XIN
VI = VSS
IIL
“L” input current
ILOAD
Output load current
P00–P07, P1 0–P17, P3 0–P3 7
VEE = VCC–43 V,
VOL =V CC
Output transistors “off”
ILEAK
Output leak current
P00–P07, P1 0–P17, P2 0–P27 ,
P30–P37, P8 0–P83
VEE = VCC–43 V,
VOL =VCC–43 V
Output transistors “off”
IREADH
“H” read current
P00–P07 , P20–P2 7, P80–P8 3
3-4
300
VI = 5 V
VRAM
When clock is stopped
Notes 1: P42, P45 , P46, and P60 of the mask option type P do not have hysteresis characteristics.
2: Except when reading ports P0, P2, or P8.
38B5 Group User’s Manual
µA
–4.0
600
900
µA
–10
µA
µA
1
2
5.5
V
APPENDIX
3.1 Electrical characteristics
Table 3.1.5 Electrical characteristics (2)
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
ICC
Parameter
Limits
Test conditions
Power source current
Min.
High-speed mode
f(X IN) = 4.2 MHz
f(X CIN) = 32 kHz
Output transistors “off”
Typ.
Max.
7.5
15
Unit
mA
High-speed mode
f(X IN) = 4.2 MHz (in WIT state)
f(X CIN) = 32 kHz
Output transistors “off”
1
mA
Middle-speed mode
f(X IN) = 4.2 MHz
f(X CIN) = stopped
Output transistors “off”
3
mA
Middle-speed mode
f(X IN) = 4.2 MHz (in WIT state)
f(X CIN) = stopped
Output transistors “off”
1
mA
Low-speed mode
f(X IN) = stopped
f(X CIN) = 32 kHz
Low-power dissipation mode (CM 3 = 0)
Output transistors “off”
60
200
µA
Low-speed mode
f(X IN) = stopped
f(X CIN) = 32 kHz (in WIT state)
Low-power dissipation mode (CM 3 = 0)
Output transistors “off”
20
40
µA
Increment when A-D conversion is executed
0.6
All oscillation stopped (in STP state)
Output transistors “off”
Ta = 25 °C
0.1
Ta = 85 °C
mA
1
µA
10
µA
3.1.4 A-D converter characteristics
Table 3.1.6 A-D converter characteristics
(VCC = 4.0 to 5.5V, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 250 kHz to 4.2 MHz in high-speed mode, unless otherwise noted)
Symbol
Parameter
Test conditions
—
Resolution
—
Absolute accuracy (excluding quantization error)
Min.
VCC = VREF = 5.12 V
Limits
Typ.
Max.
10
Bits
±1
±2.5
LSB
62
tc(φ)
150
200
µA
5.0
µA
TCONV
Conversion time
IVREF
Reference input current
IIA
Analog port input current
0.5
RLADDER
Ladder resistor
35
61
VREF = 5.0 V
38B5 Group User’s Manual
50
Unit
kΩ
3-5
APPENDIX
3.1 Electrical characteristics
3.1.5 Timing requirements and switching characteristics
Table 3.1.7 Timing requirements
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Min.
____________
Limits
Typ.
Max.
Unit
tW (RESET)
Reset input “L” pulse width
2.0
µs
tC (XIN)
Main clock input cycle time (XIN input)
238
ns
tWH (XIN)
Main clock input “H” pulse width
60
ns
tWL (XIN)
Main clock input “L” pulse width
60
ns
tC (XCIN)
Sub-clock input cycle time (XCIN input)
20
µs
tWH (XCIN)
Sub-clock input “H” pulse width
5.0
µs
tWL (XCIN)
Sub-clock input “L” pulse width
5.0
µs
tC (CNTR)
CNTR0, CNTR 1 input cycle time
4.0
µs
tWH (CNTR)
CNTR0, CNTR 1 input “H” pulse width
1.6
µs
tWL (CNTR)
CNTR0, CNTR 1 input “L” pulse width
1.6
µs
tWH (INT)
INT0 to INT4 input “H” pulse width
80
ns
tWL (INT)
INT0 to INT4 input “L” pulse width
80
ns
tC (SCLK)
Serial I/O clock input cycle time
0.95
µs
tWH (SCLK)
Serial I/O clock input “H” pulse width
400
ns
tWL (SCLK)
Serial I/O clock input “L” pulse width
400
ns
tsu (SCLK–SIN)
Serial I/O input set up time
200
ns
th (SCLK–SIN)
Serial I/O input hold time
200
ns
Table 3.1.8 Switching characteristics
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Test conditions
Min.
Typ.
Max.
Unit
tWH (SCLK)
Serial I/O clock output “H” pulse width
CL = 100 pF
tC (SCLK)/2–160
ns
tWL (SCLK)
Serial I/O clock output “L” pulse width
CL = 100 pF
tC (SCLK)/2–160
ns
td (SCLK–SOUT)
Serial I/O output delay time
tv (SCLK–SOUT)
Serial I/O output valid time
tr (SCLK)
Serial I/O clock output rising time
CL = 100 pF
40
ns
tf(SCLK)
Serial I/O clock output falling time
CL = 100 pF
40
ns
tr (Pch–strg)
P-channel high-breakdown voltage
output rising time (Note 1)
CL = 100 pF
VEE = VCC–43 V
55
ns
tr (Pch–weak)
P-channel high-breakdown voltage
output rising time (Note 2)
CL = 100 pF
VEE = VCC–43 V
1.8
µs
0.2 tc
0
ns
Notes 1: When bit 7 of the FLDC mode register (address 0EF416) is at “0”.
2: When bit 7 of the FLDC mode register (address 0EF416) is at “1”.
Serial I/O clock
output port
P52/SCLK11,
P53/SCLK12,
P56/SCLK21,
P57/SCLK22
CL
P0,P1,P2,
P3,P80–P83
High-breakdown
P-channel opendrain output port
CL
(Note)
VEE
Note: Ports P2 and P8 need external resistors.
Fig. 3.1.1 Circuit for measuring output switching characteristics
3-6
38B5 Group User’s Manual
ns
APPENDIX
3.1 Electrical characteristics
Timing Diagram
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
CNTR0,CNTR1
0.8VCC
0.2VCC
tWL(INT)
tWH(INT)
INT0–INT4
0.8VCC
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
XIN
0.8VCC
0.2VCC
tC(XCIN)
tWL(XCIN)
tWH(XCIN)
XCIN
0.8VCC
0.2VCC
tC(SCLK)
tf(SCLK)
SCLK
tWL(SCLK)
tr
tWH(SCLK)
0.8VCC
0.2VCC
tsu(SIN-SCLK)
th(SCLK-SIN)
0.8VCC
0.2VCC
SIN
td(SCLK-SOUT)
tv(SCLK-SOUT)
SOUT
Fig. 3.1.2 Timing diagram
38B5 Group User’s Manual
3-7
APPENDIX
3.2 Standard characteristics
3.2 Standard characteristics
3.2.1 Power source current standard characteristics
At 5.5 V
9
Power source current
(mA)
8
7
6
At 4.0 V
5
4
3
2
1
4.2
0
0
1
2
3
4
5
6
Frequency f(XIN) (MHz)
Fig. 3.2.1 Power source current standard characteristics
At 5.5 V
Power source current 1000
(µA)
900
800
At 4.0 V
700
600
500
400
300
200
100
4.2
0
0
1
2
3
4
5
6
Frequency f(XIN) (MHz)
Fig. 3.2.2 Power source current standard characteristics (in wait mode)
3-8
38B5 Group User's Manual
APPENDIX
3.2 Standard characteristics
3.2.2 Port standard characteristics
Port P30 IOH-VOH characteristics (25 °C)
(Same characteristics pins: P0, P1, P2, P3, P80–P83)
IOH
(mA)
-100
VCC = 5.5 V
-90
-80
VCC = 5.0 V
-70
-60
VCC = 3.0 V
-50
-40
-30
-20
-10
0
0
1.200
2.400
3.600
4.800
6.000
VOH (V)
Fig. 3.2.3 High-breakdown P-channel open-drain output port characteristics (25 °C)
Port P30 IOH–VOH characteristics (90 °C)
(Same characteristics pins: P0, P1, P2, P3, P80–P83)
IO H
(mA)
-100
VCC = 5.5 V
-90
-80
VCC = 5.0 V
-70
-60
-50
VCC = 3.0 V
-40
-30
-20
-10
0
0
1.200
2.400
3.600
4.800
6.000
VOH (V)
Fig. 3.2.4 High-breakdown P-channel open-drain output port characteristics (90 °C)
38B5 Group User's Manual
3-9
APPENDIX
3.2 Standard characteristics
Port P87 IOH-VOH characteristics (25 °C)
(Same characteristics pins: P5, P61–P65, P7, P84–P87, P9)
IO H
(mA)
-100
-90
-80
-70
-60
-50
-40
VCC = 5.5 V
-30
VCC = 5.0 V
-20
-10
VCC = 3.0 V
0
0
1.200
2.400
3.600
4.800
6.000
VOH (V)
Fig. 3.2.5 CMOS output port P-channel side characteristics (25 °C)
Port P87 IOH–VOH characteristics (90 °C)
(Same characteristics pins: P5, P61–P65, P7, P84–P87, P9)
IO H
(mA)
-100
-90
-80
-70
-60
-50
-40
VC C = 5.5 V
-30
VC C = 5.0 V
-20
-10
0
VC C = 3.0 V
0
1.200
2.400
3.600
4.800
6.000
VOH (V)
Fig. 3.2.6 CMOS output port P-channel side characteristics (90 °C)
3-10
38B5 Group User's Manual
APPENDIX
3.2 Standard characteristics
Port P87 IOL–VOL characteristics (25 °C)
(Same characteristics pins: P5, P61–P65, P7, P84–P87, P9)
IO L
(mA)
100
90
80
70
VCC = 5.5 V
60
50
VCC = 5.0 V
40
30
VCC = 3.0 V
20
10
0
0
1.200
2.400
3.600
4.800
6.000
VOL (V)
Fig. 3.2.7 CMOS output port N-channel side characteristics (25 °C)
Port P87 IOL–VOL characteristics (90 °C)
(Same characteristics pins: P5, P61–P65, P7, P84–P87, P9)
IOL
(mA)
100
90
80
70
60
VCC = 5.5 V
50
VCC = 5.0 V
40
30
20
VCC = 3.0 V
10
0
0
1.200
2.400
3.600
4.800
6.000
VOL (V)
Fig. 3.2.8 CMOS output port N-channel side characteristics (90 °C)
38B5 Group User's Manual
3-11
APPENDIX
3.2 Standard characteristics
Port P40 IOL-VOL characteristics (25 °C)
(Same characteristics pins: P40–P46, P60)
IO L
(mA)
100
90
VCC = 5.5 V
80
70
VCC = 5.0 V
60
50
40
30
VCC = 3.0 V
20
10
0
0
1.200
2.400
3.600
4.800
6.000
VOL (V)
Fig. 3.2.9 N-channel open-drain output port characteristics (25 °C)
Port P40, IOL-VOL characteristics (90 °C)
(Same characteristics pins: P40–P46, P60)
IO L
(mA)
100
90
80
VC C = 5.5 V
70
60
VC C = 5.0 V
50
40
30
VC C = 3.0 V
20
10
0
0
1.200
2.400
3.600
4.800
6.000
VOL (V)
Fig. 3.2.10 N-channel open-drain output port characteristics (90 °C)
3-12
38B5 Group User's Manual
APPENDIX
3.2 Standard characteristics
3.2.3 A-D conversion standard characteristics
Figure 3.2.11 shows the A-D conversion standard characteristics.
The lower line on the graph indicates the absolute precision error. It expresses the deviation from the ideal
value. For example, the conversion of output code from 00 16 to 01 16 occurs ideally at the point of AN 0 =
2.5 mV, but the measured value is –2 mV. Accordingly, the measured point of conversion is defined as “2.5
– 2 = 0.5 mV”.
The upper line on the graph indicates the width of input voltages equivalent to output codes. For example,
the measured width of the input voltage for output code 60 16 is 6 mV, so that the differential nonlinear error
is defined as “6 – 5 = 1 mV (0.2 LSB)”.
38B5 GROUP A-D CONVERTER ERROR & STEP WIDTH MEASUREMENT
1 LSB WIDTH
15
15.0
10
10.0
5
5.0
0
0.0
-5
1LSB WIDTH [mV]
ERROR [mV]
VCC = 5.12 [V], VREF = 5.12 [V], AN0
XIN = 4 [MHz], Temp = 25 [deg.]
-1 0
-1 5
0
16
32
48
64
80
96
112
144
160
176
192
208
224
240
256
15
15.0
10
10.0
5
5.0
0
0.0
-5
1LSB WIDTH [mV]
ERROR [mV]
128
STEP No.
ERROR (Absolute precision error)
-1 0
-1 5
256
272
288
304
320
336
352
368
384
400
416
432
448
464
480
496
512
15
15.0
10
10.0
5
5.0
0
0.0
-5
1LSB WIDTH [mV]
ERROR [mV]
STEP No.
-1 0
-1 5
512
528
544
560
576
592
606
624
640
656
672
688
704
720
736
752
768
15
15.0
10
10.0
5
5.0
0
0.0
-5
1LSB WIDTH [mV]
ERROR [mV]
STEP No.
-1 0
-1 5
768
784
800
816
832
848
864
880
896
912
928
944
960
976
992
1008
1024
STEP No.
Fig. 3.2.11 A-D conversion standard characteristics
38B5 Group User's Manual
3-13
APPENDIX
3.3 Notes on use
3.3 Notes on use
3.3.1 Notes on interrupts
(1) Switching external interrupt detection edge
For the products able to switch the external interrupt detection edge, switch it as the following
sequence.
Clear an interrupt enable bit to “0” (interrupt disabled)
↓
Switch the detection edge
↓
Clear an interrupt request bit to “0”
(no interrupt request issued)
↓
Set the interrupt enable bit to “1” (interrupt enabled)
Fig. 3.3.1 Sequence of switch detection edge
■ Reason
The interrupt circuit recognizes the switching of the detection edge as the change of external input
signals. This may cause an unnecessary interrupt.
(2) Check of interrupt request bit
● When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request
register immediately after this bit is set to “0” by using a data transfer instruction, execute one or
more instructions before executing the BBC or BBS instruction.
■ Reason
If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt
request register is cleared to “0”, the value of the interrupt request bit before being cleared to “0”
is read.
Clear the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Data transfer instruction:
LDM, LDA, STA, STX, and STY instructions
Fig. 3.3.2 Sequence of check of interrupt request bit
3-14
38B5 Group User’s Manual
APPENDIX
3.3 Notes on use
(3) Structure of interrupt control register 2
Fix the bit 7 of the interrupt control register 2
to “0”. Figure 3.3.3 shows the structure of the
interrupt control register 2.
b7
0
b0
Interrupt control register
Address 003F16
Interrupt enable bits
Not used
Fix this bit to “0”.
Fig. 3.3.3 Structure of interrupt control register 2
3.3.2 Notes on serial I/O1
(1) Clock
■ Using internal clock
After setting the synchronous clock to an internal clock, clear the serial I/O interrupt request bit
before perform the normal serial I/O transfer or the serial I/O automatic transfer.
■ Using external clock
After inputting “H” level to the external clock input pin, clear the serial I/O interrupt request bit
before performing the normal serial I/O transfer or the serial I/O automatic transfer.
(2) Using serial I/O1 interrupt
Clear bit 3 of the interrupt request register 1 to “0” by software.
(3) State of SOUT1 pin
The S OUT1 pin control bit of the serial I/O1 control register 2 can be used to select the state of the
S OUT1 pin when serial data is not transferred; either output active or high-impedance. However, when
selecting an external synchronous clock; the SOUT1 pin can become the high-impedance state by
setting the SOUT1 pin control bit to “1” when the serial I/O1 clock input is at “H” after transfer completion.
(4) Serial I/O initialization bit
● Set “0” to the serial I/O initialization bit of the serial I/O1 control register 1 when terminating a
serial transfer during transferring.
● When writing “1” to the serial I/O initialization bit, the serial I/O1 is enabled, but each register is
not initialized. Set the value of each register by program.
(5) Handshake signal
■ SBUSY1 input signal
Input an “H” level to the SBUSY1 input and an “L” level signal to the SBUSY1 input in the initial state.
When the external synchronous clock is selected, switch the input level to the S BUSY1 input and
the SBUSY1 input while the serial I/O1 clock input is in “H” state.
■ SRDY1 input•output signal
When selecting the internal synchronous clock, input an “L” level to the SRDY1 input and an “H”
level signal to the SRDY1 input in the initial state.
(6) 8-bit serial I/O mode
■ When selecting external synchronous clock
When an external synchronous clock is selected, the contents of the serial I/O1 register are being
shifted continually while the transfer clock is input to the serial I/O1 clock pin. In this case, control
the clock externally.
38B5 Group User’s Manual
3-15
APPENDIX
3.3 Notes on use
(7) In automatic transfer serial I/O mode
■ Set of automatic transfer interval
● When the SBUSY1 output is used, and the S BUSY1 output and the S STB1 output function as signals
for each transfer data set by the S BUSY1 output•SSTB1 output function selection bit of serial I/O1
control register 2; the transfer interval is inserted before the first data is transmitted/received,
and after the last data is transmitted/received. Accordingly, regardless of the contents of the
SBUSY1 output•SSTB1 output function selection bit, this transfer interval for each 1-byte data becomes
2 cycles longer than the value set by the automatic transfer interval set bits of serial I/O1 control
register 3.
● When using the SSTB1 output, regardless of the contents of the SBUSY1 output•S STB1 output function
selection bit, this transfer interval for each 1-byte data becomes 2 cycles longer than the value
set by the automatic transfer interval set bits of serial I/O1 control register 3.
● When using the combined output of S BUSY1 and SSTB1 as the signal for each of all transfer data
set, the transfer interval after completion of transmission/reception of the last data becomes 2
cycles longer than the value set by the automatic transfer interval set bits.
● Set the transfer interval of each 1-byte data transfer to 5 or more cycles of the internal clock
φ after the rising edge of the last bit of a 1-byte data.
● When selecting an external clock, the set of automatic transfer interval becomes invalid.
■ Set of serial I/O1 transfer counter
● Write the value decreased by 1 from the number of transfer data bytes to the serial I/O1 transfer
counter.
● When selecting an external clock, after writing a value to the serial I/O1 register/transfer counter,
wait for 5 or more cycles of internal clock φ before inputting the transfer clock to the serial I/
O1 clock pin.
■ Serial I/O initialization bit
A serial I/O1 automatic transfer interrupt request occurs when “0” is written to the serial I/O
initialization bit during an operation. Disable it with the interrupt enable bit as necessary by program.
3.3.3 Notes on serial I/O2
(1) Notes when selecting clock synchronous serial I/O
➀ Stop of transmission operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O2 enable bit is cleared to “0” (serial I/O2 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, SCLK21 , S CLK22 and S RDY2 function as I/O ports, the transmission
data is not output). When data is written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O2 enable bit is set to “1” at this time,
the data during internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the receive enable bit to “0” (receive disabled), or clear the serial I/O2 enable bit
to “0” (serial I/O2 disabled).
3-16
38B5 Group User’s Manual
APPENDIX
3.3 Notes on use
➂ Stop of transmit/receive operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, simultaneously clear both the transmit enable bit and receive enable bit to “0” (transmit
and receive disabled).
(when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
● Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.
If any one of transmission and reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,
the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit is not initialized by clearing the serial I/O2 enable bit to
“0” (serial I/O2 disabled) (refer to (1), ➀).
(2) Notes when selecting clock asynchronous serial I/O
➀ Stop of transmission operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O2 enable bit is cleared to “0” (serial I/O2 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, S CLK21, S CLK22 and SRDY2 function as I/O ports, the transmission
data is not output). When data is written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O2 enable bit is set to “1” at this time,
the data during internally shifting is output to the TxD pin and an operation failure occurs.
➁ Stop of receive operation
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the receive enable bit to “0” (receive disabled).
➂ Stop of transmit/receive operation
Only transmission operation is stopped.
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the transmit enable bit to “0” (transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O2 enable bit is cleared to “0” (serial I/O2 disabled), the internal transmission is running
(in this case, since pins TxD, RxD, S CLK21, S CLK22 and SRDY2 function as I/O ports, the transmission
data is not output). When data is written to the transmit buffer register in this state, data starts to
be shifted to the transmit shift register. When the serial I/O2 enable bit is set to “1” at this time,
the data during internally shifting is output to the TxD pin and an operation failure occurs.
Only receive operation is stopped.
As for the serial I/O2 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the receive enable bit to “0” (receive disabled).
(3) S RDY2 output of reception side
When signals are output from the S RDY2 pin on the reception side by using an external clock in the
clock synchronous serial I/O mode, set all of the receive enable bit, the S RDY2 output enable bit, and
the transmit enable bit to “1” (transmit enabled).
38B5 Group User’s Manual
3-17
APPENDIX
3.3 Notes on use
(4) Setting serial I/O2 control register again
Set the serial I/O2 control register again after the transmission and the reception circuits are reset
by clearing both the transmit enable bit and the receive enable bit to “0.”
Clear both the transmit enable
bit (TE) and the receive enable
bit (RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O2 control register
↓
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to “1”
Can be set with the
LDM instruction at
the same time
Fig. 3.3.4 Sequence of setting serial I/O2 control register again
(5) Data transmission control with referring to transmit shift register completion flag
The transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift
clocks. When data transmission is controlled with referring to the flag after writing the data to the
transmit buffer register, note the delay.
(6) Transmission control when external clock is selected
When an external clock is used as the synchronous clock for data transmission, set the transmit
enable bit to “1” at “H” of the serial I/O2 clock input level. Also, write the transmit data to the transmit
buffer register (serial I/O shift register) at “H” of the serial I/O2 clock input level.
(7) Transmit interrupt request when transmit enable bit is set
The transmission interrupt request bit is set and the interruption request is generated even when
selecting timing that either of the following flags is set to “1” as timing where the transmission
interruption is generated.
• Transmit buffer empty flag is set to “1”
• Transmit shift register completion flag is set to “1”
Therefore, when the transmit interrupt is used, set the transmit interrupt enable bit to transmit
enabled as the following sequence.
➀ Transmit enable bit is set to “1”
➁ Transmit interrupt request bit is set to “0”
● Reason
When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift
register completion flag are set to “1”.
(8) Using TxD pin
The P55/TxD P-channel output disable bit of UART control register is valid in both cases: using as
a normal I/O port and as the TxD pin. Do not supply Vcc + 0.3 V or more even when using the P5 5/
TxD pin as an N-channel open-drain output.
Additionally, in the serial I/O2, the TxD pin latches the last bit and continues to output it after
completing transmission.
3-18
38B5 Group User’s Manual
APPENDIX
3.3 Notes on use
3.3.4 Notes on FLD controller
● Set a value of 03 16 or more to the Toff1 time set register.
● When displaying in the gradation display mode, select the 16 timing mode by the timing number control
bit (bit 4 of FLDC mode register (address 0EF4 16) = “0”).
3.3.5 Notes on A-D converter
(1) Analog input pin
■ Make the signal source impedance for analog input low, or equip an analog input pin with an
external capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application
products on the user side.
● Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A-D conversion precision to be worse.
■ When the P64/INT 4/S BUSY1/AN 10 pin is selected as analog input pin, external interrupt function (INT4)
becomes invalid.
(2) A-D converter power source pin
The AV SS pin is A-D converter power source pin. Regardless of using the A-D conversion function
or not, connect it as following :
• AVSS : Connect to the V SS line
● Reason
If the AV SS pin is opened, the microcomputer may have a failure because of noise or others.
(3) Clock frequency during A-D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A-D conversion.
• f(X IN) is 250 kHz or more
• Use clock divided by main clock (f(X IN)) as internal system clock.
• Do not execute the STP instruction and WIT instruction
3.3.6 Notes on PWM
● For PWM 0 output, “L” level is output first.
● After data is set to the PWM register (low-order) and the PWM register (high-order), PWM waveform
corresponding to new data is output from next repetitive cycle.
PWM0 output data
change
Modified data is output from next
repetitive cycle.
Fig. 3.3.5 PWM output
38B5 Group User’s Manual
3-19
APPENDIX
3.3 Notes on use
3.3.7 Notes on watchdog timer
● The watchdog timer continues to count even while waiting for stop release. Accordingly, make sure that
watchdog timer does not underflow during this term by writing to the watchdog timer control register
(address 002B 16) once before executing the STP instruction, etc.
● Once a “1” is written to the STP instruction disable bit (bit 6) of the watchdog timer control register
(address 002B 16 ), it cannot be programmed to “0” again. This bit becomes “0” after reset.
3.3.8 Notes on reset circuit
(1) Reset input voltage control
Make sure that the reset input voltage is 0.5 V or less for Vcc of 2.7 V.
Perform switch to the high-speed mode when power source voltage is within 4.0 to 5.5 V.
(2) Countermeasure when RESET signal rise time is long
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the V SS pin. And use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
● Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
3.3.9 Notes on input and output pins
(1) Notes in stand-by state
In stand-by state* 1 for low-power dissipation, do not make input levels of an input port and an I/O
port “undefined”, especially for I/O ports of the N-channel open-drain.
Pull-up (connect the port to V CC ) or pull-down (connect the port to VSS ) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using built-in pull-up resistor, note on varied current values:
• When setting as an input port : Fix its input level
• When setting as an output port : Prevent current from flowing out to external
● Reason
Even when setting as an output port with its direction register, in the following state :
• P-channel......when the content of the port latch is “0”
• N-channel......when the content of the port latch is “1”
the transistor becomes the OFF state, which causes the ports to be the high-impedance state.
Note that the level becomes “undefined” depending on external circuits.
Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the
state that input levels of a input port and an I/O port are “undefined”. This may cause power
source current.
*1 stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
3-20
38B5 Group User’s Manual
APPENDIX
3.3 Notes on use
(2) N-channel open-drain port
P4 0–P4 2, P45, P46, P60 of N-channel open-drain output ports have built-in hysteresis circuit for input.
In standby state for low-power dissipation, do not make these pins floating state.
● Reason
When power sources for pull-up of these pins are cut off in standby state, these ports become
floating. Accordingly, a current may flow from Vcc to Vss through built-in hysteresis circuit.
(3) Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction*2, the value of the
unspecified bit may be changed.
● Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
• As for a bit which is set for an input port :
The pin state is read in the CPU, and is written to this bit after bit managing.
• As for a bit which is set for an output port :
The bit value of the port latch is read in the CPU, and is written to this bit after bit managing.
Note the following :
• Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
• As for a bit of the port latch which is set for an input port, its value may be changed even when
not specified with a bit managing instruction in case where the pin state differs from its port latch
contents.
*2 bit managing instructions : SEB, and CLB instructions
38B5 Group User’s Manual
3-21
APPENDIX
3.3 Notes on use
3.3.10 Notes on programming
(1) Processor status register
➀ Initializing of processor status register
Flags which affect program execution must be initialized after a reset.
In particular, it is essential to initialize the T and D flags because they have an important effect
on calculations.
● Reason
After a reset, the contents of the processor status register (PS) are undefined except for the I
flag which is “1”.
Reset
↓
Initializing of flags
↓
Main program
Fig. 3.3.6 Initialization of processor status register
➁ How to reference the processor status register
To reference the contents of the processor status register (PS), execute the PHP instruction once
then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its
original status.
A NOP instruction should be executed after every PLP instruction.
PLP instruction execution
↓
NOP
(S)
(S)+1
Fig. 3.3.7 Sequence of PLP instruction execution
3-22
Stored PS
Fig. 3.3.8 Stack memory contents after PHP
instruction execution
38B5 Group User’s Manual
APPENDIX
3.3 Notes on use
(2) Decimal calculations
➀ Execution of decimal calculations
The ADC and SBC are the only instructions which will yield proper decimal notation, set the
decimal mode flag (D) to “1” with the SED instruction. After executing the ADC or SBC instruction,
execute another instruction before executing the SEC, CLC, or CLD instruction.
➁ Notes on status flag in decimal mode
When decimal mode is selected, the values of three of the flags in the status register (the N, V,
and Z flags) are invalid after a ADC or SBC instruction is executed.
The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared
to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C
flag must be initialized to “0” before each calculation. To check for a borrow, the C flag must be
initialized to “1” before each calculation.
Set D flag to “1”
↓
ADC or SBC instruction
↓
NOP instruction
↓
SEC, CLC, or CLD instruction
Fig. 3.3.9 Status flag at decimal calculations
(3) JMP instruction
When using the JMP instruction in indirect addressing mode, do not specify the last address on a
page as an indirect address.
3.3.11 Programming and test of built-in PROM version
As for in the One Time PROM version (shipped in blank) and the built-in EPROM version, their built-in
PROM can be read or programmed with a general-purpose PROM programmer using a special programming
adapter.
The built-in EPROM version is available only for program development and on-chip program evaluation.
The programming test and screening for PROM of the One Time PROM version (shipped in blank) are not
performed in the assembly process and the following processes. To ensure reliability after programming,
performing programming and test according to the Figure 3.3.10 before actual use are recommended.
Programming with PROM programmer
Screening (Caution)
(Leave at 150 °C for 40 hours)
Verification with PROM programmer
Functional check in target device
Caution: The screening temperature is far higher than the
storage temperature. Never expose to 150 °C
exceeding 100 hours.
Fig. 3.3.10 Programming and testing of One Time PROM version
38B5 Group User’s Manual
3-23
APPENDIX
3.3 Notes on use
3.3.12 Notes on built-in PROM version
(1) Programming adapter
Use a special programming adapter shown in Table 3.3.1 and a general-purpose PROM programmer
when reading from or programming to the built-in PROM in the built-in PROM version.
Table 3.3.1 Programming adapter
Microcomputer
M38B59EFFP (One Time PROM version shipped in blank)
M38B59EFFS
Programming adapter
PCA4738F-80A
PCA4738L-80A
(2) Programming/reading
In PROM mode, operation is the same as that of the M5M27C101K, but programming conditions of
PROM programmer are not set automatically because there are no internal device ID codes.
Accurately set the following conditions for data programming/reading. Take care not to apply 21 V
to the VPP pin (is also used as port P4 7), or the product may be permanently damaged.
➀ Programming voltage: 12.5 V
➁ Setting of PROM programmer address: Refer to “Table 3.3.2”
Table 3.3.2 PROM programmer address setting
Microcomputer
PROM programmer start address
M38B59EFFP
Address 1080 16
M38B59EFFS
PROM programmer end address
Address FFFD 16
(3) Erasing
Contents of the windowed EPROM are erased through an ultraviolet light source with the wavelength
2537 Angstrom. At least 15 W•sec/cm 2 are required to erase EPROM contents.
3-24
38B5 Group User’s Manual
APPENDIX
3.3 Notes on use
3.3.13 Termination of unused pins
(1) Terminate unused pins
➀ Output ports : Open
➁ Input ports :
Connect each pin to V SS through each resistor of 1 kΩ to 10 kΩ.
As for pins whose potential affects to operation modes such as pins INT or others, select the VCC
pin or the VSS pin according to their operation mode.
➂ I/O ports :
• Set the I/O ports for the input mode and connect them to V SS through each resistor of 1 kΩ to
10 kΩ.
Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the I/
O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the
mode of the ports is switched over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source current may increase in the input
mode. With regard to an effects on the system, thoroughly perform system evaluation on the user
side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
(2) Termination remarks
➀ Input ports and I/O ports :
Do not open in the input mode.
● Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➁ and
➂ shown on the above.
➁ I/O ports :
When setting for the input mode, do not connect to VCC or VSS directly.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and V CC (or VSS ).
➂ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to VCC or V SS through
a resistor.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
38B5 Group User’s Manual
3-25
APPENDIX
3.4 Countermeasures against noise
3.4 Countermeasures against noise
Countermeasures against noise are described below. The following countermeasures are effective against
noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use.
3.4.1 Shortest wiring length
The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer.
The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer.
(1) Package
Select the smallest possible package to make the total wiring length short.
● Reason
The wiring length depends on a microcomputer package. Use of a small package, for example
QFP and not DIP, makes the total wiring length short to reduce influence of noise.
DIP
SDIP
SOP
QFP
Fig. 3.4.1 Selection of packages
(2) Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin as short as possible. Especially,
connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within
20mm).
● Reason
The width of a pulse input into the RESET pin is determined by the timing necessary conditions.
If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is completely initialized. This may cause
a program runaway.
Noise
Reset
circuit
RESET
VSS
VSS
N.G.
Reset
circuit
VSS
RESET
VSS
O.K.
Fig. 3.4.2 Wiring for the RESET pin
3-26
38B5 Group User’s Manual
APPENDIX
3.4 Countermeasures against noise
(3) Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is
connected to an oscillator and the V SS pin of a microcomputer as short as possible.
• Separate the V SS pattern only for oscillation from other V SS patterns.
● Reason
If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program
failure or program runaway. Also, if a potential difference is caused by the noise between the V SS
level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in
the microcomputer.
Noise
XIN
XOUT
VSS
N.G.
XIN
XOUT
VSS
O.K.
Fig. 3.4.3 Wiring for clock I/O pins
38B5 Group User’s Manual
3-27
APPENDIX
3.4 Countermeasures against noise
(4) Wiring to V PP pin of One Time PROM version and EPROM version
Connect an approximately 5 kΩ resistor to the V PP pin the shortest possible in series. When not
connecting the resistor, make the length of wiring between the VPP pin and the V SS pin the shortest
possible.
Note: Even when a circuit which included an approximately 5 kΩ resistor is used in the Mask ROM
version, the microcomputer operates correctly.
● Reason
The V PP pin of the One Time PROM and the EPROM version is the power source input pin for
the built-in PROM. When programming in the built-in PROM, the impedance of the V PP pin is low
to allow the electric current for writing flow into the PROM. Because of this, noise can enter easily.
If noise enters the V PP pin, abnormal instruction codes or data are read from the built-in PROM,
which may cause a program runaway.
Approximately
5 kΩ
P47/VPP
RESET
Fig. 3.4.4 Wiring for the VPP pin of the One Time PROM and the EPROM version
3.4.2 Connection of bypass capacitor across VSS line and V CC line
Connect an approximately 0.1 µF bypass capacitor across the V SS line and the V CC line as follows:
• Connect a bypass capacitor across the V SS pin and the V CC pin at equal length.
• Connect a bypass capacitor across the VSS pin and the V CC pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for V SS line and V CC line.
• Connect the power source wiring via a bypass capacitor to the V SS pin and the V CC pin.
AA
AA
AA
AA
AA
VCC
VSS
N.G.
AA
AA
AA
AA
AA
VCC
VSS
O.K.
Fig. 3.4.5 Bypass capacitor across the V SS line and the V CC line
3-28
38B5 Group User’s Manual
APPENDIX
3.4 Countermeasures against noise
3.4.3 Wiring to analog input pins
• Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog
input pin in series. Besides, connect the resistor to the microcomputer as close as possible.
• Connect an approximately 1000 pF capacitor across the V SS pin and the analog input pin. Besides,
connect the capacitor to the V SS pin as close as possible. Also, connect the capacitor across the analog
input pin and the V SS pin at equal length.
● Reason
Signals which is input in an analog input pin (such as an A-D converter/comparator input pin) are
usually output signals from sensor. The sensor which detects a change of event is installed far
from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer
necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer,
which causes noise to an analog input pin.
If a capacitor between an analog input pin and the V SS pin is grounded at a position far away from
the VSS pin, noise on the GND line may enter a microcomputer through the capacitor.
Noise
(Note)
Microcomputer
Analog
input pin
Thermistor
N.G.
O.K.
VSS
Note : The resistor is used for dividing
resistance with a thermistor.
Fig. 3.4.6 Analog signal line and a resistor and a capacitor
3.4.4 Oscillator concerns
Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected
by other signals.
(1) Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a
current larger than the tolerance of current value flows.
● Reason
In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and
thermal heads or others. When a large current flows through those signal lines, strong noise
occurs because of mutual inductance.
Microcomputer
Mutual inductance
M
XIN
XOUT
VSS
Large
current
GND
Fig. 3.4.7 Wiring for a large current signal line
38B5 Group User’s Manual
3-29
APPENDIX
3.4 Countermeasures against noise
(2) Installing oscillator away from signal lines where potential levels change frequently
Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential
levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines
which are sensitive to noise.
● Reason
Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect
other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms
may be deformed, which causes a microcomputer failure or a program runaway.
N.G.
Do not cross
CNTR
XIN
XOUT
VSS
Fig. 3.4.8 Wiring of signal lines where potential levels change frequently
(3) Oscillator protection using V SS pattern
As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the
position (on the component side) where an oscillator is mounted.
Connect the V SS pattern to the microcomputer V SS pin with the shortest possible wiring. Besides,
separate this V SS pattern from other V SS patterns.
An example of VSS patterns on the
underside of a printed circuit board
Oscillator wiring
pattern example
XIN
XOUT
VSS
Separate the VSS line for oscillation from other VSS lines
Fig. 3.4.9 VSS pattern on the underside of an oscillator
3-30
38B5 Group User’s Manual
APPENDIX
3.4 Countermeasures against noise
3.4.5 Setup for I/O ports
Setup I/O ports using hardware and software as follows:
<Hardware>
• Connect a resistor of 100 Ω or more to an I/O port in series.
<Software>
• As for an input port, read data several times by a program for checking whether input levels are
equal or not.
• As for an output port, since the output data may reverse because of noise, rewrite data to its port
latch at fixed periods.
• Rewrite data to direction registers and pull-up control registers at fixed periods.
Note: When a direction register is set for input port again at fixed periods, a several-nanosecond short pulse
may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise
pulse.
O.K.
Noise
Data bus
Noise
Direction register
N.G.
Port latch
I/O port
pins
Fig. 3.4.10 Setup for I/O ports
38B5 Group User’s Manual
3-31
APPENDIX
3.4 Countermeasures against noise
3.4.6 Providing of watchdog timer function by software
If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer
and the microcomputer can be reset to normal operation. This is equal to or more effective than program
runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer
provided by software.
In the following example, to reset a microcomputer to normal operation, the main routine detects errors of
the interrupt processing routine and the interrupt processing routine detects errors of the main routine.
This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
<The main routine>
• Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value
N in the SWDT once at each execution of the main routine. The initial value N should satisfy the
following condition:
N+1 ≥ ( Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others,
the initial value N should have a margin.
• Watches the operation of the interrupt processing routine by comparing the SWDT contents with
counts of interrupt processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and determines to branch to the program
initialization routine for recovery processing in the following case:
If the SWDT contents do not change after interrupt processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt processing.
• Determines that the main routine operates normally when the SWDT contents are reset to the
initial value N at almost fixed cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch to the program initialization
routine for recovery processing in the following case:
If the SWDT contents are not initialized to the initial value N but continued to decrement and if
they reach 0 or less.
≠N
Main routine
Interrupt processing routine
(SWDT)← N
(SWDT) ← (SWDT)—1
CLI
Interrupt processing
Main processing
(SWDT)
≤0?
(SWDT)
=N?
N
Interrupt processing
routine errors
>0
RTI
≤0
Return
Main routine
errors
Fig. 3.4.11 Watchdog timer by software
3-32
38B5 Group User’s Manual
APPENDIX
3.5 Control registers
3.5 Control registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (i = 0, 1, 2, 3, 4, 5, 7, 8)
(Pi: addresses 0016, 0216, 0416, 0616, 0816, 0A16, 0E16, 1016)
b
0
1
2
3
4
5
6
7
Name
Port Pi0
Port Pi1
Port Pi2
Port Pi3
Port Pi4
Port Pi5
Port Pi6
Port Pi7
Functions
●In output mode
Write •••••••• Port latch
Read •••••••• Port latch
●In input mode
Write •••••••• Port latch
Read •••••••• Value of pin
At reset R W
0
0
0
0
0
0
0
0
Fig. 3.5.1 Structure of port Pi
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (i = 0, 2, 4, 5, 7, 8)
(PiD: addresses 0116, 0516, 0916, 0B16, 0F16, 1116)
b
Name
0 Port Pi direction
register
1
2
3
4
5
6
7
Functions
0 : Port Pi0 input mode
1 : Port Pi0 output mode
0 : Port Pi1 input mode
1 : Port Pi1 output mode
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0 : Port Pi3 input mode
1 : Port Pi3 output mode
0 : Port Pi4 input mode
1 : Port Pi4 output mode
0 : Port Pi5 input mode
1 : Port Pi5 output mode
0 : Port Pi6 input mode
1 : Port Pi6 output mode
0 : Port Pi7 input mode
1 : Port Pi7 output mode
(Note)
At reset R W
0
0
0
0
0
0
0
0
Note: Bit 7 of the port P4 direction register (address 0916) does not have
direction register function because P47 is input port. When writing to bit 7
of the port P4 direction register, write “0” to the bit.
Fig. 3.5.2 Structure of port Pi direction register
38B5 Group User’s Manual
3-33
APPENDIX
3.5 Control registers
Port P6
b7 b6 b5 b4 b3 b2 b1 b0
Port P6
(P6: address 0C16)
b
0
1
2
3
4
5
6
7
Name
Functions
Port P60
●In output mode
Port P61
Write •••••••• Port latch
Port P62
Read •••••••• Port latch
●In input mode
Port P63
Write •••••••• Port latch
Port P64
Read •••••••• Value of pin
Port P65
Nothing is arranged for these bits. When these
bits are read out, the contents are undefined.
At reset R W
0
0
0
0
0
0
0
0
✕ ✕
✕ ✕
Fig. 3.5.3 Structure of port P6
Port P6 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P6 direction register
(P6D: address 0D16)
b
Name
Functions
0 Port P6 direction
register
1
0
2
0
3
4
5
6
7
0 : Port P60 input mode
1 : Port P60 output mode
0 : Port P61 input mode
1 : Port P61 output mode
0 : Port P62 input mode
1 : Port P62 output mode
0 : Port P63 input mode
1 : Port P63 output mode
0 : Port P64 input mode
1 : Port P64 output mode
0 : Port P65 input mode
1 : Port P65 output mode
Nothing is arranged for these bits. When these
bits are read out, the contents are undefined.
Fig. 3.5.4 Structure of port P6 direction register
3-34
At reset R W
38B5 Group User’s Manual
0
0
0
0
0
0
✕ ✕
✕ ✕
APPENDIX
3.5 Control registers
Port P9
b7 b6 b5 b4 b3 b2 b1 b0
Port P9
(P9: address 1216)
b
Name
0 Port P90
1 Port P91
Functions
●In output mode
Write •••••••• Port latch
Read •••••••• Port latch
●In input mode
Write •••••••• Port latch
Read •••••••• Value of pin
2 Nothing is arranged for these bits. When these
3 bits are read out, the contents are undefined.
4
5
6
7
At reset R W
0
0
0
0
0
0
0
0
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
Fig. 3.5.5 Structure of port P9
Port P9 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P9 direction register
(P9D: address 1316)
b
Name
Functions
0 Port P9 direction
register
1
0 : Port P90 input mode
1 : Port P90 output mode
0 : Port P91 input mode
1 : Port P91 output mode
2 Nothing is arranged for these bits. When these
3 bits are read out, the contents are undefined.
4
5
6
7
At reset R W
0
0
0
0
0
0
0
0
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
Fig. 3.5.6 Structure of port P9 direction register
38B5 Group User’s Manual
3-35
APPENDIX
3.5 Control registers
PWM register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
PWM register (high-order)
(PWMH: address 1416)
b
Functions
At reset R W
0 • High-order 8 bits of PWM0 output data is set.
• The values set in this register is transferred to
1
the PWM latch each sub-period cycle (64 µs).
(At f(XIN) = 4 MHz)
2
• When this register is read out, the value of the
3
PWM register (high-order) is read out.
Undefined
4
Undefined
5
Undefined
6
Undefined
7
Undefined
Undefined
Undefined
Undefined
Fig. 3.5.7 Structure of PWM register (high-order)
PWM register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
PWM register (low-order)
(PWML: address 1516)
b
Functions
0 • Low-order 6 bits of PWM0 output data is set.
• The values set in this register is transferred to
1
the PWM latch at each PWM cycle period
(4096 µs).
2
(At f(XIN) = 4 MHz)
3 • When this register is read out, the value of the
PWM latch (low-order 6 bits) is read out.
4
Undefined
5
Undefined
6 Nothing is arranged for this bit. This bit is a
write disabled bit. When this bit is read out, the
contents are “0”.
7 • This bit indicates whether the transfer to the
PWM latch is completed.
0: Transfer is completed
1: Transfer is not completed
• This bit is set to “1” at writing.
Fig. 3.5.8 Structure of PWM register (low-order)
3-36
At reset R W
38B5 Group User’s Manual
Undefined
Undefined
Undefined
Undefined
Undefined
✕
Undefined
✕
APPENDIX
3.5 Control registers
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator
(BRG: address 1616)
b
Functions
At reset R W
0 • Bit rate of the serial transfer is determined.
• This is the 8-bit counter and has the reload
1
register.
The count source is divided by n+1 owing to
2
specifying a value n.
3
Undefined
4
Undefined
5
Undefined
6
Undefined
7
Undefined
Undefined
Undefined
Undefined
Fig. 3.5.9 Structure of baud rate generator
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register
(UARTCON: address 1716)
b
Name
0 Character length
selection bit (CHAS)
1 Parity enable bit
(PARE)
2 Parity selection bit
(PARS)
3 Stop bit length
selection bit (STPS)
4 P55/TxD P-channel
output disable bit
(POFF)
Functions
At reset R W
0: 8 bits
1: 7 bits
0: Parity checking disabled
1: Parity checking enabled
0: Even parity
1: Odd parity
0: 1 stop bit
1: 2 stop bits
0
0: CMOS output (in output
mode)
1: N-channel open-drain
output (in output mode)
0
0
0
0
5 BRG clock switch bit 0: XIN or XCIN/2 (depending
on internal system clock)
1: XCIN
6 Serial I/O2 clock
0: SCLK21 (P57/SCLK22 pin is
used as I/O port or SRDY2
I/O pin selection bit
output pin.)
1: SCLK22 (P56/SCLK21 pin is
used as I/O port.)
0
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “1”.
1
0
Fig. 3.5.10 Structure of UART control register
38B5 Group User’s Manual
3-37
APPENDIX
3.5 Control registers
Serial I/O1 automatic transfer data pointer
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 automatic transfer data pointer
(SIO1DP: address 1816)
b
Functions
0 • Indicates the low-order 8 bits of the address
1 storing the start data on the serial I/O.
2 automatic transfer RAM.
3 • Data is written into the latch and read from the
4 decrement counter.
5
6
7
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Fig. 3.5.11 Structure of serial I/O1 automatic transfer data pointer
Serial I/O1 control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 1
(SIO1CON1•SC11: address 1916)
b
Name
0 Serial transfer
selection bits
1
2 Serial I/O1
synchronous clock
selection bits
(P65/SSTB1 pin
control bits)
3
Functions
b1b0
0 0: Serial I/O disabled
(Pins P62, P64, P65,
P50–P53 pins are I/O
ports.)
0 1: 8-bit serial I/O
1 0: Not available
1 1: Automatic transfer
serial I/O (8 bits)
b3b2
0 0: Internal synchronous
clock (P65 pin is I/O
port.)
0 1: External synchronous
clock (P65 pin is I/O
port.)
1 0: Internal synchronous
clock (P65 pin is
SSTB1 output.)
1 1: Internal synchronous
clock (P65 pin is
SSTB1 output.)
0
0
0
0
4 Serial I/O
initialization bit
5 Transfer mode
selection bit
0: Serial I/O initialization
1: Serial I/O enabled
0: Full-duplex
(transmit/receive) mode
(P50 pin is SIN1 input.)
1: Transmit-only mode
(P50 pin is I/O port.)
0
6 Transfer direction
selection bit
0: LSB first
1: MSB first
0
7 Serial I/O1 clock pin 0: SCLK11 (P53/SCLK12 pin
selection bit
is I/O port.)
1: SCLK12 (P52/SCLK11 pin
is I/O port.)
Fig. 3.5.12 Structure of serial I/O1 control register 1
3-38
At reset R W
38B5 Group User’s Manual
0
0
APPENDIX
3.5 Control registers
Serial I/O1 control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 2
(SIO1CON2 • SC12: address 1A16)
b
Name
Functions
0 P62/SRDY1 •
P64/SBUSY1 pin
control bits
At reset R W
0
b3b2b1b0
1
2
3
4
5
0 0 0 0: P62, P64 pins are I/O ports.
0 0 0 1: Not used
0 0 1 0: P62 pin is SRDY1 output; P64 pin is
I/O port.
0 0 1 1: P62 pin is SRDY1 output; P64 pin is
I/O port.
0 1 0 0: P62 pin is I/O port; P64 pin is
SBUSY1 input.
0 1 0 1: P62 pin is I/O port; P64 pin is
SBUSY1 input.
0 1 1 0: P62 pin is I/O port; P64 pin is
SBUSY1 output.
0 1 1 1: P62 pin is I/O port; P64 pin is
SBUSY1 output.
1 0 0 0: P62 pin is SRDY1 input; P64 pin is
SBUSY1 output.
1 0 0 1: P62 pin is SRDY1 input; P64 pin is
SBUSY1 output.
1 0 1 0: P62 pin is SRDY1 input; P64 pin is
SBUSY1 output.
1 0 1 1: P62 pin is SRDY1 input; P64 pin is
SBUSY1 output.
1 1 0 0: P62 pin is SRDY1 output; P64 pin is
SBUSY1 input.
1 1 0 1: P62 pin is SRDY1 output; P64 pin is
SBUSY1 input.
1 1 1 0: P62 pin is SRDY1 output; P64 pin is
SBUSY1 input.
1 1 1 1: P62 pin is SRDY1 output; P64 pin is
SBUSY1 input.
SBUSY1 output •
0: Functions as signal for
SSTB1 output
each 1-byte
function selection bit 1: Functions as signal for
(Valid in serial I/O1
each transfer data set
automatic transfer
mode)
Serial transfer
0: Serial transfer
status flag
completed
1: Serial transfer inprogress
0
0
0
0
0
6 SOUT1 pin control
0: Output active
bit (when serial data 1: Output high-impedance
is not transferred)
0
7 P51/SOUT1 P-channel 0: CMOS 3 state (Poutput disable bit
channel output is valid.)
1: N-channel open-drain
output (P-channel output
is invalid.)
0
Fig. 3.5.13 Structure of serial I/O1 control register 2
38B5 Group User’s Manual
3-39
APPENDIX
3.5 Control registers
Serial I/O1 register/Transfer counter
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 register/Transfer counter
(SIO1: address 1B16)
b
Name
Functions
At reset R W
•At function as serial I/O1
Undefined
0 •In 8-bit serial I/O
register:
mode:
This register becomes the
Serial I/O1 register
shift register to perform
1
Undefined
serial transmit/reception.
•In automatic transfer
Set transmit data to this
serial I/O mode:
register.
2 Transfer counter
Undefined
The serial transfer is started
by writing the transmit data.
3
4
5
6
7
•At function as transfer
counter:
Set (transfer byte number –
1) to this register.
When selecting an internal
clock, the automatic
transfer is started by writing
the transmit data.
(When selecting an external
clock, after writing a value
to this register, wait for 5 or
more cycles of the internal
system clock before
inputting the transfer clock
to the SCLK1 pin.)
Fig. 3.5.14 Structure of serial I/O1 register/Transfer counter
3-40
38B5 Group User’s Manual
Undefined
Undefined
Undefined
Undefined
Undefined
APPENDIX
3.5 Control registers
Serial I/O1 control register 3
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register 3
(SIO1CON3 • SC13: address 1C16)
b
Name
Functions
b4b3b2b1b0
0 Automatic transfer 0 0 0 0 0: 2 cycles of
interval set bits
transfer clock
(valid only when
0 0 0 0 1: 3 cycles of
1 selecting internal
transfer clock
synchronous clock)
to
1 1 1 1 0: 32 cycles of
2
transfer clock
1 1 1 1 1: 33 cycles of
3
transfer clock
4
5 Internal
synchronous clock
selection bits
6
7
At reset R W
0
0
0
0
Data is written into the
latch and read from the
decrement counter.
0
b7b6b5
0
0 0 0 : f(XIN)/4 or f(XCIN)/8
0 0 1 : f(XIN)/8 or
f(XCIN)/16
0 1 0 : f(XIN)/16 or
f(XCIN)/32
0 1 1 : f(XIN)/32 or
f(XCIN)/64
1 0 0 : f(XIN)/64 or
f(XCIN)/128
1 0 1 : f(XIN)/128 or
f(XCIN)/256
1 1 0 : f(XIN)/256 or
f(XCIN)/512
1 1 1 : Not used
0
0
Fig. 3.5.15 Structure of serial I/O1 control register 3
38B5 Group User’s Manual
3-41
APPENDIX
3.5 Control registers
Serial I/O2 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register
(SIO2CON: address 1D16)
b
Name
Functions
0: f(XIN) or f(XCIN)/2 or
f(XCIN)
1: f(XIN)/4 or f(XCIN)/8 or
f(XCIN)/4
0
1 Serial I/O2
synchronous clock
selection bit
(SCS)
•In clock synchronous
mode
0: BRG output/4
1: External clock input
•In UART mode
0: BRG output/16
1: External clock input/16
0
2 SRDY2 output
enable bit (SRDY)
0: P57 pin operates as
normal I/O pin
1: P57 pin operates as
SRDY2 output pin
0
0: When transmit buffer
3 Transmit interrupt
source selection bit
has emptied
(TIC)
1: When transmit shift
operation is completed
0
4 Transmit enable bit
(TE)
5 Receive enable bit
(RE)
6 Serial I/O2 mode
selection bit (SIOM)
0: Transmit disabled
1: Transmit enabled
0: Receive disabled
1: Receive enabled
0: Clock asynchronous
serial I/O (UART) mode
1: Clock synchronous
serial I/O mode
0
7 Serial I/O2 enable
bit (SIOE)
0: Serial I/O2 disabled
(pins P54–P57 operate
as normal I/O pins)
1: Serial I/O2 enabled
(pins P54–P57 operate
as serial I/O pins)
0
Fig. 3.5.16 Structure of serial I/O2 control register
3-42
At reset R W
0 BRG count source
selection bit (CSS)
38B5 Group User’s Manual
0
0
APPENDIX
3.5 Control registers
Serial I/O2 status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 status register
(SIO2STS: address 1E16)
b
Name
0 Transmit buffer
empty flag (TBE)
1 Receive buffer full
flag (RBF)
2 Transmit shift
register shift
completion flag
(TSC)
Functions
0: Buffer full
1: Buffer empty
0: Buffer empty
1: Buffer full
0: Transmit shift in progress
1: Transmit shift completed
3 Overrun error flag
(OE)
4 Parity error flag
(PE)
0: No error
1: Overrun error
0: No error
1: Parity error
5 Framing error flag 0: No error
1: Framing error
(FE)
6 Summing error flag 0: (OE) U (PE) U (FE) = 0
(SE)
1: (OE) U (PE) U (FE) = 1
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “1”.
At reset R W
0
0
0
0
0
0
0
1
Fig. 3.5.17 Structure of serial I/O2 status register
Serial I/O2 transmit/receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 transmit/receive buffer register
(TB/RB: address 1F16)
b
Functions
0 This is the buffer register which is used to write
transmit data or to read receive data.
1
• At write : The value is written to the transmit
buffer register. The value cannot be
2
written to the receive buffer register.
3 • At read : The contents of the receive buffer
register is read out. When a
4
character bit length is 7 bits, the
5
MSB of data stored in the receive
buffer is “0”. The contents of the
6
transmit buffer register cannot be
7
read out.
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Fig. 3.5.18 Structure of serial I/O2 transmit/receive buffer register
38B5 Group User’s Manual
3-43
APPENDIX
3.5 Control registers
Timer i
b7 b6 b5 b4 b3 b2 b1 b0
Timer i (i = 1, 3, 4, 5, 6)
(Ti: addresses 2016, 2216, 2316, 2416, 2516)
b
Functions
At reset R W
0 • Set timer i count value.
1 • The value set in this register is written to both
2 the timer i and the timer i latch at one time.
3 • When the timer i is read out, the count value
4 of the timer i is read out.
5
6
7
1
1
1
1
1
1
1
1
Fig. 3.5.19 Structure of timer i
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2
(T2: address 2116)
b
Functions
At reset R W
0 • Set timer 2 count value.
1 • The value set in this register is written to both
2 the timer 2 and the timer 2 latch at one time.
3 • When the timer 2 is read out, the count value
4 of the timer 2 is read out.
5
6
7
1
0
0
0
0
0
0
0
Fig. 3.5.20 Structure of timer 2
PWM control register
b7 b6 b5 b4 b3 b2 b1 b0
PWM control register
(PWMCON: address 2616)
b
Name
Functions
0: I/O port
0 P87/PWM output
selection bit
1: PWM output
1 Nothing is arranged for these bits. These are
2 write disabled bits. When these bits are read out,
3 the contents are “0”.
4
5
6
7
Fig. 3.5.21 Structure of PWM control register
3-44
38B5 Group User’s Manual
At reset R W
0
0
0
0
0
0
0
0
APPENDIX
3.5 Control registers
Timer 6 PWM register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 6 PWM register
(T6PWM: address 2716)
b
0
1
2
3
4
5
6
Functions
• In timer 6 PWM1 mode
“L” level width of PWM rectangular waveform is set.
• Duty of PWM rectangular waveform: n/(n + m)
Period: (n + m) × ts
n = timer 6 set value
m = timer 6 PWM register set value
ts = timer 6 count source period
At n = 0, all PWM output “L”.
At m = 0, all PWM output “H”.
(However, n = 0 has priority.)
• Selection of timer 6 PWM1 mode
Set “1” to the timer 6 operation mode selection bit.
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
7
Fig. 3.5.22 Structure of timer 6 PWM register
Timer 12 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 12 mode register
(T12M: address 2816)
b
Name
0
Timer 1 count stop
bit
Timer 2 count stop
bit
Timer 1 count
source selection
bits
1
2
3
4 Timer 2 count
source selection
bits
5
Functions
At reset R W
0: Count operation
1: Count stop
0: Count operation
1: Count stop
0
b3 b2
0
b5 b4
0
0 0: f(XIN)/8 or f(XCIN)/16
0 1: f(XCIN)
1 0: f(XIN)/16 or f(XCIN)/32
1 1: f(XIN)/64 or f(XCIN)/128
0 0: Timer 1 underflow
0 1: f(XCIN)
1 0: External count input
CNTR0
1 1: Not available
0: I/O port
6 Timer 1 output
selection bit (P45) 1: Timer 1 output
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
0
0
0
Fig. 3.5.23 Structure of timer 12 mode register
38B5 Group User’s Manual
3-45
APPENDIX
3.5 Control registers
Timer 34 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 34 mode register
(T34M: address 2916)
b
Name
0 Timer 3 count stop
bit
1 Timer 4 count stop
bit
2 Timer 3 count
source selection
3 bits
4 Timer 4 count
source selection
bits
5
Functions
At reset R W
0: Count operation
1: Count stop
0: Count operation
1: Count stop
0
b3 b2
0
b5 b4
0
0 0: f(XIN)/8 or f(XCIN)/16
0 1: Timer 2 underflow
1 0: f(XIN)/16 or f(XCIN)/32
1 1: f(XIN)/64 or f(XCIN)/128
0 0: f(XIN)/8 or f(XCIN)/16
0 1: Timer 3 underflow
1 0: External count input
CNTR1 (Note)
1 1: Not available
0: I/O port
6 Timer 3 output
selection bit (P46) 1: Timer 3 output
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
0
0
0
Note: In the mask option type P, CNTR1 function cannot be used.
Fig. 3.5.24 Structure of timer 34 mode register
Timer 56 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 56 mode register
(T56M: address 2A16)
b
Name
0 Timer 5 count stop
bit
1 Timer 6 count stop
bit
2 Timer 5 count
source selection bit
3 Timer 6 operation
mode selection bit
4 Timer 6 count
source selection
5 bits
Functions
0: Count operation
1: Count stop
0: Count operation
1: Count stop
0: f(XIN)/8 or f(XCIN)/16
1: Timer 4 underflow
0: Timer mode
1: PWM mode
b5 b4
0 0: f(XIN)/8 or f(XCIN)/16
0 1: Timer 5 underflow
1 0: Timer 4 underflow
1 1: Not available
0: I/O port
1: Timer 6 output
6 Timer 6 (PWM)
output selection bit
(P44)
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
Fig. 3.5.25 Structure of timer 56 mode register
3-46
38B5 Group User’s Manual
At reset R W
0
0
0
0
0
0
0
0
APPENDIX
3.5 Control registers
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Watchdog timer control register
(WDTCON: address 2B16)
b
Name
Functions
0 Watchdog timer H
1 (high-order 6 bits of reading exclusive)
2
3
4
5
6 STP instruction
0: STP instruction enabled
disable bit
1: STP instruction disabled
7 Watchdog timer H
0: Watchdog timer L
count source
underflow
selection bit
1: f(XIN)/16 or f(XCIN)/16
At reset R W
1
1
1
1
1
1
0
0
Fig. 3.5.26 Structure of watchdog timer control register
Timer X (low-order, high-order)
b7 b6 b5 b4 b3 b2 b1 b0
Timer X (low-order, high-order)
(TXL, TXH: addresses 2C16, 2D16)
b
Functions
0 • Set timer X count value.
1 • When the timer X write control bit of the timer
X mode register 1 is “0”, the value is written to
2
timer X and the latch at one time.
3
When the timer X write control bit of the timer
X mode register 1 is “1”, the value is written
4
only to the latch.
5
• The timer X count value is read out by reading
6
this register.
7
At reset R W
1
1
1
1
1
1
1
1
Notes 1: When reading and writing, perform them to both the highorder and low-order bytes.
2: Read both registers in order of TXH and TXL following.
3: Write both registers in order of TXL and TXH following.
4: Do not read both registers during a write, and do not write to
both registers during a read.
Fig. 3.5.27 Structure of timer X (low-order, high-order)
38B5 Group User’s Manual
3-47
APPENDIX
3.5 Control registers
Timer X mode register 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register 1
(TXM1: address 2E16)
b
Name
0 Timer X write
control bit
Functions
0 : Write value in latch and
counter
1 : Write value in latch only
0
b2 b1
1 Timer X count
0 0: f(XIN)/2 or f(XCIN)/4
source selection bits 0 1: f(XIN)/8 or f(XCIN)/16
1 0: f(XIN)/64 or f(XCIN)/128
2
1 1: Not available
3 Nothing is arranged for this bit. This is write
disabled bit. When this bit is read out, the
contents are “0”.
0
4 Timer X operating
mode bits
5
b5 b4
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width
measurement mode
6 CNTR2 active edge 0 : •Count at rising edge in
event counter mode
switch bit
•Start from “H” output in
pulse output mode
•Measure “H” pulse
width in pulse width
measurement mode
1 : •Count at falling edge in
event counter mode
•Start from “L” output in
pulse output mode
•Measure “L” pulse
width in pulse width
measurement mode
7 Timer X stop
control bit
0 : Count operating
1 : Count stop
Fig. 3.5.28 Structure of timer X mode register 1
3-48
At reset R W
38B5 Group User’s Manual
0
0
0
0
0
0
APPENDIX
3.5 Control registers
Timer X mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register 2
(TXM2: address 2F16)
b
Name
Functions
0 Real time port control
bit (P85)
1 Real time port control
bit (P86)
2 P85 data for real time
port
3 P86 data for real time
port
At reset R W
0: Real time port function is
invalid
1: Real time port function is
valid
0
0: Real time port function is
invalid
1: Real time port function is
valid
0
0: “L” output
1: “H” output
0
0: “L” output
1: “H” output
0
4 Nothing is arranged for these bits. These are
5 write disabled bits. When these bits are read
6 out, the contents are “0”.
7
0
0
0
0
0
Fig. 3.5.29 Structure of timer X mode register 2
Interrupt interval determination register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt interval determination register
(IID: address 3016)
b
Functions
0 • This register stores a value which is obtained
by counting a following interval with the
1
counter sampling clock.
2
Rising interval
3
Falling interval
Both edges interval (Note)
4
(Selected by interrupt edge selection register)
5
• Read exclusive register
6
7
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Note: When the noise filter sampling clock selection bits (bits 2, 3) of
the interrupt interval determination control register is “00”, the
both-sided edge detection function cannot be used.
Fig. 3.5.30 Structure of interrupt interval determination register
38B5 Group User’s Manual
3-49
APPENDIX
3.5 Control registers
Interrupt interval determination control register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt interval determination control register
(IIDCON: address 3116)
b
Name
Functions
At reset R W
0: Stopped
0 Interrupt interval
determination circuit 1: Operating
operating selection
bit
0
1 Counter sampling
clock selection bit
2 Noise filter
sampling clock
3 selection bits (INT2)
0: f(XIN)/128
1: f(XIN)/256
0
b3 b2
0
4 One-sided/bothsided edge
detection selection
bit
0 0: Filter is not used.
0 1: f(XIN)/32
1 0: f(XIN)/64
1 1: f(XIN)/128
0: One-sided edge
detection
1: Both-sided edge
detection (Note)
5 Nothing is arranged for these bits. These are
6 write disabled bits. When these bits are read
7 out, the contents are “0”.
0
0
0
0
0
Note: When the noise filter sampling clock selection bits (bits 2, 3) is
“00”, the both-sided edge detection function cannot be used.
Fig. 3.5.31 Structure of interrupt interval determination control register
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0
A-D control register
(ADCON: address 3216)
b
Name
0 Analog input pin
selection bits
1
2
3
Functions
b3 b2 b1 b0
0 0 0 0: P70/AN0
0 0 0 1: P71/AN1
0 0 1 0: P72/AN2
0 0 1 1: P73/AN3
0 1 0 0: P74/AN4
0 1 0 1: P75/AN5
0 1 1 0: P76/AN6
0 1 1 1: P77/AN7
1 0 0 0: P62/SRDY1/AN8
1 0 0 1: P63/AN9
1 0 1 0: P64/INT4/SBUSY1/AN10
1 0 1 1: P65/SSTB1/AN11
4 AD conversion
0: Conversion in progress
1: Conversion completed
completion bit
5 Nothing is arranged for these bits. These are
6 write disabled bits. When these bits are read
7 out, the contents are “0”.
Fig. 3.5.32 Structure of A-D control register
3-50
38B5 Group User’s Manual
At reset R W
0
0
0
0
1
0
0
0
APPENDIX
3.5 Control registers
A-D conversion register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (low-order)
(ADL: address 3316)
b
0
1
2
3
4
5
6
7
Functions
Nothing is arranged for these bits. These are write
disabled bits. When these bits are read out, the
contents are “0”.
These are A-D conversion result (low-order 2 bits)
stored bits. This is read exclusive register.
At reset R W
Undefined
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Note: Do not read this register during A-D conversion.
Fig. 3.5.33 Structure of A-D conversion register (low-order)
A-D conversion register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion register (high-order)
(ADH: address 3416)
b
Functions
0 This is A-D conversion result (high-order 8 bits) stored
1 bits. This is read exclusive register.
2
3
4
5
6
7
At reset R W
Undefined
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Undefined
0
Note: Do not read this register during A-D conversion.
Fig. 3.5.34 Structure of A-D conversion register (high-order)
38B5 Group User’s Manual
3-51
APPENDIX
3.5 Control registers
Interrupt source switch register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt source switch register
(IFR: address 3916)
b
Name
Functions
0 INT3/serial I/O2
transmit interrupt
switch bit (Note)
0: INT3 intrrupt
1: Serial I/O2 transmit
interrupt
0: INT4 interrupt
1 INT4/A-D
conversion interrupt 1: A-D conversion intrerrupt
switch bit
At reset R W
0
0
0
2 Nothing is arranged for these bits. These are
0
3 write disabled bits. When these bits are read
4 out, the contents are “0”.
0
5
0
6
0
0
7
Note: In the mask option type P, this bit is not available because INT3
function cannot be used.
Fig. 3.5.35 Structure of interrupt source switch register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register
(INTEDGE : address 3A16)
b
Name
Functions
At reset R W
0
0 INT0 interrupt edge 0 : Falling edge active
selection bit
1 : Rising edge active
0
1 INT1 interrupt edge 0 : Falling edge active
selection bit
1 : Rising edge active
0
2 INT2 interrupt edge 0 : Falling edge active
1 : Rising edge active
selection bit
0
3 INT3 interrupt edge 0 : Falling edge active
selection bit (Note) 1 : Rising edge active
0
4 INT4 interrupt edge 0 : Falling edge active
1 : Rising edge active
selection bit
0
5 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
0 : Rising edge count
6 CNTR0 pin edge
switch bit
1 : Falling edge count
0
0 : Rising edge count
7 CNTR1 pin edge
1 : Falling edge count
switch bit (Note)
Note: In the mask option type P, these bits are not available because
CNTR1 function and INT3 function cannot be used.
Fig. 3.5.36 Structure of interrupt edge selection register
3-52
38B5 Group User’s Manual
APPENDIX
3.5 Control registers
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register
(CPUM, CM: address 3B16)
b
Name
0 Processor mode
bits
1
2 Stack page
selection bit
3 XCOUT drivability
selection bit
4 Port Xc switch bit
5 Main clock (XINXOUT) stop bit
6 Main clock division
ratio selection bit
7 Internal system
clock selection bit
Functions
b1 b0
At reset R W
00 : Single-chip mode
01 :
10 :
Not available
11 :
0 : Page 0
1 : Page 1
0: Low drive
1: High drive
0
0: I/O port function
1: XCIN-XCOUT oscillation
function
0: Oscillating
1: Stopped
0
0: f(XIN) (high-speed mode)
1: f(XIN)/4 (middle-speed
mode)
0: XIN–XOUT selection
(middle-/high-speed
mode)
1: XCIN–XCOUT selection
(low-speed mode)
1
0
0
1
0
0
Fig. 3.5.37 Structure of CPU mode register
38B5 Group User’s Manual
3-53
APPENDIX
3.5 Control registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 3C16)
b
Name
Functions
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
1 INT1 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
2 INT2 interrupt
0 : No interrupt request
request bit
issued
Remote controller
1 : Interrupt request issued
/counter overflow
interrupt request bit
0
✽
3 Serial I/O1 interrupt 0 : No interrupt request
issued
request bit
Serial I/O automatic 1 : Interrupt request issued
transfer interrupt
request bit
0
✽
4 Timer X interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
5 Timer 1 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
6 Timer 2 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
7 Timer 3 interrupt
request bit
0 : No interrupt request
issued
1 : Interrupt request issued
0
✽
✽: “0” can be set by software, but “1” cannot be set.
Fig. 3.5.38 Structure of interrupt request register 1
3-54
At reset R W
0 INT0 interrupt
request bit
38B5 Group User’s Manual
APPENDIX
3.5 Control registers
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16)
b
0
1
2
3
4
5
6
7
Name
Functions
Timer 4 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
request bit (Note)
Timer 5 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
request bit
Timer 6 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
request bit
Serial I/O2 receive 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
INT3/Serial I/O2
0 : No interrupt request issued
1 : Interrupt request issued
transmit interrupt
request bit (Note)
INT4 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
request bit
A-D converter
interrupt request bit
FLD blanking
0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
FLD digit interrupt
request bit
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the contents
are “0”.
At reset R W
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽
0
✽: “0” can be set by software, but “1” cannot be set.
Note: In the mask option type P, if timer 4 interrupt whose count source is
CNTR1 input and INT3 interrupt are selected, these bits do not
become “1”.
Fig. 3.5.39 Structure of interrupt request register 2
38B5 Group User’s Manual
3-55
APPENDIX
3.5 Control registers
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 3E16)
b
Name
Functions
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
3 Serial I/O1 interrupt
enable bit
Serial I/O automatic
transfer interrupt
enable bit
4 Timer X interrupt
enable bit
5 Timer 1 interrupt
enable bit
6 Timer 2 interrupt
enable bit
7 Timer 3 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0
Fig. 3.5.40 Structure of interrupt control register 1
3-56
At reset R W
0 INT0 interrupt
enable bit
1 INT1 interrupt
enable bit
2 INT2 interrupt
enable bit
Remote controller
/counter overflow
interrupt enable bit
38B5 Group User’s Manual
0
0
0
0
0
APPENDIX
3.5 Control registers
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2
(ICON2 : address 3F16)
b
Name
0 Timer 4 interrupt
enable bit (Note)
1 Timer 5 interrupt
enable bit
2 Timer 6 interrupt
enable bit
3 Serial I/O2 receive
interrupt enable bit
4 INT3/Serial I/O2
transmit interrupt
enable bit (Note)
5 INT4 interrupt
enable bit
A-D converter
interrupt enable bit
6 FLD blanking
interrupt enable bit
FLD digit interrupt
enable bit
7 Fix “0” to this bit.
Functions
At reset R W
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0 : interrupt disabled
1 : Interrupt enabled
0
0 : interrupt disabled
1 : Interrupt enabled
0
0 : interrupt disabled
1 : Interrupt enabled
0
0
0
0
0
0
Note: In the mask option type P, timer 4 interrupt whose count source
is CNTR1 input and INT3 interrupt are not available.
Fig. 3.5.41 Structure of interrupt control register 2
38B5 Group User’s Manual
3-57
APPENDIX
3.5 Control registers
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register 1
(PULL1: address 0EF016)
b
Name
Functions
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0 Ports P50, P51 pullup control
1 Ports P52, P53 pullup control
2 Ports P54, P55 pullup control
3 Ports P56, P57 pullup control
4 Port P61 pull-up
control
5 Ports P62, P63 pullup control
6 Ports P64, P65 pullup control
At reset R W
0
0
0
0
0
0
0
0
Note: The pin set to output port is cut off from pull-up control.
Fig. 3.5.42 Structure of pull-up control register 1
Pull-up control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register 2
(PULL2: address 0EF116)
b
Name
Functions
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
7 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0 Ports P70, P71 pullup control
1 Ports P72, P73 pullup control
2 Ports P74, P75 pullup control
3 Ports P76, P77 pullup control
4 Ports P84, P85 pullup control
5 Ports P86, P87 pullup control
6 Ports P90, P91 pullup control
At reset R W
0
0
0
0
0
0
0
0
Note: The pin set to output port is cut off from pull-up control.
Fig. 3.5.43 Structure of pull-up control register 2
3-58
38B5 Group User’s Manual
APPENDIX
3.5 Control registers
P1FLDRAM write disable register
b7 b6 b5 b4 b3 b2 b1 b0
P1FLDRAM write disable register
(P1FLDRAM: address 0EF216)
b
Name
Functions
At reset R W
0 FLDRAM corre0: Operating normally
sponding to port
1: Write disabled
P10 write disable bit
0
1 FLDRAM corre0: Operating normally
sponding to port
1: Write disabled
P11 write disable bit
0
2 FLDRAM corre0: Operating normally
sponding to port
1: Write disabled
P12 write disable bit
0
3 FLDRAM corre0: Operating normally
sponding to port
1: Write disabled
P13 write disable bit
0
4 FLDRAM corresponding to port
P14 write disable bit
5 FLDRAM corresponding to port
P15 write disable bit
6 FLDRAM corresponding to port
P16 write disable bit
7 FLDRAM corresponding to port
P17 write disable bit
0: Operating normally
1: Write disabled
0
0: Operating normally
1: Write disabled
0
0: Operating normally
1: Write disabled
0
0: Operating normally
1: Write disabled
0
Fig. 3.5.44 Structure of P1FLDRAM write disable register
38B5 Group User’s Manual
3-59
APPENDIX
3.5 Control registers
P3FLDRAM write disable register
b7 b6 b5 b4 b3 b2 b1 b0
P3FLDRAM write disable register
(P3FLDRAM: address 0EF316)
b
Name
Functions
0 FLDRAM corre0: Operating normally
sponding to port
1: Write disabled
P30 write disable bit
0
1 FLDRAM corre0: Operating normally
sponding to port
1: Write disabled
P31 write disable bit
0
2 FLDRAM corre0: Operating normally
sponding to port
1: Write disabled
P32 write disable bit
0
3 FLDRAM corre0: Operating normally
sponding to port
1: Write disabled
P33 write disable bit
0
4 FLDRAM corresponding to port
P34 write disable bit
5 FLDRAM corresponding to port
P35 write disable bit
6 FLDRAM corresponding to port
P36 write disable bit
7 FLDRAM corresponding to port
P37 write disable bit
0: Operating normally
1: Write disabled
0
0: Operating normally
1: Write disabled
0
0: Operating normally
1: Write disabled
0
0: Operating normally
1: Write disabled
0
Fig. 3.5.45 Structure of P3FLDRAM write disable register
3-60
At reset R W
38B5 Group User’s Manual
APPENDIX
3.5 Control registers
FLDC mode register
b7 b6 b5 b4 b3 b2 b1 b0
FLDC mode register
(FLDM: address 0EF416)
b
Name
Functions
At reset R W
0 Automatic display
control bit (P0, P1,
P2, P3, P8)
0 : General-purpose mode
1 : Automatic display
mode
0
1 Display start bit
0 : Display stopped
1 : Display in progress (display
starts by writing “1”)
0
2 Tscan control bits
b3 b2
0
3
0 0 : 0 FLD digit interrupt
(at rising edge of each
digit)
0 1 : 1 ✕ Tdisp
1 0 : 2 ✕ Tdisp
1 1 : 3 ✕ Tdisp
FLD blanking interrupt (at
falling edge of last digit)
0
4 Timing number
control bit
0 : 16 timing mode
1 : 32 timing mode (Note 2)
0
5 Gradation display
mode selection
control bit
6 Tdisp counter count
source selection bit
0 : Not selected
1 : Selected (Notes 1, 2)
0
0 : f(XIN)/16 or f(XCIN)/32
1 : f(XIN)/64 or f(XCIN)/128
0
0 : Drivability strong
1 : Drivability weak
0
7 High-breakdown
voltage port drivability selection bit
Notes 1: When the gradation display mode is selected, the number of
timing is max. 16 timing. (Set “0” to the timing number control
bit (b4).)
2: When switching the timing number control bit (b4) or the
gradation display mode selection control bit (b5), set “0” to
the display start bit (b1) (display stop state) before that.
Fig. 3.5.46 Structure of FLDC mode register
38B5 Group User’s Manual
3-61
APPENDIX
3.5 Control registers
Tdisp time set register
b7 b6 b5 b4 b3 b2 b1 b0
Tdisp time set register
(TDISP: address 0EF516)
b
Functions
0
•Set the Tdisp time.
•When a value n is written to this register, Tdisp
time is expressed as Tdisp = (n + 1) ✕ count
source.
•When reading this register, the value in the
counter is read out.
0
(Example)
When the following condition is satisfied, Tdisp
becomes 804 µs {(200 + 1) ✕ 4 µs};
•f(XIN) = 4 MHz
•bit 6 of FLDC mode register = 0
(f(XIN)/16 is selected as Tdisp counter count
source. )
•Tdisp time set register = 200 (C816).
0
1
2
3
4
0
0
0
5
0
6
0
7
0
Fig. 3.5.47 Structure of Tdisp time set register
3-62
At reset R W
38B5 Group User’s Manual
APPENDIX
3.5 Control registers
Toff1 time set register
b7 b6 b5 b4 b3 b2 b1 b0
Toff1 time set register
(TOFF1: address 0EF616)
b
0
1
2
3
4
5
Functions
•Set the Toff1 time.
•When a value n1 is written to this register,
Toff1 time is expressed as Toff1 = n1 ✕ count
source.
(Example)
When the following condition is satisfied, Toff1
becomes 120 µs (= 30 ✕ 4 µs);
•f(XIN) = 4 MHz
•bit 6 of FLDC mode register = 0
(f(XIN)/16 is selected as Tdisp counter count
source.)
•Toff1 time set register = 30 (1E16).
At reset R W
1
1
1
1
1
1
6
1
7
1
Note: Set value of 0316 or more.
Fig. 3.5.48 Structure of Toff1 time set register
Toff2 time set register
b7 b6 b5 b4 b3 b2 b1 b0
Toff2 time set register
(TOFF2: address 0EF716)
b
Functions
0
•Set the Toff2 time.
•When a value n2 is written to this register,
Toff2 time is expressed as Toff2 = n2 ✕ count
source.
However, setting of Toff2 time is valid only for
the FLD port which is satisfied the following;
•gradation display mode
•value of FLD automatic display RAM (in
gradation display mode) = “1” (dark display).
1
(Example)
When the following condition is satisfied, Toff2
becomes 720 µs (= 180 ✕ 4 µs);
•f(XIN) = 4 MHz
•bit 6 of FLDC mode register = 0
(f(XIN)/16 is selected as Tdisp counter count
source.)
•Toff2 time set register = 180 (B416).
1
1
2
3
4
5
6
7
At reset R W
1
1
1
1
1
1
Note: When the Toff2 control bit (b7) of the port P8FLD output control
register (address 0EFC16) is set to “1”, set value of 0316 or
more to the Toff2 control register.
Fig. 3.5.49 Structure of Toff2 time set register
38B5 Group User’s Manual
3-63
APPENDIX
3.5 Control registers
FLD data pointer/FLD data pointer reload register
b7 b6 b5 b4 b3 b2 b1 b0
FLD data pointer/FLD data pointer reload register
(FLDDP: address 0EF816)
b
0
1
2
3
4
5
6
7
Functions
At reset R W
The start address of each data of FLD ports P0, Undefined
P1, P2, P3, and P8, which is transferred from
FLD automatic display RAM, is set to this
Undefined
register.
The start address becomes the address adding Undefined
the value set to this register into the last data
address of each FLD port.
Undefined
Set a value of (timing number – 1) to this
register.
Undefined
The value which is set to this address is written
to the FLD data pointer reload register.
Undefined
When reading data from this address, the value
in the FLD data pointer is read.
Undefined
When bits 5 to 7 of this register is read, “0” is
always read.
Undefined
Fig. 3.5.50 Structure of FLD data pointer/FLD data pointer reload register
Port P0FLD/port switch register
b7 b6 b5 b4 b3 b2 b1 b0
Port P0FLD/port switch register
(P0FPR: address 0EF916)
b
Name
0 Port P00FLD/port
switch bit
1 Port P01FLD/port
switch bit
2 Port P02FLD/port
switch bit
3 Port P03FLD/port
switch bit
4 Port P04FLD/port
switch bit
5 Port P05FLD/port
switch bit
6 Port P06FLD/port
switch bit
7 Port P07FLD/port
switch bit
Functions
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
Fig. 3.5.51 Structure of port P0FLD/Port switch register
3-64
38B5 Group User’s Manual
At reset R W
0
0
0
0
0
0
0
0
APPENDIX
3.5 Control registers
Port P2FLD/port switch register
b7 b6 b5 b4 b3 b2 b1 b0
Port P2FLD/port switch register
(P2FPR: address 0EFA16)
b
Name
0 Port P20FLD/port
switch bit
Port
P21FLD/port
1
switch bit
2 Port P22FLD/port
switch bit
3 Port P23FLD/port
switch bit
4 Port P24FLD/port
switch bit
5 Port P25FLD/port
switch bit
6 Port P26FLD/port
switch bit
7 Port P27FLD/port
switch bit
Functions
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
At reset R W
0
0
0
0
0
0
0
0
Fig. 3.5.52 Structure of port P2FLD/port switch register
Port P8FLD/port switch register
b7 b6 b5 b4 b3 b2 b1 b0
Port P8FLD/port switch register
(P8FPR: address 0EFB16)
b
0
1
2
3
4
5
6
7
Name
Port P80FLD/port
switch bit
Port P81FLD/port
switch bit
Port P82FLD/port
switch bit
Port P83FLD/port
switch bit
Port P84FLD/port
switch bit
Port P85FLD/port
switch bit
Port P86FLD/port
switch bit
Port P87FLD/port
switch bit
Functions
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
0 : General-purpose port
1 : FLD port
At reset R W
0
0
0
0
0
0
0
0
Fig. 3.5.53 Structure of port P8FLD/port switch register
38B5 Group User’s Manual
3-65
APPENDIX
3.5 Control registers
Port P8FLD output control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P8FLD output control register
(P8FLDCON : address 0EFC16)
b
Name
Functions
0 : Output normally
0 P84–P87 FLD
1 : Reverse output
output reverse bit
1 P84–P87/FLDRAM 0 : Operating normally
1 : Write disabled
write disable bit
0 : Operating normally
P8
4
–P8
7
Toff
2
1 : Toff invalid
invalid bit
3 P84–P87 delay
0 : No delay
control bit (Note)
1 : Delay
4 P63/AN9 dimmer
0 : Ordinary port
output control bit
1 : Dimmer output
5 Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
6 out, the contents are “0”.
7 Toff2 control bit
0 : Operating normally
(falling operation)
1 : Rising operation
At reset R W
0
0
0
0
0
0
0
0
Note: Valid only when selecting FLD port and P84–P87 Toff invalid function
Fig. 3.5.54 Structure of port P8FLD output control register
Buzzer output control register
b7 b6 b5 b4 b3 b2 b1 b0
Buzzer output control register
(BUZCON: address 0EFD16)
b
Name
0 Output frequency
selection bits
1
2 Output port
selection bits
3
Functions
0
0 0: 1 kHz (f(XIN)/4096)
0 1: 2 kHz (f(XIN)/2048)
1 0: 4 kHz (f(XIN)/1024)
1 1: Not available
0
b3b2
0
0 0: P20 and P43 function
as ordinary ports.
0 1: P43/BUZ01 functions as
a buzzer output.
1 0: P20/BUZ02/FLD0
functions as a buzzer
output.
1 1: Not available
4 Buzzer output
ON/OFF bit
0: Buzzer output OFF (“0”
output)
1: Buzzer output ON
5 Nothing is arranged for these bits. These are
6 write disabled bits. When these bits are read
7 out, the contents are “0”.
Fig. 3.5.55 Structure of buzzer output control register
3-66
At reset R W
b1b0
38B5 Group User’s Manual
0
0
0
0
0
APPENDIX
3.6 Mask ROM confirmation form
3.6 Mask ROM confirmation form
GZZ-SH54-19B<88A1>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38B57M6-XXXFP
MITSUBISHI ELECTRIC
Date:
Receipt
Section head Supervisor
signature
signature
Note : Please fill in all items marked ❈.
Date
issued
Date:
)
Submitted by
Issuance
signature
❈ Customer
TEL
(
Company
name
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data.
We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type
27512
EPROM address
000016
Product name
000F16
001016
A07F16
A08016
In the address space of the microcomputer, the internal
ROM area is from address A08016 to FFFD16. The reset
vector is stored in addresses FFFC16 and FFFD16.
ASCII code :
‘M38B57M6-’
Data
ROM (24K-130) bytes
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of the
diagram) to “FF16”.
(2) The ASCII codes of the product name “M38B57M6–”
must be entered in addresses 000016 to 000816. And set
the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right in
hexadecimal notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 33 16
‘8’ = 38 16
‘B’ = 42 16
‘5’ = 35 16
‘7’ = 37 16
‘M’ = 4D16
‘6’ = 36 16
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘–’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
38B5 Group User’s Manual
3-67
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH54-19B<88A1>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38B57M6-XXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program because ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
27512
The pseudo-command
*= $0000
.BYTE ‘M38B57M6–’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM
will not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate
mark specification form (80P6N) and attach it to the mask ROM confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
MHz
f(XIN) =
(2) How will you use the XCIN-XCOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
f(XCIN) =
kHz
❈ 4. Comments
(2/2)
3-68
38B5 Group User’s Manual
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH54-20B<88A1>
Mask ROM number
Date:
Section head Supervisor
signature
signature
Receipt
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38B57MCHXXXFP
MITSUBISHI ELECTRIC
Note : Please fill in all items marked ❈.
Date
issued
Date:
)
Submitted by
Issuance
signature
❈ Customer
TEL
(
Company
name
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data.
We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type
27512
EPROM address
000016
Product name
000F16
001016
001116
407F16
408016
In the address space of the microcomputer, the internal
ROM area is from address 4080 16 to FFFD16. The reset
vector is stored in addresses FFFC16 and FFFD16.
ASCII code :
‘M38B57MCH-’
Mask option
Data
ROM (48K-130) bytes
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of the
diagram) to “FF16”.
(2) The ASCII codes of the product name “M38B57MCH–”
must be entered in addresses 000016 to 000916. And set
the data “FF16” in addresses 000A16 to 000F16.
The ASCII codes and addresses are listed to the right in
hexadecimal notation.
The option data must be entered in address 001016.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 33 16
‘8’ = 38 16
‘B’ = 42 16
‘5’ = 35 16
‘7’ = 37 16
‘M’ = 4D16
‘C’ = 4316
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘H’ = 4816
‘–’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
(1/3)
38B5 Group User’s Manual
3-69
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH54-20B<88A1>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38B57MCH- ✽ XXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program because ASCII codes of the product name are written to addresses 000016 to 000916 of EPROM.
EPROM type
27512
*=
The pseudo-command
.BYTE
$0000
‘M38B57MCH–’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM
will not be processed.
❈ 2. Mask option specification
High-breakdown voltage ports P20 to P27 and P80 to P83 can be selected whether pull-down resistors are built-in or not
from among the following 8 types by the mask option.
Select built-in type of pull-down resistors from among the following A to G, P, and fill out the following certainly.
(Fill out the upper part of page 1/3 also.)
Set the data of the same option type name in EPROM specified address. (Set the ASCII code of A to G, P; 4116 to 4716,
5016.)
Set the following pseudo-command to the assembler source program.
EPROM type
27512
The pseudo-command
*= $0010
.BYTE $XX
Connective port of pull-down resistor
(connected at “1” writing)
Option type
P20 P21 P22 P23 P24 P25 P26 P27 P80 P81 P82 P83
A ($41)
B ($42)
C ($43)
D ($44)
E ($45)
F ($46)
G ($47)
P ($50)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
M38B57MCH-
1
1
1
1
1
1
1
1
1
1
1
1
1
XXXFP
Option type
Fill out with any one of A to G, P.
(2/3)
3-70
38B5 Group User’s Manual
1
1
1
1
1
1
1
1
1
1
1
1
1
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH54-20B<88A1>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38B57MCH- ✽ XXXFP
MITSUBISHI ELECTRIC
❈ 3. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate
mark specification form (80P6N) and attach it to the mask ROM confirmation form.
❈ 4. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
f(XIN) =
MHz
(2) How will you use the XCIN-XCOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
f(XCIN) =
kHz
❈ 5. Comments
(3/3)
38B5 Group User’s Manual
3-71
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH54-21B<88A1>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38B59MFHXXXFP
MITSUBISHI ELECTRIC
Date:
Receipt
Section head Supervisor
signature
signature
Note : Please fill in all items marked ❈.
Date
issued
Date:
)
Submitted by
Issuance
signature
❈ Customer
TEL
(
Company
name
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data.
We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this
data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type
27512
EPROM address
000016
Product name
000F16
001016
001116
107F16
108016
In the address space of the microcomputer, the internal
ROM area is from address 1080 16 to FFFD 16. The reset
vector is stored in addresses FFFC16 and FFFD16.
ASCII code :
‘M38B59MFH-’
Mask option
Data
ROM (60K-130) bytes
FFFD16
FFFE16
FFFF16
(1) Set the data in the unused area (the shaded area of the
diagram) to “FF16”.
(2) The ASCII codes of the product name “M38B59MFH–”
must be entered in addresses 000016 to 000916. And set
the data “FF16” in addresses 000A16 to 000F16.
The ASCII codes and addresses are listed to the right in
hexadecimal notation.
The option data must be entered in address 001016.
Address
000016
000116
000216
000316
000416
000516
000616
000716
(1/3)
3-72
38B5 Group User’s Manual
‘M’ = 4D16
‘3’ = 33 16
‘8’ = 38 16
‘B’ = 42 16
‘5’ = 35 16
‘9’ = 39 16
‘M’ = 4D16
‘F’ = 46 16
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘H’ = 4816
‘–’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH54-21B<88A1>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38B59MFH- ✽ XXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program because ASCII codes of the product name are written to addresses 000016 to 000916 of EPROM.
EPROM type
27512
The pseudo-command
*=
.BYTE
$0000
‘M38B59MFH–’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM
will not be processed.
❈ 2. Mask option specification
High-breakdown voltage ports P20 to P27 and P80 to P83 can be selected whether pull-down resistors are built-in or not
from among the following 8 types by the mask option.
Select built-in type of pull-down resistors from among the following A to G, P, and fill out the following certainly.
(Fill out the upper part of page 1/3 also.)
Set the data of the same option type name in EPROM specified address. (Set the ASCII code of A to G, P; 4116 to 4716,
5016.)
Set the following pseudo-command to the assembler source program.
EPROM type
27512
The pseudo-command
*= $0010
.BYTE $XX
Connective port of pull-down resistor
(connected at “1” writing)
Option type
P20 P21 P22 P23 P24 P25 P26 P27 P80 P81 P82 P83
A ($41)
B ($42)
C ($43)
D ($44)
E ($45)
F ($46)
G ($47)
P ($50)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
M38B59MFH-
1
1
1
1
1
1
XXXFP
Option type
Fill out with any one of A to G, P.
(2/3)
38B5 Group User’s Manual
3-73
APPENDIX
3.6 Mask ROM confirmation form
GZZ-SH54-21B<88A1>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38B59MFH- ✽ XXXFP
MITSUBISHI ELECTRIC
❈ 3. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate
mark specification form (80P6N) and attach it to the mask ROM confirmation form.
❈ 4. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
f(XIN) =
MHz
(2) How will you use the XCIN-XCOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
f(XCIN) =
kHz
❈ 5. Comments
(3/3)
3-74
38B5 Group User’s Manual
APPENDIX
3.7 ROM programming confirmation form
3.7 ROM programming confirmation form
GZZ-SH54-22B<88A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38B59EF-XXXFP
MITSUBISHI ELECTRIC
Date:
Receipt
Section head Supervisor
signature
signature
Note : Please fill in all items marked ❈.
Date
issued
Date:
)
Submitted by
Issuance
signature
❈ Customer
TEL
(
Company
name
Supervisor
❈ 1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based
on this data. We shall assume the responsibility for errors only if the ROM programming data on the products we
produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type
27512
EPROM address
000016
Product name
000F16
001016
107F16
108016
In the address space of the microcomputer, the internal
ROM area is from address 108016 to FFFD16. The reset
vector is stored in addresses FFFC16 and FFFD 16.
ASCII code :
‘M38B59EF-’
Data
ROM (60K-130) bytes
FFFD 16
FFFE 16
FFFF16
(1) Set the data in the unused area (the shaded area of the
diagram) to “FF16”.
(2) The ASCII codes of the product name “M38B59EF–”
must be entered in addresses 000016 to 000816. And set
the data “FF16” in addresses 000916 to 000F16.
The ASCII codes and addresses are listed to the right in
hexadecimal notation.
Address
000016
000116
000216
000316
000416
000516
000616
000716
‘M’ = 4D16
‘3’ = 3316
‘8’ = 3816
‘B’ = 4216
‘5’ = 3516
‘9’ = 3916
‘E’ = 4516
‘F’ = 4616
Address
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
‘–’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
(1/2)
38B5 Group User’s Manual
3-75
APPENDIX
3.7 ROM programming confirmation form
GZZ-SH54-22B<88A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M38B59EF-XXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program because ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
27512
The pseudo-command
*= $0000
.BYTE ‘M38B59EF–’
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation
form, the ROM will not be processed.
❈ 2. Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate
mark specification form (80P6N) and attach it to the ROM programming confirmation form.
❈ 3. Usage conditions
Please answer the following questions about usage for use in our product inspection :
(1) How will you use the XIN-XOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
MHz
f(XIN) =
(2) How will you use the XCIN-XCOUT oscillator?
Ceramic resonator
Quartz crystal
External clock input
Other (
At what frequency?
)
kHz
f(XCIN) =
❈ 4. Comments
(2/2)
3-76
38B5 Group User’s Manual
APPENDIX
3.8 Mark specification form
3.8 Mark specification form
80P6N (80-PIN QFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
64
41
40
65
Mitsubishi IC catalog name
Mitsubishi product number
(6-digit, or 7-digit)
25
80
1
24
B. Customer’s Parts Number + Mitsubishi IC Catalog Name
64
41
40
65
25
80
1
24
Customer’s Parts Number
Note : The fonts and size of characters are standard Mitsubishi type.
Mitsubishi IC catalog name
Notes 1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard Mitsubishi type.
3 : Customer’s parts number can be up to 14 alphanumeric characters for capital letters, hyphens, commas, periods and so on.
4 : If the Mitsubishi logo
is not required, check the box below.
Mitsubishi logo is not required
C. Special Mark Required
64
41
65
40
80
25
1
Notes1 : If special mark is to be printed, indicate the desired layout of the mark in the left figure. The layout will be
duplicated technically as close as possible.
Mitsubishi product number (6-digit, or 7-digit) and Mask
ROM number (3-digit) are always marked for sorting the
products.
2 : If special character fonts (e,g., customer’s trade mark
logo) must be used in Special Mark, check the box below.
For the new special character fonts, a clean font original
(ideally logo drawing) must be submitted.
24
Special character fonts required
38B5 Group User’s Manual
3-77
APPENDIX
3.9 Package outline
3.9 Package outline
80P6N-A
Plastic 80pin 14✕20mm body QFP
EIAJ Package Code
QFP80-P-1420-0.80
Weight(g)
1.58
Lead Material
Alloy 42
MD
e
JEDEC Code
–
HD
D
b2
1
ME
65
80
64
I2
E
24
HE
Recommended Mount Pad
Symbol
41
A
40
25
e
y
3-78
b
F
A1
c
A2
L1
L
Detail F
38B5 Group User’s Manual
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
–
–
3.05
0.1
0.2
0
–
–
2.8
0.3
0.35
0.45
0.13
0.15
0.2
13.8
14.0
14.2
19.8
20.0
20.2
–
0.8
–
16.5
16.8
17.1
22.5
22.8
23.1
0.4
0.6
0.8
1.4
–
–
–
–
0.1
–
0°
10°
–
–
0.5
1.3
–
–
–
–
14.6
20.6
–
–
APPENDIX
3.10 List of instruction code
3.10 List of instruction code
D7 – D 4
D3 – D0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Hexadecimal
notation
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ORA
IMM
ASL
A
SEB
0, A
—
ORA
ABS
ASL
ABS
SEB
0, ZP
ORA
DEC
ABS, Y
A
CLB
0, A
—
0000
0
BRK
ORA
JSR
IND, X ZP, IND
BBS
0, A
—
ORA
ZP
ASL
ZP
BBS
0, ZP
PHP
0001
1
BPL
ORA
IND, Y
CLT
BBC
0, A
—
ORA
ZP, X
ASL
ZP, X
BBC
0, ZP
CLC
0010
2
JSR
ABS
AND
IND, X
JSR
SP
BBS
1, A
BIT
ZP
AND
ZP
ROL
ZP
BBS
1, ZP
PLP
AND
IMM
ROL
A
SEB
1, A
BIT
ABS
0011
3
BMI
AND
IND, Y
SET
BBC
1, A
—
AND
ZP, X
ROL
ZP, X
BBC
1, ZP
SEC
AND
ABS, Y
INC
A
CLB
1, A
ROL
CLB
LDM
AND
ZP ABS, X ABS, X 1, ZP
0100
4
RTI
EOR
IND, X
STP
BBS
2, A
COM
ZP
EOR
ZP
LSR
ZP
BBS
2, ZP
PHA
EOR
IMM
LSR
A
SEB
2, A
JMP
ABS
0101
5
BVC
EOR
IND, Y
—
BBC
2, A
—
EOR
ZP, X
LSR
ZP, X
BBC
2, ZP
CLI
EOR
ABS, Y
—
CLB
2, A
—
0110
6
RTS
MUL
ADC
IND, X ZP, X
BBS
3, A
TST
ZP
ADC
ZP
ROR
ZP
BBS
3, ZP
PLA
ADC
IMM
ROR
A
SEB
3, A
JMP
IND
0111
7
BVS
ADC
IND, Y
—
BBC
3, A
—
ADC
ZP, X
ROR
ZP, X
BBC
3, ZP
SEI
ADC
ABS, Y
—
CLB
3, A
—
1000
8
BRA
STA
IND, X
RRF
ZP
BBS
4, A
STY
ZP
STA
ZP
STX
ZP
BBS
4, ZP
DEY
—
TXA
SEB
4, A
STY
ABS
STA
ABS
STX
ABS
SEB
4, ZP
1001
9
BCC
STA
IND, Y
—
BBC
4, A
STY
ZP, X
STA
ZP, X
STX
ZP, Y
BBC
4, ZP
TYA
STA
ABS, Y
TXS
CLB
4, A
—
STA
ABS, X
—
CLB
4, ZP
1010
A
LDY
IMM
LDA
IND, X
LDX
IMM
BBS
5, A
LDY
ZP
LDA
ZP
LDX
ZP
BBS
5, ZP
TAY
LDA
IMM
TAX
SEB
5, A
LDY
ABS
LDA
ABS
LDX
ABS
SEB
5, ZP
1011
B
BCS
JMP
BBC
LDA
IND, Y ZP, IND 5, A
LDY
ZP, X
LDA
ZP, X
LDX
ZP, Y
BBC
5, ZP
CLV
LDA
ABS, Y
TSX
CLB
5, A
1100
C
CPY
IMM
CMP
IND, X
WIT
BBS
6, A
CPY
ZP
CMP
ZP
DEC
ZP
BBS
6, ZP
INY
CMP
IMM
DEX
SEB
6, A
CPY
ABS
1101
D
BNE
CMP
IND, Y
—
BBC
6, A
—
CMP
ZP, X
DEC
ZP, X
BBC
6, ZP
CLD
CMP
ABS, Y
—
CLB
6, A
—
1110
E
CPX
IMM
DIV
SBC
IND, X ZP, X
BBS
7, A
CPX
ZP
SBC
ZP
INC
ZP
BBS
7, ZP
INX
SBC
IMM
NOP
SEB
7, A
CPX
ABS
1111
F
BEQ
SBC
IND, Y
BBC
7, A
—
SBC
ZP, X
INC
ZP, X
BBC
7, ZP
SED
SBC
ABS, Y
—
CLB
7, A
—
—
ASL
CLB
ORA
ABS, X ABS, X 0, ZP
AND
ABS
EOR
ABS
ROL
ABS
LSR
ABS
SEB
1, ZP
SEB
2, ZP
LSR
CLB
EOR
ABS, X ABS, X 2, ZP
ADC
ABS
ROR
ABS
SEB
3, ZP
CLB
ADC ROR
ABS, X ABS, X 3, ZP
LDX
CLB
LDY
LDA
ABS, X ABS, X ABS, Y 5, ZP
CMP
ABS
DEC
ABS
SEB
6, ZP
DEC
CLB
CMP
ABS, X ABS, X 6, ZP
SBC
ABS
INC
ABS
SEB
7, ZP
INC
CLB
SBC
ABS, X ABS, X 7, ZP
: 3-byte instruction
: 2-byte instruction
: 1-byte instruction
38B5 Group User’s Manual
3-79
APPENDIX
3.11 Machine instructions
3.11 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
ADC
(Note 1)
(Note 5)
When T = 0
A←A+M+C
When T = 1
M(X) ← M(X) + M + C
AND
(Note 1)
When TV= 0
A←A M
When T = 1 V
M(X) ← M(X) M
ASL
C←
7
0
←0
IMM
# OP n
A
# OP n
BIT,A,AR
BIT,
# OP n
ZP
# OP n
BIT,ZP,
ZPR
BIT,
# OP n
When T = 0, this instruction adds the contents
M, C, and A; and stores the results in A and C.
When T = 1, this instruction adds the contents
of M(X), M and C; and stores the results in
M(X) and C. When T=1, the contents of A remain unchanged, but the contents of status
flags are changed.
M(X) represents the contents of memory
where is indicated by X.
69 2
2
65 3
2
When T = 0, this instruction transfers the contents of A and M to the ALU which performs a
bit-wise AND operation and stores the result
back in A.
When T = 1, this instruction transfers the contents M(X) and M to the ALU which performs a
bit-wise AND operation and stores the results
back in M(X). When T = 1, the contents of A
remain unchanged, but status flags are
changed.
M(X) represents the contents of memory
where is indicated by X.
29 2
2
25 3
2
06 5
2
This instruction shifts the content of A or M by
one bit to the left, with bit 0 always being set to
0 and bit 7 of A or M always being contained in
C.
0A 2
1
#
BBC
(Note 4)
Ai or Mi = 0?
This instruction tests the designated bit i of M
or A and takes a branch if the bit is 0. The
branch address is specified by a relative address. If the bit is 1, next instruction is
executed.
13
+ 4
20i
2
17
+ 5
20i
3
BBS
(Note 4)
Ai or Mi = 1?
This instruction tests the designated bit i of the
M or A and takes a branch if the bit is 1. The
branch address is specified by a relative address. If the bit is 0, next instruction is
executed.
03
+ 4
20i
2
07
+ 5
20i
3
BCC
(Note 4)
C = 0?
This instruction takes a branch to the appointed address if C is 0. The branch address
is specified by a relative address. If C is 1, the
next instruction is executed.
BCS
(Note 4)
C = 1?
This instruction takes a branch to the appointed address if C is 1. The branch address
is specified by a relative address. If C is 0, the
next instruction is executed.
BEQ
(Note 4)
Z = 1?
This instruction takes a branch to the appointed address when Z is 1. The branch
address is specified by a relative address.
If Z is 0, the next instruction is executed.
BIT
A
BMI
(Note 4)
N = 1?
This instruction takes a branch to the appointed address when N is 1. The branch
address is specified by a relative address.
If N is 0, the next instruction is executed.
BNE
(Note 4)
Z = 0?
This instruction takes a branch to the appointed address if Z is 0. The branch address
is specified by a relative address. If Z is 1, the
next instruction is executed.
3-80
V
M
This instruction takes a bit-wise logical AND of
A and M contents; however, the contents of A
and M are not modified.
The contents of N, V, Z are changed, but the
contents of A, M remain unchanged.
38B5 Group User’s Manual
24 3
2
APPENDIX
3.11 Machine instructions
Addressing mode
ZP, X
ZP, Y
OP n
# OP n
75 4
ABS
ABS, X
ABS, Y
IND
# OP n
# OP n
# OP n
# OP n
2
6D 4
3 7D 5
3 79 5
35 4
2
2D 4
3 3D 5
3 39 5
16 6
2
0E 6
3 1E 7
3
2C 4
Processor status register
ZP, IND
# OP n
IND, X
IND, Y
REL
SP
# OP n
7
5
4
3
2
1
0
N V
T
B
D
I
Z
C
# OP n
# OP n
# OP n
3
61 6
2 71 6
2
N V
•
•
•
•
Z
C
3
21 6
2 31 6
2
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
90 2
2
•
•
•
•
•
•
•
•
B0 2
2
•
•
•
•
•
•
•
•
F0 2
2
•
•
•
•
•
•
•
•
M7 M6 •
•
•
•
Z
•
3
38B5 Group User’s Manual
#
6
30 2
2
•
•
•
•
•
•
•
•
D0 2
2
•
•
•
•
•
•
•
•
3-81
APPENDIX
3.11 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
IMM
OP n
# OP n
00 7
1
BPL
(Note 4)
N = 0?
This instruction takes a branch to the appointed address if N is 0. The branch address
is specified by a relative address. If N is 1, the
next instruction is executed.
BRA
PC ← PC ± offset
This instruction branches to the appointed address. The branch address is specified by a
relative address.
BRK
B←1
(PC) ← (PC) + 2
M(S) ← PCH
S←S–1
M(S) ← PCL
S←S–1
M(S) ← PS
S←S–1
I← 1
PCL ← ADL
PCH ← ADH
When the BRK instruction is executed, the
CPU pushes the current PC contents onto the
stack. The BADRS designated in the interrupt
vector table is stored into the PC.
BVC
(Note 4)
V = 0?
This instruction takes a branch to the appointed address if V is 0. The branch address
is specified by a relative address. If V is 1, the
next instruction is executed.
BVS
(Note 4)
V = 1?
This instruction takes a branch to the appointed address when V is 1. The branch
address is specified by a relative address.
When V is 0, the next instruction is executed.
CLB
Ai or Mi ← 0
This instruction clears the designated bit i of A
or M.
CLC
C←0
This instruction clears C.
18 2
1
CLD
D←0
This instruction clears D.
D8 2
1
CLI
I←0
This instruction clears I.
58 2
1
CLT
T←0
This instruction clears T.
12 2
1
CLV
V←0
This instruction clears V.
B8 2
1
CMP
(Note 3)
When T = 0
A–M
When T = 1
M(X) – M
When T = 0, this instruction subtracts the contents of M from the contents of A. The result is
not stored and the contents of A or M are not
modified.
When T = 1, the CMP subtracts the contents
of M from the contents of M(X). The result is
not stored and the contents of X, M, and A are
not modified.
M(X) represents the contents of memory
where is indicated by X.
COM
M←M
This instruction takes the one’s complement of
the contents of M and stores the result in M.
CPX
X–M
This instruction subtracts the contents of M
from the contents of X. The result is not stored
and the contents of X and M are not modified.
E0 2
CPY
Y–M
This instruction subtracts the contents of M
from the contents of Y. The result is not stored
and the contents of Y and M are not modified.
C0 2
DEC
A ← A – 1 or
M←M–1
This instruction subtracts 1 from the contents
of A or M.
A
# OP n
BIT, A
# OP n
2
1B
+
20i
C9 2
ZP
# OP n
BIT, ZP
# OP n
#
1F
+ 5
20i
2
1
C5 3
2
44 5
2
2
E4 3
2
2
C4 3
2
C6 5
2
2
__
3-82
38B5 Group User’s Manual
1A 2
1
APPENDIX
3.11 Machine instructions
Addressing mode
ZP, X
OP n
D5 4
D6 6
ZP, Y
# OP n
2
2
ABS
# OP n
CD 4
ABS, X
# OP n
3 DD 5
ABS, Y
# OP n
3 D9 5
IND
# OP n
3
Processor status register
ZP, IND
# OP n
IND, X
# OP n
C1 6
IND, Y
# OP n
2 D1 6
REL
# OP n
2
SP
# OP n
7
#
6
5
4
3
2
1
0
N V
T
B
D
I
Z
C
10 2
2
•
•
•
•
•
•
•
•
80 4
2
•
•
•
•
•
•
•
•
•
•
•
1
•
1
•
•
50 2
2
•
•
•
•
•
•
•
•
70 2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
0
•
•
•
•
•
•
•
•
0
•
•
•
•
0
•
•
•
•
•
•
0
•
•
•
•
•
•
N
•
•
•
•
•
Z
C
N
•
•
•
•
•
Z
•
EC 4
3
N
•
•
•
•
•
Z
C
CC 4
3
N
•
•
•
•
•
Z
C
CE 6
3 DE 7
N
•
•
•
•
•
Z
•
3
38B5 Group User’s Manual
3-83
APPENDIX
3.11 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
IMM
# OP n
DEX
X←X–1
This instruction subtracts one from the current CA 2
contents of X.
1
DEY
Y←Y–1
This instruction subtracts one from the current
contents of Y.
88 2
1
DIV
A ← (M(zz + X + 1),
M(zz + X )) / A
M(S) ← one's complement of Remainder
S←S–1
This instruction divides the 16-bit data in
M(zz+(X)) (low-order byte) and M(zz+(X)+1)
(high-order byte) by the contents of A. The
quotient is stored in A and the one's complement of the remainder is pushed onto the stack.
EOR
(Note 1)
When T = 0
–M
A←AV
When T = 0, this instruction transfers the contents of the M and A to the ALU which
performs a bit-wise Exclusive OR, and stores
the result in A.
When T = 1, the contents of M(X) and M are
transferred to the ALU, which performs a bitwise Exclusive OR and stores the results in
M(X). The contents of A remain unchanged,
but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
When T = 1
–M
M(X) ← M(X) V
49 2
A
# OP n
BIT, A
# OP n
2
ZP
# OP n
BIT, ZP
# OP n
45 3
2
E6 5
2
A5 3
2
3C 4
3
INC
A ← A + 1 or
M←M+1
This instruction adds one to the contents of A
or M.
INX
X←X+1
This instruction adds one to the contents of X.
E8 2
1
INY
Y←Y+1
This instruction adds one to the contents of Y.
C8 2
1
JMP
If addressing mode is ABS
PCL ← ADL
PCH ← ADH
If addressing mode is IND
PCL ← M (AD H, ADL)
PCH ← M (ADH, AD L + 1)
If addressing mode is ZP, IND
PCL ← M(00, AD L)
PCH ← M(00, AD L + 1)
This instruction jumps to the address designated by the following three addressing
modes:
Absolute
Indirect Absolute
Zero Page Indirect Absolute
JSR
M(S) ← PCH
S←S–1
M(S) ← PCL
S←S–1
After executing the above,
if addressing mode is ABS,
PCL ← ADL
PCH ← ADH
if addressing mode is SP,
PCL ← ADL
PCH ← FF
If addressing mode is ZP, IND,
PCL ← M(00, AD L)
PCH ← M(00, AD L + 1)
This instruction stores the contents of the PC
in the stack, then jumps to the address designated by the following addressing modes:
Absolute
Special Page
Zero Page Indirect Absolute
LDA
(Note 2)
When T = 0
A←M
When T = 1
M(X) ← M
When T = 0, this instruction transfers the contents of M to A.
When T = 1, this instruction transfers the contents of M to (M(X)). The contents of A remain
unchanged, but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
LDM
M ← nn
This instruction loads the immediate value in
M.
LDX
X←M
This instruction loads the contents of M in X.
A2 2
2
A6 3
2
LDY
Y←M
This instruction loads the contents of M in Y.
A0 2
2
A4 3
2
3-84
3A 2
38B5 Group User’s Manual
A9 2
2
1
#
APPENDIX
3.11 Machine instructions
Addressing mode
ZP, X
OP n
ZP, Y
# OP n
ABS
# OP n
ABS, X
# OP n
ABS, Y
# OP n
IND
# OP n
Processor status register
ZP, IND
# OP n
IND, X
# OP n
IND, Y
# OP n
REL
# OP n
SP
# OP n
7
#
E2 16 2
55 4
2
4D 4
3 5D 5
3 59 5
F6 6
2
EE 6
3 FE 7
3
B5 4
2
B6 4
B4 4
2
4C 3
3
20 6
3
AD 4
3 BD 5
2 AE 4
AC 4
41 6
6C 5
3 B9 5
3
3 BC 5
3
BE 5
3
3 B2 4
2
02 7
2
2 51 6
2
22 5
A1 6
2 B1 6
3
3
38B5 Group User’s Manual
2
2
6
5
4
3
2
1
0
N V
T
B
D
I
Z
C
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
3-85
APPENDIX
3.11 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
LSR
7
0→
0
→C
This instruction multiply Accumulator with the
memory specified by the Zero Page X address
mode and stores the high-order byte of the result on the Stack and the low-order byte in A.
NOP
PC ← PC + 1
This instruction adds one to the PC but does EA 2
no otheroperation.
ORA
(Note 1)
When T = 0
A←AVM
When T = 0, this instruction transfers the contents of A and M to the ALU which performs a
bit-wise “OR”, and stores the result in A.
When T = 1, this instruction transfers the contents of M(X) and the M to the ALU which
performs a bit-wise OR, and stores the result
in M(X). The contents of A remain unchanged,
but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
PHP
PLA
PLP
ROL
1
# OP n
BIT, ZP
# OP n
46 5
2
05 3
2
1
09 2
2
48 3
1
M(S) ← PS
S←S–1
This instruction pushes the contents of PS to
the memory location designated by S and decrements the contents of S by one.
08 3
1
S←S+1
A ← M(S)
This instruction increments S by one and
stores the contents of the memory designated
by S in A.
68 4
1
S←S+1
PS ← M(S)
This instruction increments S by one and
stores the contents of the memory location
designated by S in PS.
28 4
1
7
←
This instruction shifts either A or M one bit left
through C. C is stored in bit 0 and bit 7 is
stored in C.
2A 2
1
26 5
2
This instruction shifts either A or M one bit
right through C. C is stored in bit 7 and bit 0 is
stored in C.
6A 2
1
66 5
2
82 8
2
0
←C ←
RRF
7
→
3-86
# OP n
ZP
This instruction pushes the contents of A to
the memory location designated by S, and
decrements the contents of S by one.
7
C→
RTS
BIT, A
M(S) ← A
S←S–1
ROR
RTI
# OP n
4A 2
M(S) • A ← A ✽ M(zz + X)
S←S–1
PHA
# OP n
A
This instruction shifts either A or M one bit to
the right such that bit 7 of the result always is
set to 0, and the bit 0 is stored in C.
MUL
When T = 1
M(X) ← M(X) V M
IMM
0
→
0
→
This instruction rotates 4 bits of the M content
to the right.
S←S+1
PS ← M(S)
S←S+1
PCL ← M(S)
S←S+1
PCH ← M(S)
This instruction increments S by one, and
stores the contents of the memory location
designated by S in PS. S is again incremented
by one and stores the contents of the memory
location designated by S in PC L . S is again
incremented by one and stores the contents of
memory location designated by S in PC H.
S←S+1
PCL ← M(S)
S←S+1
PCH ← M(S)
(PC) ← (PC) + 1
This instruction increments S by one and
stores the contents of the memory location
designated by S in PCL. S is again
incremented by one and the contents of the
memory location is stored in PC H . PC is
incremented by 1.
40 6
1
60 6
1
38B5 Group User’s Manual
#
APPENDIX
3.11 Machine instructions
Addressing mode
ZP, X
ZP, Y
OP n
# OP n
56 6
2
ABS
ABS, X
ABS, Y
# OP n
# OP n
# OP n
4E 6
3 5E 7
3
IND
# OP n
Processor status register
ZP, IND
# OP n
IND, X
# OP n
IND, Y
# OP n
# OP n
62 15 2
15 4
2
0D 4
3 1D 5
3 19 5
3
01 6
2 11 6
REL
2
SP
# OP n
7
#
6
5
4
3
2
1
0
N V
T
B
D
I
Z
C
0
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
(Value saved in stack)
36 6
2
2E 6
3 3E 7
3
N
•
•
•
•
•
Z
C
76 6
2
6E 6
3 7E 7
3
N
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
(Value saved in stack)
•
38B5 Group User’s Manual
•
•
•
•
•
•
•
3-87
APPENDIX
3.11 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
SBC
(Note 1)
(Note 5)
When T = 0 _
A←A–M–C
When T = 1
_
M(X) ← M(X) – M – C
IMM
# OP n
When T = 0, this instruction subtracts the
value of M and the complement of C from A,
and stores the results in A and C.
When T = 1, the instruction subtracts the contents of M and the complement of C from the
contents of M(X), and stores the results in
M(X) and C.
A remain unchanged, but status flag are
changed.
M(X) represents the contents of memory
where is indicated by X.
E9 2
SEB
Ai or Mi ← 1
This instruction sets the designated bit i of A
or M.
SEC
C←1
This instruction sets C.
38 2
1
SED
D←1
This instruction set D.
F8 2
1
SEI
I←1
This instruction set I.
78 2
1
SET
T←1
This instruction set T.
32 2
1
STA
M←A
This instruction stores the contents of A in M.
The contents of A does not change.
This instruction resets the oscillation control F/
F and the oscillation stops. Reset or interrupt
input is needed to wake up from this mode.
STP
A
# OP n
BIT, A
# OP n
# OP n
2
E5 3
0B
+ 2
20i
42 2
ZP
BIT, ZP
# OP n
2
1
0F
+ 5
20i
85 4
2
1
STX
M←X
This instruction stores the contents of X in M.
The contents of X does not change.
86 4
2
STY
M←Y
This instruction stores the contents of Y in M.
The contents of Y does not change.
84 4
2
TAX
X←A
This instruction stores the contents of A in X.
The contents of A does not change.
AA 2
1
TAY
Y←A
This instruction stores the contents of A in Y.
The contents of A does not change.
A8 2
1
TST
M = 0?
This instruction tests whether the contents of
M are “0” or not and modifies the N and Z.
64 3
2
TSX
X←S
This instruction transfers the contents of S in
X.
BA 2
1
TXA
A←X
This instruction stores the contents of X in A.
8A 2
1
TXS
S←X
This instruction stores the contents of X in S.
9A 2
1
TYA
A←Y
This instruction stores the contents of Y in A.
98 2
1
The WIT instruction stops the internal clock C2 2
but not the oscillation of the oscillation circuit
is not stopped.
CPU starts its function after the Timer X over
flows (comes to the terminal count). All registers or internal memory contents except Timer
X will not change during this mode. (Of course
needs VDD).
1
WIT
Notes 1
2
3
4
5
3-88
:
:
:
:
:
The number of cycles “n” is increased by 3 when T is 1.
The number of cycles “n” is increased by 2 when T is 1.
The number of cycles “n” is increased by 1 when T is 1.
The number of cycles “n” is increased by 2 when branching has occurred.
N, V, and Z flags are invalid in decimal operation mode.
38B5 Group User’s Manual
#
2
APPENDIX
3.11 Machine instructions
Addressing mode
ZP, X
ZP, Y
OP n
# OP n
F5 4
2
95 5
2
ABS, X
ABS, Y
IND
# OP n
# OP n
# OP n
# OP n
ED 4
3 FD 5
3 F9 5
3
8D 5
2
96 5
94 5
ABS
3 9D 6
3 99 6
3
Processor status register
ZP, IND
# OP n
IND, X
IND, Y
REL
# OP n
# OP n
# OP n
E1 6
2 F1 6
2
81 7
2 91 7
2
SP
# OP n
7
#
6
5
4
3
2
1
0
N V
T
B
D
I
Z
C
N V
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
•
•
•
•
1
•
•
•
•
•
•
•
•
1
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2 8E 5
3
•
•
•
•
•
•
•
•
8C 5
3
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
38B5 Group User’s Manual
3-89
APPENDIX
3.11 Machine instructions
Symbol
Contents
Symbol
IMP
IMM
A
BIT, A
BIT, A, R
ZP
BIT, ZP
BIT, ZP, R
ZP, X
ZP, Y
ABS
ABS, X
ABS, Y
IND
Implied addressing mode
Immediate addressing mode
Accumulator or Accumulator addressing mode
Accumulator bit addressing mode
Accumulator bit relative addressing mode
Zero page addressing mode
Zero page bit addressing mode
Zero page bit relative addressing mode
Zero page X addressing mode
Zero page Y addressing mode
Absolute addressing mode
Absolute X addressing mode
Absolute Y addressing mode
Indirect absolute addressing mode
ZP, IND
Zero page indirect absolute addressing mode
IND, X
IND, Y
REL
SP
C
Z
I
D
B
T
V
N
Indirect X addressing mode
Indirect Y addressing mode
Relative addressing mode
Special page addressing mode
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
X-modified arithmetic mode flag
Overflow flag
Negative flag
+
–
✽
/
V
V
–
V
–
←
X
Y
S
PC
PS
PCH
PCL
ADH
ADL
FF
nn
zz
M
M(X)
M(S)
M(AD H, ADL)
M(00, AD L)
Ai
Mi
OP
n
#
3-90
38B5 Group User's Manual
Contents
Addition
Subtraction
Multiplication
Division
Logical OR
Logical AND
Logical exclusive OR
Negation
Shows direction of data flow
Index register X
Index register Y
Stack pointer
Program counter
Processor status register
8 high-order bits of program counter
8 low-order bits of program counter
8 high-order bits of address
8 low-order bits of address
FF in Hexadecimal notation
Immediate value
Zero page address
Memory specified by address designation of any addressing mode
Memory of address indicated by contents of index
register X
Memory of address indicated by contents of stack
pointer
Contents of memory at address indicated by ADH and
ADL, in AD H is 8 high-order bits and ADL is 8 low-order bits.
Contents of address indicated by zero page ADL
Bit i (i = 0 to 7) of accumulator
Bit i (i = 0 to 7) of memory
Opcode
Number of cycles
Number of bytes
APPENDIX
3.12 M35501FP
3.12 M35501FP
DESCRIPTION
FEATURES
The M35501FP generates digit signals for fluorescent display
when connected to the output port of a microcomputer. There are
up to 16 digit pins available, and more can be added by connecting additional M35501FPs. The number of fluorescent displays
can be increased easily by connecting the M35501FP to the
CMOS FLD output pins of an 8-bit microcomputer in
MITSUBISHI’s 38B5 Group. The M35501FP is suitable for fluorescent display control on household electric appliances, audio
products, etc.
●Digit output ............................................................. 16 (maximum)
•Up to 16 pins can be selected
•More digits available by connecting additional M35501FPs
•Output structure: high-breakdown voltage, P-channel opendrain; built-in pull-down resistor between digit output pins and
VEE pin
●Power-on reset circuit ........................................................ Built-in
●Power source voltage ................................................ 4.0 to 5.5 V
●Pull-down power source voltage ................................ Vcc – 43 V
●Operating temperature range ................................... –20 to 85 °C
●Package ............................................................................. 24P2E
●Power dissipation .............. 250 µW (at 100 kHz operation clock)
DIG1
DIG2
DIG3
DIG4
DIG5
DIG6
DIG7
←
←
←
←
←
←
←
←
←
←
23
22
21
20
19
18
17
16
15
14
13
DIG9
DIG0
←
24
DIG8
VEE
→
DIG10
PIN CONFIGURATION (TOP VIEW)
→
→
→
SEL
OVFIN
OVFOUT
DIG15
DIG14
DIG13
DIG12
DIG11
VCC
→
CLK
7
→
VSS
6
→
4
←
5
←
3
←
2
←
1
RESET
M35501FP
8
9
10
11
12
Outline: 24P2E-A
24-pin plastic-molded SSOP
Fig. 3.12.1 Pin configuration of M35501FP
38B5 Group User’s Manual
3-91
APPENDIX
3.12 M35501FP
FUNCTIONAL BLOCK
DIG15 DIG14 DIG13 DIG12 DIG11 DIG10 DIG9 DIG8 DIG7 DIG6 DIG5 DIG4 DIG3 DIG2 DIG1 DIG0
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 VEE
OVFOUT 7
Shift register
OVFIN 6
VCC
3
VSS
1
RESET 4
Optional digit
counter
Power-on
reset
5
2
CLK SEL
Fig. 3.12.2 Functional block diagram
PIN DESCRIPTION
Table 3.12.1 Pin description
Pin
VCC, VSS
RESET
Name
Power source input
Reset input
CLK
Clock input
SEL
Select input
OVFIN
Overflow signal input
OVFOUT
Overflow signal output
DIG15–
DIG0
Digit output
VEE
Pull-down power source input
3-92
Function
Apply 4.0–5.5 V to Vcc, and 0V to Vss.
Reset internal shift register (built-in power-on reset
circuit).
Digit output varies according to rising edge of clock
input.
Use when specifying the number of digits.
Input “H” when using one M35501FP. Connect to
OVFOUT pin of additional M35501FPs when using
multiple M35501FPs (to use 17 digits or more).
Leave open when using one M35501FP. Connect to
OVFIN pin of additional M35501FPs when using multiple
M35501FPs (to use 17 digits or more).
Output the digit output waveform of fluorescent
display. Leave open when not in use (VEE level
output).
Apply voltage to DIG0–DIG15 pull-down resistors.
38B5 Group User’s Manual
Output Structure
–
CMOS input level
Built-in pull-up resistor
CMOS input level
Built-in pull-down resistor
CMOS input level
Built-in pull-down resistor
CMOS input level
Fig. No.
–
3
2
2
4
CMOS output
5
High-breakdown-voltage
P-channel open-drain output
Built-in pull-down resistor
–
1
–
APPENDIX
3.12 M35501FP
PORT BLOCK
(1) DIG0–DIG15
(2) SEL, CLK
Shift register
Pull-down transistor
VEE
(3) RESET
(4) OVFIN
Pull-up transistor
(5) OVFOUT
Shift register
Fig. 3.12.3 Port block diagram
38B5 Group User’s Manual
3-93
APPENDIX
3.12 M35501FP
USAGE
Three usages of the M35501FP are described below.
(1) 16-Digit Mode: 16 digits selected
The number of digits is set to 16 by fixing the OVFIN pin to “H” and
the SEL pin to “L.” Figure 3.12.5 shows the output waveform.
(2) Optional Digit Mode: 1-16 digits selectable
When the number of CLK pin rising edges during an “H” period of
the SEL pin is n and the OVFIN pin is fixed to “H,” the number of
digits set is n. If n is 16 or more, all 16 digits are set. Figure 3.12.6
shows the output waveform.
SEL pin
n
CLK pin
Fig. 3.12.4 Digit setting
(3) Cascade Mode: 17 digits or more selectable
17 digits or more can be used by connecting two M35501FPs or
more. Figure 3.12.7 shows an example using three M35501FPs, offering 33 to 48 digit outputs.
Cascade mode will not operate if all M35501FPs are in 16-digit
mode (SEL = “L”). Use the most significant M35501FP in the optional
digit mode for DIG output. Figure 3.12.8 shows the output waveform.
3-94
38B5 Group User’s Manual
APPENDIX
3.12 M35501FP
DIGIT OUTPUT WAVEFORM
SEL
“L”
CLK
DIG0
DIG1
DIG2
DIG13
DIG14
DIG15
OVFOUT
Fig. 3.12.5 16-digit mode output waveform
RESET
SEL
CLK
DIG0
DIG1
DIG2
DIG3
DIG4
“L”
DIG15
“L”
OVFOUT
Fig. 3.12.6 Optional digit mode output waveform
38B5 Group User’s Manual
3-95
APPENDIX
3.12 M35501FP
OVFIN(1)
RESET
CLK
Select signal
RESET
DIG 0
DIG 1
CLK
DIG 14
DIG 15
SEL
OVFOUT(1)
OVFIN(2)
RESET
DIG 16
DIG 17
CLK
DIG 30
DIG 31
SEL
OVFOUT(2)
OVFIN(3)
RESET
DIG 32
DIG 33
CLK
DIG 46
DIG 47
SEL
OVFOUT(3)
Fig. 3.12.7 Cascade mode connection example: 17 digits or more selected
CLK
RESET
DIG0
DIG1
DIG2
DIG15
OVFOUT(1)
DIG16
DIG17
DIG31
OVFOUT(2)
Fig. 3.12.8 Cascade mode output waveform
3-96
38B5 Group User’s Manual
APPENDIX
3.12 M35501FP
The number of fluorescent displays can be increased by connecting
the M35501FP to the CMOS FLD output pins on a 38B5 Group microcomputer.
Segment (high-breakdown-voltage: 36 pins + CMOS: 4 pins)
(1 pin used as CLK.)
P27–P20
M38B5X
Fluorescent Display (FLD)
P07–P00
P17–P10
P37–P30
P83 –P80
P84
SEL
M35501
Digits
DIG0 –DIG15
CLK
Fig. 3.12.9 Connection example with 38B5 Group microcomputer (1 to 16 digits)
This FLD controller can control up to 32 digits using the 32 timing
mode of the 38B5 Group microcomputer.
Segment (high-breakdown-voltage: 36 pins + CMOS: 4 pins)
(1 pin is used as CLK.)
P27–P20
M38B5X
P07–P00
Fluorescent Display (FLD)
P17–P10
P37–P30
P83–P80
P84
SEL
M35501
CLK
Digits
DIG0–DIG15
OVFOUT OVFIN
OVFIN OVFOUT
SEL
Digits
DIG16–DIG31
M35501
CLK
Fig. 3.12.10 Connection example with 38B5 Group microcomputer (17 to 32 digits)
38B5 Group User’s Manual
3-97
APPENDIX
3.12 M35501FP
RESET CIRCUIT
To reset the controller, the RESET pin should be held at “L” for 2
µs or more. Reset is released when the RESET pin is returned to
“H” and the power source voltage is between 4.0 V and 5.5 V.
Notes1: Perform the reset release when CLK input signal is “L.”
2: When setting the number of digits by SEL signal, optional digit
counter is set to “0” by reset.
RESET
CLK
DIG0
DIG1
DIG2
DIG3
Fig. 3.12.11 Digit output waveform when reset signal is input
3-98
38B5 Group User’s Manual
APPENDIX
3.12 M35501FP
POWER-ON RESET
Reset can be performed automatically during power on (power-on
reset) by the built-in power-on reset circuit. When using this circuit, set 100 µs or less for the period in which it takes to reach
minimum operation guaranteed voltage from reset.
If the rising time exceeds 100 µs, connect the capacitor between
the RESET pin and VSS at the shortest distance. Consequently,
the RESET pin should be held at “L” until the minimum operation
guaranteed voltage is reached.
VDD
Pull-up transistor
Power-on reset circuit
output voltage
RESET
pin
Power-on reset
circuit
Reset state
(Note)
Internal reset signal
Note:
This symbol represents a parasitic diode.
Applied voltage to the RESET pin must be VDD or less.
Reset released
Power-on
Fig. 3.12.12 Power-on reset circuit
38B5 Group User’s Manual
3-99
APPENDIX
3.12 M35501FP
Table 3.12.2 Absolute maximum ratings
Symbol
VCC
VEE
VI
VI
VO
VO
Pd
Topr
Tstg
Parameter
Power source voltage
Pull-down power source voltage
Input voltage CLK, SEL, OVFIN
Input voltage RESET
Output voltage DIG0–DIG15
Output voltage OVFOUT
Power dissipation
Operating temperature
Storage temperature
Conditions
Ratings
Unit
•All voltages are based on VSS.
•Output transistors are off.
–0.3 to 7.0
VCC –45 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VCC +0.3
VCC –45 to VCC +0.3
–0.3 to VCC +0.3
250
–20 to 85
–40 to 125
V
V
V
V
V
V
mW
°C
°C
Ta = 25 °C
Table 3.12.3 Recommended operating conditions (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
VCC
VSS
VEE
VIH
VIH
VIL
VIL
Parameter
Power source voltage
Power source voltage
Pull-down power source voltage
“H” input voltage CLK, SEL, OVFIN
“H” input voltage RESET
“L” input voltage CLK, SEL, OVFIN
“L” input voltage RESET
Min.
4.0
Limits
Typ.
5.0
0
VCC –43
0.8V CC
0.8V CC
0
0
Max.
5.5
VSS
VCC
VCC
0.2VCC
0.2VCC
Unit
V
V
V
V
V
V
V
Table 3.12.4 Recommended operating conditions (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
IOH(peak)
IOH(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
CLK
Parameter
“H” peak output current DIG0 – DIG15 (Note 1)
“H” peak output current OVFOUT (Note 1)
“L” peak output current OVF OUT (Note 1)
“H” average current DIG0 – DIG15 (Note 2)
“H” average current OVF OUT (Note 2)
“L” average current OVFOUT (Note 2)
Clock input frequency
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current is an average value measured over 100 ms.
3-100
38B5 Group User’s Manual
Limits
Min.
Typ.
Max.
–36
–10
10
–18
–5.0
5.0
2
Unit
mA
mA
mA
mA
mA
mA
MHz
APPENDIX
3.12 M35501FP
Table 3.12.5 Electrical characteristics (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
VOH
“H” output voltage
DIG output
DIG0–DIG15
OVFOUT
OVFOUT
CLK, OVFIN
RESET
OVFIN
RESET
CLK, SEL
VOH
VOL
VT+ — VT–
“H” output voltage
“L” output voltage
Hysteresis
IIH
“H” input current
IIH
“H” input current
IIL
“L” input current
IIL
“L” input current
OVFIN
CLK, SEL
RESET
ILOAD
Output load current
DIG0 – DIG15
ILEAK
Output leakage current
DIG0–DIG15
ICC
Power source
I OH = –18 mA
I OH = –10 mA
I OL = 10 mA
VCC = 5.0 V
Min.
VCC –2.0
Limits
Typ.
VCC –2.0
VI = V SS
VCC = 5.0 V
VEE = VCC –43 V
VOL = VCC
Output transistors are off.
VEE = VCC –43 V
VOL = VCC –43 V
Output transistors are off.
VCC = 5.0 V, CLK = 100 kHz
Output transistors are off.
38B5 Group User’s Manual
2.0
V
V
V
5.0
µA
140
µA
–5.0
µA
0.4
30
Unit
V
VI = V CC
VI = V CC
VCC = 5.0 V
VI = V SS
Max.
70
–60
–130
–185
µA
500
650
800
µA
–10
µA
50
µA
3-101
APPENDIX
3.12 M35501FP
Table 3.12.6 Timing requirements (VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
t w(RESET)
t c( CLK)
t wH(CLK)
t wL( CLK)
t su(SEL )
t h( SEL)
t h( CLK)
Parameter
Min.
2
500
200
200
500
500
500
Reset input “L” pulse width
Clock input cycle time
Clock input “H” pulse width
Clock input “L” pulse width
Select input setup time
Select input hold time
Clock input setup time
tw(RESET)
vcc
RESET
0.8V CC
vss
0.2V CC
tc(CLK)
twL(CLK)
twH(CLK)
vcc
CLK
0.2VCC
vss
0.8VCC
vcc
SEL
vss
vcc
CLK
vss
tsu(SEL)
th(SEL) th(CLK)
Fig. 3.12.13 Timing diagram
3-102
Limits
Typ.
38B5 Group User’s Manual
Max.
Unit
µs
ns
ns
ns
ns
ns
ns
APPENDIX
3.13 SFR memory map
3.13 SFR memory map
000016
Port P0 (P0)
002016
Timer 1 (T1)
000116
Port P0 direction register (P0D)
002116
Timer 2 (T2)
000216
Port P1 (P1)
002216
Timer 3 (T3)
000316
002316
Timer 4 (T4)
000416
Port P2 (P2)
002416
Timer 5 (T5)
000516
Port P2 direction register (P2D)
002516
Timer 6 (T6)
000616
Port P3 (P3)
002616
PWM control register (PWMCON)
000716
002716
Timer 6 PWM register (T6PWM)
000816
Port P4 (P4)
002816
Timer 12 mode register (T12M)
000916
Port P4 direction register (P4D)
002916
Timer 34 mode register (T34M)
000A16
Port P5 (P5)
002A16
Timer 56 mode register (T56M)
000B16
Port P5 direction register (P5D)
002B16
Watchdog timer control register (WDTCON)
000C16
Port P6 (P6)
002C16
Timer X (low-order) (TXL)
000D16
Port P6 direction register (P6D)
002D16
Timer X (high-order) (TXH)
000E16
Port P7 (P7)
002E16
Timer X mode register 1 (TXM1)
000F16
Port P7 direction register (P7D)
002F16
Timer X mode register 2 (TXM2)
001016
Port P8 (P8)
003016
Interrupt interval determination register (IID)
001116
Port P8 direction register (P8D)
003116
Interrupt interval determination control register (IIDCON)
001216
Port P9 (P9)
003216
A-D control register (ADCON)
001316
Port P9 direction register (P9D)
003316
A-D conversion register (low-order) (ADL)
001416
PWM register (high-order) (PWMH)
003416
A-D conversion register (high-order) (ADH)
001516
PWM register (low-order) (PWM L)
003516
001616
Baud rate generator (BRG)
003616
001716
UART control register (UARTCON)
003716
001816
Serial I/O1 automatic transfer data pointer (SIO1DP)
003816
001916
Serial I/O1 control register 1 (SIO1CON1)
003916
Interrupt source switch register (IFR)
001A16
Serial I/O1 control register 2 (SIO1CON2)
003A16
Interrupt edge selection register (INTEDGE)
001B16
Serial I/O1 register/Transfer counter (SIO1)
003B16
CPU mode register (CPUM)
001C16
Serial I/O1 control register 3 (SIO1CON3)
003C16
Interrupt request register 1(IREQ1)
001D16
Serial I/O2 control register (SIO2CON)
003D16
Interrupt request register 2(IREQ2)
001E16
Serial I/O2 status register (SIO2STS)
003E16
Interrupt control register 1(ICON1)
001F16
Serial I/O2 transmit/receive buffer register (TB/RB)
003F16
Interrupt control register 2(ICON2)
0EF016
Pull-up control register 1 (PULL1)
0EF816
FLD data pointer (FLDDP)
0EF116
Pull-up control register 2 (PULL2)
0EF916
Port P0FLD/port switch register (P0FPR)
0EF216
P1FLDRAM write disable register (P1FLDRAM)
0EFA16
Port P2FLD/port switch register (P2FPR)
0EF316
P3FLDRAM write disable register (P3FLDRAM)
0EFB16
Port P8FLD/port switch register (P8FPR)
0EF416
FLDC mode register (FLDM)
0EFC16 Port P8FLD output control register (P8FLDCON)
0EF516
Tdisp time set register (TDISP)
0EFD16 Buzzer output control register (BUZCON)
0EF616
Toff1 time set register (TOFF1)
0EFE16
0EF716
Toff2 time set register (TOFF2)
0EFF16
38B5 Group User’s Manual
3-103
APPENDIX
3.14 Pin configuration
41
43
42
45
44
47
46
49
48
50
52
51
54
53
56
55
58
57
60
59
62
61
64
65
66
40
67
39
38
68
37
69
36
70
35
71
34
33
72
M38B5xMxH-XXXXFP
73
32
74
31
75
30
76
29
77
28
78
27
79
80
26
24
23
22
21
20
19
18
17
15
16
13
14
11
12
9
10
8
7
4
5
6
3
P30/FLD24
P31/FLD25
P32/FLD26
P33/FLD27
P34/FLD28
P35/FLD29
P36/FLD30
P37/FLD31
P80/FLD32
P81/FLD33
P82/FLD34
P83/FLD35
VEE
P84/FLD36
P85/RTP0/FLD37
P86/RTP1/FLD38
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
P61/CNTR0/CNTR2
(Note) P60/CNTR1
P47/INT2
RESET
P91/XCOUT
P90/XCIN
Vss
XIN
XOUT
Vcc
P46/T3OUT
P45/T1OUT
P44/PWM1
P43/BUZ01
(Note) P42/INT3
P41/INT1
P40/INT0
P87/PWM0/FLD39
2
25
1
P57/SRDY2/ SCLK22
P56/SCLK21
P55/TxD
P54/RxD
P53/SCLK12
P52/SCLK11
P51/SOUT1
P50/SIN1
AVSS
VREF
P65/SSTB1/AN11
P64/INT4/SBUSY1 /AN10
P63/AN9
P62/SRDY1/AN8
P77/AN7
P76/AN6
63
P20/BUZ02/FLD0
P21/FLD1
P22/FLD2
P23/FLD3
P24/FLD4
P25/FLD5
P26/FLD6
P27/FLD7
P00/FLD8
P01/FLD9
P02/FLD10
P03/FLD11
P04/FLD12
P05/FLD13
P06/FLD14
P07/FLD15
P10/FLD16
P11/FLD17
P12/FLD18
P13/FLD19
P14/FLD20
P15/FLD21
P16/FLD22
P17/FLD23
3.14 Pin configuration
Note: In the mask option type P, INT3 and CNTR1 cannot be used.
(Top view)
Package type: 80P6N-A
80-pin plastic molded QFP
3-104
38B5 Group User’s Manual
MITSUBISHI SEMICONDUCTORS
USER’S MANUAL
38B5 Group
Nov. First Edition 1998
Editioned by
Committee of editing of Mitsubishi Semiconductor USER’S MANUAL
Published by
Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission
of Mitsubishi Electric Corporation.
©1998 MITSUBISHI ELECTRIC CORPORATION
User’s Manual
38B5 Group
MITSUBISHI ELECTRIC CORPORATION
HEAD OFFICE: MITSUBISHI DENKI BLDG., MARUNOUCHI, TOKYO 100. TELEX: J24532 CABLE: MELCO TOKYO
© 1998 MITSUBISHI ELECTRIC CORPORATION.
New publication, effective Nov. 1998.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev.
No.
1.0
38B5 Group User’s Manual
Revision Description
First Edition
Rev.
date
981202
(1/1)