ee Fr ad HS t e L Ro plian m Co C18xx Model 5X7 mm SMD, 1.8V, LVCMOS Frequency Range: Frequency Stability: Temperature Range: Operating: (Option M) Storage: Input Voltage: Input Current: Output: Symmetry: Rise/Fall Time: Logic: Clock Oscillator 1MHz to 100MHz ±20ppm to ±100ppm Load: Jitter RMS: 12KHz~20MHz 0°C to 70°C -20°C to 70°C -55°C to 120°C 1.8V ± 0.2V 30mA Max @ 15pF LVCMOS 45/55% Max @ 50% Vdd 1ns Typ, 3.5ns Max "0" = 10% Vdd Max "1" = 90% Vdd Min 15pF Max 0.5ps Typ, 1ps Max Aging: <3ppm 1st/yr, 1ppm every year thereafter SUGGESTED PAD LAYOUT Dimensions inches (mm) All dimensions are Max unless otherwise specified. .283 Max (7.20) P/N DC Freq Designed to meet today's requirements for low voltage applications. The power saving sleep function of the C18xx turns the oscillator circuit off for maximum efficiency. Available on 16mm tape and reel in quantities of 1K. .055 Typ. (1.40 Typ.) .204 Max (5.02) .075 Max (1.80) #1 #2 #4 #3 .071 SQ (1.80) .165 (4.19) .045 ±.008 (1.14 ±.20) .200 ±.005 (5.08 ±.13) Denotes pad 1 .200 (5.08) 0.01uF Bypass Capacitor Recommended TEMPERATURE RECOMMENDED REFLOW SOLDERING PROFILE Ramp-Up 3°C/Sec Max. 260°C Critical Temperature Zone Crystek Part Number Guide Ramp-Down 6°C/Sec. 217°C Example: C1892-44.736MHZ Example: CM1892-44.736MHZ 200°C 150°C Temperature Preheat 180 Secs. Max. 8 Minutes Max. 90 Secs. Max. 260°C for 10 Secs. Max. Frequency Stability 0/ 70°C -20/ 70°C -40/ 85°C C1890 C1892 C1891 C1898 CM1890 CM1892 CM1891 NA CE1890 +/- 100ppm CE1892 +/- 50ppm CE1891 +/- 25ppm NA +/- 20ppm NOTE: Reflow Profile with 240°C peak also acceptable. OUT mA M pin 3 pin 4 Vdd PWR Supply VM Bypass Cap. pin 1 High Impedance GND or "LOW" OUT O/P Load incl Probe Cl OSC. GND pin 2 Oscillation OPEN or "HIGH" Tri-State Function Function pin 1 Output pin Open "1" level 0.7V Min "0" level 0.3V Max Active Active High Z Specifications subject to change without notice. TD-02061 Rev.H