Revised May 2005 MM74HCT573 • MM74HCT574 Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop General Description Features The MM74HCT573 octal D-type latches and MM74HCT574 octal D-type flip-flop advanced silicon-gate CMOS technology, which provides the inherent benefits of low power consumption and wide power supply range, but are LS-TTL input and output characteristic and pin-out compatible. The 3-STATE outputs are capable of driving 15 LS-TTL loads. All inputs are protected from damage due to static discharge by internal diodes to VCC and ground. ■ TTL input characteristic compatible ■ Typical propagation delay: 18 ns ■ Low input current: 1 PA maximum ■ Low quiescent current: 80 PA maximum ■ Compatible with bus-oriented systems ■ Output drive capability: 15 LS-TTL loads When the MM74HCT573 Latch Enable input is HIGH, the Q outputs will follow the D inputs. When the Latch Enable goes LOW, data at the D inputs will be retained at the outputs until Latch Enable returns HIGH again. When a high logic level is applied to the Output Control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The MM74HCT574 are positive edge triggered flip-flops. Data at the D inputs, meeting the setup and hold time requirements, are transferred to the Q outputs on positive going transitions of the Clock (CK) input. When a high logic level is applied to the Output Control (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs. Ordering Codes: Order Number Package Number MM74HCT573WM M20B MM74HCT573SJ MM74HCT573MTC M20D MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HCT573N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide MM74HCT574WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide MM74HCT574SJ MM74HCT574MTC MM74HCT574N M20D MTC20 N20A 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. © 2005 Fairchild Semiconductor Corporation DS010627 www.fairchildsemi.com MM74HCT573 • MM74HCT574 Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop February 1990 MM74HCT573 • MM74HCT574 Connection Diagrams Truth Tables MM74HCT573 Output Control LE Data Output L H H H L H L L L L X Q0 H X X Z H HIGH Level L LOW Level Q0 Level of output before steady-state input conditions were established. Z High Impedance State Top View MM74HCT573 MM74HCT574 Output Control LE Data Output H H L n n L L L L X Q0 H X X Z L H L Q0 X Z n Top View MM74HCT574 www.fairchildsemi.com 2 HIGH Level LOW Level Level of output before steady-state input conditions were established. Don’t Care High Impedance State Transition from LOW-to-HIGH Recommended Operating Conditions Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) 0.5 to 7.0V 1.5 to VCC 1.5V 0.5 to VCC 0.5V r 20 mA r 35 mA r 70 mA 65qC to 150qC 600 mW S. O. Package only 500 mW Max Units 4.5 5.5 V 0 VCC V 40 85 qC 500 ns DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times tr, tf Power Dissipation (PD) (Note 3) Min Supply Voltage (VCC) Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: 12 mW/qC from 65qC to 85qC. Lead Temperature (TL) 260qC (Soldering 10 seconds) DC Electrical Characteristics VCC 5V r 10% (unless otherwise specified) Symbol VIH Parameter TA Conditions 25qC Typ Minimum HIGH Level TA 40 to 85qC TA 55 to 125qC Guaranteed Limits Units 2.0 2.0 2.0 V 0.8 0.8 0.8 V Input Voltage VIL Maximum LOW Level Input Voltage VOH VOL IIN IOZ Minimum HIGH Level VIN Output Voltage |IOUT| VIH or VIL 20 PA VCC VCC 0.1 VCC 0.1 VCC 0.1 |IOUT| 6.0 mA, VCC 4.5V 4.2 3.98 3.84 3.7 |IOUT| 7.2 mA, VCC 5.5V 5.7 4.98 4.84 4.7 V Maximum LOW Level VIN Voltage |IOUT| VIH or VIL 20 PA 0 0.1 0.1 0.1 |IOUT| 6.0 mA, VCC 4.5V 0.2 0.26 0.33 0.4 |IOUT| 7.2 mA, VCC 5.5V 0.2 0.26 0.33 0.4 r0.1 r1.0 r1.0 PA r0.5 r5.0 r10 PA 8.0 80 160 PA 1.5 1.8 2.0 mA Maximum Input VIN Current VIH or VIL VCC or GND, Maximum 3-STATE VOUT Output Leakage Enable VCC or GND V VIH or VIL Current ICC Maximum Quiescent VIN Supply Current IOUT VIN VCC or GND 0 PA 2.4V or 0.5V (Note 4) Note 4: Measured per pin. All others tied to VCC or ground. 3 www.fairchildsemi.com MM74HCT573 • MM74HCT574 Absolute Maximum Ratings(Note 1) (Note 2) MM74HCT573 • MM74HCT574 AC Electrical Characteristics MM74HCT573 VCC 5.0V, tr tf 6 ns, TA 25qC (unless otherwise specified) Symbol Parameter Typ Guaranteed Limit Units CL 45 pF 17 27 ns CL 45 pF 16 27 ns tPZH Maximum Enable Propagation Delay CL 45 pF 21 30 ns tPZL Control to Output RL 1 k: tPHZ Maximum Disable Propagation Delay CL 5 pF 14 23 ns tPLZ Control to Output 1 k: tPHL Maximum Propagation Delay tPLH Data to Output tPHL Maximum Propagation Delay tPLH Latch Enable to Output Conditions RL tW Minimum Clock Pulse Width 15 ns tS Minimum Setup Time Data to Clock 5 ns tH Minimum Hold Time Clock to Data 12 ns AC Electrical Characteristics MM74HCT573 VCC 5.0V r 10%, tr tf Symbol 6 ns (unless otherwise specified) Parameter tPHL Maximum Propagation tPLH Delay Data to Output tPHL Maximum Propagation Delay tPLH Latch Enable to Output tPZH tPZL TA Conditions 25q TA Typ 40 to 85qC TA 55 to 125qC Guaranteed Limits Units CL 50 pF 18 30 38 45 ns CL 50 pF 17 30 44 53 ns Maximum Enable Propagation CL 50 pF 22 30 38 45 ns Delay Control to Output RL 1 k: 15 30 38 45 ns 6 12 15 18 ns tPHZ Maximum Disable Propagation CL 50 pF tPLZ Delay Control to Output RL 1 k: CL 50 pF tTHL Maximum Output tTLH Rise and Fall Time tW Minimum Clock Pulse Width 15 20 24 ns tS Minimum Setup Time Data to Clock 3 5 6 8 ns tH Minimum Hold Time Clock to Data 4 12 15 18 ns CIN Maximum Input Capacitance 10 10 10 pF COUT Maximum Output Capacitance 20 20 20 CPD Power Dissipation Capacitance OC VCC (Note 5) OC GND Note 5: CPD determines the no load dynamic power consumption, PD IS CPD VCC fICC. www.fairchildsemi.com 5 52 CPD VCC2 fICC VCC, and the no load dynamic current consumption, 4 pF pF VCC 5.0V, tr tf MM74HCT573 • MM74HCT574 AC Electrical Characteristics MM74HCT574 6 ns, TA 25qC Symbol Parameter fMAX Maximum Clock Frequency tPHL Maximum Propagation Delay tPLH to Output tPZH tPZL Conditions Typ Guaranteed Limit Units 60 33 MHz CL 45 pF 17 27 ns Maximum Enable Propagation Delay CL 45 pF 19 28 ns Control to Output RL 1 k: tPHZ Maximum Disable Propagation Delay CL 45 pF 14 25 ns tPLZ Control to Output RL 1 k: tW Minimum Clock Pulse Width 15 ns tS Minimum Setup Time Data to Clock 12 ns tH Minimum Hold Time Clock to Data 5 ns AC Electrical Characteristics MM74HCT574 VCC 5.0V r 10%, tr Symbol tf 6 ns (unless otherwise specified) Parameter Conditions TA 25qC Typ fMAX Maximum Clock Frequency tPHL Maximum Propagation Delay tPLH Clock to Output tPZH tPZL TA 40 to 85qC TA 55 to 125qC Units Guaranteed Limits 33 28 23 MHz CL 50 pF 18 30 38 45 ns Maximum Enable Propagation CL 50 pF 22 30 38 45 ns Delay Control to Output RL 1 k: 15 30 38 45 ns 6 12 15 18 ns ns tPHZ Maximum Disable Propagation CL 50 pF tPLZ Delay Control to Output RL 1 k: CL 50 pF tTHL Maximum Output tTLH Rise and Fall Time tW Minimum Clock Pulse Width 15 20 24 tS Minimum Setup Time Data to Clock 6 12 15 18 ns tH Minimum Hold Time Clock to Data 1 5 6 8 ns CIN Maximum Input Capacitance 10 10 10 pF COUT Maximum Output Capacitance 20 20 20 pF CPD Power Dissipation Capacitance OC V CC 5 (Note 6) OC GND 58 Note 6: CPD determines the no load power consumption, PD pF CPD VCC2 f ICC VCC, and the no load dynamic current consumption, IS 5 CPD VCC f ICC. www.fairchildsemi.com MM74HCT573 • MM74HCT574 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B www.fairchildsemi.com 6 MM74HCT573 • MM74HCT574 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 7 www.fairchildsemi.com MM74HCT573 • MM74HCT574 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 www.fairchildsemi.com 8 MM74HCT573 • MM74HCT574 Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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