AD AD8346 0.8 ghz-2.5 ghz quadrature modulator Datasheet

a
FEATURES
High Accuracy
1 Degree rms Quadrature Error @ 1.9 GHz
0.2 dB I/Q Amplitude Balance @ 1.9 GHz
Broad Frequency Range: 0.8 GHz–2.5 GHz
Sideband Suppression: –46 dBc @ 0.8 GHz
Sideband Suppression: –36 dBc @ 1.9 GHz
Modulation Bandwidth: DC–70 MHz
0 dBm Output Compression Level @ 0.8 GHz
Noise Floor: –147 dBm/Hz
Single 2.7 V–5.5 V Supply
Quiescent Operating Current: 45 mA
Standby Current: 1 ␮A
16-Lead TSSOP Package
0.8 GHz–2.5 GHz
Quadrature Modulator
AD8346
FUNCTIONAL BLOCK DIAGRAM
IBBP
1
16
QBBP
IBBN
2
15
QBBN
COM1
3
14
COM4
COM1
4
13
COM4
LOIN
5
12
VPS2
LOIP
6
VPS1
7
ENBL
PHASE
SPLITTER
11 VOUT
10 COM3
AD8346
8
BIAS
9
COM2
APPLICATIONS
Digital and Spread Spectrum Communication Systems
Cellular/PCS/ISM Transceivers
Wireless LAN/Wireless Local Loop
QPSK/GMSK/QAM Modulators
Single-Sideband (SSB) Modulators
Frequency Synthesizers
Image Reject Mixer
PRODUCT DESCRIPTION
The AD8346 is a silicon RFIC I/Q modulator for use from
0.8 GHz to 2.5 GHz. Its excellent phase accuracy and amplitude balance allow high performance direct modulation to RF.
The differential LO input is applied to a polyphase network
phase splitter that provides accurate phase quadrature from
0.8 GHz to 2.5 GHz. Buffer amplifiers are inserted between
two sections of the phase splitter to improve the signal-to-noise
ratio. The I and Q outputs of the phase splitter drive the LO
inputs of two Gilbert-cell mixers. Two differential V-to-I converters connected to the baseband inputs provide the baseband
modulation signals for the mixers. The outputs of the two mixers
are summed together at an amplifier which is designed to drive a
50 Ω load.
This quadrature modulator can be used as the transmit modulator in digital systems such as PCS, DCS, GSM, CDMA, and
ISM transceivers. The baseband quadrature inputs are directly
modulated by the LO signal to produce various QPSK and
QAM formats at the RF output.
Additionally, this quadrature modulator can be used with direct
digital synthesizers in hybrid phase-locked loops to generate
signals over a wide frequency range with millihertz resolution.
The AD8346 is supplied in a 16-lead TSSOP package, measuring 6.5 × 5.1 × 1.1 mm. It is specified to operate over a
–40°C to +85°C temperature range and 2.7 V to 5.5 V supply
voltage range. The device is fabricated on Analog Devices’ high
performance 25 GHz bipolar silicon process.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
(V = 5 V; T = +25ⴗC, LO frequency = 1900 MHz; LO level = –10 dBm; BB frequency
AD8346–SPECIFICATIONS
= 100 kHz; BB inputs are dc biased to 1.2 V; BB input level = 1.0 V p-p each pin for 2.0 V p-p differential drive; LO source and RF output load
S
A
impedances are 50 ⍀, dBm units are referenced to 50 ⍀ unless otherwise noted.)
Parameters
RF OUTPUT
Operating Frequency
Quadrature Phase Error
I/Q Amplitude Balance
Output Power
Output VSWR
Output P1 dB
Carrier Feedthrough
Sideband Suppression
IM3 Suppression
Equivalent Output IP3
Output Noise Floor
Conditions
Min
Typ
0.8
(See Figure 29 for Setup)
(See Figure 29 for Setup)
I and Q Channels in Quadrature
Max
Units
2.5
GHz
Degree rms
dB
dBm
20 MHz Offset from LO
1
0.2
–10
1.25:1
–3
–42
–36
–60
+20
–147
RESPONSE TO CDMA IS95
BASEBAND SIGNALS
ACPR (Adjacent Channel Power Ratio)
EVM (Error Vector Magnitude)
Rho (Waveform Quality Factor)
(See Figure 29 for Setup)
(See Figure 29 for Setup)
(See Figure 29 for Setup)
–72
2.5
0.9974
dBc
%
MODULATION INPUT
Input Resistance
Modulation Bandwidth
–3 dB
12
70
kΩ
MHz
LO INPUT
LO Drive Level
Input VSWR
ENABLE
ENBL HI Threshold
ENBL LO Threshold
ENBL Turn-On Time
ENBL Turn-Off Time
–13
–12
–6
–35
–25
dBm
dBm
dBc
dBc
dBm
dBm/Hz
–6
dBm
2.0
V
V
1.9:1
0.5
Settle to Within 0.5 dB of Final
SSB Output Power
Time for Supply Current to Drop
Below 2 mA
POWER SUPPLIES
Voltage
Current Active (ENBL HI)
Current Standby (ENBL LO)
2.7
35
2.5
µs
12
µs
45
1
5.5
55
20
V
mA
µA
Specifications subject to change without notice.
–2–
REV. 0
AD8346
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may effect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage VPS1, VPS2 . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Input Power LOIP, LOIN (re. 50 Ω) . . . . . . . . . . . . +10 dBm
Min Input Voltage IBBP, IBBN, QBBP, QBBN . . . . . . . . 0 V
Max Input Voltage IBBP, IBBN, QBBP, QBBN . . . . . . . 2.5 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 500 mW
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C/W
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8346 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model
Temperature Range
Package Description
AD8346ARU
AD8346ARU-REEL
AD8346ARU-REEL7
AD8346-EVAL
–40°C to +85°C
Tube (16-Lead TSSOP) Thin Shrink Small Outline Package
13" Tape and Reel
7" Tape and Reel
Evaluation Board
PIN CONFIGURATION
IBBP 1
16
IBBN 2
15
QBBP
QBBN
COM1 3
14
COM4
AD8346 13 COM4
TOP VIEW
LOIN 5 (Not to Scale) 12 VPS2
COM1 4
REV. 0
LOIP 6
11
VPS1 7
10
COM3
ENBL 8
9
COM2
–3–
VOUT
Package
Option
RU-16
AD8346
PIN FUNCTION DESCRIPTIONS
Equivalent
Circuit
Pin
Name
Description
1
IBBP
2
IBBN
3
4
5
COM1
COM1
LOIN
6
LOIP
7
VPS1
8
9
10
11
12
ENBL
COM2
COM3
VOUT
VPS2
13
14
15
COM4
COM4
QBBN
16
QBBP
I Channel Baseband Positive Input Pin. Input should be dc biased to approximately 1.2 V.
Nominal characterized ac swing is 1 V p-p (0.7 V to 1.7 V). This makes the differential
input 2 V p-p when IBBN is 180 degrees out of phase from IBBP.
I Channel Baseband Negative Input Pin. Input should be dc biased to approximately 1.2 V.
Nominal characterized ac swing is 1 V p-p (0.7 V to 1.7 V). This makes the differential
input 2 V p-p when IBBN is 180 degrees out of phase from IBBP.
Ground pin for the LO phase splitter and LO buffers.
Ground pin for the LO phase splitter and LO buffers.
LO Negative Input Pin. Internal dc bias (approximately VPS1–800 mV) is supplied. This
pin must be ac coupled.
LO Positive Input Pin. Internal dc bias (approximately VPS1–800 mV) is supplied. This
pin must be ac coupled.
Power supply pin for the bias cell and LO buffers. This pin should be decoupled using
local 100 pF and 0.01 µF capacitors.
Enable Pin. A high level enables the device; a low level puts the device in sleep mode.
Ground pin for the input stage of output amplifier.
Ground pin for the output stage of output amplifier.
50 Ω DC Coupled RF Output. User must provide ac coupling on this pin.
Power supply pin for Baseband input voltage to current converters and mixer core. This pin
should be decoupled using local 100 pF and 0.01 µF capacitors.
Ground pin for Baseband input voltage to current converters and mixer core.
Ground pin for Baseband input voltage to current converters and mixer core.
Q Channel Baseband Negative Input. Input should be dc biased to approximately 1.2 V.
Nominal characterized ac swing is 1 V p-p. This makes the differential input 2 V p-p when
QBBN is 180 degrees out of phase from QBBP.
Q Channel Baseband Positive Input. Input should be dc biased to approximately 1.2 V.
Nominal characterized ac swing is 1 V p-p. This makes the differential input 2 V p-p when
QBBN is 180 degrees out of phase from QBBP.
VPS2
Circuit A
Circuit A
Circuit B
Circuit B
Circuit C
Circuit D
Circuit A
Circuit A
VPS1
BUFFER
TO MIXER
CORE
75kV
TO BIAS FOR
STARTUP/
SHUTDOWN
75kV
9kV
INPUT
30kV
ENBL
3kV
40kV
ACTIVE LOADS
Circuit A
780V
Circuit C
VPS2
VPS1
LOIN
43V
PHASE
SPLITTER
CONTINUES
VOUT
LOIP
43V
Circuit B
Circuit D
Figure 1. Equivalent Circuits
–4–
REV. 0
Typical Performance Characteristics–AD8346
–6
T = +258C
VP = +5.5V
–9
VP = +5V
–10
VP = +3V
–11
VP = +2.7V
–12
–13
–7
LO = 800MHz, –10dBm
–8
LO = 1900MHz, –6dBm
–9
–10
–11
LO = 1900MHz, –10dBm
–12
–14
–15
–40 –30 –20 –10 0
Figure 2. Single Sideband (SSB) Output Power (POUT) vs. LO frequency
(FLO). I and Q inputs driven in quadrature at Baseband Freq (FBB) =
100 kHz with differential amplitude
of 2.00 V p-p.
–41
–45
VP = +2.7V
–49
–40 –30 –20 –10 0
Figure 4. Carrier Feedthrough vs.
Temperature. FLO = 1900 MHz, LO
input level = –10 dBm.
–2
–3
–4
–5
–6
–6
25
VP = +5V
T = –408C
–2
–4
30
PERCENTAGE
SSB OUTPUT P1dB – dBm
–1
VP = +2.7V
T = –408C
–8
VP = +2.7V
T = +858C
–10
–14
100
Figure 5. I and Q Input Bandwidth.
FLO =1900 MHz, I or Q inputs driven
with differential amplitude of 2.00 V
p-p.
10
–90 –86 –82 –78 –74 –70 –66 –62 –58 –54 –50 –46
Figure 6. SSB Output 1 dB Compression Point (OP 1 dB) vs. FLO. I and Q
inputs driven in quadrature at FBB =
100 kHz.
CARRIER FEEDTHROUGH – dBm/
AFTER NULLING TO <–60dBm @ 258C
Figure 7. Histogram showing
Carrier Feedthrough distributions at
the temperature extremes after nulling at ambient at FLO = 1900 MHz,
LO input level = –10 dBm.
–32
VP = +3V
–10
VP = +5V
–12
VP = +2.7V
–13
–14
CARRIER FEEDTHROUGH – dBm
VP = +5.5V
–9
T = +258C
T = +258C
VP = +5.5V
–38
–40
VP = +3V
–42
–44
–46
VP = +5V
–48
VP = +2.7V
–50
–52
–54
–40 –30 –20 –10 0
10 20 30 40 50 60 70 80
TEMPERATURE – 8C
Figure 8. SSB POUT vs. Temperature.
FLO = 1900 MHz, I and Q inputs
driven in quadrature with differential amplitude of 2.00 V p-p at FBB =
100 kHz.
REV. 0
15
LO FREQUENCY – MHz
–36
–8
–15
20
0
800 1000 1200 1400 1600 1800 2000 2200 2400
–7
–11
T = +858C
T = –408C
5
–12
–7
10 20 30 40 50 60 70 80
TEMPERATURE – 8C
VP = +5V
T = +858C
0
0
1
10
BASEBAND FREQUENCY – MHz
VP = +3V
–47
2
1
–8
0.1
VP = +5V
–43
10 20 30 40 50 60 70 80
Figure 3. SSB POUT vs. Temperature.
I and Q inputs driven in quadrature
with differential amplitude of 2.00 V
p-p at FBB = 100 kHz.
2
OUTPUT POWER VARIATION – dB
VP = +5.5V
–39
TEMPERATURE – 8C
LO FREQUENCY – MHz
SSB OUTPUT POWER – dBm
–37
–51
–13
800 1000 1200 1400 1600 1800 2000 2200 2400
SIDEBAND SUPPRESSION – dBc
SSB POWER – dBm
–8
SSB OUTPUT POWER – dBm
–7
–35
LO = 800MHz, –6dBm
CARRIER FEEDTHROUGH – dBm
–6
VP = +5.5V
–34
–36
VP = +5V
–38
–40
VP = +3V
–42
–44
VP = +2.7V
–46
–48
800 1000 1200 1400 1600 1800 2000 2200 2400
LO FREQUENCY – MHz
Figure 9. Carrier Feedthrough vs. FLO.
LO input level = –10 dBm.
–5–
900 1100 1300 1500 1700 1900 2100 2300 2500
LO FREQUENCY – MHz
Figure 10. Sideband Suppression
vs. FLO. VPOS = 2.7 V, I and Q inputs
driven in quadrature with differential
amplitude of 2.00 V p-p at FBB =
100 kHz.
AD8346
–30
–2
–32
–40
VP = +5.5V
VP = +3V
–36
VP = +5V
VP = +2.7V
–40
–60
–70
VP = +5.5V
SSB POUT
INPUT THIRD HARMONIC
DISTORTION – dBc
–32
SB SUPPRESSION – dBc
FREQUENCY – MHz
–30
VP = +3V
VP = +5.5V
VP = +2.7V
VP = +5V
–38
–40
–42
10 20 30 40 50 60 70 80
–8
–5
–12
–50
–55
–14
–60
–16
–65
–18
3RD HARMONIC
–70
1
1.5
2
2.5
BASEBAND DIFFERENTIAL INPUT
VOLTAGE – VP-P
–10
–15
T = –408C
–20
–25
–30
–20
–35
–22
–40
T = +258C
T = +858C
800 1000 1200 1400 1600 1800 2000 2200 2400
3
FREQUENCY – MHz
Figure 15. 3rd Harmonic Distortion
and SSB Output Power vs. Baseband
differential input voltage level. FLO
=1900 MHz, I and Q inputs driven in
quadrature at FBB = 100 kHz.
–40
0
–10
TEMPERATURE – 8C
Figure 14. Sideband Suppression vs.
Temperature. FLO = 1900 MHz, I and
Q inputs driven in quadrature with
differential amplitude of 2.00 V p-p at
FBB = 100 kHz.
–6
–45
–80
0.5
–44
Figure 13. Return Loss of LOIN Input
vs. F LO. VPOS = 5.0 V, LOIP pin ac
coupled to ground.
–40
–75
–40 –30 –20 –10 0
–14
800 1000 1200 1400 1600 1800 2000 2200 2400
10 20 30 40 50 60 70 80
–35
–36
T = +858C
–12
–18
Figure 12. 3rd Harmonic Distortion
vs. Temperature. FLO =1900 MHz,
I and Q inputs driven in quadrature
with differential amplitude of 2.00 V
p-p at FBB = 100 kHz.
–30
–34
–8
–10
TEMPERATURE – 8C
Figure 11. Sideband Suppression vs.
FBB. FLO = 1900 MHz, I and Q inputs
driven in quadrature with differential
amplitude of 2.00 V p-p.
T = +258C
–20
–40 –30 –20 –10 0
20
T = –408C
–6
–16
–44
4
6
8 10 12 14 16 18
BASEBAND FREQUENCY – MHz
VP = +3V
–55
–65
2
VP = +2.7V
–50
–42
0
VP = +5V
RETURN LOSS – dB
–38
–4
–45
SSB OUTPUT POWER – dBm
–34
RETURN LOSS – dB
INPUT THIRD HARMONIC
DISTORTION – dBc
SB SUPPRESSION – dBc
0
–35
Figure 16. Return Loss of VOUT Output vs. FLO. VPOS = 2.7 V.
52
0
50
–5
VP = +3V
–50
VP = +5.5V
–55
VP = +5V
48
RETURN LOSS – dB
–45
SUPPLY CURRENT – mA
INPUT THIRD HARMONIC
DISTORTION – dBc
VP = +2.7V
VP = +5.5V
46
VP = +5V
44
42
VP = +3V
–10
–15
–20
–25
–30
40
–60
T = –408C
T = +258C
VP = +2.7V
–35
38
–65
0
2
4
6
8 10 12 14 16 18
BASEBAND FREQUENCY – MHz
20
Figure 17. 3rd Harmonic Distortion
vs. FBB. FLO =1900 MHz, I and Q inputs
driven in quadrature with differential
amplitude of 2.00 V p-p.
36
–40
T = +858C
–40
–20
0
20
40
60
TEMPERATURE – 8C
80
Figure 18. Power Supply Current vs.
Temperature
–6–
800 1000 1200 1400 1600 1800 2000 2200 2400
FREQUENCY – MHz
Figure 19. Return Loss of VOUT Output vs. FLO. VPOS = 5.0 V.
REV. 0
AD8346
the phase-splitters. The outputs of the second phase-splitter are
fed into the driver amplifiers for the mixers’ LO inputs.
CIRCUIT DESCRIPTION
OVERVIEW
The AD8346 can be divided into the following sections: Local
Oscillator (LO) Interface, Mixer, Voltage-to-Current (V-to-I)
Converter, Differential-to-Single-ended (D-to-S) Converter,
and Bias. A detailed block diagram of the part is shown in Figure 20.
V-to-I Converter
The LO Interface generates two LO signals, with 90 degrees of
phase difference between them, to drive two mixers in quadrature. Baseband voltage signals are converted into current form
in the V-to-I converters, feeding into two mixers. The output of
the mixers are combined to feed the D-to-S converter which
provides the 50 Ω output interface. Bias currents to each section
are controlled by the Enable (ENBL) signal. Detailed description of each section follows.
Mixers
Each baseband input pin is connected to an op amp driving an
emitter follower. Feedback at the emitter maintains a current
proportional to the input voltage through the transistor. This
current is fed to the two mixers in differential form.
There are two double-balanced mixers, one for the In-Phase
Channel (I-channel) and one for the Quadrature Channel (Qchannel). Each mixer uses the Gilbert-cell design with four
cross-connected transistors. The bases of the transistors are
driven by the LO signal of the corresponding channel. The
output currents from the two mixers are summed together in
two resistors in series with two coupled on-chip inductors. The
signal developed across the R-L loads are sent to the D-to-S stage.
LO Interface
The differential LO inputs allow the user to drive the LO differentially in order to achieve maximum performance. The LO can
be driven single-endedly but the LO feedthrough performance
will be degraded, especially towards the higher end of the frequency range. The LO Interface consists of interleaved stages of
polyphase network phase-splitters and buffer amplifiers. The
phase-splitter contains resistors and capacitors connected in a
circular manner to split the LO signal into I and Q paths in
precise quadrature with each other. The signal on each path
goes through a buffer amplifier to make up for the loss and high
frequency roll-off. The two signals then go through another
polyphase network to enhance the quadrature accuracy. The
broad operating frequency range of 0.8 GHz to 2.5 GHz is
achieved by staggering the RC time constants in each stage of
Differential-to-Single-Ended Converter
The differential-to-single-ended converter consists of two emitter followers driving a totem-pole output stage. Output impedance is established by the emitter resistors in the output transistors.
The output of this stage is connected to the output (VOUT) pin.
Bias
A bandgap reference circuit based on the ∆-VBE principle generates the Proportional-To-Absolute-Temperature (PTAT) currents used by the different sections as references. The bandgap
voltage is also used to generate a temperature-stable current in
the V-to-I converters to produce a temperature independent
slew rate. When the bandgap reference is disabled by pulling
down the ENBL pin, all other sections are shut off accordingly.
IBBP
IBBN
V-TO-I
V-TO-I
AD8346
MIXER
LOIN
LOIP
PHASE
SPLITTER
2
PHASE
SPLITTER
1
D-TO-S
MIXER
ENBL
BIAS CELL
V-TO-I
V-TO-I
QBBP
QBBN
Figure 20. Detailed Block Diagram
REV. 0
–7–
VOUT
AD8346
IP
1
IBBI
2
IBBN
3
COM1
COM4 14
4
COM1
COM4 13
5
LOIN
VPS2 12
6
LOIP
VOUT 11
C6
100pF
5
1
T1
2
ETC1-1-13
4
+VS
QBBN 15
AD8346
IN
LO
QP
QBBP 16
C7
100pF
3
C4
0.01mF
C3
100pF
QN
7
VPS1
COM3 10
8
ENBL
COM2 9
C1
100pF
C2
0.01mF
+VS
VOUT
C5
100pF
Figure 21. Basic Connections
The LO terminal can be driven single-ended as shown in Figure
22 at the expense of slightly higher LO feedthrough. LOIN is ac
coupled to ground using a capacitor and LOIP is driven through
a coupling capacitor from a (single-ended) 50 Ω source (this
scheme could also be reversed with LOIP being ac-coupled to
ground).
Basic Connections
The basic connections for operating the AD8346 are shown in
Figure 21. A single power supply of between 2.7 V and 5.5 V is
applied to pins VPS1 and VPS2. A pair of ESD protection
diodes are connected internally between VPS1 and VPS2 so
these must be tied to the same potential. Both pins should be
individually decoupled using 100 pF and 0.01 µF capacitors,
located as close as possible to the device. For normal operation,
the enable pin, ENBL, must be pulled high. The turn-on threshold
for ENBL is 2 V. To put the device in its power-down mode,
ENBL must be pulled below 0.5 V. Pins COM1 to COM4
should all be tied to a low impedance ground plane.
RF Output
The RF output is designed to drive a 50 Ω load but must be ac
coupled as shown in Figure 21. If the I and Q inputs are driven
in quadrature by 2 V p-p signals, the resulting output power will
be around –10 dBm (see Figure 2 for variation in output power
over frequency).
The I and Q ports should be driven differentially. This is convenient as most modern high speed DACs have differential outputs. For optimal performance, the drive signal should be a
2 V p-p (differential) signal with a bias level of 1.2 V, that is,
each input swings from 0.7 V to 1.7 V. The I and Q inputs have
input impedances of 12 kΩ. By dc coupling the DAC to the
AD8346 and applying small offset voltages, the LO feedthrough
can be reduced to well below its nominal value of –42 dBm (see
Figure 7).
Interface to AD9761 TxDAC®
Figure 23 shows a dc coupled current output DAC interface.
The use of dual integrated DACs such as the AD9761 with
specified ± 0.02 dB and ± 0.004 dB gain and offset matching
characteristics ensures minimum error contribution (over temperature) from this portion of the signal chain. The use of a
precision thin-film resistor network sets the bias levels precisely,
to prevent the introduction of offset errors, which will increase
LO feedthrough. For instance, selecting resistor networks with
0.1% ratio matching characteristics will maintain 0.03 dB gain
and offset matching performance.
LO Drive
The return loss of the LO port is shown in Figure 13. No additional matching circuitry is required to drive this port from a
50 Ω source. For maximum LO suppression at the output, a
differential LO drive is recommended. In Figure 21, this is
achieved using a balun (M/A-COM Part Number ETC1-1-13).
The output of the balun, is ac coupled to the LO inputs which
have a bias level about 800 mV below supply. An LO drive level
of between –6 dBm and –12 dBm is required. For optimal performance, a drive level of –10 dBm is recommended although a
level of –6 dBm will result in more stable temperature performance (see Figure 3). Higher levels will degrade linearity while
lower levels will tend to increase the noise floor.
Using resistive division, the dc bias level at the I and Q inputs to
the AD8346 is set to approximately 1.2 V. The four current
outputs of the DAC each delivers a full-scale current of 10 mA,
giving a voltage swing of 0 V to 1 V (at the DAC output). This
results in a 0.5 V p-p swing at the I and Q inputs of the AD8346
(resulting in a 1 V p-p differential swing).
Note that the ratio matching characteristics of the resistive network, as opposed to its absolute accuracy, is critical in preserving the gain and offset balance between the I and Q signal path.
By applying small dc offsets to the I and Q signals from the
DAC, the LO suppression can be reduced from its nominal
value of –42 dBm to as low as –60 dBm while holding to approximately –50 dBm over temperature (see Figure 7 for a plot
of LO feedthrough over temperature for an offset compensated
circuit.)
100pF
LO
LOIP
AD8346
LOIN
100pF
Figure 22. Single-Ended LO Drive
TxDAC is a registered trademark of Analog Devices, Inc.
–8–
REV. 0
AD8346
+5V
+5V
634V
DVDD
DCOM
500V
AVDD
100V
"I"
DAC
23
VPS1
VPS2
IBBP
CFILTER
IOUTB
S
IBBN
500V
100V
DAC
DATA
INPUTS
0.1mF
500V
IOUTA
LATCH
"I"
500V
VOUT
AD9761
500V
100V
QOUTA
LATCH
"Q"
"Q"
DAC
23
SLEEP
FS ADJ
PHASE
SPLITTER
LOIN
500V
0.5V p-p EACH PIN
WITH VCM = 1.2V
100V
MUX
CONTROL
CLOCK
QBBP
CFILTER
QOUTB
SELECT
WRITE
LOIP
500V
500V
QBBN
AD8346
REFIO
RSET
2kV
0.1mF
Figure 23. AD8346 Interface to AD9761 TxDAC
The network shown has a high-pass corner frequency of
approximately 14.3 kHz (note that the 12 kΩ input impedance of the AD8346 has been factored into this calculation). Increasing the resistors in the network or increasing
the coupling capacitance will reduce the corner frequency
further.
AC Coupled Interface
An ac coupled interface can also be implemented. This is shown
in Figure 24. This has the advantage that there is almost no
voltage loss due to the biasing network, allowing the AD8346
inputs to be driven by the full 2 V p-p differential signal from the
AD9761 (each of the DAC’s four outputs delivering 1 V p-p).
Note that the LO suppression can be manually optimized
by replacing a portion of the four “top” 2.43 kΩ resistors
with potentiometers. In this case, the “bottom” four resistors in the biasing network would no longer need to be
precision devices.
As in the dc coupled case, the bias levels on the I and Q inputs
should be set to as precise a level as possible, relative to each
other. This prevents the introduction of additional input offset
voltages. In the example shown, the bias level on each input is
set to approximately 1.2 V. The 2.43 kΩ resistors should have a
ratio tolerance of 0.1% or better.
+5V
+5V
1kV
DVDD
DCOM
AVDD
IOUTA
LATCH
"I"
"I"
DAC
23
IOUTB
2.43kV
100V 0.01mF
CFILTER
IBBP
VPS1
VPS2
S
IBBN
2.43kV
VOUT
AD9761
LOIP
QOUTA
LATCH
"Q"
"Q"
DAC
23
QOUTB
WRITE
CLOCK
100V
MUX
CONTROL
SLEEP
FS ADJ
RSET
2kV
0.01mF
CFILTER
100V
SELECT
2.43kV
2.43kV
2.43kV
0.1mF
–9–
PHASE
SPLITTER
LOIN
QBBN
0.01mF
1V p-p EACH PIN
WITH VCM = 1.2V
REFIO
QBBP
2.43kV
Figure 24. AC-Coupled DAC Interface
REV. 0
0.1mF
2.43kV
100V 0.01mF
DAC
DATA
INPUTS
2.43kV
AD8346
AD8346
EVALUATION BOARD
The schematic of the AD8346 evaluation board is shown in
Figure 25. This is a 4-layer FR4 board, the two center layers
being used as ground planes and the top and bottom layers
being used for signal and power respectively. The layout and
silkscreen of the top (signal) layer is shown in Figure 26. The
circuit closely follows the basic connections circuit shown in
Figure 21. For normal operation the board’s only jumper should
be in place (connecting ENBL to the supply). If the jumper is
removed, ENBL will be pulled to ground by a 10 kΩ resistor,
putting the device into its power-down mode.
All connectors are SMA-type. The I and Q inputs are dc coupled
to allow direct connection to a dual DAC with differential outputs. The local oscillator input is driven through a balun
(M/A-COM Part Number. ETC1-1-13). To implement a singleended drive, remove the balun and replace it with two surface
mount 0 Ω resistors (i.e., from Pin 4 to 3 and Pin 1 to 5 of the
balun).
1 IBBI
IP
2 IBBN
C6
100pF
5
1
T1
2
ETC1-1-13
4
+VS
QBBN 15
AD8346
IN
LO
QP
QBBP 16
C4
0.01mF
C7
100pF
3
C3
100pF
QN
3 COM1
COM4 14
4 COM1
COM4 13
5 LOIN
VPS2 12
6 LOIP
VOUT 11
7 VPS1
COM3 10
8 ENBL
COM2 9
C1
100pF
C2
0.01mF
+VS
VOUT
C5
100pF
ENBL
LK1
10kV
+VS
Figure 25. Evaluation Board Schematic
Figure 26. Layout and Silkscreen of Evaluation Board Signal Layer
–10–
REV. 0
AD8346
CHARACTERIZATION SETUPS
SSB Setup
CDMA Setup
Two main setups were used to characterize this product. These
setups are shown below in Figures 27 and 29. Figure 27 shows
the setup used to evaluate the product as a Single Sideband modulator. The AD8346 Motherboard had circuitry that converted
the single-ended I and Q inputs from the arbitrary function
generator to differential inputs with a dc bias of approximately
1.2 V. In addition, the Motherboard also provided connections
for power supply routing. The HP34970A and its associated
plug-in 34901 were used to monitor power supply currents and
voltages being supplied to the AD8346 Evaluation Board (a full
schematic of the AD8346 Evaluation Board can be found in
Figure 25). The 2 HP34907 plug-ins were used to provide additional miscellaneous dc and control signals to the Motherboard.
The LO was driven by an RF signal generator (through the
balun on the evaluation board to present a differential LO signal
to the device) and the output was measured with a spectrum
analyzer. With the I channel driven with a sine wave and the Q
channel driven with a cosine wave, the lower sideband is the
single sideband output. The typical SSB output spectrum is
shown below in Figure 28.
IEEE
For evaluating the AD8346 with CDMA waveforms the setup
shown in Figure 29 was used. This is essentially the same as that
used for the single sideband characterization except the AFG2020
was replaced with the AWG2021 for providing the I and Q
input signals, and the spectrum analyzer used to monitor the
output was changed to an FSEA30 Rohde-Schwarz analyzer
with vector demodulation capability. The I/Q input signals for
these measurements were IS95 baseband signals generated with
Tektronix I/Q SIM software and downloaded to the AWG2021.
For measuring ACPR the I/Q input signals used were generated
with Pilot (Walsh Code 00), Sync (WC 32), Paging (WC 01),
and 6 Traffic (WC 08, 09, 10, 11, 12, 13) channels active. The
I/Q SIM software was set for 32× oversampling and was using a
BS equifilter. Figure 30 shows the typical output spectrum for
this configuration. The ACPR was measured 885 kHz away
from the carrier frequency.
For performing EVM, Rho, phase, and amplitude balance measurements the I/Q input signals used were generated with only
the Pilot Channel (Walsh Code 00) active. The I/Q SIM software was set for 32× oversampling and was using a CDMA
equifilter.
IEEE
HP34970A
D1
D2
D3
34901 34907 34907
D1
+15V MAX
COM
+25V MAX
–25V MAX
IEEE
HP3631
RFOUT
I IN
Q IN
D1
OUTPUT 1
OUTPUT 2
IEEE
ARB FUNC. GEN
HP3631
IN
IP
QP
IP
QP
QN
AD8346
EVAL BOARD
LO
ENBL
+15V MAX
COM
+25V MAX
–25V MAX
IEEE
GND
VP
IN
HP8648C
TEKAFG2020
D3
AD8346
VOUT
P1
D2
D3
34901 34907 34907
VN MOTHERBOARD
P1
IEEE
D2
VPS1
HP34970A
D1
QN
D2
AD8346
RF I/P
CAL OUT
HP8648C
28VOLT
IEEE
RFOUT
IEEE
OUTPUT 1
Q IN
OUTPUT 2
IN
IP
QP
IP
QP
QN
AD8346
QN
EVAL BOARD
LO
ENBL
VOUT
P1
SPECTRUM
ANALYZER
IEEE
FSEA30
RF I/P
IEEE
SPECTRUM
ANALYZER
IEEE
PC CONTROLLER
PC CONTROLLER
Figure 27. Evaluation Board SSB Test Setup
Figure 29. Evaluation Board CDMA Test Setup
0
–20
–10
–30
–20
–40
–30
–50
–40
–60
–50
–70
–60
–80
–70
–90
–80
–100
–90
–110
CH PWR = –20.7dBm
ACP UPR = –71.8dBc
ACP LWR = –71.7dBc
–120
–100
CENTER 1.9GHz
50kHz/
SPAN 500kHz
CENTER 1.9GHz
Figure 28. Typical SSB Output Spectrum
REV. 0
IEEE
ARB FUNC. GEN
GND
VP
IN
SWEEP OUT
I IN
VN MOTHERBOARD
P1
HP8593E
TEKAFG2020
D3
VPS1
187.5kHz/
SPAN 1.875MHz
Figure 30. Typical CDMA Output Spectrum
–11–
AD8346
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C3516–8–3/99
16-Lead TSSOP
(RU-16)
0.201 (5.10)
0.193 (4.90)
9
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
16
1
8
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
88
08
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
PRINTED IN U.S.A.
0.0256
SEATING (0.65)
PLANE BSC
0.0433
(1.10)
MAX
–12–
REV. 0