DP8051
Pipelined High Performance
8-bit Microcontroller
ver 3.10
OVERVIEW
DP8051 is an ultra high performance,
speed optimized soft core of a single-chip 8bit embedded controller dedicated for operation with fast (typically on-chip) and slow (offchip) memories. The core has been designed
with a special concern about performance to
power consumption ratio. This ratio is extended by an advanced power management
unit PMU.
DP8051 soft core is 100% binarycompatible with the industry standard 8051 8bit microcontroller. There are two configurations of DP8051: Harward where internal data
and program buses are separated, and von
Neumann with common program and external
data bus. DP8051 has Pipelined RISC architecture 10 times faster compared to standard
architecture and executes 85-200 million instructions per second. This performance can
also be exploited to great advantage in low
power applications where the core can be
clocked over ten times more slowly than the
original implementation for no performance
penalty.
DP8051 is delivered with fully automated
testbench and complete set of tests allowing
easy package validation at each stage of SoC
design flow.
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are trademarks of their respective owners.
CPU FEATURES
●
100% software compatible with industry
standard 8051
●
Pipelined RISC architecture enables to
execute instructions 10 times faster compared to standard 8051
●
24 times faster multiplication
●
12 times faster addition
●
Up to 256 bytes of internal (on-chip) Data
Memory
●
Up to 64K bytes of internal (on-chip) or
external (off-chip) Program Memory
●
Up to 16M bytes of external (off-chip) Data
Memory
●
User programmable Program Memory Wait
States solution for wide range of memories
speed
●
User programmable External Data Memory
Wait States solution for wide range of
memories speed
●
De-multiplexed Address/Data bus to allow
easy connection to memory
●
Dedicated signal for Program Memory
writes.
●
Interface for additional Special Function
Registers
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●
Fully synthesizable, static synchronous
design with positive edge clocking and no
internal tri-states
●
Scan test ready
●
2.0 GHz virtual clock frequency in a 0.35u
technological process
PERIPHERALS
●
DoCD™ debug unit
○
Processor execution control
Run
●
Two 16-bit timer/counters
○
Timers clocked by internal source
○
Auto reload 8-bit timers
○
Externally gated event counters
●
Full-duplex serial port
○
Synchronous mode, fixed baud rate
○
8-bit asynchronous mode, fixed baud rate
○
9-bit asynchronous mode, fixed baud rate
○
9-bit asynchronous mode, variable baud rate
CONFIGURATION
Halt
Step into instruction
Skip instruction
○
Read-write all processor contents
Program Counter (PC)
Program Memory
Internal (direct) Data Memory
Special Function Registers (SFRs)
The following parameters of the DP8051 core
can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless
changing appropriate constants in package file.
There is no need to change any parts of the
code.
•
Internal Program Memory
type
- synchronous
- asynchronous
•
Internal Program ROM
Memory size
0 - 64kB
-
•
Internal Program RAM
Memory size
0 - 64kB
-
•
Internal Program Memory
fixed size
- true
- false
External Data Memory
○
Hardware execution breakpoints
Program Memory
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
○
Hardware breakpoints activated at a certain
-
• Power Management Mode
- used
- unused
• Stop mode
- used
- unused
• DoCD debug unit
- used
- unused
Program address (PC)
Address by any write into memory
Address by any read from memory
Address by write into memory a required data
Address by read from memory a required data
○
●
Three wire communication interface
subroutines
location
• Interrupts
Power Management Unit
○
Power management mode
○
Switchback feature
○
Stop mode
●
Besides mentioned above parameters all
available peripherals and external interrupts
can be excluded from the core by changing
appropriate constants in package file.
Interrupt Controller
○
2 priority levels
○
2 external interrupt sources
○
3 interrupt sources from peripherals
●
Four 8-bit I/O Ports
○
Bit addressable data direction for each line
○
Read/write of single line and 8-bit group
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are trademarks of their respective owners.
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DESIGN FEATURES
DELIVERABLES
♦ Source code:
◊ VHDL Source Code or/and
◊ VERILOG Source Code or/and
◊ Encrypted, or plain text EDIF netlist
♦ VHDL & VERILOG test bench environment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
◊ HDL core specification
◊ Datasheet
♦ Synthesis scripts
♦ Example application
♦ Technical support
◊ IP Core implementation support
◊ 3 months maintenance
●
●
●
Delivery the IP Core updates, minor and
major versions changes
Delivery the documentation updates
Phone & email support
♦
○ ROM located in address range between
0000h ÷ (ROMsize-1)
○ RAM located in address range between
(RAMsize-1) ÷ FFFFh
External Program Memory can be implemented as ROM or RAM located in address range between ROMsize ÷ RAMsize.
♦
INTERNAL DATA MEMORY:
The DP8051 can address Internal Data
Memory of up to 256 bytes The Internal
Data Memory can be implemented as Single-Port synchronous RAM.
♦
EXTERNAL DATA MEMORY:
The DP8051 soft core can address up to
16 MB of External Data Memory. Extra
DPX (Data Pointer eXtended) register is
used for segments swapping.
♦
USER SPECIAL FUNCTION REGISTERS:
Up to 104 External (user) Special Function Registers (ESFRs) may be added to
the DP8051 design. ESFRs are memory
mapped into Direct Memory between addresses 80 hex and FF hex in the same
manner as core SFRs and may occupy any
address that is not occupied by a core
SFR.
♦
WAIT STATES SUPPORT:
The DP8051 soft core is dedicated for
operation with wide range of Program and
Data memories. Slow Program and External Data memory may assert a memory
Wait signal to hold up CPU activity.
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design license allows use IP Core in
single FPGA bitstream and ASIC implementation.
Unlimited Designs, One Year licenses allow
use IP Core in unlimited number of FPGA bitstreams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time restriction
except One Year license where time of use is
limited to 12 months.
●
Single Design license for
○
VHDL, Verilog source code called HDL
Source
○
Encrypted, or plain text EDIF called Netlist
●
PROGRAM MEMORY:
The DP8051 soft core is dedicated for
operation with Internal and External Program Memory. Internal Program Memory
can be implemented as:
One Year license for
○
●
Encrypted Netlist only
Unlimited Designs license for
○
HDL Source
○
Netlist
●
Upgrade from
○
HDL Source to Netlist
○ Single Design to Unlimited Designs
All trademarks mentioned in this document
are trademarks of their respective owners.
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Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
SYMBOL
port0i(7:0)
port1i(7:0)
port2i(7:0)
port3i(7:0)
BLOCK DIAGRAM
port0o(7:0)
port1o(7:0)
port2o(7:0)
port3o(7:0)
prgramdata(7:0)
prgromdata(7:0)
prgaddr(15:0)
prgdatao(7:0)
prgramwr
prgromdata(7:0) prgaddr(15:0)
prgramdata(7:0) prgdatao(7:0)
prgramwr
xdatai(7:0)
ready
iprgromsize(2:0)
iprgramsize(2:0)
ramdatai(7:0)
sfrdatai(7:0)
int0
int1
t0
t1
gate0
gate1
rxdi
xaddr(23:0)
xdatao(7:0)
xdataz
xprgrd
xprgwr
xdatard
xdatawr
xaddr(23:0)
xdatao(7:0)
xdatai(7:0)
xdataz
ready
xprgrd
xprgwr
xdatard
xdatawr
ramaddr(7:0)
ramdatao(7:0)
ramwe
ramoe
ramaddr(7:0)
ramdatao(7:0)
ramdatai(7:0)
ramwe
ramoe
sfraddr(6:0)
sfrdatao(7:0)
sfroe
sfrwe
sfraddr(6:0)
sfrdatao(7:0)
sfrdatao(7:0)
sfroe
sfrwe
clk
reset
stop
pmm
reset
clk
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are trademarks of their respective owners.
Program
memory
interface
Timers
t0
t1
gate0
gate1
UART
rxdi
rxdo
txd
Interrupt
controller
int0
int1
Control
Unit
Power
Management
Unit
Internal data
memory
DoCD™
Debug Unit
interface
User SFR’s
interface
stop
pmm
docddatai
docddatao
docdclk
ALU
PINS DESCRIPTION
PIN
rxdo
txd
I/O Port
registers
External
memory
interface
iprgromsize(2:0)
iprgramsize(2:0)
port0(7:0)
port1(7:0)
port2(7:0)
port3(7:0)
Opcode
decoder
TYPE
DESCRIPTION
clk
input
Global clock
reset
input
Global reset
port0i[7:0]
input
Port 0 input
port1i[7:0]
input
Port 1 input
port2i[7:0]
input
Port 2 input
port3i[7:0]
input
Port 3 input
iprgramsize[2:0]
input
Size of on-chip RAM CODE
iprgromsize[2:0]
input
Size of on-chip ROM CODE
prgramdata[7:0]
input
Data bus from int. RAM prog. memory
prgromdata[7:0]
input
Data bus from int. ROM prog. memory
xdatai[7:0]
input
Data bus from external memories
ready
input
External memory data ready
ramdatai[7:0]
input
Data bus from internal data memory
sfrdatai[7:0]
input
Data bus from user SFR’s
int0
input
External interrupt 0
int1
input
External interrupt 1
t0
input
Timer 0 input
t1
input
Timer 1 input
gate0
input
Timer 0 gate input
gate1
input
Timer 1 gate input
rxdi
input
Serial receiver input
docddatai
input
DoCD™ data input
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port0o[7:0]
output Port 0 output
port1o[7:0]
output Port 1 output
port2o[7:0]
output Port 2 output
port3o[7:0]
output Port 3 output
prgaddr[15:0]
output Internal program memory address bus
prgdatao[7:0]
output Data bus for internal program memory
prgramwr
output Internal program memory write
xaddr[23:0]
output Address bus for external memories
xdatao[7:0]
output Data bus for external memories
xdataz
output Turn xdata bus into ‘Z’ state
xprgrd
output External program memory read
xprgwr
output External program memory write
xramrd
output External data memory read
xramwr
output External data memory write
ramaddr[7:0]
output Internal Data Memory address bus
ramdatao[7:0]
output Data bus for internal data memory
ramoe
output Internal data memory output enable
ramwe
output Internal data memory write enable
sfraddr[6:0]
output Address bus for user SFR’s
sfrdatao[7:0]
output Data bus for user SFR’s
sfroe
output User SFR’s read enable
sfrwe
output User SFR’s write enable
docddatao
output DoCD™ data output
docdclk
output DoCD™ clock line
pmm
output Power management mode indicator
stop
output Stop mode indicator
rxdo
output Serial receiver output
txd
output Serial transmitter output
UNITS SUMMARY
ALU – Arithmetic Logic Unit performs the
arithmetic and logic operations during execution of an instruction. It contains accumulator
(ACC), Program Status Word (PSW), (B) registers and related logic such as arithmetic unit,
logic unit, multiplier and divider.
Opcode Decoder – Performs an instruction
opcode decoding and the control functions for
all other blocks.
Control Unit – Performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and
manages execution of all microcontroller tasks.
Program Memory Interface – Contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program
Memory can be also written. This feature allows usage of a small boot loader loading new
program into ROM, RAM, EPROM or FLASH
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are trademarks of their respective owners.
EEPROM storage via UART, SPI, I2C or
DoCD™ module.
External Memory Interface - Contains memory access related registers such as Data
Page High (DPH), Data Page Low (DPL) and
Data Pointer eXtended (DPX) registers. It performs the external Program and Data Memory
addressing and data transfers. Program fetch
cycle length can be programmed by user. This
feature is called Program Memory Wait States,
and allows core to work with different speed
program memories.
Internal Data Memory Interface – Internal
Data Memory interface controls access into the
internal 256 bytes memory. It contains 8-bit
Stack Pointer (SP) register and related logic.
User SFRs Interface – Special Function Registers interface controls access to the special
registers. It contains standard and used defined registers and related logic. User defined
external devices can be quickly accessed
(read, written, modified) using all direct addressing mode instructions.
Interrupt Controller – Interrupt control module
is responsible for the interrupt manage system
for the external and internal interrupt sources.
It contains interrupt related registers such as
Interrupt Enable (IE), Interrupt Priority (IP) and
(TCON) registers.
Timers – System timers module. Contains two
16 bits configurable timers: Timer 0 (TH0,
TL0), Timer 1 (TH1, TL1) and Timers Mode
(TMOD) registers. In the timer mode, timer
registers are incremented every 12 CLK periods when appropriate timer is enabled. In the
counter mode the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are
opened (GATE0, GATE1). T0, T1 input pins
are sampled every CLK period. It can be used
as clock source for UARTs.
UART0 – Universal Asynchronous Receiver &
Transmitter module is full duplex, meaning it
can transmit and receive concurrently. Includes
Serial Configuration register (SCON), serial
receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning it
can commence reception of a second byte
before a previously received byte has been
read from the receive register. Writing to
SBUF0 loads the transmit register, and reading
SBUF0 reads a physically separate receive
register. Works in 3 asynchronous and 1 synhttp://www.DigitalCoreDesign.com
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chronous modes. UART0 can be synchronized
by Timer 1.
Ports - Block contains 8051’s general purpose
I/O ports. Each of port’s pin can be read/write
as a single bit or as a 8-bit bus P0, P1, P2, P3.
Power Management Unit – Block contains
advanced power saving mechanisms with
switchback feature, allowing external clock
control logic to stop clocking (Stop mode) or
run core in lower clock frequency (Power Management Mode) to significantly reduce power
consumption. Switchback feature allows
UARTs, and interrupts to be processed in full
speed mode if enabled. It is very desired when
microcontroller is planned to use in portable
and power critical applications.
DoCD™ Debug Unit – it’s a real-time hardware debugger provides debugging capability
of a whole SoC system. In contrast to other onchip debuggers DoCD™ provides non-intrusive
debugging of running application. It can halt,
run, step into or skip an instruction, read/write
any contents of microcontroller including all
registers, internal, external, program memories, all SFRs including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed if any write/read
occurred at particular address with certain data
pattern or without pattern. The DoCD™ system
includes three-wire interface and complete set
of tools to communicate and work with core in
real time debugging. It is built as scalable unit
and some features can be turned off to save
silicon and reduce power consumption. A special care on power consumption has been
taken, and when debugger is not used it is
automatically switched in power save mode.
Finally whole debugger is turned off when debug option is no longer used.
PROGRAM CODE SPACE
IMPLEMENTATION
and 64kB is typically used for timing critical
part of the code e.g. interrupt subroutines,
arithmetic functions etc. This part of the code is
typically implemented as RAM and can be
loaded by the BOOT code during initialization
phase from Off-chip memory or through RS232
interface from external device. From the two
mentioned above spaces program code is
executed without wait-states and can achieve
a top performance up to 200 million instructions per second (many instructions executed
in one clock cycle). The Off-chip Program
Memory located in address space between
1kB and 60kB is typically used for main code
and constants. This part of the code is usually
implemented as ROM, SRAM or FLASH device. Because of relatively long access time
the program code executed from mentioned
above devices must be fetched with additional
Wait-States. Number of required Wait-States
depends on memory access time and DP8051
clock frequency. In most cases the proper
number of Wait-States cycles is between 2-5.
The READY pin can be also dynamically
modulated e.g. by SDRAM controller.
0xFFFF
0xF000
On chip Memory
(implemented as RAM)
Off chip Memory
(implemented as ROM,
SRAM or FLASH)
0x0400
0x0000
On-chip Memory
(implemented as ROM)
The figure below shows a typical Program
Memories connections in system with DP8051
Microcontroller core.
The figure below shows an example Program Memory space implementation in systems with DP8051 Microcontroller core. The
On-chip Program Memory located in address
space between 0kB and 1kB is typically used
for BOOT code with system initialization functions. This part of the code is typically implemented as ROM. The On-chip Program Memory located in address space between 60kB
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prgramdatai
prgdatao
8
8
prgramwr
On-chip Memory
(implemented as RAM)
0 Wait-State access
12
prgaddr
10
prgromdata
i
DP8051
xdatai
8
On-chip Memory
(implemented as ROM)
0 Wait-State access
ASIC or FPGA
chip
8
xdatao
xaddr
Off-chip Memory
(implemented as
FLASH, or SRAM)
eg. 2-5 Wait-State
access
16
xprgrd
xprgwr
ready
80C51
80C310
DP8051
Wait-States
manager
PERFORMANCE
The following tables give a survey about the
Core area and performance in ASICs Devices
(CPU features and peripherals have been included):
Optimization
area
speed
Fmax
100 MHz
250 MHz
Core performance in ASIC devices
For a user the most important is application
speed improvement. The most commonly used
arithmetic functions and theirs improvement
are shown in table below. Improvement was
computed as {80C51 clock periods} divided by
{DP8051 clock periods} required to execute an
identical function. More details are available in
core documentation.
Function
8-bit addition (immediate data)
8-bit addition (direct addressing)
8-bit addition (indirect addressing)
8-bit addition (register addressing)
8-bit subtraction (immediate data)
8-bit subtraction (direct addressing)
8-bit subtraction (indirect addressing)
Improvement
9,00
9,00
9,00
12,00
9,00
9,00
9,00
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12,00
16,00
9,60
12,00
12,00
13,60
12,00
12,00
12,60
11,12
Dhrystone Benchmark Version 2.1 was used to
measure Core performance. The following table gives a survey about the DP8051 performance in terms of Dhrystone/sec and VAX MIPS
rating.
Device
The described above implementation should be
treated as an example. All Program Memory
spaces are fully configurable. For timing-critical
applications whole program code can be implemented as on-chip ROM and (or) RAM and
executed without Wait-States, but for some
other applications whole program code can be
implemented as off-chip ROM or FLASH and
executed with required number Wait-State cycles.
Device
0.25u typical
0.25u typical
8-bit subtraction (register addressing)
8-bit multiplication
8-bit division
16-bit addition
16-bit subtraction
16-bit multiplication
32-bit addition
32-bit subtraction
32-bit multiplication
Average speed improvement:
Target
0.25u
Clock
frequency
12 MHz
33 MHz
250 MHz
Dhry/sec
(VAX MIPS)
268 (0.153)
1550 (0.882)
43700 (24.872)
Core performance in terms of Dhrystones
43700
45000
40000
35000
30000
25000
20000
15000
10000
268
5000
1550
0
80C51 (12MHz)
80C310 (33MHz)
DP8051 (250MHz)
Area utilized by the each unit of DP8051 core
in vendor specific technologies is summarized
in table below.
Component
CPU*
Interrupt Controller
Power Management Unit
I/O ports
Timers
UART0
Total area
Area
[Gates]
[FFs]
5900
450
50
400
550
650
8000
285
40
5
35
50
60
475
*CPU – consisted of ALU, Opcode Decoder, Control Unit, Program &
Internal & External Memory Interfaces, User SFRs Interface
Core components area utilization
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1
2
4
4
-
-
-
-
-
Fixed Point
Coprocessor
Floating Point
Coprocessor
2
3
SPI
I\O Ports
1
1
2
Master I2C Bus
Controller
Slave I2C Bus
Controller
UART
2
2
2
Watchdog
Timer/Counters
2
5
15
Compare/Capture
Data Pointers
Interface for
additional SFRs
Power Management Unit
Internal Data Memory
space
External Data Memory
space
External Data / Program
Memory Wait States
Stack space size
off-chip
on-chip ROM
64k 64k 64k 256 256 16M
64k 64k 64k 256 256 16M
64k 64k 64k 256 256 16M
Interrupt levels
10
10
10
Interrupt sources
DP8051CPU
DP8051
DP8051XP
Program
Memory
space
on-chip RAM
Design
Architecture speed grade
The main features of each DP8051 family member have been summarized in table below. It gives
a briefly member characterization helping user to select the most suitable IP Core for its application.
User can specify its own peripheral set (including listed below and the others) and requests the core
modifications.
-
-
DP8051 family of Pipelined High Performance Microcontroller Cores
4
4
-
-
-
-
DP80390 family of Pipelined High Performance Microcontroller Cores
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-
Fixed Point
Coprocessor
Floating Point
Coprocessor
1
2
SPI
I\O Ports
2
3
Master I C Bus
Controller
Slave I2C Bus
Controller
UART
1
1
2
2
Timer/Counters
2
2
2
Watchdog
Data Pointers
2
5
15
Compare/Capture
Interrupt levels
Interface for
additional SFRs
Interrupt sources
64k 64k 16M 256 256 16M
64k 64k 16M 256 256 16M
64k 64k 16M 256 256 16M
Power Management Unit
Internal Data Memory
space
External Data Memory
space
External Data / Program
Memory Wait States
Stack space size
off-chip
10
10
10
on-chip ROM
DP80390CPU
DP80390
DP80390XP
Program
Memory
space
on-chip RAM
Design
Architecture speed grade
The main features of each DP80390 family member have been summarized in table below. It gives
a briefly member characterization helping user to select the most suitable IP Core for its application.
User can specify its own peripheral set (including listed below and the others) and requests the core
modifications.
-
-
CONTACTS
For any modification or special request contact to DCD.
Headquarters:
Wroclawska 94
41-902 Bytom, POLAND
e-mail: iinnffoo@
@ddccdd..ppll
tel.
: +48 32 282 82 66
fax
: +48 32 282 74 37
Field Office:
Texas Research Park
14815 Omicron Dr. suite 100
San Antonio, TX 78245, USA
USS@
@ddccdd..ppll
e-mail: iinnffooU
tel.
: +1 210 422 8268
fax
: +1 210 679 7511
Distributors:
Please check hhtttpp::///w
ww
ww
w..ddccdd..ppll//aappaarrttnn..pphhpp
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