18-Bit, 2 MSPS PulSAR 15 mW ADC in LFCSP (QFN) AD7986 FEATURES APPLICATION DIAGRAM 18-bit resolution with no missing codes Throughput: 2 MSPS (TURBO = high), 1.5 MSPS (TURBO = low) Low power dissipation 15 mW at 2 MSPS, with external reference 26 mW at 2 MSPS with internal reference INL: ±1 LSB typical, ±2.5 LSB maximum SNR 95.5 dB, with on-chip reference 97.0 dB, with external reference 4.096 V internal reference: typical drift of 10 ppm/°C True differential analog input voltage range: ±VREF 0 V to VREF with VREF up to 5.0 V Allows use of any input range No pipeline delay Logic interface: 1.8 V/2.5 V/2.7 V Serial interface: SPI/QSPI™/MICROWIRE™/DSP compatible Ability to daisy-chain multiple ADCs with busy indicator 20-lead 4 mm × 4 mm LFCSP (QFN) V+ 5V 1.8V TO 2.7V 2.5V 15Ω 0V TO BVDD AVDD, DVDD 2.7nF VREF IN+ V– AD7986 V+ 2.7nF SDI SCK SDO IN– REF 15Ω VREF TO 0V VIO TURBO GND1 CNV VIO 3- OR 4-WIRE INTERFACE: SPI, CS DAISY CHAIN (TURBO = LOW) 10µF 07956-001 V– NOTES 1. GND REFERS TO REFGND, AGND, AND DGND. Figure 1. GENERAL DESCRIPTION The AD7986 is an 18-bit, 2 MSPS successive approximation, analog-to-digital converter (ADC). It contains a low power, high speed, 18-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and a versatile serial interface port. On the rising edge of CNV, the AD7986 samples the voltage difference between the IN+ and IN− pins. The voltages on these pins usually swing in opposite phases between 0 V and VREF. It features a very high sampling rate turbo mode (TURBO = high) and a reduced power normal mode (TURBO = low) for low power applications where the power is scaled with the throughput. APPLICATIONS Battery-powered equipment Data acquisition systems Medical instruments Seismic data acquisition systems In normal mode (TURBO = low), the SPI-compatible serial interface also features the ability, using the SDI input, to daisychain several ADCs on a single 3-wire bus and provide an optional busy indicator. It is compatible with 1.8 V, 2.5 V, and 2.7 V using the separate VIO supply. The AD7986 is available in a 20-lead LFCSP (QFN) with operation specified from −40°C to +85°C. Table 1. MSOP, LFCSP (QFN) 14-/16-/18-Bit PulSAR® ADCs Type 14-Bit 16-Bit 100 kSPS AD7940 AD7680 AD7683 AD7684 18-Bit 1 250 kSPS AD79421 AD76851 AD76871 AD7694 AD76911 400 kSPS to 500 kSPS AD79461 AD76861 AD76881 AD76931 AD76901 ≥1000 kSPS ADC Driver AD79801 AD79831 ADA4941-1 ADA4841-x AD79821 AD79841 AD7986 ADA4941-1 ADA4841-x AD8021 Pin-for-pin compatible. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009–2011 Analog Devices, Inc. All rights reserved. AD7986 TABLE OF CONTENTS Features .............................................................................................. 1 Analog Inputs.............................................................................. 15 Applications ....................................................................................... 1 Driver Amplifier Choice ........................................................... 15 Application Diagram ........................................................................ 1 Voltage Reference Input ............................................................ 16 General Description ......................................................................... 1 Power Supply............................................................................... 16 Revision History ............................................................................... 2 Digital Interface .............................................................................. 17 Specifications..................................................................................... 3 Data Reading Options ............................................................... 18 Timing Specifications .................................................................. 5 CS Mode, 3-Wire Without Busy Indicator ............................. 19 Absolute Maximum Ratings ............................................................ 6 CS Mode, 3-Wire with Busy Indicator .................................... 20 ESD Caution .................................................................................. 6 CS Mode, 4-Wire Without Busy Indicator ............................. 21 Pin Configuration and Function Descriptions ............................. 7 CS Mode, 4-Wire with Busy Indicator .................................... 22 Typical Performance Characteristics ............................................. 9 Chain Mode Without Busy Indicator ...................................... 23 Terminology .................................................................................... 12 Chain Mode with Busy Indicator ............................................. 24 Theory of Operation ...................................................................... 13 Application Hints ........................................................................... 25 Circuit Information .................................................................... 13 Layout .......................................................................................... 25 Converter Operation .................................................................. 13 Evaluating the AD7986 Performance ...................................... 25 Conversion Modes of Operation .............................................. 13 Outline Dimensions ....................................................................... 27 Typical Connection Diagram.................................................... 14 Ordering Guide .......................................................................... 27 REVISION HISTORY 3/11—Rev. A to Rev. B Added Common-Mode Input Range Parameter, Table 2 ........... 3 8/10—Rev. 0 to Rev. A Changes to Conversion Time: CNV Rising Edge to Data Available (Turbo Mode/Normal Mode) Parameter, Table 4 ....... 5 Changes to Figure 32 ...................................................................... 22 4/09—Revision 0: Initial Version Rev. B | Page 2 of 28 AD7986 SPECIFICATIONS AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = −40°C to +85°C, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Common-Mode Input Range Analog Input CMRR Leakage Current at 25°C Input Impedance ACCURACY No Missing Codes Differential Linearity Error Integral Linearity Error Transition Noise Gain Error, TMIN to TMAX3 Gain Error Temperature Drift Zero Error, TMIN to TMAX3 Zero Temperature Drift Power Supply Sensitivity THROUGHPUT Conversion Rate Transient Response AC ACCURACY Dynamic Range Signal-to-Noise Ratio, SNR Spurious-Free Dynamic Range, SFDR Total Harmonic Distortion4, THD Signal-to-(Noise + Distortion), SINAD SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay Conditions Min 18 Typ (IN+) − (IN−) IN+, IN− IN+, IN− fIN = 500 kHz Acquisition phase −VREF −0.1 VREF × 0.475 −20 ±0.60 ±1.00 2.0 ±2.4 ±0.5 −0.8 +VREF VREF + 0.1 VREF × 0.525 V V V dB1 nA +1.50 +2.50 +20 +0.8 ±0.3 ±4 AVDD = 2.5 V ± 5% 0 2.00 100 Full-scale step 1 Unit Bits VREF × 0.5 100 250 See the Analog Inputs section 18 −0.95 −2.50 VREF = 4.096 V, internal reference VREF = 5.0 V, external reference fIN = 20 kHz, VREF = 4.096 V, internal reference fIN = 20 kHz, VREF = 5.0 V, external reference fIN = 20 kHz fIN = 20 kHz, VREF = 4.096 V, internal reference fIN = 20 kHz, VREF = 5.0 V, external reference fIN = 20 kHz, VREF = 4.096 V Max Bits LSB2 LSB2 LSB2 LSB2 ppm/°C mV ppm/°C LSB2 MSPS ns 95.5 97 94.5 96.5 98 95.5 dB1 96.5 97.0 dB1 −115 −113 dB1 dB1 −114 dB1 95.5 dB1 19 0.7 MHz ns 94.5 dB1 All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. LSB means least significant bit. With the ±4.096 V input range, one LSB is 31.25 µV. See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference. 4 Tested fully in production at fIN = 1 kHz. 2 3 Rev. B | Page 3 of 28 AD7986 AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = −40°C to +85°C, unless otherwise noted. Table 3. Parameter INTERNAL REFERENCE Output Voltage Temperature Drift Line Regulation Turn-On Settling Time REFIN Output Voltage REFIN Output Resistance EXTERNAL REFERENCE Voltage Range Current Drain REFERENCE BUFFER REFIN Input Voltage Range REFIN Input Current DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay Conditions PDREF = low TA= 25°C −40°C to +85°C AVDD = 2.5 V ± 5% CREF = 10 μF, CREFBUFIN = 0.1 μF REFIN @ 25°C Min Typ Max Unit 4.081 4.096 ±10 ±50 220 1.2 7.5 4.111 V ppm/°C ppm/V ms V kΩ 5.1 500 V µA 1.2 160 V µA VOL VOH POWER SUPPLIES AVDD, DVDD BVDD VIO VIO Range Standby Current1, 2 Power Dissipation With Internal Reference Without Internal Reference With Internal Reference Without Internal Reference TEMPERATURE RANGE3 Specified Performance ISINK = +500 µA ISOURCE = −500 µA Serial, 18 bits, twos complement Conversion results available immediately after completed conversion 0.4 VIO − 0.3 Specified performance 2.375 4.75 1.8 PDREF = high, REFIN = low 2.4 2 MSPS, VREF = 5.0 V −0.3 +0.9 × VIO −1 −1 +0.1 × VIO VIO + 0.3 +1 +1 2.5 5.0 2.5 AVDD = DVDD = VIO = 2.5 V, BVDD = 5.0 V 2.25 2 MSPS throughput 2 MSPS throughput 1.5 MSPS throughput 1.5 MSPS throughput 29 15 26 11.5 TMIN to TMAX −40 1 With all digital inputs forced to VIO or GND as required. During acquisition phase. 3 Contact an Analog Devices, Inc., sales representative for the extended temperature range. 2 Rev. B | Page 4 of 28 V V µA µA V V 2.625 5.25 2.7 V 34 16.5 30 13 mW mW mW mW +85 °C V V µA AD7986 TIMING SPECIFICATIONS AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = −40°C to +85°C, unless otherwise noted.1 Table 4. Parameter Conversion Time: CNV Rising Edge to Data Available (Turbo Mode/Normal Mode) Acquisition Time Time Between Conversions (Turbo Mode/Normal Mode) CNV Pulse Width (CS Mode) Data Read During Conversion (Turbo Mode/Normal Mode) Quiet Time During Acquisition from Last SCK Falling Edge to CNV Rising Edge SCK Period (CS Mode) SCK Period (Chain Mode) SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay CNV or SDI Low to SDO D17 MSB Valid (CS Mode) CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge SDI Valid Hold Time from CNV Rising Edge (CS Mode) SDI Valid Hold Time from CNV Rising Edge (Chain Mode) SCK Valid Setup Time from CNV Rising Edge (Chain Mode) SCK Valid Hold Time from CNV Rising Edge (Chain Mode) SDI Valid Setup Time from SCK Falling Edge (Chain Mode) SDI Valid Hold Time from SCK Falling Edge (Chain Mode) SDI High to SDO High (Chain Mode with Busy Indicator) Min Typ Max 400/500 100 500/660 10 200/300 20 9 11 3.5 3.5 2 6 10 8 4 0 0 5 5 2 3 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns See Figure 2 and Figure 3 for load conditions. 10% VIO IOL 90% VIO tDELAY 1.4V TO SDO CL 20pF 500µA IOH tDELAY VIH1 VIL1 VIH1 VIL1 1MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS SPECIFICATIONS IN TABLE 3. Figure 2. Load Circuit for Digital Interface Timing Figure 3. Voltage Levels for Timing Rev. B | Page 5 of 28 07956-003 500µA 07956-002 1 Symbol tCONV tACQ tCYC tCNVH tDATA tQUIET tSCK tSCK tSCKL tSCKH tHSDO tDSDO tEN tDIS tSSDICNV tHSDICNV tHSDICNV tSSCKCNV tHSCKCNV tSSDISCK tHSDISCK tDSDOSDI AD7986 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs IN+, IN− to GND 1 Supply Voltage REF, BVDD to GND, REFGND AVDD, DVDD, VIO to GND AVDD and DVDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature θJA Thermal Impedance 20-Lead LFCSP (QFN) Lead Temperatures Vapor Phase (60 sec) Infrared (15 sec) 1 Rating −0.3 V to VREF + 0.3 V or ±130 mA −0.3 V to +6.0 V −0.3 V to +2.7 V +3 V to −6 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −65°C to +150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 30.4°C/W 215°C 220°C See the Analog Inputs section for an explanation of IN+ and IN −. Rev. B | Page 6 of 28 AD7986 1 2 3 4 5 PIN 1 INDICATOR AD7986 TOP VIEW (Not to Scale) 15 TURBO 14 SDI 13 CNV 12 SCK 11 DVDD IN+ PDREF VIO SDO DGND 6 7 8 9 10 REF REF REFGND REFGND IN– 07956-004 20 19 18 17 16 REFIN BVDD AGND AGND AVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SYSTEM GROUND PLANE. Figure 4. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1, 2 Mnemonic REF Type1 AI 3, 4 5 6 7 REFGND IN− IN+ PDREF AI AI AI DI 8 VIO P 9 10 11 12 13 SDO DGND DVDD SCK CNV DO P P DI DI 14 SDI DI 15 TURBO DI Description Reference Output/Input Voltage. When PDREF = low, the internal reference and buffer are enabled, producing 4.096 V on this pin. When PDREF = high, the internal reference and buffer are disabled, allowing an externally supplied voltage reference up to 5.0 V. Decoupling is required with or without the internal reference and buffer. This pin is referred to the REFGND pins and should be decoupled closely to the REFGND pins with a 10 µF capacitor. Reference Input Analog Ground. Differential Negative Analog Input. Differential Positive Analog Input. Internal Reference Power-Down Input. When low, the internal reference is enabled. When high, the internal reference is powered down and an external reference must be used. Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, or 2.7 V). Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. Digital Power Ground. Digital Power. Nominally at 2.5 V. Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part: chain mode or CS mode. In CS mode, the SDO pin is enabled when CNV is low. In chain mode, the data should be read when CNV is high. Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 18 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. Conversion Mode Selection. When TURBO = high, the maximum throughput (2 MSPS) is achieved. The ADC does not power down between conversions. When TURBO = low, the maximum throughput is lower (1.5 MSPS). The ADC powers down between conversions. Rev. B | Page 7 of 28 AD7986 Pin No. 16 17,18 19 Mnemonic AVDD AGND BVDD Type1 P P P 20 REFIN AI/O 21 (EPAD) Exposed Pad EP 1 Description Input Analog Power. Nominally at 2.5 V. Analog Power Ground. Reference buffer power. Nominally 5.0 V. If an external reference buffer is used to achieve the maximum SNR performance with 5 V reference, the reference buffer must be powered down by connecting the REFIN pin to ground. The external reference buffer must be connected to the BVDD pin. Internal Reference Output/Reference Buffer Input. When PDREF = low, the internal band gap reference produces a 1.2 V (typical) voltage on this pin, which needs external decoupling (0.1 µF typical). When PDREF = high, use an external reference to provide a 1.2 V (typical) to this pin. When PDREF = high, and REFIN = low, the on-chip reference buffer and band gap are powered down. An external reference must be connected to REF and BVDD. The exposed pad is not connected internally. For increased reliability of the solder joints, it is recommended that the pad be soldered to the system ground plane. AI = analog input, AI/O = bidirectional analog; DI = digital input, DO = digital output, and P = power. Rev. B | Page 8 of 28 AD7986 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = DVDD = VIO = 2.5 V, BVDD = 5.0 V, VREF = 5.0 V, external reference (PDREF = high, REFIN = low), unless otherwise noted. 2.5 2.0 POSITIVE INL = +1.57LSB NEGATIVE INL = –1.25LSB 2.0 POSITIVE DNL = +0.54LSB NEGATIVE DNL = –0.60LSB 1.5 1.5 1.0 0.5 DNL (LSB) INL (LSB) 1.0 0 –0.5 0.5 0 –0.5 –1.0 –1.0 –1.5 –2.5 0 65,536 131,072 CODE 196,608 07956-008 –1.5 07956-005 –2.0 –2.0 0 262,144 65,536 Figure 5. Integral Nonlinearity vs. Code 45,000 131,072 CODE 262,144 Figure 8. Differential Nonlinearity vs. Code 45,000 41,811 41,434 38,665 40,000 40,000 35,204 196,608 34,894 35,000 35,000 30,000 30,000 COUNTS COUNTS 30,897 25,000 20,000 15,000 25,000 20,000 15,000 10,211 10,000 7662 6399 5000 0 0 101 3FF6 1661 3FF8 1418 3FFA 3FFC CODE IN HEX 68 3FFE 3 0 5000 0 2283 0 4 3FF5 0 Figure 6. Histogram of DC Input at Code Center (External Reference) 1002 34 142 3FF7 3FF9 3FFB 3FFD CODE IN HEX 0 1 Figure 9. Histogram of DC Input at Code Transition (External Reference) 45,000 40,000 39,395 40,000 1 3FFF 07956-009 8250 07956-006 10,000 37,385 36,210 35,000 35,000 30,000 31,020 29,138 30,000 COUNTS COUNTS 25,000 25,000 20,000 22,077 18,953 20,000 15,000 12,773 11,107 10,000 10,000 6513 3662 0 0 3FFEC 1 55 2932 547 3FFEE 407 35 3FF0 3FF2 3FF4 CODE IN HEX 3FF6 6879 5000 3FF8 0 0 07956-007 5000 Figure 7. Histogram of DC Input at Code Center (Internal Reference) 0 1 1438 1282 3 150 3FFEB 3FFED 3FFEF 3FF1 3FF3 CODE IN HEX 3FF5 165 16 3FF7 0 07956-010 15,000 3FF9 Figure 10. Histogram of DC Input at Code Transition (Internal Reference) Rev. B | Page 9 of 28 AD7986 0 0 fS = 2MSPS fIN = 20kHz SNR = 97.0dB THD = –114.0dB SINAD = 97.0dB –20 –40 –40 AMPLITUDE (dB) –80 –100 –120 –140 –60 –80 –100 –120 –140 07956-111 –160 –180 –200 0 200k 400k 600k FREQUENCY (Hz) 800k 07956-114 AMPLITUDE (dB) –60 fS = 2MSPS fIN = 20kHz SNR = 95.5dB THD = –113.0dB SINAD = 95.5dB –20 –160 –180 1M 0 Figure 11. FFT Plot (External Reference) 200k 400k 600k FREQUENCY (Hz) 800k 1M Figure 14. FFT Plot (Internal Reference) 18 100 –95 125 –100 120 SNR 17 16 THD (dB) ENOB 90 ENOB (Bits) –105 115 SFDR (dB) SINAD SFDR –110 110 THD –115 105 –120 100 2.5 3.0 3.5 4.0 REFERENCE VOLTAGE (V) 4.5 14 5.0 –125 95 2.5 3.0 Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage 3.5 4.0 REFERENCE VOLTAGE (V) 4.5 07956-015 80 07956-212 15 85 5.0 Figure 15. THD and SFDR vs. Reference Voltage 100 –80 –85 –90 95 THD (dB) –95 90 –100 –105 –110 85 80 1k 10k 100k FREQUENCY (Hz) 07956-216 –115 07956-013 SINAD (dB) SNR, SINAD (dB) 95 –120 –125 1M 1k Figure 13. SINAD vs. Frequency 10k 100k FREQUENCY (Hz) Figure 16. THD vs. Frequency Rev. B | Page 10 of 28 1M AD7986 3.0 99 IREF 2.5 97 96 95 94 93 92 2.0 IAVDD 1.5 1.0 0.5 IBVDD 91 –9 –8 –7 –6 –5 –4 INPUT LEVEL (dB) –3 –2 –1 0 0 –55 07956-032 90 –10 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (C) Figure 17. SNR vs. Input Level 07956-034 98 SUPPLY CURRENT (mA) SNR (dB REFERRED TO FULL SCALE) 100 Figure 19. Operating Currents vs. Temperature 3.0 14 IREF 12 SUPPLY CURRENT (µA) 2.0 IAVDD IDVDD 1.0 8 6 4 IAVDD + IDVDD + IVIO IBVDD 0.5 2 IVIO 0 2.375 10 2.425 2.475 2.525 2.575 AVDD AND DVDD VOLTAGE (V) 2.625 Figure 18. Operating Currents vs. Supply Voltage 0 –55 –35 –15 5 25 45 65 85 105 TEMPERATURE (°C) Figure 20. Power-Down Currents vs. Temperature Rev. B | Page 11 of 28 125 07956-035 1.5 07956-033 SUPPLY CURRENT (mA) 2.5 AD7986 TERMINOLOGY Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 22). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error Zero error is the difference between the ideal midscale voltage, that is, 0 V, from the actual voltage producing the midscale output code, that is, 0 LSB. Gain Error The first transition (from 100 ... 00 to 100 ... 01) should occur at a level ½ LSB above nominal negative full scale (−4.095984 V for the ±4.096 V range). The last transition (from 011 … 10 to 011 … 11) should occur for an analog voltage 1½ LSB below the nominal full scale (+4.095953 V for the ±5 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD as follows: ENOB = (SINADdB − 1.76)/6.02 and is expressed in bits. Noise-Free Code Resolution Noise-free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. It is calculated as Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise) and is expressed in bits. Effective Resolution Effective resolution is calculated as Effective Resolution = log2(2N/RMS Input Noise) and is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels. It is measured with a signal at −60 dBF so that it includes all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-(Noise + Distortion) (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value of SINAD is expressed in decibels. Aperture Delay Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied. Rev. B | Page 12 of 28 AD7986 THEORY OF OPERATION IN+ SWITCHES CONTROL LSB MSB REF 131,072C 65,536C 4C 2C C SW+ C BUSY COMP REFGND 131,072C 65,536C 4C 2C C C OUTPUT CODE LSB MSB CONTROL LOGIC SW– 07956-011 CNV IN– Figure 21. ADC Simplified Schematic CIRCUIT INFORMATION The AD7986 is a fast, low power, single-supply, precise, 18-bit ADC using a successive approximation architecture. The AD7986 features different modes to optimize performance according to the application. In turbo mode, the AD7986 is capable of converting 2,000,000 samples per second (2 MSPS). The AD7986 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. The AD7986 can be interfaced to any 1.8 V to 2.7 V digital logic family. It is available in a 20-lead LFCSP (QFN) that allows space savings and flexible configurations. two capacitor arrays are then disconnected from the analog inputs and connected to the REFGND input. Therefore, the differential voltage between Input IN+ and Input IN− captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between REFGND and REF, the comparator input varies by binaryweighted voltage steps (VREF/2, VREF/4 … VREF/262,144). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase, and the control logic generates the ADC output code and a busy signal indicator. Because the AD7986 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process. CONVERTER OPERATION The AD7986 is a successive approximation ADC based on a charge redistribution DAC. Figure 21 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 18 binary-weighted capacitors that are connected to the two comparator inputs. CONVERSION MODES OF OPERATION During the acquisition phase, terminals of the array tied to the input of the comparator are connected to AGND via SW+ and SW−. All independent switches are connected to the analog inputs. Therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− inputs. When the acquisition phase is complete and the CNV input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SW− are opened first. The The AD7986 features two conversion modes of operation: turbo and normal. Turbo conversion mode (TURBO = high) allows the fastest conversion rate of up to 2 MSPS, and does not power down between conversions. The first conversion in turbo mode should be ignored because it contains meaningless data. For applications that require lower power and slightly slower sampling rates, the normal mode (TURBO = low) allows a maximum conversion rate of 1.5 MSPS, and powers down between conversion. The first conversion in normal mode does contain meaningful data. Rev. B | Page 13 of 28 AD7986 Transfer Functions Table 7. Output Codes and Ideal Input Voltages Description FSR − 1 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR 011 ... 111 011 ... 110 011 ... 101 1 2 100 ... 010 Analog Input VREF = 5 V +4.095969 V +31.25 µV 0V −31.25 µV −4.095969 V −4.096 V Digital Output Code (Hex) 0x1FFFF1 0x00001 0x00000 0x3FFFF 0x20001 0x200002 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − REFGND). This is also the code for an underranged analog input (VIN+ − VIN− below REFGND). TYPICAL CONNECTION DIAGRAM 100 ... 001 100 ... 000 –FSR –FSR + 1 LSB +FSR – 1 LSB +FSR – 1.5 LSB –FSR + 0.5 LSB ANALOG INPUT Figure 23 shows an example of the recommended connection diagram for the AD7986 when multiple supplies are available. 07956-012 Figure 22. ADC Ideal Transfer Function 5V 2.5V 1.8V TO 2.7V V+ 15Ω 0V TO VREF 2.7nF IN+ DD VIO BVDD AVDD, DVDD TURBO SDI V– AD7986 V+ SCLK SDO IN– CNV VIO 3- OR 4-WIRE INTERFACE: SPI, CS DAISY CHAIN (TURBO = LOW) 15Ω REF GND1 VREF TO 0V 2.7nF 10µF V– NOTES 1. GND REFERS TO REFGND, AGND, AND DGND. Figure 23. Typical Application Diagram with Multiple Supplies Rev. B | Page 14 of 28 07956-016 ADC CODE (TWOS COMPLEMENT) The ideal transfer characteristic for the AD7986 is shown in Figure 22 and Table 7. AD7986 ANALOG INPUTS DRIVER AMPLIFIER CHOICE Figure 24 shows an equivalent circuit of the input structure of the AD7986. Although the AD7986 is easy to drive, the driver amplifier must meet the following requirements: The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN+ and IN−. Care must be taken to ensure that the analog input signal does not exceed the reference input voltage (REF) by more than 0.3 V. If the analog input signal exceeds this level, the diodes become forward-biased and start conducting current. These diodes can handle a forward-biased current of 130 mA maximum. However, if the supplies of the input buffer (for example, the V+ and V− supplies of the buffer amplifier in Figure 23) are different from those of REF, the analog input signal may eventually exceed the supply rails by more than 0.3 V. In such a case (for example, an input buffer with a short circuit), the current limitation can be used to protect the part. • SNRLOSS RIN CIN IN+ OR IN– D2 07956-014 CPIN GND Figure 24. Equivalent Analog Input Circuit The analog input structure allows the sampling of the true differential signal between IN+ and IN−. By using these differential inputs, signals common to both inputs are rejected. During the acquisition phase, the impedance of the analog inputs (IN+ or IN−) can be modeled as a parallel combination of Capacitor CPIN and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 400 Ω and is a lumped component composed of serial resistors and the on resistance of the switches. CIN is typically 30 pF and is mainly the ADC sampling capacitor. During the sampling phase, where the switches are closed, the input impedance is limited to CPIN. RIN and CIN make a one-pole, low-pass filter that reduces undesirable aliasing effects and limits noise. When the source impedance of the driving circuit is low, the AD7986 can be driven directly. Large source impedances significantly affect the ac performance, especially THD. The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency. 62.5 = 20 log π 2 34.4 + f −3dB (Ne N )2 2 where: f–3dB is the input bandwidth, in megahertz, of the AD7986 (20 MHz) or the cutoff frequency of the input filter, if one is used. N is the noise gain of the amplifier (for example, 1 in buffer configuration). eN is the equivalent input noise voltage of the op amp, in nV/√Hz. REF D1 The noise generated by the driver amplifier must be kept as low as possible to preserve the SNR and transition noise performance of the AD7986. The noise from the driver is filtered by the AD7986 analog input circuit’s one-pole, lowpass filter, made by RIN and CIN or by the external filter, if one is used. Because the typical noise of the AD7986 is 62.5 µV rms, the SNR degradation due to the amplifier is • • For ac applications, the driver should have a THD performance commensurate with the AD7986. For multichannel multiplexed applications, the driver amplifier and the AD7986 analog input circuit must settle for a full-scale step onto the capacitor array at an 18-bit level (0.0004%, 4 ppm). In the data sheet of the driver amplifier, settling at 0.1% to 0.01% is more commonly specified. This may differ significantly from the settling time at an 18-bit level and should be verified prior to driver selection. Table 8. Recommended Driver Amplifiers Amplifier AD8021 AD8022 ADA4899-1 AD8014 Rev. B | Page 15 of 28 Typical Application Very low noise and high frequency Low noise and high frequency Ultralow noise and high frequency Low power and high frequency AD7986 VOLTAGE REFERENCE INPUT The advantages of directly using the external voltage reference are: The AD7986 allows the choice of a very low temperature drift internal voltage reference, an external reference, or an external buffered reference. • The internal reference of the AD7986 provides excellent performance and can be used in almost all applications. The SNR and dynamic range improvement (about 1.7 dB) resulting from the use of a larger reference voltage (5 V) instead of a typical 4.096 V reference when the internal reference is used. This is calculated by 4.096 SNR = 20 log 5. 0 Internal Reference, REF = 4.096V (PDREF = Low) To use the internal reference, the PDREF input must be low. This enables the on-chip band gap reference and buffer, resulting in a 4.096 V reference on the REF pin (1.2 V on REFIN). The internal reference is temperature compensated to 4.096 V ± 15 mV. The reference is trimmed to provide a typical drift of 10 ppm/°C. The output resistance of REFIN is 6 kΩ when the internal reference is enabled. It is necessary to decouple this pin with a ceramic capacitor of at least 100 nF. The output resistance of REFIN and the decoupling capacitor form an RC filter, which helps to reduce noise. Because the output impedance of REFIN is typically 6 kΩ, relative humidity (among other industrial contaminants) can directly affect the drift characteristics of the reference. A guard ring is typically used to reduce the effects of drift under such circumstances. However, the fine pitch of the AD7986 makes this difficult to implement. One solution, in these industrial and other types of applications, is to use a conformal coating, such as Dow Corning® 1-2577 or HumiSeal® 1B73. External 1.2 V Reference and Internal Buffer (PDREF = High) To use an external reference along with the internal buffer, PDREF should be high. This powers down the internal reference and allows the 1.2 V reference to be applied to REFIN, producing 4.096 V (typically) on the REF pin. External Reference (PDREF = High, REFIN = Low) To apply an external reference voltage directly to the REF pin, PDREF should be tied high, and REFIN should be tied low. BVDD should also be driven to the same potential as REF. For example, if REF = 2.5 V, BVDD should be tied to 2.5 V. • The power savings when the internal reference is powered down (PDREF high). Reference Decoupling The AD7986 voltage reference input, REF, has a dynamic input impedance that requires careful decoupling between the REF and REFGND pins. The Layout section describes how this can be done. When using an external reference, a very low impedance source (for example, a reference buffer using the AD8031 or the AD8605), and a 10 µF (X5R, 0805 size) ceramic chip capacitor are appropriate for optimum performance. If an unbuffered reference voltage is used, the decoupling value depends on the reference used. For instance, a 22 µF (X5R, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift ADR43x reference. If desired, a reference decoupling capacitor with values as small as 2.2 µF can be used with minimal impact on performance, especially DNL. Regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF and REFGND pins. POWER SUPPLY The AD7986 uses four power supply pins: an analog supply (AVDD), a buffer supply (BVDD), a digital supply (DVDD), and a digital input/output interface supply (VIO). VIO allows direct interface with any logic between 1.8 V and 2.7 V. To reduce the number of supplies needed, VIO, DVDD, and AVDD can be tied together. The AD7986 is independent of power supply sequencing among all of its supplies. Additionally, it is very insensitive to power supply variations over a wide frequency range. Rev. B | Page 16 of 28 AD7986 DIGITAL INTERFACE Although the AD7986 has a reduced number of pins, it offers flexibility in its serial interface modes. When in CS mode, the AD7986 is compatible with SPI, MICROWIRE™, QSPI™, and digital hosts. In this mode, the AD7986 can use either a 3-wire or a 4-wire interface. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections, which is useful, for instance, in isolated applications. A 4-wire interface using the SDI, CNV, SCK, and SDO signals allows CNV, which initiates conversions, to be independent of the readback timing (SDI). This is useful in low jitter sampling or simultaneous sampling applications. When in chain mode, the AD7986 provides a daisy-chain feature using the SDI input for cascading multiple ADCs on a single data line similar to a shift register. Chain mode is only available in normal mode (TURBO = low). The mode in which the part operates depends on the SDI level when the CNV rising edge occurs. The CS mode is selected if SDI is high, and the chain mode is selected if SDI is low. The SDI hold time is such that when SDI and CNV are connected together, the chain mode is always selected. In normal mode operation, the AD7986 offers the option of forcing a start bit in front of the data bits. This start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. The busy indicator feature is enabled in CS mode if CNV or SDI is low when the ADC conversion ends (see Figure 28 and Figure 32), and TURBO must be kept low for both digital interfaces. When CNV is low, reading can occur during conversion and acquisition, and when split across acquisition and conversion, as detailed in the following sections. A discontinuous SCK is recommended because the part is selected with CNV low, and SCK activity begins to clock out data. Note that in the following sections, the timing diagrams indicate digital activity (SCK, CNV, SDI, and SDO) during the conversion. However, due to the possibility of performance degradation, digital activity should occur only prior to the safe data reading time, tDATA, because the AD7986 provides error correction circuitry that can correct for an incorrect bit decision during this time. From tDATA to tCONV, there is no error correction, and conversion results may be corrupted. Similarly, tQUIET, the time from the last falling edge of SCK to the rising edge of CNV, must remain free of digital activity. The user should configure the AD7986 and initiate the busy indicator (if desired in normal mode) prior to tDATA. It is also possible to corrupt the sample by having SCK near the sampling instant. Therefore, it is recommended to keep the digital pins quiet for approximately 20 ns before and 10 ns after the rising edge of CNV, using a discontinuous SCK whenever possible to avoid any potential performance degradation. Rev. B | Page 17 of 28 AD7986 DATA READING OPTIONS There are three different data reading options for the AD7986. There is the option to read during conversion, to split the read across acquisition and conversion (see Figure 27 and Figure 28), and in normal mode, to read during acquisition. The desired SCK frequency largely determines which reading option to pursue. Reading During Conversion, Fast Hosts (Turbo or Normal Mode) For turbo mode (2 MSPS), fSCK = 65 MHz; tDATA = 200 ns Number_SCK_Edges = 65 MHz × 200 ns = 13 Thirteen bits are read during conversion (n), and five bits are read during acquisition (n). For normal mode (1.5 MSPS), When reading during conversion (n), conversion results are for the previous (n − 1) conversion. Reading should only occur up to tDATA and, because this time is limited, the host must use a fast SCK. The required SCK frequency is calculated by f SCK ≥ To determine how to split the read for a particular SCK frequency, follow these examples to read data from conversion (n − 1). Number _ SCK _ Edges t DATA To determine the SCK frequency, follow these examples to read data from conversion (n − 1). fSCK = 50 MHz; tDATA = 300 ns Number_SCK_Edges = 50 MHz × 300 ns = 15 Fifteen bits are read during conversion (n), and three bits are read during acquisition (n). For slow throughputs, the time restriction is dictated by the user’s required throughput, and the host is free to run at any speed. Similar to the reading during acquisition, for slow hosts, the data access must take place during the acquisition phase with additional time into the conversion. Note that data access spanning conversion requires the CNV to be driven high to initiate a new conversion, and data access is not allowed when CNV is high. Thus, the host must perform two bursts of data access when using this method. Turbo mode (2 MSPS): Number_SCK_Edges = 18; tDATA = 200 ns fSCK = 18/200 ns = 90 MHz Normal mode (1.5 MSPS): Reading During Acquisition, Any Speed Hosts (Turbo or Normal Mode) Number_SCK_Edges = 18; tDATA = 300 ns fSCK = 18/300 ns = 60 MHz The time between tDATA and tCONV is an I/O quiet time where digital activity should not occur, or sensitive bit decisions may be corrupt. Split-Reading, Any Speed Host (Turbo or Normal Mode) To allow for slower SCK, there is the option of a split read where data access starts at the current acquisition (n) and spans into the conversion (n). Conversion results are for the previous (n − 1) conversion. When reading during acquisition (n), conversion results are for the previous (n − 1) conversion. Maximum throughput is achievable in normal mode (1.5 MSPS); however, in turbo mode, 2 MSPS throughput is not achievable. For the maximum throughput, the only time restriction is that the reading takes place during the tACQ (minimum) time. For slow throughputs, the time restriction is dictated by throughput required by the user, and the host is free to run at any speed. Thus for slow hosts, data access must take place during the acquisition phase. Similar to reading during conversion, split-reading should only occur up to tDATA. For the maximum throughput, the only time restriction is that split-reading take place during the tACQ (minimum) + tDATA − tQUIET time. The time between the falling edge of SCK and CNV rising is an acquisition quiet time, tQUIET. Rev. B | Page 18 of 28 AD7986 CS MODE, 3-WIRE WITHOUT BUSY INDICATOR conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD7986 enters the acquisition phase and powers down. When CNV goes low, the MSB is output onto SDO. The remaining data bits are clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided that it has an acceptable hold time. After the 18th SCK falling edge or when CNV goes high (whichever occurs first), SDO returns to high impedance. This mode is usually used when a single AD7986 is connected to an SPI-compatible digital host. The connection diagram is shown in Figure 25, and the corresponding timing is given in Figure 26. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. Once a conversion is initiated, it continues until completion irrespective of the state of CNV. This can be useful, for instance, to bring CNV low to select other SPI devices, such as analog multiplexers; however, CNV must be returned high before the minimum CONVERT DIGITAL HOST CNV VIO SDI AD7986 DATA IN SDO 07956-018 SCK CLK Figure 25. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High) tCYC > tCONV tCONV tDATA tCNVH SDI = 1 tCONV tDATA CNV tACQ ACQUISITION (n - 1) CONVERSION (n – 1) (I/O QUIET TIME) ACQUISITION (n) (QUIET TIME) (I/O QUIET TIME) CONVERSION (n) ACQUISITION (n + 1) tQUIET 16 17 1 18 16 2 17 tHSDO tEN SDO tDSDO tEN 2 0 1 tDIS END DATA (n – 2) 17 tDIS 18 tSCK 16 15 BEGIN DATA (n – 1) 2 Figure 26. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High) Rev. B | Page 19 of 28 1 tDIS END DATA (n – 1) 0 tDIS 07956-116 SCK AD7986 CS MODE, 3-WIRE WITH BUSY INDICATOR When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. The AD7986 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided that it has an acceptable hold time. After the optional 19th SCK falling edge, SDO returns to high impedance. This mode is usually used when a single AD7986 is connected to an SPI-compatible digital host having an interrupt input. It is only available in normal conversion mode (TURBO = low). The connection diagram is shown in Figure 27, and the corresponding timing is given in Figure 28. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. SDO is maintained in high impedance until the completion of the conversion irrespective of the state of CNV. Prior to the minimum conversion time, CNV can be used to select other SPI devices, such as analog multiplexers, but CNV must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. If multiple AD7986 devices are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. Meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. CONVERT VIO DIGITAL HOST CNV VIO 47kΩ SDI AD7986 DATA IN SDO IRQ TURBO 07956-020 SCK CLK Figure 27. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High) TURBO = 0 SDI = 1 tCYC tCNVH CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION (QUIET TIME) tSCK tQUIET tSCKL 1 2 3 17 tHSDO 18 19 tSCKH tDSDO SDO D17 D16 tDIS D1 D0 Figure 28. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High) Rev. B | Page 20 of 28 07956-021 SCK AD7986 CS MODE, 4-WIRE WITHOUT BUSY INDICATOR but SDI must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD7986 enters the acquisition phase and powers down. Each ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided that it has an acceptable hold time. After the 18th SCK falling edge, SDO returns to high impedance and another AD7986 can be read. This mode is usually used when multiple AD7986 devices are connected to an SPI-compatible digital host. A connection diagram example using two AD7986 devices is shown in Figure 29, and the corresponding timing is given in Figure 30. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback. (If SDI and CNV are low, SDO is driven low.) Prior to the minimum conversion time, SDI can be used to select other SPI devices, such as analog multiplexers, CS2 CS1 CONVERT CNV AD7986 SDO SDI AD7986 SCK DIGITAL HOST SDO SCK 07956-022 SDI CNV DATA IN CLK Figure 29. CS Mode, 4-Wire Without Busy Indicator Connection Diagram tCYC tCONV tDATA tCONV tDATA CNV tACQ ACQUISITION (n – 1) (I/O QUIET TIME) CONVERSION (n – 1) (QUIET TIME) ACQUISITION (n) (I/O QUIET ACQUISITION (n + 1) TIME) CONVERSION (n) tHSDICNV SDI tSSDICNV tQUIET 16 17 1 18 2 16 17 tHSDO tEN SDO tDSDO tEN 2 1 END DATA (n – 2) 17 0 tHSDO 18 tSCK 16 15 BEGIN DATA (n – 1) 2 tDIS END DATA (n – 1) Figure 30. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing Rev. B | Page 21 of 28 1 0 tDIS 07956-120 SCK AD7986 CS MODE, 4-WIRE WITH BUSY INDICATOR used to select other SPI devices, such as analog multiplexers, but SDI must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD7986 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided that it has an acceptable hold time. After the optional 19th SCK falling edge or SDI going high (whichever occurs first), SDO returns to high impedance. This mode is usually used when a single AD7986 is connected to an SPI-compatible digital host with an interrupt input and when it is desired to keep CNV, which is used to sample the analog input, independent of the signal used to select the data reading. This independence is particularly important in applications where low jitter on CNV is desired. This mode is only available in normal conversion mode (TURBO = low). The connection diagram is shown in Figure 31, and the corresponding timing is given in Figure 32. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback. (If SDI and CNV are low, SDO is driven low.) Prior to the minimum conversion time, SDI can be CS1 CONVERT VIO DIGITAL HOST CNV 47kΩ AD7986 SCK DATA IN SDO IRQ TURBO 07956-024 SDI CLK Figure 31. CS Mode, 4-Wire with Busy Indicator Connection Diagram TURBO = 0 tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION (I/O QUIET TIME) tSSDICNV SDI tSCK tHSDICNV tSCKL 1 2 3 tHSDO 17 18 19 tSCKH tDSDO tDIS tEN SDO D17 D16 D1 Figure 32. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing Rev. B | Page 22 of 28 D0 07956-025 SCK tQUIET AD7986 CHAIN MODE WITHOUT BUSY INDICATOR held high during the conversion phase and the subsequent data readback. When the conversion is complete, the MSB is output onto SDO, and the AD7986 enters the acquisition phase and powers down. The remaining data bits stored in the internal shift register are clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 18 × N clocks are required to read back the N ADCs. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate and consequently more AD7986 devices in the chain, provided that the digital host has an acceptable hold time. The maximum conversion rate may be reduced due to the total readback time. This mode can be used to daisy-chain multiple AD7986 devices on a 3-wire serial interface. It is only available in normal conversion mode (TURBO = low). This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using two AD7986 devices is shown in Figure 33, and the corresponding timing is given in Figure 34. When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects the chain mode, and disables the busy indicator. In this mode, CNV is CONVERT CNV AD7986 SDI A SCK SDO SDI DIGITAL HOST AD7986 B SCK TURBO DATA IN SDO TURBO 07956-026 CNV CLK Figure 33. Chain Mode Without Busy Indicator Connection Diagram TURBO= 0 tCYC ACQUISITION tCONV tACQ ACQUISITION CONVERSION tSSCKCNV SCK tSCKH 1 tHSCKCNV 2 tSSDISCK tEN SDOA = SDIB 3 4 tSCK 17 18 20 21 35 36 37 38 39 tSCKL tHSDISCK DA17 DA16 DA15 19 DA 1 SDOB = SDIC 55 tDSDOSDI tDSDOSDI DB17 DB16 DB15 DB1 DB0 DA17 DA16 DA1 DA0 DC17 DC16 DC15 DC1 DC0 DB17 DB16 DB1 DB0 DA17 DA16 tDSDOSDI SDOC 54 DA0 tHSDO tDSDO tDSDOSDI 53 tDSDOSDI Figure 34. Chain Mode Without Busy Indicator Serial Interface Timing Rev. B | Page 23 of 28 DA1 DA0 07956-027 CNV = SDIA AD7986 CHAIN MODE WITH BUSY INDICATOR subsequent data readback. When all ADCs in the chain have completed their conversions, the SDO pin of the ADC closest to the digital host (see the AD7986 ADC labeled C in Figure 35) is driven high. This transition on SDO can be used as a busy indicator to trigger the data readback controlled by the digital host. The AD7986 then enters the acquisition phase and powers down. The data bits stored in the internal shift register are clocked out, MSB first, by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 18 × N + 1 clocks are required to read back the N ADCs. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate and consequently more AD7986 devices in the chain, provided that the digital host has an acceptable hold time. This mode can also be used to daisy-chain multiple AD7986 devices on a 3-wire serial interface while providing a busy indicator. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using three AD7986 devices is shown in Figure 35, and the corresponding timing is given in Figure 36. When SDI and CNV are low, SDO is driven low. With SCK high, a rising edge on CNV initiates a conversion, selects the chain mode, and enables the busy indicator feature. In this mode, CNV is held high during the conversion phase and the CONVERT SDI CNV AD7986 A SCK SDO SDI CNV AD7986 B SCK TURBO SDO SDI DIGITAL HOST AD7986 C SCK TURBO SDO DATA IN IRQ TURBO 07956-028 CNV CLK Figure 35. Chain Mode with Busy Indicator Connection Diagram TURBO = 0 tCYC ACQUISITION tCONV tACQ ACQUISITION CONVERSION tQUIET SCK tSCKH 1 tHSCKCNV 2 tSSDISCK tEN SDOA = SDIB 3 4 tSCK 17 18 19 20 21 35 36 37 38 39 tSCKL tHSDISCK tDSDOSDI DA17 DA16 DA15 DA1 DA0 DB17 DB16 DB15 DB 1 DB0 DA17 DA16 DA1 DA0 55 DC17 DC16 DC15 D C1 DC0 DB17 DB16 DB1 DB0 DA17 DA16 tDSDOSDI tDSDOSDI SDOC 54 tDSDOSDI tHSDO tDSDO SDOB = SDIC 53 tDSDOSDI Figure 36. Chain Mode with Busy Indicator Serial Interface Timing Rev. B | Page 24 of 28 DA1 DA0 07956-029 CNV = SDIA AD7986 APPLICATION HINTS LAYOUT The printed circuit board (PCB) that houses the AD7986 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7986, with its analog signals on the left side and its digital signals on the right side, eases this task. Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7986 is used as a shield. Fast switching signals, such as CNV or clocks, should not run near analog signal paths. Crossover of digital and analog signals should be avoided. At least one ground plane should be used. It can be common or split between the digital and analog sections. In the latter case, the planes should be joined underneath the AD7986 devices. The AD7986 voltage reference input, REF, has a dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the REF and REFGND pins and connecting them with wide, low impedance traces. Finally, the power supplies, VDD and VIO of the AD7986, should be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7986 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. EVALUATING THE AD7986 PERFORMANCE The evaluation board package for the AD7986 (EVAL-AD7986EB) includes a fully assembled and tested evaluation board and software for controlling the board from a PC via the converter evaluation and development board, EVAL-CED1Z. Rev. B | Page 25 of 28 AD7986 AVDD BVDD REF REF REF PADDLE 1 2 GND GND GND GND 3 4 DVDD 5 GND 6 GND 07956-030 GND VIO Figure 37. Example Layout of the AD7986 (Top Layer) 5V EXTERNAL REFERENCE (ADR435 OR ADR445) REF REF AVDD CAVDD CBVDD BVDD REF GND CREF GND GND GND GND CDVDD DVDD GND GND VIO CVIO VIO 07956-031 GND Figure 38. Example Layout of the AD7986 (Bottom Layer) Rev. B | Page 26 of 28 AD7986 OUTLINE DIMENSIONS 0.60 MAX 4.00 BSC SQ 0.60 MAX 15 PIN 1 INDICATOR 20 16 1 PIN 1 INDICATOR 3.75 BSC SQ 0.50 BSC 2.65 2.50 SQ 2.35 EXPOSED PAD (BOTTOM VIEW) 5 10 1.00 0.85 0.80 12° MAX SEATING PLANE 0.50 0.40 0.30 0.80 MAX 0.65 TYP 0.30 0.23 0.18 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 090408-B TOP VIEW 6 11 Figure 39. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-20-4) Dimensions shown in millimeters ORDERING GUIDE Model1, 2, 3 AD7986BCPZ AD7986BCPZ-RL7 EVAL-AD7986EBZ EVAL-CED1Z 1 2 3 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Tray 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7” Tape and Reel Evaluation Board Converter Evaluation and Development Board Package Option CP-20-4 CP-20-4 Z = RoHS Compliant Part. The EVAL-AD7986EBZ can be used as a standalone evaluation board or in conjunction with the EVAL-CED1Z for evaluation/demonstration purposes. The EVAL-CED1Z allows a PC to control and communicate with all Analog Devices evaluation boards ending in the EB designator. Rev. B | Page 27 of 28 Ordering Quantity 490 1,500 AD7986 NOTES ©2009–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07956-0-3/11(B) Rev. B | Page 28 of 28