Linear LTC2433-1IMS Differential input 16-bit no latency ds adc Datasheet

LTC2433-1
Differential Input
16-Bit No Latency ∆Σ ADC
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FEATURES
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DESCRIPTIO
16-Bit Differential ADC in a Tiny MSOP
Low Supply Current: 200µA, 4µA in Autosleep
Rail-to-Rail Differential Input/Reference
0.12LSB INL, No Missing Codes
0.16LSB Full-Scale Error and 5µV Offset
1.45µV RMS Noise, Independent of VREF
Very Low Transition Noise: <0.02LSB
Operates with a Reference as Low as 100mV with
16-Bit Resolution
Internal Oscillator—No External Components
Required
87dB Min, Simultaneous 50Hz and 60Hz Notch Filter
Single Supply 2.7V to 5.5V Operation
Pin Compatible with the 20/24-Bit LTC2431/LTC2411
Available in 10-Lead MSOP Package
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APPLICATIO S
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Direct Sensor Digitizer
Weight Scales
Direct Temperature Measurement
Gas Analyzers
Strain-Gage Transducers
Instrumentation
Data Acquisition
Industrial Process Control
The converter accepts any external differential reference
voltage from 0.1V to VCC for flexible ratiometric and
remote sensing measurement configurations. The fullscale differential input range is from – 0.5 •␣ VREF to 0.5 •
VREF. The reference common mode voltage, VREFCM, and
the input common mode voltage, VINCM, may be independently set anywhere between GND and VCC. The DC
common mode input rejection is better than 140dB.
The LTC2433-1 communicates through a flexible 3-wire
digital interface which is compatible with SPI and
MICROWIRETM protocols.
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
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The LTC®2433-1 is a differential input micropower 16-bit
No Latency ∆ΣTM analog-to-digital converter with an integrated oscillator. It provides 0.12LSB INL and 1.45µV
RMS noise independent of VREF. It uses delta-sigma
technology and provides single conversion settling of the
digital filter. Through a single pin, the LTC2433-1 can be
configured for better than 87dB input differential mode
rejection at 50Hz and 60Hz ±2%, or it can be driven by an
external oscillator for a user defined rejection frequency.
The internal oscillator requires no external frequency
setting components.
TYPICAL APPLICATIO
Minimum Resolvable Signal vs VREF
1µF
1
4.9k
(100mV)
100Ω
2
4
VCC
FO
REF +
IN+
LTC2433-1
5
IN–
3
REF –
SDO
GND
CS
6
10
SCK
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
9
8
7
24331 TA01
3-WIRE
SPI INTERFACE
MINIMUM RESOLVABLE SIGNAL (µV)*
90
5V REF
80
70
60
50
40
30
20
10
0
5
4
3
2
VREF (V)
24331 TA02
*FOR VREF ≥ 0.5V THE RESOLUTION
IS LIMITED BY STEP SIZE
0
1
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LTC2433-1
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ABSOLUTE
RATI GS
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PACKAGE/ORDER I FOR ATIO
(Notes 1, 2)
Supply Voltage (VCC) to GND .......................– 0.3V to 7V
Analog Input Voltage
to GND .................................... – 0.3V to (VCC + 0.3V)
Reference Input Voltage
to GND .................................... – 0.3V to (VCC + 0.3V)
Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V)
Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2433-1C ............................................ 0°C to 70°C
LTC2433-1I ........................................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART NUMBER
LTC2433-1CMS
LTC2433-1IMS
TOP VIEW
VCC
REF+
REF –
IN+
IN–
1
2
3
4
5
10
9
8
7
6
FO
SCK
SDO
CS
GND
MS PART MARKING
MS10 PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 110°C/W
LTAEY
LTAEZ
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4, 6)
PARAMETER
CONDITIONS
MIN
Resolution (No Missing Codes)
0.1V ≤ VREF ≤ VCC, –0.5 • VREF ≤ VIN ≤ 0.5 • VREF, (Note 5)
Integral Nonlinearity (Note 15)
5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)
●
5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V, (Note 6)
REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)
●
TYP
MAX
UNITS
0.06
0.12
0.30
1.25
LSB
LSB
LSB
5
20
µV
16
Bits
Offset Error (Note 15)
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN+ = IN– ≤ VCC, (Note 13)
Offset Error Drift
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN+ = IN– ≤ VCC
Positive Full-Scale Error (Note 15)
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.75REF+, IN– = 0.25 • REF+
Positive Full-Scale Error Drift
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.75REF+, IN– = 0.25 • REF+
Negative Full-Scale Error (Note 15)
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.25 • REF+, IN– = 0.75 • REF+
Negative Full-Scale Error Drift
2.5V ≤ REF+ ≤ VCC, REF– = GND,
IN+ = 0.25 • REF+, IN– = 0.75 • REF+
0.04
ppm of VREF/°C
Total Unadjusted Error
5V ≤ VCC ≤ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V
5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V
REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6)
0.20
0.20
0.25
LSB
LSB
LSB
Output Noise
5V ≤ VCC ≤ 5.5V, REF+ = 5V, REF – = GND,
GND ≤ IN– = IN+ ≤ VCC, (Note 12)
1.45
µVRMS
●
20
●
0.16
nV/°C
1.25
0.04
●
0.16
LSB
ppm of VREF/°C
1.25
LSB
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LTC2433-1
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CO VERTER CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
Input Common Mode Rejection DC
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN– = IN+ ≤ VCC (Note 5)
●
130
140
MAX
UNITS
Input Common Mode Rejection
49Hz to 61.2Hz
2.5V ≤ REF+ ≤ VCC, REF– = GND,
GND ≤ IN – = IN+ ≤ VCC, (Notes 5, 7)
●
140
dB
Input Normal Mode Rejection
49Hz to 61.2Hz
(Note 5, 7)
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87
dB
Reference Common Mode
Rejection DC
2.5V ≤ REF+ ≤ VCC, GND ≤ REF– ≤ 2.5V,
VREF = 2.5V, IN– = IN+ = GND (Note 5)
●
130
Power Supply Rejection, DC
Power Supply Rejection,
Simultaneous 50Hz/60Hz ±2%
dB
140
dB
REF+ = 2.5V, REF– = GND, IN– = IN+ = GND
120
dB
REF+
120
dB
= 2.5V, REF– = GND, IN– = IN+ = GND, (Note 7)
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A ALOG I PUT A D REFERE CE
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
IN+
Absolute/Common Mode IN+ Voltage
CONDITIONS
MIN
TYP
MAX
UNITS
●
GND – 0.3
VCC + 0.3
IN–
Absolute/Common Mode IN– Voltage
●
GND – 0.3
VCC + 0.3
V
VIN
Input Differential Voltage Range
(IN+ – IN–)
●
–VREF/2
VREF/2
V
REF+
Absolute/Common Mode REF+ Voltage
●
0.1
VCC
V
REF–
Absolute/Common Mode REF– Voltage
●
GND
VCC – 0.1
V
VREF
Reference Differential Voltage Range
(REF+ – REF–)
●
0.1
VCC
V
CS (IN+)
V
IN+ Sampling Capacitance
6
pF
CS
(IN–)
IN–
6
pF
CS
(REF+)
REF+ Sampling Capacitance
6
pF
CS (REF–)
REF– Sampling Capacitance
6
pF
IDC_LEAK
(IN+)
IN+
IDC_LEAK
(IN–)
IN–
Sampling Capacitance
DC Leakage Current
●
–100
1
100
nA
CS = VCC
= 5V, IN – = 5.5V
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–100
1
100
nA
IDC_LEAK (REF+)
REF+ DC Leakage Current
CS = VCC = 5V, REF+ = 5.5V
●
–100
1
100
nA
(REF–)
REF– DC Leakage Current
= 5V, REF – = GND
●
–100
1
100
nA
IDC_LEAK
DC Leakage Current
CS = VCC
= 5V, IN+ = GND
CS = VCC
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LTC2433-1
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage
CS, FO
2.7V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 3.3V
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VIL
Low Level Input Voltage
CS, FO
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
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VIH
High Level Input Voltage
SCK
2.7V ≤ VCC ≤ 5.5V (Note 8)
2.7V ≤ VCC ≤ 3.3V (Note 8)
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VIL
Low Level Input Voltage
SCK
4.5V ≤ VCC ≤ 5.5V (Note 8)
2.7V ≤ VCC ≤ 5.5V (Note 8)
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IIN
Digital Input Current
CS, FO
0V ≤ VIN ≤ VCC
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IIN
Digital Input Current
SCK
0V ≤ VIN ≤ VCC (Note 8)
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CIN
Digital Input Capacitance
CS, FO
CIN
Digital Input Capacitance
SCK
(Note 8)
VOH
High Level Output Voltage
SDO
IO = –800µA
●
VOL
Low Level Output Voltage
SDO
IO = 1.6mA
●
VOH
High Level Output Voltage
SCK
IO = –800µA (Note 9)
●
VOL
Low Level Output Voltage
SCK
IO = 1.6mA (Note 9)
●
IOZ
Hi-Z Output Leakage
SDO
●
TYP
MAX
UNITS
2.5
2.0
V
V
0.8
0.6
V
V
2.5
2.0
V
V
0.8
0.6
V
V
–10
10
µA
–10
10
µA
10
pF
10
pF
VCC – 0.5
V
0.4
V
VCC – 0.5
V
–10
0.4
V
10
µA
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POWER REQUIRE E TS
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
Conversion Mode
Sleep Mode
Sleep Mode
CONDITIONS
MIN
●
CS = 0V (Note 14)
CS = VCC (Notes 11, 14)
CS = VCC, 2.7V ≤ VCC ≤ 3.3V
(Notes 11, 14)
●
●
TYP
2.7
200
4
2
MAX
UNITS
5.5
V
300
13
µA
µA
µA
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LTC2433-1
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TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
fEOSC
External Oscillator Frequency Range
●
tHEO
External Oscillator High Period
●
tLEO
External Oscillator Low Period
tCONV
Conversion Time
FO = 0V
External Oscillator (Note 10)
fISCK
Internal SCK Frequency
Internal Oscillator (Note 9)
External Oscillator (Notes 9, 10)
DISCK
Internal SCK Duty Cycle
(Note 9)
●
fESCK
External SCK Frequency Range
(Note 8)
●
tLESCK
External SCK Low Period
(Note 8)
●
tHESCK
External SCK High Period
(Note 8)
●
250
tDOUT_ISCK
Internal SCK 19-Bit Data Output Time
Internal Oscillator (Notes 9, 11)
External Oscillator (Notes 9, 10)
●
●
1.06
tDOUT_ESCK
External SCK 19-Bit Data Output Time
(Note 8)
●
t1
CS ↓ to SDO Low Z
●
0
200
ns
t2
CS ↑ to SDO High Z
●
0
200
ns
t3
CS ↓ to SCK ↓
(Note 9)
●
0
200
ns
t4
CS ↓ to SCK ↑
(Note 8)
●
50
tKQMAX
SCK ↓ to SDO Valid
MAX
UNITS
2.56
2000
kHz
0.25
390
µs
●
0.25
390
µs
●
●
143.8
tKQMIN
SDO Hold After SCK ↓
●
15
ns
t5
SCK Set-Up Before CS ↓
●
50
ns
t6
SCK Hold After CS ↓
●
Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified.
VREF = REF + – REF –, VREFCM = (REF + + REF –)/2; VIN = IN+ – IN –,
VINCM = (IN + + IN –)/2.
Note 4: FO pin tied to GND or to an external conversion clock source
with fEOSC = 139,800Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a precise analog input voltage. Maximum specifications are limited by
the LSB step size (VREF/216) and the single shot measurement. Typical
specifications are measured from the center of the quantization band.
Note 7: FO = GND (internal oscillator) or fEOSC = 139,800Hz ±2%
(external oscillator).
Note 8: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is fESCK and is expressed in kHz.
146.7
149.6
20510/fEOSC (in kHz)
17.5
fEOSC/8
45
ms
ms
kHz
kHz
55
%
2000
kHz
250
ns
ns
1.09
1.11
152/fEOSC (in kHz)
ms
ms
19/fESCK (in kHz)
ms
ns
220
●
(Note 5)
TYP
50
ns
ns
Note 9: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance CLOAD = 20pF.
Note 10: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 11: The converter uses the internal oscillator.
FO = 0V.
Note 12: 1.45µV RMS noise is independent of VREF. Since the noise
performance is limited by the quantization, lowering VREF improves the
effective resolution.
Note 13: Guaranteed by design and test correlation.
Note 14: The low sleep mode current is valid only when CS is high.
Note 15: These parameters are guaranteed by design over the full
supply and temperature range. Automated testing procedures are
limited by the LSB step size (VREF/65,536).
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LTC2433-1
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VCC (Pin 1): Positive Supply Voltage. Bypass to GND with
a 10µF tantalum capacitor in parallel with 0.1µF ceramic
capacitor as close to the part as possible.
REF + (Pin 2), REF – (Pin 3): Differential Reference Input.
The voltage on these pins can have any value between GND
and VCC as long as the reference positive input, REF +, is
maintained more positive than the reference negative
input, REF –, by at least 0.1V.
IN+ (Pin 4), IN – (Pin 5): Differential Analog Input. The
voltage on these analog inputs can have any value between
GND and VCC. Within these limits the converter bipolar
input range (VIN = IN+ – IN–) extends from – 0.5 • (VREF )
to 0.5 • (VREF ). Outside this input range the converter
produces unique overrange and underrange output codes.
GND (Pin 6): Ground. Connect this pin to a ground plane
through a low impedance connection.
CS (Pin 7): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 8): Three-State Digital Output. During the Data
Output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = VCC) the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS LOW.
SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as digital input for the external serial interface
clock during the Data Output period. A weak internal pullup is automatically activated in Internal Serial Clock Operation mode. The Serial Clock Operation mode is determined by the logic level applied to the SCK pin at power up
or during the most recent falling edge of CS.
FO (Pin 10): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the FO pin is connected to GND (FO = 0V), the
converter uses its internal oscillator and rejects 50Hz and
60Hz simultaneously. When FO is driven by an external
clock signal with a frequency fEOSC, the converter uses this
signal as its system clock and the digital filter has 87dB
minimum rejection in the range fEOSC/2560 ±14% and
110dB minimum rejection at fEOSC/2560 ±4%.
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FU CTIO AL DIAGRA
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INTERNAL
OSCILLATOR
VCC
GND
IN +
IN –
AUTOCALIBRATION
AND CONTROL
+
–∫
∫
FO
(INT/EXT)
∫
∑
SDO
SERIAL
INTERFACE
ADC
SCK
CS
DECIMATING FIR
DAC
24331 FD
REF +
REF –
Figure 1. Functional Block Diagram
TEST CIRCUITS
VCC
1.69k
SDO
SDO
1.69k
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
CLOAD = 20pF
24361 TA03
CLOAD = 20pF
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
24361 TA04
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APPLICATIO S I FOR ATIO
CONVERTER OPERATION
Converter Operation Cycle
The LTC2433-1 is a low power, ∆Σ ADC with differential
input/reference and an easy-to-use 3-wire serial interface
(see Figure 1). Its operation is made up of three states.
The converter operating cycle begins with the conversion,
followed by the low power sleep state and ends with the
data output (see Figure 2). The 3-wire interface consists
of serial data output (SDO), serial clock (SCK) and chip
select (CS).
Initially, the LTC2433-1 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
The part remains in the sleep state as long as CS is HIGH.
While in this sleep state, power consumption is reduced by
nearly two orders of magnitude. The conversion result is
held indefinitely in a static shift register while the converter
is in the sleep state.
Once CS is pulled LOW, the device exits the low power
mode and enters the data output state. If CS is pulled HIGH
before the first rising edge of SCK, the device returns to the
low power sleep mode and the conversion result is still
held in the internal static shift register. If CS remains LOW
after the first rising edge of SCK, the device begins
outputting the conversion result. Taking CS high at this
point will terminate the data output state and start a new
CONVERT
SLEEP
FALSE
CS = LOW
AND
SCK
conversion. There is no latency in the conversion result.
The data output corresponds to the conversion just performed. This result is shifted out on the serial data out pin
(SDO) under the control of the serial clock (SCK). Data is
updated on the falling edge of SCK allowing the user to
reliably latch data on the rising edge of SCK (see Figure 3).
The data output state is concluded once 19 bits are read
out of the ADC or when CS is brought HIGH. The device
automatically initiates a new conversion and the cycle
repeats. In order to maintain compatibility with 24-/32-bit
data transfers, it is possible to clock the LTC2433-1 with
additional serial clock pulses. This results in additional
data bits which are logic HIGH.
Through timing control of the CS and SCK pins, the
LTC2433-1 offers several flexible modes of operation
(internal or external SCK and free-running conversion
modes). These various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of
operation are described in detail in the Serial Interface
Timing Modes section.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50Hz and
60Hz plus their harmonics. The filter rejection performance is directly related to the accuracy of the converter
system clock. The LTC2433-1 incorporates a highly accurate on-chip oscillator. This eliminates the need for external frequency setting components such as crystals or
oscillators. Clocked by the on-chip oscillator, the
LTC2433-1 achieves a minimum of 87dB rejection over
the range 49Hz to 61.2Hz.
TRUE
Ease of Use
DATA OUTPUT
24331 F02
Figure 2. LTC2433-1 State Transition Diagram
The LTC2433-1 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
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APPLICATIO S I FOR ATIO
The LTC2433-1 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation described above. The advantage of continuous calibration is
extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2433-1 automatically enters an internal reset state
when the power supply voltage VCC drops below approximately 2V. This feature guarantees the integrity of the
conversion result and of the serial interface mode selection. (See the 2-wire I/O sections in the Serial Interface
Timing Modes section.)
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a typical duration of 1ms. The POR signal clears
all internal registers. Following the POR signal, the
LTC2433-1 starts a normal conversion cycle and follows
the succession of states described above. The first conversion result following POR is accurate within the specifications of the device if the power supply voltage is restored
within the operating range (2.7V to 5.5V) before the end of
the POR time interval.
Reference Voltage Range
This converter accepts a truly differential external reference voltage. The absolute/common mode voltage specification for the REF + and REF – pins covers the entire range
from GND to VCC. For correct converter operation, the
REF + pin must always be more positive than the REF – pin.
The LTC2433-1 can accept a differential reference voltage
from 0.1V to VCC. The converter output noise is determined by the thermal noise of the front-end circuits, and
as such, its value in microvolts is nearly constant with
reference voltage. A decrease in reference voltage will
significantly improve the converter’s effective resolution,
since the thermal noise (1.45µV) is well below the quantization level of the device (75.6µV for a 5V reference). At
the minimum reference (100mV) the thermal noise
remains constant at 1.45µV RMS (or 8.7µVP-P), while the
quantization is reduced to 1.5µV per LSB. As a result,
lowering the reference improves the effective resolution
for low level input voltages.
Input Voltage Range
The analog input is truly differential with an absolute/
common mode range for the IN+ and IN– input pins
extending from GND – 0.3V to VCC + 0.3V. Outside these
limits, the ESD protection devices begin to turn on and the
errors due to input leakage current increase rapidly. Within
these limits, the LTC2433-1 converts the bipolar differential input signal, VIN = IN+ – IN–, from – FS = – 0.5 • VREF to
+FS = 0.5 • VREF where VREF = REF+ – REF–. Outside this
range, the converter indicates the overrange or the
underrange condition using distinct output codes.
Input signals applied to the analog input pins may extend
by 300mV below ground and above VCC. In order to limit
any fault current, resistors of up to 5k may be added in
series with the pins without affecting the performance of
the device. In the physical layout, it is important to maintain the parasitic capacitance of the connection between
these series resistors and the corresponding pins as low
as possible; therefore, the resistors should be located as
close as practical to the pins. The effect of the series
resistance on the converter accuracy can be evaluated
from the curves presented in the Input Current/Reference
Current sections. In addition, series resistors will introduce a temperature dependent offset error due to the input
leakage current. A 10nA input leakage current will develop
a 1LSB offset error on an 8k resistor if VREF = 5V. This error
has a very strong temperature dependency.
Output Data Format
The LTC2433-1 serial output data stream is 19 bits long.
The first 3 bits represent status information indicating the
conversion state and sign. The next 16 bits are the conversion result, MSB first. The third and fourth bit together are
also used to indicate an underrange condition (the differential input voltage is below –FS) or an overrange condition (the differential input voltage is above +FS).
24331fa
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Bit 18 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 17 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 16 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this
bit is LOW.
Bit 15 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 16 also
provides the underrange or overrange indication. If both
Bit 16 and Bit 15 are HIGH, the differential input voltage is
above +FS. If both Bit 16 and Bit 15 are LOW, the
differential input voltage is below –FS.
The function of these bits is summarized in Table 1.
Table 1. LTC2433-1 Status Bits
Bit 18 Bit 17 Bit 16 Bit 15
EOC DMY SIG MSB
Input Range
VIN ≥ 0.5 • VREF
0
0
1
1
0V ≤ VIN < 0.5 • VREF
0
0
1
0
–0.5 • VREF ≤ VIN < 0V
0
0
0
1
VIN < – 0.5 • VREF
0
0
0
0
Bits 15-0 are the 16-Bit conversion result MSB first.
Bit 0 is the least significant bit (LSB).
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external microcontroller. Bit 18 (EOC) can be captured on the first rising
edge of SCK. Bit 17 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 18th SCK and may be latched on
the rising edge of the 19th SCK pulse. On the falling edge
of the 19th SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 18) for the next conversion cycle. Table 2 summarizes
the output data format.
In order to remain compatible with some SPI
microcontrollers, more than 19 SCK clock pulses may be
applied. As long as these clock edges are complete before
the conversion ends, they will not effect the serial data.
However, switching SCK during a conversion may generate ground currents in the device leading to extra offset
and noise error sources.
As long as the voltage on the analog input pins is maintained within the – 0.3V to (VCC + 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 • VREF to
+FS = 0.5 • VREF. For differential input voltages greater than
+FS, the conversion result is clamped to the value corresponding to the +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
CS
SDO
BIT 18
BIT 17
BIT 16
BIT 15
EOC
“O”
SIG
MSB
BIT 14
BIT 1
BIT 0
LSB16
Hi-Z
SCK
1
SLEEP
2
3
4
5
DATA OUTPUT
17
18
19
CONVERSION
24331 F03
Figure 3. Output Data Timing
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Table 2. LTC2433-1 Output Data Format
Differential Input Voltage
VIN *
Bit 18
EOC
Bit 17
DMY
Bit 16
SIG
Bit 15
MSB
Bit 14
Bit 13
Bit 12
…
Bit 0
VIN* ≥ 0.5 • VREF**
0
0
1
1
0
0
0
…
0
0.5 • VREF** – 1LSB
0
0
1
0
1
1
1
…
1
0.25 • VREF**
0
0
1
0
1
0
0
…
0
0.25 • VREF** – 1LSB
0
0
1
0
0
1
1
…
1
0
0
0
1
0
0
0
0
…
0
–1LSB
0
0
0
1
1
1
1
…
1
– 0.25 • VREF**
0
0
0
1
1
0
0
…
0
– 0.25 • VREF** – 1LSB
0
0
0
1
0
1
1
…
1
– 0.5 • VREF**
0
0
0
1
0
0
0
…
0
VIN* < –0.5 • VREF**
0
0
0
0
1
1
1
…
1
*The differential input voltage VIN = IN+ – IN–.
**The differential reference voltage VREF = REF+ – REF–.
–80
–85
–90
NORMAL MODE REJECTION (dB)
NORMAL MODE REECTION RATIO (dB)
–80
–100
–100
–120
–130
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
48
50
52
54
56
58
60
62
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
24361 F04
–140
–12
–8
–4
0
4
8
12
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY fEOSC/2560(%)
24361 F05
Figure 4. LTC2433-1 Normal Mode
Rejection When Using an Internal Oscillator
Simultaneous Frequency Rejection
The LTC2433-1 internal oscillator provides better than
87dB normal mode rejection over the range of 49Hz to
61.2Hz as shown in Figure 4. For this simultaneous 50Hz/
60Hz rejection, FO should be connected to GND.
When a fundamental rejection frequency different from
the range 49Hz to 61.2Hz is required or when the converter
must be sychronized with an outside source, the LTC2433-1
can operate with an external conversion clock. The conveter
automatically detects the presence of an external clock
signal at the FO pin and turns off the internal oscillator. The
frequency fEOSC of the external signal must be at least
Figure 5. LTC2433-1 Normal Mode Rejection When
Using an External Oscillator of Frequency fEOSC
2560Hz to be detected. The external clock signal duty cycle
is not significant as long as the minimum and maximum
specifications for the high and low periods, tHEO and tLEO,
are observed.
While operating with an external conversion clock of a
frequency fEOSC, the LTC2433-1 provides better than 110dB
normal mode rejection in a frequency range fEOSC/2560
±4%. The normal mode rejection as a function of the input
frequency deviation from fEOSC/2560 is shown in Figure 5.
Whenever an external clock is not present at the FO pin the
converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2433-1
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operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
outside specifications but the following conversions will
not be affected. If the change occurs during the data output
state and the converter is in the Internal SCK mode, the
serial clock duty cycle may be affected but the serial data
stream will remain valid.
dividing the internal conversion clock by 8. In the External
SCK mode of operation, the SCK pin is used as input. The
internal or external SCK mode is selected on power-up and
then reselected every time a HIGH-to-LOW transition is
detected at the CS pin. If SCK is HIGH or floating at powerup or during this transition, the converter enters the internal SCK mode. If SCK is LOW at power-up or during this
transition, the converter enters the external SCK mode.
Table 3 summarizes the duration of each state and the
achievable output data rate as a function of FO.
The serial data output pin, SDO (Pin 8), provides the result
of the last conversion as a serial bit stream (MSB first)
during the data output state. In addition, the SDO pin is
used as an end of conversion indicator during the conversion and sleep states.
SERIAL INTERFACE PINS
The LTC2433-1 transmits the conversion results and
receives the start of conversion command through a
synchronous 3-wire interface. During the conversion and
sleep states, this interface can be used to assess the
converter status and during the data output state it is used
to read the conversion result.
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 9) is used to
synchronize the data transfer. Each bit of data is shifted out
the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2433-1 creates its own serial clock by
Serial Data Output (SDO)
When CS (Pin 7) is HIGH, the SDO driver is switched to a
high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW.
Chip Select Input (CS)
The active LOW chip select, CS (Pin 7), is used to test the
conversion status and to enable the data output transfer as
described in the previous sections.
Table 3. LTC2433-1 State Duration
State
Operating Mode
CONVERT
Internal Oscillator
FO = LOW
Simultaneous 50Hz/60Hz Rejection
Duration
147ms, Output Data Rate ≤ 6.8 Readings/s
External Oscillator
FO = External Oscillator
with Frequency fEOSC kHz
(fEOSC/2560 Rejection)
20510/fEOSCs, Output Data Rate ≤ fEOSC/20510 Readings/s
Internal Serial Clock
FO = LOW
(Internal Oscillator)
As Long As CS = LOW But Not Longer Than 1.09ms
(19 SCK cycles)
FO = External Oscillator with
Frequency fEOSC kHz
As Long As CS = LOW But Not Longer Than 152/fEOSCms
(19 SCK cycles)
SLEEP
DATA OUTPUT
As Long As CS = HIGH Until CS = LOW and SCK
External Serial Clock with
Frequency fSCK kHz
As Long As CS = LOW But Not Longer Than 19/fSCKms
(19 SCK cycles)
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operation. These include internal/external serial clock,
2- or 3-wire I/O, single cycle conversion and autostart. The
following sections describe each of these serial interface
timing modes in detail. In all these cases, the converter
can use the internal oscillator (FO = LOW) or an external
oscillator connected to the FO pin. Refer to Table␣ 4 for a
summary.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2433-1 will abort any serial data
transfer in progress and start a new conversion cycle
anytime a LOW-to-HIGH transition is detected at the CS
pin after the converter has entered the data output state
(i.e., after the first rising edge of SCK occurs with
CS␣ =␣ LOW).
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
Grounding CS will force the ADC to continuously convert
at the maximum output rate selected by FO.
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 6.
The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock pin
(SCK) must be LOW during each CS falling edge.
SERIAL INTERFACE TIMING MODES
The LTC2433-1’s 3-wire interface is SPI and MICROWIRE
compatible. This interface offers several flexible modes of
Table 4. LTC2433-1 Interface Timing Modes
Configuration
SCK
Source
Conversion
Cycle
Control
Data
Output
Control
Connection
and
Waveforms
External SCK, Single Cycle Conversion
External
CS and SCK
CS and SCK
Figures 6, 7
External SCK, 2-Wire I/O
External
SCK
SCK
Figure 8
Internal SCK, Single Cycle Conversion
Internal
CS ↓
CS ↓
Figures 9, 10
Internal SCK, 2-Wire I/O, Continuous Conversion
Internal
Continuous
Internal
Figure 11
2.7V TO 5.5V
1µF
1
VCC
FO
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
10
LTC2433-1
REFERENCE
VOLTAGE
0.1V TO VCC
2
REF +
3
REF –
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
4
IN +
SDO
5
IN –
CS
6
SCK
9
3-WIRE
SPI INTERFACE
8
7
GND
CS
TEST EOC
SDO
Hi-Z
BIT 18
BIT 17
BIT 16
BIT 15
EOC
“O”
SIG
MSB
BIT 14
BIT 13
BIT 2
BIT 1
BIT 0
TEST EOC
LSB
Hi-Z
Hi-Z
SCK
(EXTERNAL)
CONVERSION
SLEEP
SLEEP
DATA OUTPUT
CONVERSION
24331 F06
TEST EOC
(OPTIONAL)
Figure 6. External Serial Clock, Single Cycle Operation
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SDO goes HIGH (EOC = 1) indicating a conversion is in
progress.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC␣ =␣ 1 while a conversion is in progress and EOC = 0 if
the device is in the sleep state. With CS high, the device
automatically enters the low power sleep state once the
conversion is complete.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the
19th falling edge of SCK, see Figure 7. On the rising edge
of CS, the device aborts the data output state and immediately initiates a new conversion. This is useful for aborting an invalid conversion cycle or synchronizing the start
of a conversion.
When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift register. Data is shifted out the SDO pin on each falling edge of
SCK. This enables external circuitry to latch the output on
the rising edge of SCK. EOC can be latched on the first
rising edge of SCK and the last bit of the conversion result
can be latched on the 19th rising edge of SCK. On the 19th
falling edge of SCK, the device begins a new conversion.
2.7V TO 5.5V
1µF
1
VCC
FO
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
10
LTC2433-1
REFERENCE
VOLTAGE
0.1V TO VCC
2
REF +
3
REF –
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
4
IN +
SDO
5
IN –
CS
6
SCK
9
3-WIRE
SPI INTERFACE
8
7
GND
CS
BIT 0
SDO
TEST EOC
EOC
Hi-Z
Hi-Z
BIT 18
BIT 17
BIT 16
BIT 15
EOC
“O”
SIG
MSB
BIT 14
Hi-Z
BIT 5
TEST EOC
BIT 4
Hi-Z
SCK
(EXTERNAL)
SLEEP
CONVERSION
DATA
OUTPUT
SLEEP
DATA OUTPUT
SLEEP
CONVERSION
24331 F07
TEST EOC (OPTIONAL)
Figure 7. External Serial Clock, Reduced Data Output Length
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External Serial Clock, 2-Wire I/O
Internal Serial Clock, Single Cycle Operation
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an externally generated serial clock (SCK) signal, see Figure 8. CS
may be permanently tied to ground, simplifying the user
interface or isolation barrier.
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 9.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
typically 1ms after VCC exceeds 2V. The level applied to
SCK at this time determines if SCK is internal or external.
SCK must be driven LOW prior to the end of POR in order
to enter the external serial clock timing mode.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is ready.
EOC = 1 while the conversion is in progress and EOC␣ =␣ 0
once the conversion ends. On the falling edge of EOC, the
conversion result is loaded into an internal static shift register. Data is shifted out the SDO pin on each falling edge
of SCK enabling external circuitry to latch data on the rising edge of SCK. EOC can be latched on the first rising edge
of SCK. On the 19th falling edge of SCK, SDO goes HIGH
(EOC␣ =␣ 1) indicating a new conversion has begun.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state during the EOC test. In
order to allow the device to return to the low power sleep
state, CS must be pulled HIGH before the first rising edge
of SCK. In the internal SCK timing mode, SCK goes HIGH
2.7V TO 5.5V
1µF
1
VCC
FO
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
10
LTC2433-1
REFERENCE
VOLTAGE
0.1V TO VCC
2
REF +
3
REF –
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
4
IN +
SDO
5
IN –
CS
6
SCK
9
3-WIRE
SPI INTERFACE
8
7
GND
CS
SDO
BIT 18
BIT 17
BIT 16
BIT 15
EOC
“O”
SIG
MSB
BIT 14
BIT 13
BIT 2
BIT 1
BIT 0
LSB
SCK
(EXTERNAL)
CONVERSION
DATA OUTPUT
CONVERSION
24331 F08
Figure 8. External Serial Clock, CS = 0 Operation (2-Wire)
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VCC
2.7V TO 5.5V
1µF
1
VCC
FO
10
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
10k
LTC2433-1
REFERENCE
VOLTAGE
0.1V TO VCC
2
REF +
3
REF –
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
4
IN +
SDO
5
IN –
CS
6
SCK
9
3-WIRE
SPI INTERFACE
8
7
GND
<tEOCtest
CS
SDO
Hi-Z
BIT 18
BIT 17
BIT 16
BIT 15
EOC
“O”
SIG
MSB
BIT 14
BIT 13
BIT 2
BIT 1
BIT 0
TEST EOC
LSB
Hi-Z
Hi-Z
Hi-Z
SCK
(INTERNAL)
CONVERSION
SLEEP
DATA OUTPUT
SLEEP
CONVERSION
24331 F09
TEST EOC
(OPTIONAL)
Figure 9. Internal Serial Clock, Single Cycle Operation
and the device begins outputting data at time tEOCtest after
the falling edge of CS (if EOC = 0) or tEOCtest after EOC goes
LOW (if CS is LOW during the falling edge of EOC). The
value of tEOCtest is 23µs if the device is using its internal
oscillator (F0 = logic LOW). If FO is driven by an external
oscillator of frequency fEOSC, then tEOCtest is 3.6/fEOSC. If
CS is pulled HIGH before time tEOCtest, the device returns
to the sleep state and the conversion result is held in the
internal static shift register.
If CS remains LOW longer than tEOCtest, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle concludes
after the 19th rising edge. Data is shifted out the SDO pin
on each falling edge of SCK. The internally generated serial
clock is output to the SCK pin. This signal may be used to
shift the conversion result into external circuitry. EOC can
be latched on the first rising edge of SCK and the last bit
of the conversion result on the 19th rising edge of SCK.
After the 19th rising edge, SDO goes HIGH (EOC = 1), SCK
stays HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 19th rising edge of
SCK, see Figure 10. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for aborting an invalid
conversion cycle, or synchronizing the start of a conversion. If CS is pulled HIGH while the converter is driving
SCK LOW, the internal pull-up is not available to restore
SCK to a logic HIGH state. This will cause the device to exit
the internal serial clock mode on the next falling edge of
CS. This can be avoided by adding an external 10k pull-up
resistor to the SCK pin or by never pulling CS HIGH when
SCK is LOW.
Whenever SCK is LOW, the LTC2433-1’s internal pull-up
at pin SCK is disabled. Normally, SCK is not externally
driven if the device is in the internal SCK timing mode.
However, certain applications may require an external
driver on SCK. If this driver goes Hi-Z after outputting a
LOW signal, the LTC2433-1’s internal pull-up remains
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VCC
2.7V TO 5.5V
1µF
1
VCC
FO
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
10
10k
LTC2433-1
REFERENCE
VOLTAGE
0.1V TO VCC
2
REF +
3
REF –
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
4
IN +
SDO
5
IN –
CS
6
> tEOCtest
SCK
9
3-WIRE
SPI INTERFACE
8
7
GND
<tEOCtest
CS
TEST EOC
BIT 0
SDO
EOC
Hi-Z
Hi-Z
Hi-Z
BIT 18
BIT 17
BIT 16
BIT 15
EOC
“O”
SIG
MSB
BIT 14
BIT 13
Hi-Z
BIT 2
TEST EOC
Hi-Z
SCK
(INTERNAL)
SLEEP
CONVERSION
DATA
OUTPUT
SLEEP
SLEEP
DATA OUTPUT
CONVERSION
24331 F10
TEST EOC
(OPTIONAL)
Figure 10. Internal Serial Clock, Reduced Data Output Length
disabled. Hence, SCK remains LOW. On the next falling
edge of CS, the device is switched to the external SCK
timing mode. By adding an external 10k pull-up resistor to
SCK, this pin goes HIGH once the external driver goes
Hi-Z. On the next CS falling edge, the device will remain in
the internal SCK timing mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the
conversion status. If the device is in the sleep state (EOC
= 0), SCK will go LOW. Once CS goes HIGH (within the time
period defined above as tEOCtest), the internal pull-up is
activated. For a heavy capacitive load on the SCK pin, the
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 11. CS may be permanently tied to ground, simplifying the user interface or isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after VCC exceeds 2V. An internal weak
pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
24331fa
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2.7V TO 5.5V
1µF
1
VCC
FO
10
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
LTC2433-1
REFERENCE
VOLTAGE
0.1V TO VCC
2
REF +
3
REF –
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
4
IN +
SDO
5
IN –
CS
6
SCK
9
8
3-WIRE
SPI INTERFACE
7
GND
CS
SDO
BIT 18
BIT 17
BIT 16
BIT 15
EOC
“O”
SIG
MSB
BIT 14
BIT 13
BIT 2
BIT 1
BIT 0
LSB
SCK
(INTERNAL)
CONVERSION
DATA OUTPUT
CONVERSION
24331 F11
Figure 11. Internal Serial Clock, Continuous Operation
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
data output state. The data output cycle begins on the
first rising edge of SCK and ends after the 19th rising
edge. Data is shifted out the SDO pin on each falling edge
of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result can be latched on the 19th rising
edge of SCK. After the 19th rising edge, SDO goes HIGH
(EOC = 1) indicating a new conversion is in progress. SCK
remains HIGH during the conversion.
PRESERVING THE CONVERTER ACCURACY
The LTC2433-1 is designed to reduce as much as possible
the conversion result sensitivity to device decoupling,
PCB layout, antialiasing circuits, line frequency perturbations and so on. Nevertheless, in order to preserve the
accuracy capability of this part, some simple precautions
are desirable.
Digital Signal Levels
The LTC2433-1’s digital interface is easy to use. Its digital
inputs (FO, CS and SCK in External SCK mode of operation)
accept standard TTL/CMOS logic levels and the internal
hysteresis receivers can tolerate edge rates as slow as
100µs. However, some considerations are required to take
advantage of the exceptional accuracy and low supply
current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(VCC␣ –␣ 0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (FO, CS and SCK
in External SCK mode of operation) is within this range, the
LTC2433-1 power supply current may increase even if the
signal in question is at a valid logic level. For micropower
operation, it is recommended to drive all digital input
signals to full CMOS levels [VIL < 0.4V and VOH >
(VCC – 0.4V)].
24331fa
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During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the
LTC2433-1 pins may severely disturb the analog to digital
conversion process. Undershoot and overshoot can occur because of the impedance mismatch at the converter
pin when the transition time of an external control signal
is less than twice the propagation delay from the driver to
LTC2433-1. For reference, on a regular FR-4 board, signal
propagation velocity is approximately 183ps/inch for
internal traces and 170ps/inch for surface traces. Thus, a
driver generating a control signal with a minimum transition time of 1ns must be connected to the converter pin
through a trace shorter than 2.5 inches. This problem
becomes particularly difficult when shared control lines
are used and multiple reflections may occur. The solution
is to carefully terminate all transmission lines close to
their characteristic impedance.
Parallel termination near the LTC2433-1 pin will eliminate
this problem but will increase the driver power dissipation.
A series resistor between 27Ω and 56Ω placed near the
driver will also eliminate this problem without additional
power dissipation. The actual resistor value depends upon
the trace impedance and connection topology.
An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The multiple ground pins used
in this package configuration, as well as the differential
input and reference architecture, reduce substantially the
converter’s sensitivity to ground currents.
Particular attention must be given to the connection of the
FO signal when the LTC2433-1 is used with an external
conversion clock. This clock is active during the conversion time and the normal mode rejection provided by the
internal digital filter is not very high at this frequency. A
normal mode signal of this frequency at the converter
reference terminals may result in DC gain and INL errors.
A normal mode signal of this frequency at the converter
input terminals may result in a DC offset error. Such
perturbations may occur due to asymmetric capacitive
coupling between the FO signal trace and the converter
input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation
between the FO signal trace and the input/reference signals. When the FO signal is parallel terminated near the
converter, substantial AC current is flowing in the loop
formed by the FO connection trace, the termination and the
ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or reference. In this situation, the user must reduce to a minimum
the loop area for the FO signal as well as the loop area for
the differential input and reference connections.
Driving the Input and Reference
The input and reference pins of the LTC2433-1 converter
are directly connected to a network of sampling capacitors. Depending upon the relation between the differential
input voltage and the differential reference voltage, these
capacitors are switching between these four pins
transfering small amounts of charge in the process. A
simplified equivalent circuit is shown in Figure 12, where
IN+ and IN– refer to the selected differential channel and
the unselected channel is omitted for simplicity.
For a simple approximation, the source impedance RS
driving an analog input pin (IN+, IN–, REF+ or REF–) can be
considered to form, together with RSW and CEQ (see
Figure␣ 12), a first order passive network with a time
constant τ = (RS + RSW) • CEQ. The converter is able to
sample the input signal with better than 1LSB accuracy if
the sampling period is at least 11 times greater than the
input circuit time constant τ. The sampling process on the
four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worstcase circumstances, the errors may add.
When using the internal oscillator (FO = LOW), the
LTC2433-1’s front-end switched-capacitor network is
clocked at 69900Hz corresponding to a 14.3µs sampling
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IREF+
− VREFCM
( )AVG = VIN + V0INCM
.5 • REQ
−V + V
−V
I(IN− )
= IN INCM REFCM
AVG
0.5 • REQ
VCC
I IN+
RSW (TYP)
20k
ILEAK
VREF+
ILEAK
VCC
IIN+
ILEAK
RSW (TYP)
20k
VIN+
CEQ
6pF
(TYP)
ILEAK
IIN –
VCC
RSW (TYP)
20k
ILEAK
(
+ VREFCM
IN
−
)AVG = 1.5 • VREF0−.5V•INCM
REQ
VREF • REQ
(
+ VREFCM
IN
+
)AVG = −1.5 • VREF0.−5 •VINCM
REQ
VREF • REQ
I REF −
V2
where:
VREF = REF + − REF −
VIN –
 REF + + REF − 
VREFCM = 

2


ILEAK
IREF –
V2
I REF +
VCC
ILEAK
VIN = IN+ − IN−
RSW (TYP)
20k
24331 F12
VREF –
ILEAK
 IN+ − IN− 
VINCM = 

2


REQ = 11.9MΩ INTERNAL OSCILLATOR 50Hz / 60Hz Notch (FO = LOW)
SWITCHING FREQUENCY
fSW = 69900Hz INTERNAL OSCILLATOR (FO = LOW)
fSW = 0.5 • fEOSC EXTERNAL OSCILLATOR
(
)
REQ = 1.67 • 1012 / fEOSC EXTERNAL OSCILLATOR
Figure 12. LTC2433-1 Equivalent Analog Input Circuit
Input Current
If complete settling occurs on the input, conversion results will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 12 shows the
mathematical expressions for the average bias currents
flowing through the IN + and IN – pins as a result of the
sampling charge transfers when integrated over a substantial time period (longer than 64 internal clock cycles).
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 13. The CPAR capacitor
includes the LTC2433-1 pin capacitance (5pF typical) plus
the capacitance of the test fixture used to obtain the results
shown in Figures 14 and 15. A careful implementation can
bring the total input capacitance (CIN + CPAR) closer to 5pF
thus achieving better performance than the one predicted
RSOURCE
VINCM + 0.5VIN
IN +
CIN
CPAR
≅ 20pF
RSOURCE
VINCM – 0.5VIN
LTC2433-1
IN –
CIN
CPAR
≅ 20pF
24331 F13
Figure 13. An RC Network at IN + and IN –
3
+FS ERROR (LSB)
period. Thus, for settling errors of less than 1LSB, the
driving source impedance should be chosen such that τ ≤
14.3µs/11 = 1.3µs. When an external oscillator of frequency fEOSC is used, the sampling period is 2/fEOSC and,
for a settling error of less than 1LSB, τ ≤ 0.18/fEOSC.
VCC = 5V
REF + = 5V CIN = 0.01µF
REF – = GND
IN + = 5V
IN – = 2.5V
FO = GND
TA = 25°C
2
CIN = 0.001µF
CIN = 100pF
1
CIN = 0pF
0
1
10
100
1k
RSOURCE (Ω)
10k
100k
24331 F14
Figure 14. +FS Error vs RSOURCE at IN+ or IN– (Small CIN)
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8
VCC = 5V
REF + = 5V
REF – = GND
IN + = GND
IN – = 2.5V CIN = 0pF
FO = GND
TA = 25°C
CIN = 100pF
–1
+FS ERROR (LSB)
–FS ERROR (LSB)
0
CIN = 0.001µF
–2
CIN = 0.01µF
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
CIN = 10µF
CIN = 1µF
4
CIN = 0.1µF
CIN = 0.01µF
0
–3
1
10
100
1k
RSOURCE (Ω)
10k
100k
24331 F15
Figure 15. –FS Error vs RSOURCE at IN+ or IN– (Small CIN)
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
24331 F16
Figure 16. +FS Error vs RSOURCE at IN+ or IN– (Large CIN)
0
–FS ERROR (ppm OF VREF)
CIN = 0.01µF
CIN = 0.1µF
–4
–8
VCC = 5V
REF + = 5V
REF – = GND
IN + = 1.25V
IN – = 3.75V
FO = GND
TA = 25°C
CIN = 10µF
CIN = 1µF
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
24331 F17
Figure 17. –FS Error vs RSOURCE at IN+ or IN– (Large CIN)
by Figures 14 and 15. For simplicity, two distinct situations can be considered.
For relatively small values of input capacitance (CIN <
0.01µF), the voltage on the sampling capacitor settles
almost completely and relatively large values for the
source impedance result in only small errors. Such values
for CIN will deteriorate the converter offset and gain
performance without significant benefits of signal filtering
and the user is advised to avoid them. Nevertheless, when
small values of CIN are unavoidably present as parasitics
of input multiplexers, wires, connectors or sensors, the
LTC2433-1 can maintain its accuracy while operating with
relative large values of source resistance as shown in
Figures 14 and 15. These measured results may be slightly
different from the first order approximation suggested
earlier because they include the effect of the actual second
order input network together with the nonlinear settling
process of the input amplifiers. For small CIN values, the
settling on IN+ and IN – occurs almost independently and
there is little benefit in trying to match the source impedance for the two pins.
Larger values of input capacitors (CIN > 0.01µF) may be
required in certain configurations for antialiasing or general input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When FO = LOW (internal oscillator and 50Hz/60Hz notch),
the typical differential input resistance is 6MΩ which will
generate a gain error of approximately 1LSB at full scale
for each 180Ω of source resistance driving IN+ or IN –.
When FO is driven by an external oscillator with a frequency fEOSC (external conversion clock operation), the
typical differential input resistance is 0.84 • 1012/fEOSCΩ
and each ohm of source resistance driving IN+ or IN – will
result in 3.7 • 10 –8 • fEOSCLSB gain error at full scale. The
effect of the source resistance on the two input pins is
additive with respect to this gain error. The typical +FS and
–FS errors as a function of the sum of the source resistance seen by IN+ and IN– for large values of CIN are shown
in Figures 16 and 17.
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In addition to this gain error, an offset error term may also
appear. The offset error is proportional with the mismatch
between the source impedance driving the two input pins
IN+ and IN– and with the difference between the input and
reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the converter average input current will not degrade the INL
performance, indirect distortion may result from the modulation of the offset error by the common mode component
of the input signal. Thus, when using large CIN capacitor
values, it is advisable to carefully match the source impedance seen by the IN+ and IN– pins. When FO = LOW
(internal oscillator and 50Hz/60Hz notch), every 180Ω
mismatch in source impedance transforms a full-scale
common mode input signal into a differential mode input
signal of 1LSB. When FO is driven by an external oscillator
with a frequency fEOSC, every 1Ω mismatch in source
impedance transforms a full-scale common mode input
signal into a differential mode input signal of 3.7 • 10–8
• fEOSCLSB. Figure 18 shows the typical offset error due to
input common mode voltage for various values of source
resistance imbalance between the IN+ and IN– pins when
large CIN values are used.
3
VCC = 5V
REF + = 5V
REF – = GND
IN + = IN – = VINCM
A
OFFSET ERROR (LSB)
2
B
1
C
E
–1
F
FO = GND
TA = 25°C
RSOURCEIN – = 500Ω
CIN = 10µF
–2
G
–3
0
0.5
1
1.5
2 2.5 3
VINCM (V)
A: ∆RIN = +400Ω
B: ∆RIN = +200Ω
C: ∆RIN = +100Ω
D: ∆RIN = 0Ω
3.5
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by IN+ and
IN–, the expected drift of the dynamic current, offset and
gain errors will be insignificant (about 1% of their respective values over the entire temperature and voltage range).
Even for the most stringent applications, a one-time
calibration operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 15k source resistance will create
a 0LSB typical and 1LSB maximum offset voltage.
Reference Current
D
0
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
4
4.5
5
E: ∆RIN = –100Ω
F: ∆RIN = –200Ω
G: ∆RIN = –400Ω
24331 F18
Figure 18. Offset Error vs Common Mode Voltage
(VINCM = IN+ = IN–) and Input Source Resistance
Imbalance (∆RIN = RSOURCEIN+ – RSOURCEIN–) for
Large CIN Values (CIN ≥ 1µF)
In a similar fashion, the LTC2433-1 samples the differential reference pins REF+ and REF– transfering small amount
of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can be
analyzed in the same two distinct situations.
For relatively small values of the external reference capacitors (CREF < 0.01µF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
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Larger values of reference capacitors (CREF > 0.01µF) may
be required as reference filters in certain configurations.
Such capacitors will average the reference sampling charge
and the external source resistance will see a quasi constant reference differential impedance. When FO = LOW
(internal oscillator and 50Hz/60Hz notch), the typical
differential reference resistance is 4.2MΩ which will generate a gain error of approximately 1LSB full scale for each
120Ω of source resistance driving REF+ or REF–. When FO
is driven by an external oscillator with a frequency fEOSC
(external conversion clock operation), the typical differential reference resistance is 0.60 • 1012/fEOSCΩ and each
ohm of source resistance drving REF+ or REF– will result
in 5.1 • 10–8 • fEOSCLSB gain error at full scale. The effect
of the source resistance on the two reference pins is
additive with respect to this gain error. The typical +FS and
–FS errors for various combinations of source resistance
seen by the REF+ and REF– pins and external capacitance
CREF connected to these pins are shown in Figures 19, 20,
21 and␣ 22.
In addition to this gain error, the converter INL performance is degraded by the reference source impedance.
When FO = LOW (internal oscillator and 50Hz/60Hz notch),
every 1000Ω of source resistance driving REF+ or REF–
translates into about 1LSB additional INL error. When FO
is driven by an external oscillator with a frequency fEOSC,
every 1000Ω of source resistance driving REF+ or REF–
3
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
–1
–FS ERROR (LSB)
+FS ERROR (LSB)
0
CREF = 0pF
CREF = 100pF
–2
VCC = 5V
REF + = 5V
REF – = GND
IN + = 1.25V
IN – = 3.75V
2 FO = GND
TA = 25°C
CREF = 0pF
CREF = 100pF
1
CREF = 0.001µF
CREF = 0.001µF
CREF = 0.01µF
CREF = 0.01µF
–3
1
10
100
1k
RSOURCE (Ω)
10k
0
100k
1
10
100
1k
RSOURCE (Ω)
10k
24331 F20
24331 F19
Figure 19. +FS Error vs RSOURCE at REF+ or REF– (Small CIN)
Figure 20. –FS Error vs RSOURCE at REF+ or REF– (Small CIN)
0
10
VCC = 5V
REF + = 5V
REF – = GND
IN + = 1.25V
IN – = 3.75V
FO = GND
TA = 25°C
CREF = 0.01µF
CREF = 10µF
CREF = 1µF
– FS ERROR (LSB)
+FS ERROR (LSB)
CREF = 0.1µF
–5
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
–10
100k
CREF = 10µF
CREF = 1µF
5
CREF = 0.1µF
CREF = 0.01µF
0
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
24331 F21
Figure 21. +FS Error vs RSOURCE at REF+ and REF– (Large CREF)
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
24331 F22
Figure 22. –FS Error vs RSOURCE at REF+ and REF– (Large CREF)
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translates into about 7.15 • 10–6 • fEOSCLSB additional INL
error. Figure␣ 23 shows the typical INL error due to the
source resistance driving the REF+ or REF– pins when
large CREF values are used. The effect of the source
resistance on the two reference pins is additive with
respect to this INL error. In general, matching of source
impedance for the REF+ and REF– pins does not help the
gain or the INL error. The user is thus advised to minimize
the combined source impedance driving the REF+ and
REF– pins rather than to try to match it.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typical better than
0.5%. Such a specification can also be easily achieved by
an external clock. When relatively stable resistors
(50ppm/°C) are used for the external source impedance
seen by REF+ and REF–, the expected drift of the dynamic
current gain error will be insignificant (about 1% of its
value over the entire temperature and voltage range). Even
for the most stringent applications a one-time calibration
operation may be sufficient.
INL (LSB)
1
RSOURCE = 1000Ω
0
–1
–0.5 –0.4–0.3–0.2–0.1 0 0.1 0.2 0.3 0.4 0.5
VINDIF/VREFDIF
VCC = 5V
FO = GND
REF+ = 5V
CREF = 10µF
TA = 25°C
REF– = GND
24331 F23
VINCM = 0.5 • (IN + + IN –) = 2.5V
Figure 23. INL vs Differential Input Voltage (VIN = IN+ – IN–)
and Reference Source Resistance (RSOURCE at REF+ and REF–
for Large CREF Values (CREF ≥ 1µF)
In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
(±10nA max), results in a small gain error. A 100Ω source
resistance will create a 0.05µV typical and 0.5µV maximum full-scale error.
Output Data Rate
When using its internal oscillator, the LTC2433-1 can
produce up to 6.8 readings per second. The actual output
data rate will depend upon the length of the sleep and data
output phases which are controlled by the user and which
can be made insignificantly short. When operated with an
external conversion clock (FO connected to an external
oscillator), the LTC2433-1 output data rate can be increased as desired. The duration of the conversion phase
is 20510/fEOSC. If fEOSC = 139,800Hz, the converter behaves as if the internal oscillator is used with simultaneous
50Hz/60Hz. There is no significant difference in the
LTC2433-1 performance between these two operation
modes.
An increase in fEOSC over the nominal 139,800Hz will
translate into a proportional increase in the maximum
output data rate. This substantial advantage is nevertheless accompanied by three potential effects, which must
be carefully considered.
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent performance degradation can be substantially reduced by relying upon the LTC2433-1’s exceptional common mode
rejection and by carefully eliminating common mode to
differential mode conversion sources in the input circuit.
The user should avoid single-ended input filters and
should maintain a very high degree of matching and
symmetry in the circuits driving the IN+ and IN– pins.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
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input and/or reference capacitors (CIN, CREF) are used, the
previous section provides formulae for evaluating the
effect of the source resistance upon the converter performance for any value of fEOSC. If small external input and/
or reference capacitors (CIN, CREF) are used, the effect of
the external source resistance upon the LTC2433-1 typical
performance can be inferred from Figures 14, 15, 19 and
20 in which the horizontal axis is scaled by 139,800/fEOSC.
15
VCC = 5V
VREF = 5V
VINCM = 2.5V
VIN = 0V
FO = EXT OSC
VCC = 5V
VREF = 5V
IN + = 3.75V
IN – = 1.25V
FO = EXT OSC
12
+FS ERROR (LSB)
OFFSET ERROR (LSB)
8
Third, an increase in the frequency of the external oscillator above 460800Hz (a more than 3× increase in the output
data rate) will start to decrease the effectiveness of the
internal autocalibration circuits. This will result in a progressive degradation in the converter accuracy and linearity. Typical measured performance curves for output data
rates up to 100 readings per second are shown in Figures␣ 24, 25, 26, 27, 28 and 29. In order to obtain the
TA = 85°C
0
9
6
TA = 85°C
3
TA = 25°C
TA = 25°C
0
–3
–8
0
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
24331 F25
24331 F24
Figure 24. Offset Error vs Output Data Rate and Temperature
Figure 25. +FS Error vs Output Data Rate and Temperature
50
6
–FS ERROR (LSB)
3
0
TA = 85°C
–3
VCC = 5V
VREF = 5V
–6 IN + = 1.25V
IN – = 3.75V
FO = EXT OSC
–9
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
24331 F26
Figure 26. –FS Error vs Output Data Rate and Temperature
NUMBER OF READINGS (%)
TA = 25°C
40
GAUSSIAN DISTRIBUTION
m = 3.1µV
σ = 1.59µVRMS
30
VCC = 5V
VREF = 0.1V
VIN = 0V
REF+ = 0.1V
REF – = GND
IN+ = GND
IN– = GND
FO = 2.048MHz
TA = 125°C
20
10
0
–1
0
1
3
2
OUTPUT CODE
4
5
2433 F27
Figure 27. Noise Histogram (Output Rate = 100Hz,
VCC = 5V, VREF = 100mV, 125°C)
24331fa
25
LTC2433-1
U
W
U U
APPLICATIO S I FOR ATIO
22
3
VREF = 2.5V
OFFSET ERROR (LSB)
RESOLUTION (BITS)
20
18
16
VCC = 5V
VREF+ = 5V
VREF – = GND
VINCM = 2.5V
–2.5V < VIN < 2.5V
FO = EXTERNAL OSCILLATOR
14
12
10
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/sec)
2433 F28
0
VREF = 5V
–3
VCC = 5V
REF – = GND
VINCM = 2.5V
VIN = 0V
FO = EXT OSC
TA = 25°C
–6
–9
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
24331 F29
Figure 28. Integral Nonlinearity vs Output Data Rate
Figure 29. Offset Error vs Output
Data Rate and Reference Voltage
highest possible level of accuracy from this converter at
output data rates above 20 readings per second, the user
is advised to maximize the power supply voltage used and
to limit the maximum ambient operating temperature. In
certain circumstances, a reduction of the differential reference voltage may be beneficial.
the output code will be stable to ±1LSB for a fixed input. As
the reference is decreased further, the measured noise will
approach 1.45µVRMS.
Increasing Input Resolution by Reducing Reference
Voltage
The resolution of the LTC2433-1 can be increased by
reducing the reference voltage. It is often necessary to
amplify low level signals to increase the voltage resolution
of ADCs that cannot operate with a low reference voltage.
The LTC2433-1 can be used with reference voltages as low
as 100mV, corresponding to a ±50mV input range with full
16-bit resolution. Reducing the reference voltage is functionally equivalent to amplifying the input signal, however
no amplifier is required.
The LTC2433-1 has a 76µV LSB when used with a 5V
reference, however the thermal noise of the inputs is
1.45µVRMS and is independent of reference voltage. Thus
reducing the reference voltage will increase the resolution
at the inputs as long as the LSB voltage is significantly
larger than 1.45µVRMS. A 570mV reference corresponds
to a 8.7µV LSB, which is approximately the peak-to-peak
value of the 1.45µVRMS input thermal noise. At this point,
Figure 30 shows two methods of dividing down the
reference voltage to the LTC2433-1. Where absolute accuracy is required, a precision divider such as the Vishay
MPM series dividers in a SOT-23 package may be used. A
51:1 divider provides a 98mV reference to the LTC2433-1
from a 5V source. The resulting ±49mV input range and
1.5µV LSB is suitable for thermocouple and 10mV fullscale strain gauge measurements.
If high initial accuracy is not critical, a standard 2%
resistor array such as the Panasonic EXB series may be
used. Single package resistor arrays provide better temperature stability than discrete resistors. An array of eight
resistors can be configured as shown to provide a 294mV
reference to the LTC2433-1 from a 5V source. The fully
differential property of the LTC2433-1 reference terminals
allow the reference voltage to be taken from four central
resistors in the network connected in parallel, minimizing
drift in the presence of thermal gradients. This is an ideal
reference for medium accuracy sensors such as silicon
micromachined pressure and force sensors. These devices typically have accuracies on the order of 2% and fullscale outputs of 50mV to 200mV.
24331fa
26
LTC2433-1
U
PACKAGE DESCRIPTIO
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.50
0.305 ± 0.038
(.0197)
(.0120 ± .0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
0.497 ± 0.076
(.0196 ± .003)
REF
10 9 8 7 6
3.00 ± 0.102
(.118 ± .004)
NOTE 4
4.90 ± 0.15
(1.93 ± .006)
DETAIL “A”
0° – 6° TYP
GAUGE PLANE
1 2 3 4 5
0.53 ± 0.01
(.021 ± .006)
DETAIL “A”
1.10
(.043)
MAX
0.86
(.034)
REF
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
NOTE:
BSC
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.13 ± 0.076
(.005 ± .003)
MSOP (MS) 0802
24331fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC2433-1
U
TYPICAL APPLICATIO
PANASONIC EXB-2HV202G
REF +
5V
8 × 2k
ARRAY
5V
0.1µF
4.7µF
REF –
VREF = 294mV
±147mV INPUT RANGE
4.5µV LSB
1
2
5V
VISHAY MPM1001/5002B
3
50k
REF +
FO
REF –
IN+
LTC2433-1
5
IN–
SCK
SDO
6
1k
10
REF +
4
5V
HONEYWELL
FSL05N2C
500 GRAM
FORCE SENSOR
VCC
GND
CS
9
8
7
24331 F30
REF –
VREF = 95.04mV
±49mV INPUT RANGE
1.5µV LSB
Figure 30. Increased Resolution Bridge/Temperature Measurement
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1019
Precision Bandgap Reference, 2.5V, 5V
3ppm/°C Drift, 0.05% Max
LTC1043
Dual Precision Instrumentation Switched Capacitor
Building Block
Precise Charge, Balanced Switching, Low Power
LTC1050
Precision Chopper Stabilized Op Amp
No External Components 5µV Offset, 1.6µVP-P Noise
LT1236A-5
Precision Bandgap Reference, 5V
0.05% Max, 5ppm/°C Drift
LT1461
Micropower Precision LDO Reference
High Accuracy 0.04% Max, 3ppm/°C Max Drift
LTC2400
24-Bit, No Latency ∆Σ ADC in SO-8
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2401/LTC2402
1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP
0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2404/LTC2408
4-/8-Channel, 24-Bit, No Latency ∆Σ ADC
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2410
24-Bit, Fully Differential, No Latency ∆Σ ADC
0.16ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA
LTC2411
24-Bit, No Latency ∆Σ ADC in MSOP
1.45µVRMS Noise, 2ppm INL, Pin Compatible with LTC2433-1
LTC2412
2-Channel, 24-Bit, Pin Compatible with LTC2436-1
800nV Noise, 2ppm INL, 3ppm TUE, 200µA
LTC2413
24-Bit, No Latency ∆Σ ADC
Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise
LTC2414/LTC2418
8-/16-Channel, 24-Bit No Latency ∆Σ ADC
0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA
LTC2415
24-Bit, No Latency ∆Σ ADC with 15Hz Output Rate
Pin Compatible with the LTC2410
LTC2420
20-Bit, No Latency ∆Σ ADC in SO-8
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400
LTC2424/LTC2428
4-/8-Channel, 20-Bit, No Latency ∆Σ ADCs
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408
LTC2431
20-Bit, Differential No Latency ∆Σ ADC
Pin Compatible with LTC2433-1
LTC2436-1
Low Cost 16-Bit ∆Σ ADC
800nVRMS Noise 2-Channel Ping-Pong
LTC2440
High Speed, Low Noise 24-Bit ADC
4kHz Output Rate, 200µV Noise, 24.6 ENOBs
24331fa
28
Linear Technology Corporation
LT/TP 0104 1K REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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 LINEAR TECHNOLOGY CORPORATION 2003