ON MC74ACT574MEL Octal d flip−flop with 3−state output Datasheet

MC74AC574, MC74ACT574
Octal D Flip−Flop with
3−State Outputs
The MC74AC574/74ACT574 is a high−speed, low power octal
flip−flop with a buffered common Clock (CP) and a buffered common
Output Enable (OE). The information presented to the D inputs is
stored in the flip−flops on the LOW−to−HIGH Clock (CP) transition.
The MC74AC574/74ACT574 is functionally identical to the
MC74AC374/74ACT374 except for the pinouts.
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PDIP−20
N SUFFIX
CASE 738
Features
• Inputs and Outputs on Opposite Sides of Package Allowing Easy
•
•
•
•
•
•
Interface with Microprocessors
Useful as Input or Output Port for Microprocessors
Functionally Identical to MC74AC374/74ACT374
3-State Outputs for Bus-Oriented Applications
Outputs Source/Sink 24 mA
′ACT574 Has TTL Compatible Inputs
Pb−Free Packages are Available
1
SOIC−20W
DW SUFFIX
CASE 751D
1
VCC
O0
O1
O2
O3
O4
O5
O6
O7
CP
20
19
18
17
16
15
14
13
12
11
TSSOP−20
DT SUFFIX
CASE 948E
1
1
2
3
4
5
6
7
8
9
10
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
SOEIAJ−20
M SUFFIX
CASE 967
1
Figure 1. Pinout: 20−Lead Packages Conductors
(Top View)
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 6 of this data sheet.
PIN ASSIGNMENT
PIN
FUNCTION
D0−D7
Data Inputs
CP
Clock Pulse Input
OE
3−State Output Enable Input
O0−O7
3−State Outputs
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
D0 D1 D2 D3 D4 D5 D6 D7
CP
OE
O0 O1 O2 O3 O4 O5 O6 O7
Figure 2. Logic Symbol
© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 8
1
Publication Order Number:
MC74AC574/D
MC74AC574, MC74ACT574
FUNCTIONAL DESCRIPTION
FUNCTION TABLE
The MC74AC574/74ACT574 consists of eight edgetriggered flip−flops with individual D−type inputs and
3−state true outputs. The buffered clock and buffered Output
Enable are common to all flip−flops. The eight flip−flops
will store the state of their individual D inputs that meet the
setup and hold time requirements on the LOW−to−HIGH
Clock (CP) transition. With the Output Enable (OE) LOW,
the contents of the eight flip−flops are available at the
outputs. When OE is HIGH, the outputs go to the high
impedance state. Operation of the OE input does not affect
the state of the flip−flops.
D0
D1
Inputs
Internal
Outputs
Function
OE
CP
D
Q
On
H
H
H
H
L
L
L
L
H
H
L
H
L
H
L
H
L
H
NC
NC
L
H
L
H
NC
NC
Z
Z
Z
Z
L
H
NC
NC
H
H
Hold
Hold
Load
Load
Data Available
Data Available
No Change in Data
No Change in Data
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Clock Transition
NC = No Change
D2
D3
D4
D5
D6
D7
CP
C
D
C
D
C
D
C
D
C
D
C
C
D
D
C
Q
Q
Q
Q
Q
Q
Q
Q
O0
O1
O2
O3
O4
O5
O6
O7
D
OE
NOTE:
This diagram is provided only for the understanding of logic operations
and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
−0.5 to +7.0
V
V
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
−0.5 to VCC +0.5
DC Output Voltage (Referenced to GND)
VOUT
−0.5 to VCC +0.5
V
DC Input Current, per Pin
±20
mA
IOUT
DC Output Sink/Source Current, per Pin
±50
mA
ICC
DC VCC or GND Current per Output Pin
±50
mA
Tstg
Storage Temperature
−65 to +150
°C
IIN
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2
MC74AC574, MC74ACT574
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
tr, tf
Parameter
Min
Typ
Max
′AC
2.0
5.0
6.0
′ACT
4.5
5.0
5.5
0
−
VCC
VCC @ 3.0 V
−
150
−
VCC @ 4.5 V
−
40
−
VCC @ 5.5 V
−
25
−
VCC @ 4.5 V
−
10
−
VCC @ 5.5 V
−
8.0
−
−
−
140
°C
−40
25
85
°C
Supply Voltage
DC Input Voltage, Output Voltage (Ref. to GND)
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
Unit
V
V
ns/V
tr, tf
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
TJ
Junction Temperature (PDIP)
TA
Operating Ambient Temperature Range
IOH
Output Current − High
−
−
−24
mA
IOL
Output Current − Low
−
−
24
mA
ns/V
1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. VIN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
DC CHARACTERISTICS
Symbol
Parameter
VCC
(V)
74AC
74AC
TA = +25°C
TA = −40°C to +85°C
Typ
VIH
VIL
VOH
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
Unit
Conditions
Guaranteed Limits
3.0
1.5
2.1
2.1
4.5
2.25
3.15
3.15
5.5
2.75
3.85
3.85
3.0
1.5
0.9
0.9
4.5
2.25
1.35
1.35
5.5
2.75
1.65
1.65
3.0
2.99
2.9
2.9
4.5
4.49
4.4
4.4
5.5
5.49
5.4
5.4
VOUT = 0.1 V
V
or VCC − 0.1 V
VOUT = 0.1 V
V
or VCC − 0.1 V
IOUT = −50 mA
V
*VIN = VIL or VIH
VOL
3.0
−
2.56
2.46
4.5
−
3.86
3.76
5.5
−
4.86
4.76
3.0
0.002
0.1
0.1
4.5
0.001
0.1
0.1
5.5
0.001
0.1
0.1
3.0
−
0.36
0.44
4.5
−
0.36
0.44
5.5
−
0.36
0.44
5.5
−
±0.1
±1.0
mA
VI = VCC, GND
†Minimum Dynamic
Output Current
5.5
−
−
75
mA
VOLD = 1.65 V Max
5.5
−
−
−75
mA
VOHD = 3.85 V Min
Maximum Quiescent Supply Current
5.5
−
8.0
80
mA
VIN = VCC or GND
Maximum Low Level
Output Voltage
V
−12 mA
IOH
−24 mA
−24 mA
IOUT = 50 mA
V
*VIN = VIL or VIH
IIN
IOLD
IOHD
ICC
Maximum Input
Leakage Current
V
3
IOL
24 mA
24 mA
* All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
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12 mA
MC74AC574, MC74ACT574
AC CHARACTERISTICS (For Figures and Waveforms − See AND8277/D at www.onsemi.com)
Symbol
Parameter
VCC*
(V)
74AC
74AC
TA = +25°C
CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
Min
Typ
Max
Min
Max
Unit
Fig.
No.
fmax
Maximum Clock
Frequency
3.3
5.0
75
95
−
−
−
−
60
85
−
−
MHz
3−3
tPLH
Propagation Delay
CP to On
3.3
5.0
3.5
2.0
−
−
13.5
9.5
3.5
2.0
15
11
ns
3−6
tPHL
Propagation Delay
CP to On
3.3
5.0
3.5
2.0
−
−
12
8.5
3.5
2.0
13.5
9.5
ns
3−6
tPZH
Output Enable Time
3.3
5.0
2.5
2.0
−
−
11
8.5
2.5
2.0
12
9.0
ns
3−7
tPZL
Output Enable Time
3.3
5.0
3.0
1.5
−
−
10.5
8.0
3.5
2.0
11.5
9.0
ns
3−8
tPHZ
Output Disable Time
3.3
5.0
4.0
2.0
−
−
12
9.5
4.5
2.0
13
10.5
ns
3−7
tPLZ
Output Disable Time
3.3
5.0
2.0
1.5
−
−
9.0
7.5
2.5
1.5
10
8.5
ns
3−8
Unit
Fig.
No.
* Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
AC OPERATING REQUIREMENTS
Symbol
Parameter
VCC*
(V)
74AC
74AC
TA = +25°C
CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
Typ
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Dn to CP
3.3
5.0
−
−
2.5
1.5
3.0
2.0
ns
3−9
th
Hold Time, HIGH or LOW
Dn to CP
3.3
5.0
−
−
1.5
1.5
1.5
1.5
ns
3−9
3.3
5.0
−
−
6.0
4.0
7.0
5.0
ns
3−6
CP Pulse Width
HIGH or LOW
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
tw
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4
MC74AC574, MC74ACT574
DC CHARACTERISTICS
Symbol
Parameter
VCC
(V)
74ACT
74ACT
TA = +25°C
TA = −40°C to +85°C
Typ
Unit
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
VOUT = 0.1 V
or VCC − 0.1 V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
VOUT = 0.1 V
or VCC − 0.1 V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
V
4.5
5.5
−
−
3.86
4.86
3.76
4.76
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
4.5
5.5
−
−
0.36
0.36
0.44
0.44
V
*VIN = VIL or VIH
24 mA
IOL
24 mA
Maximum Input
Leakage Current
5.5
−
±0.1
±1.0
mA
VI = VCC, GND
Additional Max. ICC/Input
5.5
0.6
1.5
mA
VI = VCC − 2.1 V
Maximum
3-State
Current
5.5
−
±0.5
±5.0
mA
VI (OE) = VIL, VIH
VI = VCC, GND
VO = VCC, GND
5.5
−
−
75
mA
VOLD = 1.65 V Max
5.5
−
−
−75
mA
VOHD = 3.85 V Min
5.5
−
8.0
80
mA
VIN = VCC or GND
VOL
IIN
DICCT
IOZ
IOLD
IOHD
ICC
Maximum Low Level
Output Voltage
†Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
IOUT = −50 mA
*VIN = VIL or VIH
IOH −24 mA
−24 mA
V
IOUT = 50 mA
V
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS (For Figures and Waveforms − See AND8277/D at www.onsemi.com)
Symbol
Parameter
VCC*
(V)
74ACT
74ACT
TA = +25°C
CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
Min
Typ
Max
Min
Max
Unit
Fig.
No.
fmax
Maximum Clock
Frequency
5.0
100
−
−
85
−
ns
3−3
tPLH
Propagation Delay
CP to On
5.0
2.5
−
11
2.0
12
ns
3−6
tPHL
Propagation Delay
CP to On
5.0
2.0
−
10
1.5
11
ns
3−6
tPZH
Output Enable Time
5.0
2.0
−
9.5
1.5
10
ns
3−7
tPZL
Output Enable Time
5.0
2.0
−
9.0
1.5
10
ns
3−8
tPHZ
Output Disable Time
5.0
2.0
−
10.5
1.5
11.5
ns
3−7
tPLZ
Output Disable Time
5.0
2.0
−
8.5
1.5
9.0
ns
3−8
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
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5
MC74AC574, MC74ACT574
AC OPERATING REQUIREMENTS
Symbol
VCC*
Parameter
(V)
74ACT
74ACT
TA = +25°C
CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
Typ
Unit
Fig.
No.
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Dn to CP
5.0
−
2.5
2.5
ns
3−9
th
Hold Time, HIGH or LOW
Dn to CP
5.0
−
1.0
1.0
ns
3−9
5.0
−
3.0
4.0
ns
3−6
CP Pulse Width
HIGH or LOW
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
tw
CAPACITANCE
Symbol
Parameter
Value Typ
Unit
Test Conditions
CIN
Input Capacitance
4.5
pF
VCC = 5.0 V
CPD
Power Dissipation Capacitance
40
pF
VCC = 5.0 V
MARKING DIAGRAMS
PDIP−20
SOIC−20W
TSSOP−20
20
20
20
1
1
1
20
20
20
74AC574
AWLYWWG
1
20
ACT
574
ALYWG
G
ACT574
AWLYYWWG
MC74ACT574N
AWLYYWWG
20
AC
574
ALYWG
G
AC574
AWLYYWWG
MC74AC574N
AWLYYWWG
SOEIAJ−20
1
1
1
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
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6
74ACT574
AWLYWWG
1
MC74AC574, MC74ACT574
ORDERING INFORMATION
Device
Package
MC74AC574N
PDIP−20
MC74AC574NG
PDIP−20
(Pb−Free)
MC74ACT574N
PDIP−20
MC74ACT574NG
PDIP−20
(Pb−Free)
MC74AC574DW
SOIC−20
MC74AC574DWG
SOIC−20
(Pb−Free)
MC74AC574DWR2
SOIC−20
MC74AC574DWR2G
SOIC−20
(Pb−Free)
MC74ACT574DW
SOIC−20
MC74ACT574DWG
SOIC−20
(Pb−Free)
MC74ACT574DWR2
SOIC−20
MC74ACT574DWR2G
SOIC−20
(Pb−Free)
MC74AC574DTR2
TSSOP−20*
MC74AC574DTR2G
TSSOP−20*
MC74ACT574DTR2
TSSOP−20*
MC74ACT574DTR2G
TSSOP−20*
MC74AC574M
SOEIAJ−20
MC74AC574MG
SOEIAJ−20
(Pb−Free)
MC74AC574MEL
SOEIAJ−20
MC74AC574MELG
SOEIAJ−20
(Pb−Free)
MC74ACT574M
SOEIAJ−20
MC74ACT574MG
SOEIAJ−20
(Pb−Free)
MC74ACT574MEL
SOEIAJ−20
MC74ACT574MELG
SOEIAJ−20
(Pb−Free)
Shipping †
18 Units / Rail
38 Units / Rail
1000 / Tape & Reel
38 Units / Rail
1000 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
40 Units / Rail
2000 / Tape & Reel
40 Units / Rail
2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*These packages are inherently Pb−Free.
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7
MC74AC574, MC74ACT574
PACKAGE DIMENSIONS
PDIP−20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738−03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
−A−
20
11
1
10
B
L
C
−T−
K
SEATING
PLANE
M
N
E
G
F
J
D
20 PL
0.25 (0.010)
20 PL
0.25 (0.010)
M
T A
M
T B
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
M
SOIC−20W
DW SUFFIX
CASE 751D−05
ISSUE G
20
11
X 45 _
h
1
10
20X
B
B
0.25
M
T A
S
B
S
A
L
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
q
A
B
M
D
18X
e
A1
SEATING
PLANE
C
T
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8
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
MC74AC574, MC74ACT574
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE C
20X
0.15 (0.006) T U
2X
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
K
K1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
S
J J1
11
B
−U−
L
PIN 1
IDENT
SECTION N−N
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
A
−V−
N
F
DETAIL E
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A
6.40
6.60
0.252
0.260
B
4.30
4.50
0.169
0.177
−−−
−−− 0.047
C
1.20
D
0.05
0.15
0.002
0.006
F
0.50
0.75
0.020
0.030
G
0.65 BSC
0.026 BSC
−W−
H
0.27
0.37
0.011
0.015
J
0.09
0.20
0.004
0.008
J1
0.09
0.16
0.004
0.006
K
0.19
0.30
0.007
0.012
K1
0.19
0.25
0.007
0.010
L
6.40 BSC
0.252 BSC
M
0_
8_
0_
8_
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
9
MC74AC574, MC74ACT574
PACKAGE DIMENSIONS
SOEIAJ−20
M SUFFIX
CASE 967−01
ISSUE A
20
LE
11
Q1
E HE
1
M_
L
10
DETAIL P
Z
D
VIEW P
e
A
c
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
A1
b
0.13 (0.005)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
0.10 (0.004)
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.15
0.25
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
0.81
INCHES
MIN
MAX
−−− 0.081
0.002
0.008
0.014
0.020
0.006
0.010
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−− 0.032
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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10
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For additional information, please contact your local
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MC74AC574/D