FAN4800 Low Startup Current PFC/PWM Controller Combinations Features Description Low Startup Current (100µA Typical) The FAN4800 is a controller for power-factor-corrected, switched-mode power supplies. Power Factor Correction (PFC) allows the use of smaller, lower-cost bulk capacitors, reduces power line loading and stress on the switching FETs, and results in a power supply that fully complies with IEC-1000-3-2 specifications. Intended as a BiCMOS version of the industry-standard ML4800, the FAN4800 includes circuits for the implementation of leading-edge, average-current, boost-type power factor correction and a trailing-edge Pulse Width Modulator (PWM). A gate driver with 1A capabilities minimizes the need for external driver circuits. Low-power requirements improve efficiency and reduce component costs. Low Operating Current (2.5mA Typical) Low Total Harmonic Distortion, High Power Factor Pin-Compatible Upgrade for the ML4800 Average Current, Continuous or Discontinuous Boost, Leading-Edge PFC Slew Rate Enhanced Transconductance Error Amplifier for Ultra-Fast PFC Response Internally Synchronized Leading-Edge PFC and Trailing-Edge PWM Reduction of Ripple Current in the Storage Capacitor between the PFC and PWM Sections PWM Configurable for Current Mode or Voltage Mode Additional Folded-Back Current Limit for PWM Section 20V BiCMOS Process VIN OK Guaranteed Turn-on PWM at 2.25V VCC OVP Comparator, Low-Power Detect Comparator Current-Fed Gain Modulator for Improved Noise Immunity Brownout Control, Over-Voltage Protection, UVLO, Soft-Start, and Reference OK An over-voltage comparator shuts down the PFC section in the event of a sudden decrease in load. The PFC section also includes peak current limiting and input voltage brownout protection. The PWM section can be operated in current or voltage mode, at up to 250kHz, and includes an accurate 50% duty cycle limit to prevent transformer saturation. The FAN4800 includes a folded-back current limit for the PWM section to provide short-circuit protection. Available in16-DIP Package 16-PDIP Applications Desktop PC Power Supply Internet Server Power Supply Uninterruptible Power Supply (UPS) Battery Charger DC Motor Power Supply Monitor Power Supply Telecom System Power Supply Distributed Power Ordering Information Part Number Operating Temperature Range Package Packing Method Marking Code FAN4800IN -40°C to +125°C 16-PDIP Rail FAN4800 FAN4800IN_G -40°C to +125°C 16-PDIP Rail FAN4800 © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com FAN4800 — Low Startup Current PFC/PWM Controller Combinations November 2010 VEAO 15 16 VFB 0.3V 2.5V 2 4 3 7 1 IEAO Low Power Detector 3.5k 13 VCC POWER FACTOR CORRECTOR PFC OVP VCC OVP VCC 17.9V 7.5V REFERENCE 2.78V S 0.5V 3.5k Q R -1V GAIN MODULATOR 14 TRI-FAULT IAC VRMS VREF PFC OUT PFC ILIMIT PFC CMP S Q 12 R ISENSE RAMP1 OSCILLATOR CLK 8 RAMP2 PFC OUT PWM OUT PWM DUTY DUTY CYCLE LIMIT 350 PWM CMP 6 VDC 0.9V SS CMP VCC PWM OUT S 20μA 5 SS 350 1.0V VFB 2.25V VIN OK 9 Q 11 R DC ILIMIT GND VREF DC ILIMIT Q PULSE WIDTH MODULATOR S R VCC 10 UVLO FAN4800 Rev.02 Figure 1. Internal Block Diagram © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 2 FAN4800 — Low Startup Current PFC/PWM Controller Combinations Block Diagram FAN4800 — Low Startup Current PFC/PWM Controller Combinations Pin Configuration 1 IEAO VEAO 16 2 IAC VFB 15 3 ISENSE VREF 14 4 VRMS VCC 5 SS PFC OUT 12 6 VDC PWM OUT 11 7 RAMP1 8 RAMP2 13 GND 10 DC ILIMIT 9 FAN4800 Rev.03 Figure 2. Pin Configuration (Top View) Pin Definitions Pin # Name 1 IEAO PFC transconductance current error amplifier output Description 2 IAC PFC gain control reference input 3 ISENSE Current sense input to the PFC current limit comparator 4 VRMS Input for PFC RMS line voltage compensation 5 SS Connection point for the PWM soft-start capacitor 6 VDC PWM voltage feedback input 7 RAMP1 (RtCt) 8 RAMP2 (PWM RAMP) 9 DC ILIMIT 10 GND Oscillator timing node; timing set by RT, CT In current mode, this pin functions as the current-sense input. In voltage mode, it is the PWM input from the PFC output (feed forward ramp). PWM current-limit comparator input Ground 11 PWM OUT PWM driver output 12 PFC OUT PFC driver output 13 VCC Positive supply 14 VREF Buffered output for the internal 7.5V reference 15 VFB PFC transconductance voltage error amplifier input 16 VEAO © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 PFC transconductance voltage error amplifier output www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. VCC Positive Supply Voltage IEAO PFC Transconductance Current Error Amplifier Output VISENSE ISENSE Voltage Voltage on Any Other Pin Max. Unit 20 V 0 5.5 V -3.0 0.7 V GND-0.3 VCC+0.3 V IREF IREF Current 10 mA IAC IAC Input Current 1 mA IPFC_OUT Peak PFC OUT Current, Source or Sink 1 A IPWM_OUT Peak PWM OUT Current, Source or Sink 1 A PFC OUT, PWM OUT Energy per Cycle 1.5 µJ +150 °C Storage Temperature Range -65 +150 °C TA Operating Temperature Range -40 +125 °C TL Lead Temperature (Soldering,10 Seconds) +260 °C θJA Thermal Resistance 80 °C/W TJ TSTG Junction Temperature © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 4 FAN4800 — Low Startup Current PFC/PWM Controller Combinations Absolute Maximum Ratings Unless otherwise stated, these specifications apply: VCC = 15V, RT = 52.3KΩ, CT = 470pF, and TA = -40°C to 125°C. Symbol Parameter Condition Min. Typ. Max. Unit 6 V 70 90 µmho 2.55 VOLTAGE ERROR AMPLIFIER VFB Input Voltage Range(1) 0 gm1 Transconductance 50 Vref(PFC) Feedback Reference Voltage 2.45 2.50 Ib(VEAO) Input Bias Current(2) -1.00 -0.05 mA VEAO(H) Output High-Voltage 5.8 6.0 V VEAO(L) Output Low-Voltage Isink(V) Sink Current TA = 25°C, VFB = 3V, VEAO = 6.0V Source Current TA = 25°C, VFB = 1.5V VEAO = 1.5V Isource(V) GV PSRR1 TA = 25°C Open-Loop Gain(1)(3) Power Supply Rejection Ratio(1) 11V < VCC < 16.5V V 0.1 0.4 V -35 -20 µA 30 40 µA 50 60 dB 50 60 dB CURRENT ERROR AMPLIFIER VIEAO gm2 Input Voltage Range(1) -1.5 Transconductance 50 Voffset Input Offset Voltage Ibeao Current(1) Input Bias TA = 25°C Output High-Voltage IEAO(L) Output Low-Voltage Isink(I) Sink Current ISENSE = +0.5, IEAO = 4.0V Source Current ISENSE = -0.5, IEAO = 1.5V Gi PSRR2 Open-Loop 4.00 Gain(1) Power Supply Rejection V 100 µmho 25 mV -1 IEAO(H) Isource(I) 85 0.7 Ratio(1) 11V < VCC < 16.5V µA 4.25 V 1.0 1.2 V -65 -35 µA 35 75 µA 60 70 dB 60 75 dB 2.78 PFC OVP COMPARATOR Vovp HY(ovp) Threshold Voltage TA = 25°C 2.70 Hysteresis TA = 25°C 230 TA = 25°C 0.15 TA = 25°C TA = 25°C 2.90 V 350 mV 0.30 0.40 V 17.5 17.9 18.5 V 1.40 1.50 1.65 V 2 4 ms 0.5 0.6 V LOW-POWER DETECT COMPARATOR Vth(lp) Threshold Voltage VCC OVP COMPARATOR VCC_OVP Threshold Voltage HY(VCC_OVP) Hysteresis TRI-FAULT DETECT td(F) Time to Fault Detect HIGH(1) F(L) Fault Detect LOW © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 VFB = VFault Detect LOW to VFB = Open. 470pF from VFB to GND 0.4 www.fairchildsemi.com 5 FAN4800 — Low Startup Current PFC/PWM Controller Combinations Electrical Characteristics Unless otherwise stated, these specifications apply: VCC = 15V, RT = 52.3kΩ, CT = 470pF, and TA = -40°C to 125°C. Symbol Parameter Condition Min. Typ. Max. Unit -1.10 -1.00 -0.90 V 5 100 mV 250 ns PFC ILIMIT COMPARATOR Vth(cs) Vth(cs)-Vgm td(pfc_off) Threshold Voltage (PFC ILIMIT VTH – Gain Modulator Output) Delay to Output(1) DC ILIMIT COMPARATOR Vth(DC) td(pwm_off) Threshold Voltage Delay to 0.95 Output(1) 1.00 1.05 250 V ns VIN OK COMPARATOR Vth(OK) Threshold Voltage 2.10 2.45 V HY(OK) Hysteresis 0.8 1.0 1.2 V GAIN MODULATOR G1 IAC = 100μA, VRMS = 0, VFB = 1V, TA = 25°C 0.70 0.84 0.95 G2 IAC = 100μA, VRMS = 1.1V, VFB = 1V, TA = 25°C 1.80 2.00 2.20 G3 IAC = 150μA, VRMS = 1.8V, VFB = 1V, TA = 25°C 0.90 1.00 1.10 G4 IAC = 300μA, VRMS = 3.3V, VFB = 1V, TA = 25°C 0.25 0.32 0.40 Gain(3) BW Vo(gm) Band Width(1) IAC = 100μA Output Voltage = 3.5kΩ x (ISENSE – IOFFSET) IAC = 250μA, VRMS = 1.1V, VFB = 2V, TA = 25°C Gain(3) 10 0.80 1.00 MHz 1.20 V 81 kHz OSCILLATOR Initial Accuracy TA = 25°C Δfosc1 Voltage Stability 11V < VCC < 16.5V Δfosc2 Temperature Stability fosc1 fosc2 Vramp tdead Total Variation Line, Temp 68 % 2 % 66 (1) Ramp Valley to Peak Voltage 84 2.75 PFC Dead Time VRAMP2 = 0V, VRAMP1 = 2.5V 6.5 Vref1 Output Voltage TA = 25°C, I(VREF) = 1mA 7.4 kHz V 685 CT Discharge Current Idis 1 ns 15.0 mA 7.6 V REFERENCE 7.5 ΔVref1 Line Regulation 11V < VCC < 16.5V 10 25 mV ΔVref2 Load Regulation 0mA < I(VREF) < 7mA 10 20 mV ΔVref4 Temperature Stability Vref2 ΔVref5 (1) Total Variation (1) Long Term Stability © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 0.4 % Line, Load, Temperature 7.35 7.65 V TJ = 125°C, 1000 hours 5 25 mV www.fairchildsemi.com 6 FAN4800 — Low Startup Current PFC/PWM Controller Combinations Electrical Characteristics (Continued) Unless otherwise stated, these specifications apply: VCC = 15V, RT = 52.3kΩ, CT = 470pF, TA = -40°C to 125°C. Symbol Parameter Condition Min. Typ. Max. Unit 0 % PFC Dmin. Minimum Duty Cycle VIEAO > 4.0V Dmax. Maximum Duty Cycle VIEAO < 1.2V RON(low)1 RON(low)2 Vol1 RON(high)1 RON(high)2 tr(pfc) Output Low Rdson Output Low Voltage(1) Output High Rdson Rise/Fall Time(1) 92 95 % IOUT = -20mA at TA = 25°C 15 Ω IOUT = -100mA at TA = 25°C 15 Ω IOUT = -10mA, VCC = 9V, TA = 25°C 0.4 0.8 V IOUT = 20mA at TA = 25°C 15 20 Ω IOUT = 100mA at TA = 25°C 15 20 Ω CL = 1000pF 50 ns PWM D RON(low)3 RON(low)4 Vol2 RON(high)3 RON(high)4 tr(pwm) PWM(ls) Duty Cycle Range Output Low Rdson Output Low Voltage Output High Rdson Rise/Fall Time 0-42 0-47 0-49 % IOUT = -20mA at TA = 25°C 15 Ω IOUT = -100mA at TA = 25°C 15 Ω IOUT = -10mA, VCC = 9V, TA = 25°C 0.4 0.8 V IOUT = 20mA at TA = 25°C 15 20 Ω IOUT = 100mA at TA = 25°C 15 20 Ω CL = 1000pF(1) PWM Comparator Level Shift 50 0.6 ns 0.9 1.2 V 100 200 µA SUPPLY Ist Startup Current VCC = 12V, CL = 0pF Iop Operating Current 14V, CL = 0pF 2.5 7.0 mA Vth(start) Under-Voltage Lockout Threshold 12.74 13.00 13.26 V Vth(hys) Under-Voltage Lockout Hysteresis 2.80 3.00 3.20 V Notes: 1. This parameter, although guaranteed by design, is not 100% production tested. 2. Includes all bias currents to other circuits connected to the VFB pin. 3. Gain = K × 5.375V; K = (ISENSE – IOFFSET) × [IAC × (VEAO – 0.625)] -1; VEAO (MAX.) = 6V. © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 7 FAN4800 — Low Startup Current PFC/PWM Controller Combinations Electrical Characteristics (Continued) FAN4800 — Low Startup Current PFC/PWM Controller Combinations 100 126 119 Transconductance ( mho) Transconductance ( mho) Typical Performance Characteristics 112 105 98 91 84 77 70 63 90 80 70 60 50 40 30 20 10 0 56 -10 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 VFB (V) 0.4 0.6 0.8 Figure 4. Current Error Amplifier (gmi) Transconductance 2.2 0.40 2.0 0.35 1.8 0.30 1.6 1.4 0.25 Gain Variable Gain Block Constant (K) Figure 3. Voltage Error Amplifier (gmv) Transconductance -0.8 -0.6 -0.4 -0.2 0.0 0.2 ISENSE (V) 0.20 1.2 1.0 0.15 0.8 0.10 0.6 0.4 0.05 0.2 0.00 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VRMS (V) 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VRMS (V) Figure 5. Gain Modulator Transfer Characteristic (K) K= IGAINMOD − IOFFSET mV −1 I AC × (6 − 0.625) © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 Figure 6. Gain vs. VRMS Gain = (1) ISENSE − IOFFSET I AC (2) www.fairchildsemi.com 8 The FAN4800 consists of an average-current controlled, continuous boost Power Factor Correction (PFC) frontend and a synchronized Pulse Width Modulator (PWM) back-end. The PWM can be used in either current or voltage mode. In voltage mode, feed forward from the PFC output bus can be used to improve the PWM’s line regulation. In either mode, the PWM stage uses conventional trailing-edge, duty-cycle modulation. This proprietary leading/trailing edge modulation results in a higher usable PFC error amplifier bandwidth and can significantly reduce the size of the PFC DC bus capacitor. One of these conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage. A commonly used value is 385VDC, to allow for a high line of 270VAC rms. The second condition is that the current drawn from the line at any given instant must be proportional to the line voltage. Establishing a suitable voltage control loop for the converter, which in turn drives a current error amplifier and switching output driver, satisfies the first of these requirements. The second requirement is met by using the rectified AC line voltage to modulate the output of the voltage control loop. Such modulation causes the current error amplifier to command a power stage current that varies directly with the input voltage. To prevent ripple, which necessarily appears at the output of boost circuit (typically about 10VAC on a 385VDC level), from introducing distortion back through the voltage error amplifier, the bandwidth of the voltage loop is deliberately kept low. A final refinement is to adjust the overall gain of the PFC section to be proportional to 1/VIN2, which linearizes the transfer function of the system as the AC input voltage. The synchronization of the PWM with the PFC simplifies the PWM compensation due to the controlled ripple on the PFC output capacitor (the PWM input capacitor). The PWM section of the FAN4800 runs at the same frequency as the PFC. In addition to power factor correction, a number of protection features are built into the FAN4800. These include soft-start, PFC over-voltage protection, peak current limiting, brownout protection, duty-cycle limiting, and under-voltage lockout (UVLO). Since the boost converter in the FAN4800 PFC is current averaging, no slope compensation is required. Power Factor Correction Power Factor Correction treats a nonlinear load like a resistive load to the AC line. For a resistor, the current drawn from the line is in phase with and proportional to the line voltage, so the power factor is unity (one). A common class of nonlinear load is the input of most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. 1. PFC Section 1.1 Gain Modulator Figure 1 shows a block diagram of the PFC section of the FAN4800. The gain modulator is the heart of the PFC, as the circuit block controls the response of the current loop to line voltage waveform and frequency, RMS line voltage, and PFC output voltages. There are three inputs to the gain modulator: The peak charging effect, which occurs on the input filter capacitor in these supplies, causes brief high-amplitude pulses of current to flow from the power line, rather than a sinusoidal current in phase with the line voltage. Such supplies present a power factor to the line of less than one (i.e., they cause significant current harmonics of the power line frequency to appear at the input). If the input current drawn by such a supply (or any nonlinear load) can be made to follow the input voltage in instantaneous amplitude, it appears resistive to the supply. 1. A current representing the instantaneous input voltage (amplitude and wave shape) to the PFC. The rectified AC input sine wave is converted to a proportional current via a resistor and is then fed into the gain modulator at IAC. Sampling current in this way minimizes ground noise, required in high-power, switching-power conversion environments. The gain modulator responds linearly to this current. To hold the input current draw of a device drawing power from the AC line in phase with and proportional to the input voltage, that device must be prevented from loading the line except in proportion to the instantaneous line voltage. To accomplish this, the PFC section of the FAN4800 uses a boost mode DC-DC converter. The input to the converter is the full-wave, rectified, AC line voltage. No bulk filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges (at twice line the frequency) from zero volts to a peak value of the AC input and back to zero. By forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current drawn from the power line is proportional to the input line voltage. © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 2. A voltage proportional to the long-term RMS AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at VRMS. The output of the gain modulator is inversely proportional to VRMS2 (except at unusually low values of VRMS, where special gain contouring takes over to limit power dissipation of the circuit components under heavy brownout conditions). The relationship between VRMS and gain is called K and is illustrated in Figure 5. www.fairchildsemi.com 9 FAN4800 — Low Startup Current PFC/PWM Controller Combinations Functional Description The inverting input of the current error amplifier is a virtual ground. Given this fact, and the arrangement of the duty cycle modulator polarities internal to the PFC, an increase in positive current from the gain modulator causes the output stage to increase its duty cycle until the voltage on ISENSE is adequately negative to cancel this increased current. Similarly, if the gain modulator’s output decreases, the output duty cycle decreases to achieve a less negative voltage on the ISENSE pin. The output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. This current is applied to the virtual ground (negative) input of the current error amplifier. In this way, the gain modulator forms the reference for the current error loop and ultimately controls the instantaneous current draw of the PFC from the power line. The general form of the output of the gain modulator is: IGAINMOD = I AC × VEAO V 2 RMS × 1V 1.4 Cycle-By-Cycle Current Limiter and Selecting RS (3) As well as being a part of the current feedback loop, the ISENSE pin is a direct input to the cycle-by-cycle current limiter for the PFC section. If the input voltage at this pin is ever less than -1V, the output of the PFC is disabled until the protection flip-flop is reset by the clock pulse at the start of the next PFC power cycle. More precisely, the output current of the gain modulator is given by: IGAINMOD = K × (VEAO − 0.625) × I AC (4) RS is the sensing resistor of the PFC boost converter. During the steady state, line input current x RS equals IGAINMOD x 3.5K. where K is in units of V -1. The output current of the gain modulator is limited around 228.57µA and the maximum output voltage of the gain modulator is limited to 228.57µA x 3.5K = 0.8V. Since the maximum output voltage of the gain modulator is IGAINMOD maximum x 3.5k = 0.8V during the steady state, RS x line input current is limited to below 0.8V as well. Therefore, to choose RS, use the following equation: This 0.8V also determines the maximum input power. However, IGAINMOD cannot be measured directly from ISENSE. ISENSE = IGAINMOD – IOFFSET and IOFFSET can only be measured when VEAO is less than 0.5V and IGAINMOD is 0A. Typical IOFFSET is around 60µA. RS = 0.8V × VINPEAK 2 × LineInput Power (5) For example, if the minimum input voltage is 80VAC and the maximum input RMS power is 200Watt, RS = (0.8V x 80V x 1.414) / (2 x 200) = 0.226Ω. 1.2 Selecting RAC for IAC pin IAC pin is the input of the gain modulator. IAC is also a current mirror input and requires current input. Selecting a proper resistor RAC provides a good sine wave current derived from the line voltage and helps program the maximum input power and minimum input line voltage. 1.5 PFC OVP In the FAN4800, the PFC OVP comparator serves to protect the power circuit from being subjected to excessive voltages if the load changes suddenly. A resistor divider from the high-voltage DC output of the PFC is fed to VFB. When the voltage on VFB exceeds 2.78V, the PFC output driver is shut down. The PWM section continues to operate. The OVP comparator has 280mV of hysteresis and the PFC does not restart until the voltage at VFB drops below 2.50V. VCC OVP can also serve as a redundant PFC OVP protection. VCC OVP threshold is 17.9V with 1.5V hysteresis. RAC = VIN peak x 7.9K. For example, if the minimum line voltage is 80VAC, the RAC = 80 x 1.414 x 7.9K = 894kΩ. 1.3 Current Error Amplifier, IEAO The current error amplifier’s output controls the PFC duty cycle to keep the average current through the boost inductor a linear function of the line voltage. At the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current, which results from a negative voltage being impressed upon the ISENSE pin. The negative voltage on ISENSE represents the sum of all currents flowing in the PFC circuit and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier. © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 10 FAN4800 — Low Startup Current PFC/PWM Controller Combinations 3. The output of the voltage error amplifier, VEAO. The gain modulator responds linearly to variation in VEAO. 15 16 4 3 7 1 VFB 0.3V 2.5V 2 IEAO Low Power Detector 3.5k IAC VRMS 13 VCC POWER FACTOR CORRECTOR PFC OVP VCC OVP VCC 17.9V 2.78V 3.5k S 0.5V Q R PFC OUT PFC ILIMIT PFC CMP S Q 12 R ISENSE RAMP1 14 TRI-FAULT -1V GAIN MODULATOR VREF 7.5V REFERENCE OSCILLATOR CLK FAN4800 Rev.02 Figure 7. PFC Section Block Diagram 1.6 Error Amplifier Compensation The voltage loop gain(s) is given by: The PWM loading of the PFC can be modeled as a negative resistor because an increase in the input voltage to the PWM causes a decrease in the input current. This response dictates the proper compensation of the two transconductance error amplifiers. = ≈ Figure 8 shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points. The current-loop compensation is returned to VREF to produce a soft-start characteristic on the PFC: As the reference voltage increases from 0V, it creates a differentiated voltage on IEAO, which prevents the PFC from immediately demanding a full duty cycle on its boost converter. PIN × 2.5V V 2OUTDC × ΔVEAO × S × CDC (6) × GMV × ZC where: ZC: Compensation network for the voltage loop. GMV: Transconductance of VEAO . PIN: Average PFC input power. V2OUTDC: PFC boost output voltage (typical designed value is 380V). CDC: 1.7 PFC Voltage Loop There are two major concerns when compensating the voltage loop error amplifier (VEAO); stability and transient response. Optimizing interaction between transient response and stability requires that the error amplifier’s open-loop crossover frequency half that of the line frequency, or 23Hz for a 47Hz line (lowest anticipated international power frequency). The gain vs. input voltage of the FAN4800’s voltage error amplifier (VEAO) has a specially shaped non-linearity, so that under steady-state operating conditions, the transconductance of the error amplifier is at a local minimum. Rapid perturbation in line or load conditions causes the input to the voltage error amplifier (VFB) to deviate from its 2.5V (nominal) value. If this happens, the transconductance of the voltage error amplifier increases significantly, as shown in the Figure 4. This raises the gain-bandwidth product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than would occur with conventional linear gain characteristics. © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 ΔVOUT ΔVFB ΔV × × EAO ΔVEAO ΔVOUT ΔVFB PFC boost output capacitor. 1.8 PFC Current Loop The compensation of the current amplifier (IEAO) is similar to that of the voltage error amplifier (VEAO) with the exception of the choice of crossover frequency. The crossover frequency of the current amplifier should be at least ten times that of the voltage amplifier to prevent interaction with the voltage loop. It should also be limited to less than one sixth of the switching frequency, e.g., 16.7kHz for a 100kHz switching frequency. The current loop gain(s) is given by: = ΔVISENSE ΔDOFF ΔIEAO × × ΔDOFF ΔIEAO ΔVISENSE ≈ (7) VOUTDC × RS × GMI × ZCI S × L × 2.5V www.fairchildsemi.com 11 FAN4800 — Low Startup Current PFC/PWM Controller Combinations VEAO ZCI: Compensation network for the current loop. GMI: Transconductance of IEAO. Selecting an RFILTER equal to 50Ω keeps the offset of the IEAO less than 5mV. Design the pole of ISENSE filter at fpfc/6, one sixth of the PFC switching frequency, so the boost inductor can be reduced six times without disturbing the stability. The capacitor of the ISENSE filter, CFILTER, is approximately 283nF. VOUTDC: PFC boost output voltage (typical designed value is 380V). The equation uses the worstcase condition to calculate the ZCI. RS: Sensing resistor of the boost converter. 2.5V: Amplitude of the PFC leading modulation ramp. L: Boost inductor. VBIAS A modest degree of gain contouring is applied to the transfer characteristic of the current error amplifier to increase its response speed to current-loop perturbations. However, the boost inductor is usually the dominant factor in overall current loop response. Therefore, this contouring is significantly less marked than that of the voltage error amplifier. This is illustrated in Figure 8. RBIAS VCC 0.22μF Ceramic 15V Zener FAN4800 Vref GND FAN4800 Rev.03 PFC Output VEAO 15 16 IEAO 1 Figure 9. External Component Connection to VCC VFB 1.9 Oscillator (RAMP1) 2.5V The oscillator frequency is determined by the values of RT and CT, which determine the ramp and off-time of the oscillator output clock: 3.5k 2 4 3 IAC VRMS Gain Modulator 3.5k PFC CMP fO S C = ISENSE 1 tR A M P + tD E A D (8) FAN4800 Rev.02 The dead time of the oscillator is derived from the following equation: Figure 8. Compensation Network Connection for the Voltage and Current Error Amplifiers ⎛V -1.00 ⎞ tRAMP = CT × RT × ln ⎜ REF ⎟ V -3.75 ⎝ REF ⎠ There is an RC filter between RS and ISENSE pin. There are two reasons to add a filter at the ISENSE pin: at VREF = 7.5V and tRAMP = CT x RT x 0.55. 1) Protection: During startup or in-rush current conditions, there is a large voltage across RS, which is the sensing resistor of the PFC boost converter. It requires the ISENSE filter to attenuate the energy. The dead time of the oscillator may be determined using: t DEAD = 2) To reduce L, the boost inductor: The ISENSE filter also can reduce the boost inductor value since the ISENSE filter behaves like an integrator before the ISENSE pin, which is the input of the current error amplifier, IEAO. © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 (9) 2.75V × CT = 227 × CT 12.11mA (10) The dead time is so small (tRAMP>>tDEAD) that the operating frequency can typically be approximated by: fOSC = 1 tRAMP (11) www.fairchildsemi.com 12 FAN4800 — Low Startup Current PFC/PWM Controller Combinations The ISENSE filter is an RC filter. The resistor value of the ISENSE filter is between 100Ω and 50Ω because IOFFSET x RS can generate an offset voltage of IEAO. where: cycle current, it also softly discharges the voltage of the soft-start capacitor. It limits the PWM duty cycle mode and the power dissipation is reduced during the deadshort condition. For the application circuit shown in Figures 12 and 13, with the oscillator running at: fOSC = 100kHz = 1 tRAMP 2.3 VIN OK Comparator (12) The VIN OK comparator monitors the DC output of the PFC and inhibits the PWM if the voltage on VFB is less than its nominal 2.25V. Once the voltage reaches 2.25V, which corresponds to the PFC output capacitor being charged to its rated boost voltage, the soft-start begins. solving for CT x RT yields 1.96 x 10-4. CT is 390pF and RT is 51.1kΩ, selecting standard components values. The dead time of the oscillator adds to the maximum PWM duty cycle (it is an input to the duty cycle limiter). With zero oscillator dead time, the maximum PWM duty cycle is typically 47%. Take care not to make CT too large, which could extend the maximum duty cycle beyond 50%. This can be accomplished by using no greater than a 390pF capacitor for CT. 2.4 PWM Control (RAMP2) When the PWM section is used in current mode, RAMP2 is generally used as the sampling point for a voltage, representing the current in the primary of the PWM’s output transformer. The voltage is derived either from a current sensing resistor or a current transformer. In voltage mode, RAMP2 is the input for a ramp voltage generated by a second set of timing components (RRAMP2, CRAMP2) that have a minimum value of 0V and a peak value of approximately 5V. In voltage mode, feed forward from the PFC output bus is an excellent way to derive the timing ramp for the PWM stage. 2. PWM Section 2.1 Pulse Width Modulator (PWM) The operation of the PWM section of the FAN4800 is straightforward, but there are several points that should be noted. Foremost among these is the inherent synchronization of PWM with the PFC section of the device, from which it also derives its basic timing. The PWM is capable of current-mode or voltage-mode operation. In current-mode applications, the PWM ramp (RAMP2) is usually derived directly from a current sensing resistor or current transformer in the primary of the output stage. it is thereby representative of the current flowing in the converter’s output stage. DC ILIMIT, which provides cycleby-cycle current limiting, is typically connected to RAMP2 in such applications. For voltage-mode operation and certain specialized applications, RAMP2 can be connected to a separate RC timing network to generate a voltage ramp against which VDC is compared. Under these conditions, the use of voltage feed-forward from the PFC bus can assist in line regulation accuracy and response. As in current-mode operation, the DC ILIMIT input is used for output stage over-current protection. 2.5 Soft-Start (SS) PWM startup is controlled by selection of the external capacitor at soft-start. A current source of 20mA supplies the charging current for the capacitor and startup of the PWM begins at 0.9V. Startup delay can be programmed by the following equation: CSS = tDELAY × (13) where CSS is the required soft-start capacitance and the tDELAY is the desired startup delay. It is important that the time constant of the PWM softstart allows the PFC time to generate sufficient output power for the PWM section. The PWM startup delay should be at least 5ms. Solving for the minimum value of CSS: No voltage error amplifier is included in the PWM stage of the FAN4800, as this function is generally performed on the output side of the PWM’s isolation boundary. To facilitate the design of opto-coupler feedback circuitry, an offset has been built into the PWM’s RAMP2 input that allows VDC to command a 0% duty cycle for input voltages below typical 0.9V. CSS = 5ms × 20μA = 111nF 0.9V (14) Use caution when using this minimum soft-start capacitance value because it can cause premature charging of the SS capacitor and activation of the PWM section if VFB is in the hysteresis band of the VIN OK comparator at startup. The magnitude of VFB at startup is related both to line voltage and nominal PFC output voltage. Typically, a 1.0µF soft-start capacitor allows time for VFB and PFCOUT to reach their nominal values prior to activation of the PWM section at line voltages between 90Vrms and 265Vrms. 2.2 PWM Current Limit The DC ILIMIT pin is a direct input to the cycle-by-cycle current limiter for the PWM section. Should the input voltage at this pin ever exceed 1V, the output flip-flop is reset by the clock pulse at the start of the next PWM power cycle. When the DC ILIMIT triggers the cycle-by- © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 20μA 0.9V www.fairchildsemi.com 13 FAN4800 — Low Startup Current PFC/PWM Controller Combinations 1.10 Example 2.8 Leading/Trailing Modulation After turning on the FAN4800 at 13V, the operating voltage can vary from 10V to 17.9V. The threshold voltage of the VCC OVP comparator is 17.9V and its hysteresis is 1.5V. When VCC reaches 17.9V, PFC OUT is LOW, and the PWM section is not disturbed. There are two ways to generate VCC: use auxiliary power supply around 15V or use bootstrap winding to self-bias the FAN4800 system. The bootstrap winding can be either taped from the PFC boost choke or from the transformer of the DC-to-DC stage. Conventional PWM techniques employ trailing-edge modulation, in which the switch turns on right after the trailing edge of the system clock. The error amplifier output is then compared with the modulating ramp up. The effective duty cycle of the trailing edge modulation is determined during the on-time of the switch. Figure 10 shows a typical trailing-edge control scheme. In the case of leading-edge modulation, the switch is turned off exactly at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch is turned on. The effective duty-cycle of the leading-edge modulation is determined during off-time of the switch. Figure 11 shows a leading-edge control scheme. The ratio of the bootstrap’s winding transformer should be set between 18V and 15V. A filter network is recommended between VCC (pin 13) and bootstrap winding. The resistor of the filter can be set as: RFILTER × IVCC ≈ 2V , IVCC = IOP + (QPFCFET +QPWMFET ) × fSW IOP One of the advantages of this control technique is that it requires only one system clock. Switch 1 (SW1) turns off and Switch 2 (SW2) turns on at the same instant to minimize the momentary no-load period, thus lowering ripple voltage generated by the switching action. With such synchronized switching, the ripple voltage of the first stage is reduced. Calculation and evaluation have shown that the 120Hz component of the PFC’s output ripple voltage can be reduced by as much as 30% using the leading-edge modulation method. (15) = 2.5A (typ.) If VCC goes beyond 17.9V, the PFC gate (pin 12) drive goes LOW and the PWM gate drive (pin 11) remains working. The resistor’s value must be chosen to meet the operating current requirement of the FAN4800 itself (5mA, maximum) in addition to the current required by the two gate driver outputs. 2.7 Example To obtain a desired VBIAS voltage of 18V, a VCC of 15V, and the FAN4800 driving a total gate charge of 90nC at 100kHz (e.g. one IRF840 MOSFET and two IRF820 MOSFET), the gate driver current required is: IGATEDRIVE = 100kHz × 90nC = 9mA RBIAS = = VBIAS − VCC ICC + IG (16) (17) 18V − 15V 5mA + 9mA Choose RBIAS = 214Ω (18) Bypass the FAN4800 locally with a 1.0μF ceramic capacitor. In most applications, an electrolytic capacitor of between 47μF and 220μF is also required across the part both for filtering and as a part of the startup bootstrap circuitry. © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 14 FAN4800 — Low Startup Current PFC/PWM Controller Combinations 2.6 Generating VCC I2 I1 + I3 RAMP I4 VIN RL C1 DC VEAO SW1 REF U3 TIME VEAO EA DFF CMP R RAMP U1 OSC D Q U2 CLK Q CLK U4 TIME FAN4800 Rev.02 Figure 10. Typical Trailing-Edge Control Scheme SW2 L1 I2 I1 + I3 RAMP I4 VIN RL C1 DC VEAO SW1 U3 TIME VEAO EA DFF CMP REF R RAMP U1 OSC D Q U2 CLK Q U4 CLK TIME FAN4800 Rev.02 Figure 11. Typical Leading-Edge Control Scheme © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 15 FAN4800 — Low Startup Current PFC/PWM Controller Combinations SW2 L1 Figure 12. Current-Mode Application © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 16 www.fairchildsemi.com D13 1N5401 D12 1N5401 RAMP1 R5D R5C 1.2 R5B 1.2 R5A 1.2 1.2 ISENSE AC INPUT C1 85 TO 265Vac 0.68uF F1 3.15A R31 100 C26 100nF C3 0.1uF C19 1uF R4 15.4k C2 0.47uF R3 110k R2B 453k R2A 453k BR1 4A, 600V KBL06 C18 470pF R1B 500k R1A 500k C11 10nF C30 330uF 25V R27 75k 8 7 6 5 4 3 2 1 R21 22 RAMP2 RAMP1 VDC SS VRMS ISENSE IAC U1 C7 NOT USED C6 1.5nF DC ILIMIT GND PWM OUT PFC OUT VCC VREF VFB VEAO FAN4800 R12 71.5k R10 6.2k R6 41.7k C4 10nF D1 ISL9R460P2 Q1 FQPF9N50 R28 240 D9 MBRS 140 D2 1N5406 IEAO Q1G L1 9 10 11 12 13 14 15 16 C5 100uF 450V C17 220pF C12 10uF 35V D8 MBRS 140 R7B 178k R7A 178k R8 2.37k C31 1nF VFB D10 MBRS 140 C15 10nF T1A R15 3 C20 1uF R9 1.1k R20A 2.2 C16 1uF VCC C13 0.1uF C14 1uF R11 845k R20B 2.2 T2 D11B MBR2545CT C8 68nF VREF C9 10nF R16 10k R13 10k Q4 MMBT3904 NOTE : PRI GND C10 15uF R23 1.5k C24 1uF VDC U3 TL431A U2 MOC8112 L2 R26 10k C22 4.7uF R25 2.26k C23 100nF R24 1.2k C21 2200uF 25V R22 8.66k R18 220 12V RETURN 12V RET 12V, 100W 12V L1; PREMIER MAGNETICS TDS-1047 L2; PREMIER MAGNETICS VTP-05007 T1; PREMIER MAGNETICS PMGO-03 T2; PREMIER MAGNETICS TSO-735 VDC / +380V D11A MBR2545CT RAMP2 / DC ILIMIT D6 RGF1J D5 RGF1J Q3 FQPF6N50 Q2 FQPF 6N50 D4 MMBZ5245B R19 220 Q3G D7 MMBZ5245B R14 33 T1B R30 4.7k Q2G C25 0.1uF R17 33 D3 RGF1J FAN4800 — Low Startup Current PFC/PWM Controller Combinations Typical Application Circuit Figure 13. Voltage-Mode Application © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 17 www.fairchildsemi.com D13 1N5401 D12 1N5401 RAMP1 R5D R5C 1.2 R5B 1.2 R5A 1.2 1.2 ISENSE AC INPUT C1 85 TO 265Vac 0.68uF F1 3.15A R31 100 C26 100nF C3 0.1uF C19 1uF R4 15.4k C2 0.47uF R3 110k R2B 453k R2A 453k BR1 4A, 600V KBL06 C18 470pF R1B 500k R1A 500k 8 7 6 5 4 3 2 1 R21 22 RAMP2 RAMP1 VDC SS VRMS ISENSE IAC U1 C7 NOT USED C6 1.5nF R29 61.9k DC ILIMIT GND PWM OUT PFC OUT VCC VREF VFB VEAO FAN4800 R12 71.5k R10 6.2k R6 41.7k C4 10nF D1 ISL9R460P2 Q1 FQPF9N50 R28 240 D9 MBRS 140 D2 1N5406 IEAO Q1G C27 C11 10nF 470pF C30 330uF 25V R27 75k L1 9 10 11 12 13 14 15 16 C5 100uF 450V C17 220pF C12 10uF 35V D8 MBRS 140 R7B 178k R7A 178k R8 2.37k C31 1nF VFB D10 MBRS 140 C15 10nF T1A R15 3 C20 1uF R9 1.1k R20A 2.2 C16 1uF VCC C13 0.1uF C14 1uF R11 845k R20B 2.2 T2 D11B MBR2545CT C8 68nF VREF C9 10nF R16 10k R13 10k Q4 MMBT3904 NOTE : PRI GND C10 15uF R23 1.5k C24 1uF VDC U3 TL431A U2 MOC8112 L2 R26 10k C22 4.7uF R25 2.26k C23 100nF R24 1.2k C21 2200uF 25V R22 8.66k R18 220 12V RETURN 12V RET 12V, 100W 12V L1; PREMIER MAGNETICS TDS-1047 L2; PREMIER MAGNETICS VTP-05007 T1; PREMIER MAGNETICS PMGO-03 T2; PREMIER MAGNETICS TSO-735 VDC / +380V D11A MBR2545CT RAMP2 / DC ILIMIT D6 RGF1J D5 RGF1J Q3 FQPF6N50 Q2 FQPF 6N50 D4 MMBZ5245B R19 220 Q3G D7 MMBZ5245B R14 33 T1B R30 4.7k Q2G C25 0.1uF R17 33 D3 RGF1J FAN4800 — Low Startup Current PFC/PWM Controller Combinations Typical Application Circuit (Continued) A 19.68 18.66 9 16 6.60 6.09 1 8 (0.40) TOP VIEW 0.38 MIN 5.33 MAX 8.13 7.62 3.42 3.17 3.81 2.92 2.54 0.35 0.20 0.58 A 0.35 1.78 1.14 15 0 8.69 17.78 SIDE VIEW NOTES: UNLESS OTHERWISE SPECIFIED A THIS PACKAGE CONFORMS TO JEDEC MS-001 VARIATION BB B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR PROTRUSIONS D) CONFORMS TO ASME Y14.5M-1994 E) DRAWING FILE NAME: N16EREV1 Figure 14. 16-Lead Plastic Dual In-Line Package (DIP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 18 FAN4800 — Low Startup Current PFC/PWM Controller Combinations Physical Dimensions FAN4800 — Low Startup Current PFC/PWM Controller Combinations © 2005 Fairchild Semiconductor Corporation FAN4800 Rev. 1.0.6 www.fairchildsemi.com 19