Holtek HT48R01A Small package i/o type 8-bit otp mcu Datasheet

HT48R01A
Small Package I/O Type 8-Bit OTP MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
- HA0016E Writing and Reading to the HT24 EEPROM with the HT48 MCU Series
- HA0018E Controlling the HT1621 LCD Controller with the HT48 MCU Series
- HA0049E Read and Write Control of the HT1380
- HA0075E MCU Reset and Oscillator Circuits Application Note
Features
· Operating voltage:
· Power down and wake-up functions to reduce power
fSYS= 4MHz: 2.2V~5.5V
fSYS= 8MHz: 3.3V~5.5V
fSYS= 12MHz: 4.5V~5.5V
consumption
· Up to 0.33ms instruction cycle with 12MHz system
clock at VDD= 5V
· 7 bidirectional I/O lines and 1 input line
· 4-level subroutine nesting
· External interrupt input shared with an I/O line
· Bit manipulation instruction
· Single 8-bit programmable Timer/Event Counter
· Table read instructions
with overflow interrupt and 7-stage prescaler
· 63 powerful instructions
· External crystal system oscillator
· All instructions executed in one or two machine cy-
· Fully integrated internal RC oscillator available with
cles
three frequencies: 4MHz, 8MHz or 12MHz
· Low voltage reset function
· Watchdog Timer function
· 10-pin ultra-small MSOP package
· Buzzer function
General Description
selections, and being supplied in an extremely small
outline MSOP 10-pin package opens up a huge range of
new application possibilities for these devices, some of
which may include industrial control, consumer products, household appliances subsystem controllers, etc.
The HT48R01A is 8-bit high performance, RISC architecture microcontroller specifically designed for a wide
range of applications. The usual Holtek microcontroller
features of low power consumption, I/O flexibility, timer
functions, oscillator options, power down and wake-up
functions, watchdog timer and low voltage reset, combine to provide devices with a huge range of functional
options while still maintaining cost effectiveness. Their
fully integrated system oscillator, with three frequency
Rev. 1.10
1
August 4, 2008
HT48R01A
Device Markings
A suffix with the number 1, 2 or 3 will be added to each of the part numbers and printed on the package. The suffix number denotes the fixed oscillation frequency of the internal RC oscillator as shown.
Part No.
Device Marking
Internal RC Oscillator Frequency
HT48R01A
48R01A1
48R01A2
48R01A3
4MHz
8MHz
12MHz
Block Diagram
The following block diagram illustrates the main functional blocks.
W a tc h d o g
T im e r
O T P
P r o g r a m m in g
C ir c u itr y
W a tc h d o g
T im e r O s c illa to r
S ta c k
I/O
P o rts
O T P
P ro g ra m
M e m o ry
R A M D a ta
M e m o ry
8 - b it
R IS C
M C U
C o re
R e s e t
C ir c u it
In te rru p t
C o n tr o lle r
R C /C ry s ta l
O s c illa to r
B u z z e r
D r iv e r
T im e r
L o w
V o lta g e
R e s e t
In te rn a l
O s c illa to r
Pin Assignment
1
2
P A 1 /B Z
3
P A 0 /B Z
4
V S S
5
1 0
P A 3 /IN T
P A 2 /T M R 0
P A 4
9
P A 5 /O S C 2
8
P A 6 /O S C 1
7
6
P A 7 /R E S
V D D
H T 4 8 R 0 1 A
1 0 M S O P -A
Rev. 1.10
2
August 4, 2008
HT48R01A
Pin Description
Configuration
Options
Description
¾
Bidirectional 2 line I/O. Each pin can be setup as a wake-up input using the
wake-up register. Software instructions determine if the pin is a CMOS output
or a Schmitt Trigger input. A pull-high resistor can be connected using the
pull-high register. PA0/PA1 are pin-shared with the BZ/BZ input pins, the
function of which is chosen via a configuration option.
¾
Bidirectional single line I/O. The pin can be setup as a wake-up input using
the wake-up register. Software instructions determine if the pin is a CMOS
output or a Schmitt Trigger input. A pull-high resistor can be connected using
the pull-high register. PA2 is pin-shared with the TMR0 input.
¾
Bidirectional single line I/O. The pin can be setup as a wake-up input using
the wake-up register. Software instructions determine if the pin is a CMOS
output or a Schmitt Trigger input. A pull-high resistor can be connected using
the pull-high register. PA3 is pin-shared with the INT input.
¾
Bidirectional single line I/O. The pin can be setup as a wake-up input using
the wake-up register. Software instructions determine if the pin is a CMOS
output or a Schmitt Trigger input. A pull-high resistor can be connected using
the pull-high register.
I/O
RC, Crystal,
RTC or I/O
Bidirectional 2-line I/O. The pins can be setup as wake-up inputs using the
wake-up register. Software instructions determine if the pin is a CMOS output
or a Schmitt Trigger input. A pull-high resistors can be connected using the
pull-high register. Configuration options determine if the pins are to be used
as oscillator pins or I/O pins. Configuration options also determine which oscillator mode is selected. The four oscillator modes are:
1. Internal RC OSC: both pins configured as I/Os.
2. External crystal OSC: both pins configured as OSC1/OSC2.
3. Internal RC + RTC OSC: both pins configured as OSC1, OSC2.
4. External RC OSC+PA5: PA6 configured as OSC1 pin, PA5 configured
as I/O.
If the internal RC OSC is selected, the frequency will be fixed at either 4MHz,
8MHz or 12MHz, dependent upon which device is chosen.
I
PA7 or RES
Active low Schmitt trigger reset input or PA7 input. A configuration option determines which function is selected. PA7 has a wake-up function but does not
have a pull-high function.
VDD
¾
¾
Positive power supply
VSS
¾
¾
Negative power supply, ground
Pin Name
PA0/BZ
PA1/BZ
PA2/TMR0
I/O
I/O
I/O
PA3/INT
I/O
PA4
I/O
PA6/OSC1
PA5/OSC2
PA7/RES
Note:
Each pin on PA except PA7 can be selected to have a pull-high resistor.
Rev. 1.10
3
August 4, 2008
HT48R01A
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
IDD1
IDD2
Operating Voltage
¾
5.5
V
¾
fSYS=8MHz
3.3
¾
5.5
V
¾
fSYS=12MHz
4.5
¾
5.5
V
¾
1
2
mA
¾
2.5
5
mA
¾
2
4
mA
¾
4
8
mA
¾
6
12
mA
¾
1
2
mA
¾
2.5
5
mA
¾
2
4
mA
¾
4
8
mA
¾
6
12
mA
¾
20
30
mA
¾
40
60
mA
¾
¾
5
mA
¾
¾
10
mA
¾
¾
1
mA
¾
¾
2
mA
¾
¾
5
mA
¾
¾
10
mA
Operating Current
(Crystal OSC, RC OSC)
3V
Operating Current
(Crystal OSC, RC OSC)
3V
No load, fSYS=4MHz
5V
No load, fSYS=8MHz
5V
Operating Current (Internal
RC+RTC OSC, Normal Mode)
3V
Operating Current (Internal
RC+RTC OSC, Normal Mode)
3V
5V
No load, fSYS=12MHz
No load, fSYS=4MHz
5V
No load, fSYS=8MHz
5V
IDD6
Operating Current (Internal
RC+RTC OSC, Normal Mode)
IDD7
Operating Current (Internal
RC+RTC OSC, Slow Mode)
3V
Standby Current
(WDT Enabled, RTC Off)
3V
Standby Current
(WDT Disabled, RTC Off)
Unit
2.2
IDD4
ISTB2
Max.
fSYS=4MHz
Operating Current
(Crystal OSC, RC OSC)
ISTB1
Typ.
¾
IDD3
IDD5
Min.
Conditions
VDD
5V
No load, fSYS=12MHz
No load, fSYS=32768Hz
5V
No load, system HALT
5V
3V
No load, system HALT
5V
3V
Standby Current
(WDT Disabled, RTC On)
5V
VIL1
Input Low Voltage for PA0~PA7,
TMR0 and INT
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage forPA0~PA7,
TMR0 and INT
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLVR1
Low Voltage Reset 1
¾
3.98
4.2
4.42
V
ISTB3
Rev. 1.10
No load, system HALT
QOSC=1
Configuration option: 4.2V
4
August 4, 2008
HT48R01A
Test Conditions
Symbol
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
VLVR2
Low Voltage Reset 2
¾
Configuration option: 3.15V
2.98
3.15
3.32
V
VLVR3
Low Voltage Reset 3
¾
Configuration option: 2.1V
1.98
2.1
2.22
V
IOL
4
8
¾
mA
I/O Port Sink Current
10
20
¾
mA
-2
-4
¾
mA
-5
-10
¾
mA
20
60
100
kW
10
30
50
kW
3V
VOL=0.1VDD
5V
IOH
3V
I/O Port Source Current
VOH=0.9VDD
5V
RPH
3V
¾
Pull-high Resistance
5V
A.C. Characteristics
Symbol
fSYS1
fSYS2
Parameter
System Clock
(Crystal OSC, RC OSC)
System Clock
(Internal RC OSC)
(±5%)
fSYS3
System Clock (32768 Crystal)
fTIMER
Timer I/P Frequency (TMR)
tWDTOSC Watchdog Oscillator Period
Ta=25°C
Test Conditions
Conditions
VDD
Min.
Typ.
Max.
Unit
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
¾
4.5V~5.5V
400
¾
12000
kHz
4.5V~
12MHz, Ta=25°C
5.5V
11400 12000 12600
kHz
3.3V~
8MHz, Ta=25°C
5.5V
7600
8000
8400
kHz
2.7V~
4MHz, Ta=25°C
5.5V
3800
4000
4200
kHz
¾
32768
¾
Hz
¾
¾
¾
2.2V~5.5V
0
¾
4000
kHz
¾
3.3V~5.5V
0
¾
8000
kHz
¾
4.5V~5.5V
0
¾
12000
kHz
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
Wake-up from Power Down
¾
1024
¾
tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tLVR
Low Voltage Width to Reset
¾
¾
0.25
1
2
ms
VPOR
VDD Start Voltage to Ensure
Power-on Reset
¾
¾
¾
¾
100
mV
RPOR
VDD Rise Time to Ensure
Power-on Reset
¾
¾
0.035
¾
¾
V/ms
Note: tSYS=1/fSYS1, 1/fSYS2 or 1/fSYS3
Rev. 1.10
5
August 4, 2008
HT48R01A
System Architecture
A key factor in the high-performance features of the
Holtek range of microcontrollers is attributed to the internal system architecture. The range of devices take advantage of the usual features found within RISC
microcontrollers providing increased speed of operation
and enhanced performance. The pipelining scheme is
implemented in such a way that instruction fetching and
instruction execution are overlapped, hence instructions
are effectively executed in one cycle, with the exception
of branch or call instructions. An 8-bit wide ALU is used
in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation,
increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the
Accumulator and the ALU. Certain internal registers are
implemented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of
these registers along with additional architectural features ensure that a minimum of external components is
required to provide a functional I/O and A/D control system with maximum reliability and flexibility.
Clocking and Pipelining
The main system clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The
Program Counter is incremented at the beginning of the
T1 clock during which time a new instruction is fetched.
The remaining T2~T4 clocks carry out the decoding and
execution functions. In this way, one T1~T4 clock cycle
forms one instruction cycle. Although the fetching and
execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the
microcontroller ensures that instructions are effectively
executed in one instruction cycle. The exception to this
are instructions where the contents of the Program
Counter are changed, such as subroutine calls or
jumps, in which case the instruction will take one more
instruction cycle to execute.
For instructions involving branches, such as jump or call
instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications
O s c illa to r C lo c k
( S y s te m C lo c k )
P h a s e C lo c k T 1
P h a s e C lo c k T 2
P h a s e C lo c k T 3
P h a s e C lo c k T 4
P ro g ra m
C o u n te r
P ip e lin in g
P C
P C + 1
F e tc h In s t. (P C )
E x e c u te In s t. (P C -1 )
P C + 2
F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
1
M O V A ,[1 2 H ]
2
C A L L D E L A Y
3
C P L [1 2 H ]
:
5
:
D E L A Y :
E x e c u te In s t. 1
F e tc h In s t. 2
E x e c u te In s t. 2
F e tc h In s t. 3
F lu s h P ip e lin e
F e tc h In s t. 6
4
6
F e tc h In s t. 1
E x e c u te In s t. 6
F e tc h In s t. 7
N O P
Instruction Fetching
Rev. 1.10
6
August 4, 2008
HT48R01A
Program Counter
to pre-fetch. Further information on the PCL register can
be found in the Special Function Register section.
During program execution, the Program Counter is used
to keep track of the address of the next instruction to be
executed. It is automatically incremented by one each
time an instruction is executed except for instructions,
such as ²JMP² or ²CALL² that demand a jump to a
non-consecutive Program Memory address. Note that
the Program Counter width varies with the Program
Memory capacity depending upon which device is selected. However, it must be noted that only the lower 8
bits, known as the Program Counter Low Register, are
directly addressable by user.
Stack
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack has 4 levels and is neither part of the data nor part
of the program space, and is neither readable nor
writeable. The activated level is indexed by the Stack
Pointer, SP, and is neither readable nor writeable. At a
subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program
Counter is restored to its previous value from the stack.
After a device reset, the Stack Pointer will point to the
top of the stack.
When executing instructions requiring jumps to
non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the
microcontroller manages program control by loading the
required address into the Program Counter. For conditional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.
If the stack is full and an enabled interrupt takes place,
the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack
Pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack
overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program
branching.
The lower byte of the Program Counter, known as the
Program Counter Low register or PCL, is available for
program control and is a readable and writeable register. By transferring data directly into this register, a short
program jump can be executed directly, however, as
only this low byte is available for manipulation, the
jumps are limited to the present page of memory, that is
256 locations. When such program jumps are executed
it should also be noted that a dummy cycle will be inserted.
P ro g ra m
T o p o f S ta c k
S ta c k L e v e l 1
S ta c k L e v e l 2
S ta c k
P o in te r
The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might
cause program branching, so an extra cycle is needed
B o tto m
C o u n te r
P ro g ra m
M e m o ry
S ta c k L e v e l 3
S ta c k L e v e l 4
o f S ta c k
Program Counter Bits
Mode
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Initial Reset
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter Overflow
0
0
0
0
0
0
1
0
0
0
@3
@2
@1
@0
Skip
Program Counter + 2
Loading PCL
PC9
PC8
@7
@6
@5
@4
Jump, Call Branch
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
PC9~PC8: Current Program Counter bits
@7~@0: PCL bits
#9~#0: Instruction code address bits
S9~S0: Stack register bits
Rev. 1.10
7
August 4, 2008
HT48R01A
Arithmetic and Logic Unit - ALU
begin execution if the external interrupt is enabled and
the stack is not full. The external interrupt active edge
transition type, whether high to low, low to high or both
is specified in the CTRL1 register.
The arithmetic-logic unit or ALU is a critical area of the
microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main
microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or
logical operations after which the result will be placed in
the specified register. As these ALU calculation or operations may result in carry, borrow or other status
changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the
following functions:
· Location 008H
This internal vector is used by the Timer/Event Counter 0. If a counter overflow occurs, the program will
jump to this location and begin execution if the
timer/event counter interrupt is enabled and the stack
is not full.
0 0 0 H
0 0 4 H
· Arithmetic operations: ADD, ADDM, ADC, ADCM,
SUB, SUBM, SBC, SBCM, DAA
0 0 8 H
· Logic operations: AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
In itia lis a tio n
V e c to r
E x te rn a l
In te rru p t V e c to r
T im e r /E v e n t C o u n te r
In te rru p t V e c to r
0 0 C H
· Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
0 1 0 H
· Increment and Decrement INCA, INC, DECA, DEC
· Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
0 1 4 H
SIZA, SDZA, CALL, RET, RETI
3 0 0 H
Program Memory
3 F F H
The Program Memory is the location where the user
code or program is stored. The device is supplied with
One-Time Programmable, OTP, memory where users
can program their application code into the device. By
using the appropriate programming tools, OTP devices
offer users the flexibility to freely develop their applications which may be useful during debug or for products
requiring frequent upgrades or program changes. OTP
devices are also applicable for use in applications that
require low or medium volume production runs.
1 4 b its
N o t Im p le m e n te d
Program Memory Structure
Look-up Table
Any location within the Program Memory can be defined
as a look-up table where programmers can store fixed
data. To use the look-up table, the table pointer must
first be setup by placing the lower order address of the
look up data to be retrieved in the table pointer register,
TBLP. This register defines the lower 8-bit address of
the look-up table.
Structure
The Program Memory has a capacity of 1K by 14. The
Program Memory is addressed by the Program Counter
and also contains data, table information and interrupt
entries. Table data, which can be setup in any location
within the Program Memory, is addressed by separate
table pointer registers.
After setting up the table pointer, the table data can be
retrieved from the current Program Memory page or last
Program Memory page using the ²TABRDC[m]² or
²TABRDL [m]² instructions, respectively. When these instructions are executed, the lower order table byte from
the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the
Program Memory will be transferred to the TBLH special
register. Any unused bits in this transferred higher order
byte will be read as ²0².
Special Vectors
Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.
· Location 000H
This vector is reserved for use by the device reset for
program initialisation. After a device reset is initiated, the
program will jump to this location and begin execution.
· Location 004H
This vector is used by the external interrupt. If the external interrupt pin on the device receives an edge
transition, the program will jump to this location and
Rev. 1.10
8
August 4, 2008
HT48R01A
Table Location Bits
Instruction
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
TABRDC [m]
PC9
PC8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
PC9~PC8: Current Program Counter bits
@7~@0: Table Pointer TBLP bits
The following diagram illustrates the addressing/data
flow of the look-up table:
P ro g ra m C o u n te r
H ig h B y te
which is stored there using the ORG statement. The
value at this ORG statement is ²300H² which refers to
the start address of the last page within the 1K Program
Memory of the HT48R01A microcontrollers. The table
pointer is setup here to have an initial value of ²06H².
This will ensure that the first data read from the data table will be at the Program Memory address ²306H² or 6
locations after the start of the last page. Note that the
value for the table pointer is referenced to the first address of the present page if the ²TABRDC [m]² instruction is being used. The high byte of the table data which
in this case is equal to zero will be transferred to the
TBLH register automatically when the ²TABRDL [m]² instruction is executed.
P ro g ra m
M e m o ry
T B L P
T B L H
S p e c ifie d b y [m ]
T a b le C o n te n ts H ig h B y te
T a b le C o n te n ts L o w
B y te
Table Program Example
The following example shows how the table pointer and
table data is defined and retrieved from the device. This
example uses raw table data located in the last page
tempreg1
tempreg2
db
db
:
:
?
?
; temporary register #1
; temporary register #2
mov
a,06h
; initialise table pointer - note that this address
; is referenced
mov
tblp,a
:
:
; to the last page or present page
tabrdl
tempreg1
;
;
;
;
dec
tblp
; reduce value of table pointer by one
tabrdl
tempreg2
;
;
;
;
;
;
;
;
transfers value in table referenced by table pointer
to tempregl
data at prog. memory address ²306H² transferred to
tempreg1 and TBLH
transfers value in table referenced by table pointer
to tempreg2
data at prog.memory address ²305H² transferred to
tempreg2 and TBLH
in this example the data ²1AH² is transferred to
tempreg1 and data ²0FH² to register tempreg2
the value ²00H² will be transferred to the high byte
register TBLH
:
:
org
300h
dc
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Rev. 1.10
; sets initial address of last page
9
August 4, 2008
HT48R01A
General Purpose Data Memory
Because the TBLH register is a read-only register and
cannot be restored, care should be taken to ensure its
protection if both the main routine and Interrupt Service
Routine use the table read instructions. If using the table
read instructions, the Interrupt Service Routines may
change the value of TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read
instructions should be avoided. However, in situations
where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any
main routine table-read instructions. Note that all table
related instructions require two instruction cycles to
complete their operation.
All microcontroller programs require an area of
read/write memory where temporary data can be stored
and retrieved for use later. It is this area of RAM memory
that is known as General Purpose Data Memory. This
area of Data Memory is fully accessible by the user program for both read and write operations. By using the
²SET [m].i² and ²CLR [m].i² instructions individual bits
can be set or reset under program control giving the
user a large range of flexibility for bit manipulation in the
Data Memory.
Special Purpose Data Memory
This area of Data Memory is where registers, necessary
for the correct operation of the microcontroller, are
stored. Most of the registers are both readable and
writable but some are protected and are readable only,
the details of which are located under the relevant Special Function Register section. Note that for locations
that are unused, any read instruction to these addresses
will return the value ²00H².
Data Memory
The Data Memory is a volatile area of 8-bit wide RAM
internal memory and is the location where temporary information is stored. Divided into two sections, the first of
these is an area of RAM where special function registers
are located. These registers have fixed locations and
are necessary for correct operation of the device. Many
of these registers can be read from and written to directly under program control, however, some remain
protected from user manipulation. The second area of
Data Memory is reserved for general purpose use. All
locations within this area are read and write accessible
under program control.
Special Function Registers
To ensure successful operation of the microcontroller,
certain internal registers are implemented in the Data
Memory area. These registers ensure correct operation
of internal functions such as timers, interrupts, etc., as
well as external functions such as I/O data control and
A/D converter operation. The location of these registers
within the Data Memory begins at the address 00H. Any
unused Data Memory locations between these special
function registers and the point where the General Purpose Memory begins is reserved and attempting to read
data from these locations will return a value of 00H.
Structure
The two sections of Data Memory, the Special Purpose
and General Purpose Data Memory are located at consecutive locations. All are implemented in RAM and are
8 bits wide but the length of each memory section is dictated by the type of microcontroller chosen. The start
address of the Data Memory for all devices is the address ²00H². Registers which are common to all
microcontrollers, such as ACC, PCL, etc., have the
same Data Memory address.
Indirect Addressing Registers - IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register
space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data
manipulation uses these Indirect Addressing Registers
and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in
no actual read or write operation to these registers but
rather to the memory location specified by their corresponding Memory Pointer, MP0 or MP1. Acting as a
pair, IAR0 with MP0 and IAR1 with MP1 can together access data from the Data Memory. As the Indirect Addressing Registers are not physically implemented,
reading the Indirect Addressing Registers indirectly will
return a result of ²00H² and writing to the registers indirectly will result in no operation.
0 0 H
S p e c ia l P u r p o s e
D a ta M e m o ry
1 F H
2 0 H
G e n e ra l P u rp o s e
D a ta M e m o ry
5 F H
Data Memory Structure
Note:
Most of the Data Memory bits can be directly
manipulated using the ²SET [m].i² and ²CLR
[m].i² with the exception of a few dedicated bits.
The Data Memory can also be accessed
through the memory pointer registers.
Rev. 1.10
10
August 4, 2008
HT48R01A
0 0 H
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
Memory Pointers - MP0, MP1
Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in
the same way as normal registers providing a convenient way with which to address and track data. When
any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the
microcontroller is directed to, is the address specified by
the related Memory Pointer, bit 7 of the Memory
Pointers is not required to address the full memory
space. It must be noted that when bit 7 of the Memory
Pointers for these devices is read, a value of ²1² will be
returned. The following example shows how to clear a
section of four Data Memory locations already defined as
locations adres1 to adres4.
0 4 H
A C C
0 5 H
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
W D T S
0 A H
S T A T U S
0 B H
IN T C 0
0 C H
0 D H
T M R 0
0 E H
T M R 0 C
0 F H
S p e c ia l P u r p o s e
D a ta M e m o ry
1 0 H
1 1 H
1 2 H
P A
1 3 H
P A C
1 4 H
P A P U
1 5 H
P A W K
1 6 H
C T R L 0
1 7 H
C T R L 1
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
G e n e ra l P u rp o s e
D a ta M e m o ry
(6 4 B y te s )
5 F H
: U n u s e d ,
re a d a s "0 0 "
Special Purpose Data Memory
data .section ¢data¢
adres1
db ?
adres2
db ?
adres3
db ?
adres4
db ?
block
db ?
code .section at 0 ¢code¢
org 00h
start:
mov
mov
mov
mov
a,04h
; setup size of block
block,a
a,offset adres1; Accumulator loaded with first RAM address
mp0,a
; setup memory pointer with first RAM address
clr
inc
sdz
jmp
IAR0
mp0
block
loop
loop:
; clear the data at address defined by MP0
; increment memory pointer
; check if last memory location has been cleared
continue:
The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses.
Rev. 1.10
11
August 4, 2008
HT48R01A
Accumulator - ACC
Status Register - STATUS
The Accumulator is central to the operation of any
microcontroller and is closely related with operations
carried out by the ALU. The Accumulator is the place
where all intermediate results from the ALU are stored.
Without the Accumulator it would be necessary to write
the result of each calculation or logical operation such
as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads.
Data transfer operations usually involve the temporary
storage function of the Accumulator; for example, when
transferring data between one user defined register and
another, it is necessary to do this by passing the data
through the Accumulator as no direct transfer between
two registers is permitted.
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO).
These arithmetic/logical operation and system management flags are used to record the status and operation of
the microcontroller.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO
flag can be affected only by a system power-up, a WDT
time-out or by executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by executing the
²HALT² or ²CLR WDT² instruction or during a system
power-up.
Program Counter Low Register - PCL
To provide additional program control functions, the low
byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area
of the Data Memory. By manipulating this register, direct
jumps to other program locations are easily implemented. Loading a value directly into this PCL register
will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only
jumps within the current Program Memory page are permitted. When such operations are used, note that a
dummy cycle will be inserted.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
· C is set if an operation results in a carry during an ad-
dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
· AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
Look-up Table Registers - TBLP, TBLH
· Z is set if the result of an arithmetic or logical operation
These two special function registers are used to control
operation of the look-up table which is stored in the Program Memory. TBLP is the table pointer and indicates
the location where the table data is located. Its value
must be setup before any table read commands are executed. Its value can be changed, for example using the
²INC² or ²DEC² instructions, allowing for easy table data
pointing and reading. TBLH is the location where the
high order byte of the table data is stored after a table
read data instruction has been executed. Note that the
lower order table data byte is transferred to a user defined location.
is zero; otherwise Z is cleared.
· OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit,
or vice versa; otherwise OV is cleared.
· PDF is cleared by a system power-up or executing the
²CLR WDT² instruction. PDF is set by executing the
²HALT² instruction.
· TO is cleared by a system power-up or executing the
²CLR WDT² or ²HALT² instruction. TO is set by a
WDT time-out.
b 7
b 0
T O
P D F
O V
Z
A C
C
S T A T U S R e g is te r
A r
C a
A u
Z e
O v
ith m e
r r y fla
x ilia r y
r o fla g
e r flo w
g
tic /L o g ic O p e r a tio n F la g s
c a r r y fla g
S y s te m M
P o w e r d o w
W a tc h d o g
N o t im p le m
fla g
a n
n
tim
e
a g e m e n t F la g s
fla g
e - o u t fla g
n te d , re a d a s "0 "
Status Register
Rev. 1.10
12
August 4, 2008
HT48R01A
feature of these registers is the ability to directly program single bits using the ²SET [m].i² and ²CLR [m].i²
instructions. The ability to change I/O pins from output to
input and vice versa by manipulating specific bits of the
I/O control registers during normal program operation is
a useful feature of these devices.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the interrupt routine can change the status register, precautions must be
taken to correctly save it.
Interrupt Control Registers - INTC0
System Control Register - CTRL0
The 8-bit register, known as INTC0, control the operation of both external, and internal timer interrupts. By
setting various bits within this register using standard bit
manipulation instructions, the enable/disable function of
each interrupt can be independently controlled. A master interrupt bit within this register, the EMI bit, acts like a
global enable/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an interrupt routine is entered to disable further interrupt and
is set by executing the ²RETI² instruction.
This register is used to provide control over certain internal functions including certain system clock options, the
buzzer selection control and an RTC Oscillator quick
start up function.
Timer/Event Counter Register
This register is used to provide control over certain internal functions including the External Interrupt edge trigger type and the Watchdog Timer control function.
When the buzzer function, BZ or BZ, is disabled, then
these two pins will have a normal I/O function. If enabled, the BZ or BZ outputs will still be controlled by the
related I/O port control and data settings.
System Control Register - CTRL1
The device contains one integrated 8-bit Timer/Event
Counter. An associated register known as TMR0 is the
location where the timer¢s 8-bit value is located. An associated control register, known as TMR0C, contains
the setup information for this timer.
Wake-up Function Register - PAWK
When the microcontroller enters the Power Down Mode,
various methods exist to wake the device up and continue with normal operation. One method is to allow a
low going edge on the I/O pins to have a wake-up function. This register is used to select which I/O pins are
used to have this wake-up function.
Input/Output Ports and Control Registers
Within the area of Special Function Registers, the port
PA data I/O register and its associated control register
PAC play a prominent role. These registers are mapped
to specific addresses within the Data Memory as shown
in the Data Memory table. The PA data I/O register, is
used to transfer the appropriate output or input data on
the PA port. The PAC control register specifies which
pins of PA are set as inputs and which are set as outputs. To setup a pin as an input, the corresponding bit of
the control register must be set high, for an output it
must be set low. During program initialisation, it is important to first setup the control registers to specify which
pins are outputs and which are inputs before reading
data from or writing data to the I/O ports. One flexible
Rev. 1.10
Pull-high Register - PAPU
The I/O pins, if configured as inputs, can have internal
pull-high resistors connected, which eliminates the need
for external pull-high resistors. This register selects which
I/O pins are connected to internal pull-high resistors.
13
August 4, 2008
HT48R01A
b 7
B Z E N 1
B Z E N 0
Q O S C
b 0
C L K M O D
S y s te m
S y
0 :
1 :
N o
o p
s te m
h ig h
lo w s
te th
tio n s
C o n tr o l R e g is te r
c lo c k m
s p e e d p e e d - R
a t th e s e
h a v e s e
C T R L 0
o d e s e le c tio n
In te rn a l R C a s
T C a s s y s te m
s e le c tio n s a r e
le c te d th e In te
s y s te m
c lo c k ,
o n ly v a
rn a l R C
c lo c k
In te r n a l R C o s c illa to r s to p p e d
lid if th e o s c illa to r c o n fig u r a tio n
+ R T C a s th e s y s te m c lo c k
R T C o s c illa to r q u ic k s ta r t- u p fu n c tio n
0 : q u ic k s ta r t- u p
1 : s lo w s ta r t- u p
B Z
0 0
0 1
1 0
1 1
E N [1
: b o th
: re s e
: B Z o
: B Z a
:0 ]
d is
rv e
n ly
n d
= B Z , B Z
a b le
e n a b le
B Z e n a b le
N o t im p le m e n te d , r e a d a s " 0 "
System Control Register - CTRL0
b 7
IN T E S 1
IN T E S 0
b 0
W D T E N 3 W D T E N 2 W D T E N 1 W D T E N 0
S y s te m
C o n tr o l R e g is te r
C T R L 1
W D T fu n c tio n
0
1
X
X
d is a b le
o th e r v a lu e s - e n a b le
0
1
X
X
N o t im p le m e n te d , r e a d a s " 0 "
E x te r n a l in te r r u p t e d g e tr ig g e r ty p e
IN T E S 1
IN T E S 0
0
0
d is a b le
0
1
r is in g e d g e tr ig g e r
1
0
fa llin g e d g e tr ig g e r
1
1
d u a l e d g e tr ig g e r
System Control Register - CTRL1
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on
their I/O ports. There are seven I/O pins whose input or
output designation is under user program control and an
additional input pin. Additionally, as there are pull-high
resistor and wake-up software configurations for each
pin, the user is provided with an I/O structure to meet the
needs of a wide range of application possibilities.
have the capability of being connected to an internal
pull-high resistor. These pull-high resistors are
selectable via a register known as PAPU, located in the
Data Memory. The pull-high resistors are implemented
using weak PMOS transistors.
Each device has a single I/O port known as Port A,
which has a corresponding data register known as PA.
This register is mapped to the Data Memory with an address as shown in the Special Purpose Data Memory table. Seven of these I/O lines can be used for input and
output operations and one line as an input only. For input operation, these ports are non-latching, which
means the inputs must be ready at the T2 rising edge of
instruction ²MOV A,[m]², where m denotes the port address. For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
If the HALT instruction is executed, the device will enter
the Power Down Mode, where the system clock will stop
resulting in power being conserved, a feature that is important for battery and other low-power applications.
Various methods exist to wake-up the microcontroller,
one of which is to change the logic condition on one of
the PA0~PA7 pins from high to low. After a HALT instruction forces the microcontroller into entering the Power
Down Mode, the processor will remain idle or in a
low-power state until the logic condition of the selected
wake-up pin on Port A changes from high to low. This
function is especially suitable for applications that can
be woken up via external switches. Note that pins PA0 to
PA7 can be selected individually to have this wake-up
feature using an internal register known as PAWK, located in the Data Memory.
Port A Wake-up
Pull-high Resistors
Many product applications require pull-high resistors for
their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, I/O pins PA0~PA6, when configured as an input
Rev. 1.10
14
August 4, 2008
HT48R01A
· Buzzer
I/O Port Control Registers
Buzzer output pins BZ and BZ are pin-shared with I/O
pins PA0 and PA1. The buzzer function is selected by
setting the appropriate bits in the CTRL0 register.
Note that the corresponding bits of the port control
register, PAC, must setup the pins as outputs to enable the buzzer outputs. If the PAC port control register has setup the pins as inputs, then the pins will
functions as normal logic inputs with the usual
pull-high options, even if the buzzer function has been
selected.
Port A has its own control register, known as PAC, which
controls the input/output configuration. With this control
register, each PA0~PA6 I/O pin with or without pull-high
resistors can be reconfigured dynamically under software control. Pins PA0 to PA6 port are directly mapped
to a bit in its associated port control register. For the I/O
pin to function as an input, the corresponding bit of the
control register must be written as a ²1². This will then
allow the logic state of the input pin to be directly read by
instructions. When the corresponding bit of the control
register is written as a ²0², the I/O pin will be setup as a
CMOS output. If the pin is currently setup as an output,
instructions can still be used to read the output register.
However, it should be noted that the program will in fact
only read the status of the output data latch and not the
actual logic status of the output pin.
I/O Pin Structures
The diagrams illustrate the I/O pin internal structures. As
the exact logical construction of the I/O pin may differ
from these drawings, they are supplied as a guide only
to assist with the functional understanding of the I/O
pins.
Pin-shared Functions
Programming Considerations
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design
constraints on designers but by supplying pins with
multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the
multi-function I/O pins is set by configuration options
while for others the function is set by application program control.
Within the user program, one of the first things to consider is port initialisation. After a reset, the PA data register and PAC port control register will be set high. This
means that all I/O pins will default to an input state, the
level of which depends on the other connected circuitry
and whether pull-high options have been selected. If the
PAC port control register, is then programmed to setup
some pins as outputs, these output pins will have an initial high output value unless the associated PA port data
register is first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide
by loading the correct value into the port control register
or by programming individual bits in the port control register using the ²SET [m].i² and ²CLR [m].i² instructions.
Note that when using these bit control instructions, a
read-modify-write operation takes place. The
microcontroller must first read in the data on the entire
port, modify it to the required new bit values and then rewrite this data back to the output ports.
· External Interrupt Input
The external interrupt pin, INT, is pin-shared with the
I/O pin PA3. To use the pin as an external interrupt input the correct bits in the INTCO register must be programmed. The pin must also be setup as an input by
setting the appropriate bit in the Port Control Register.
A pull-high resistor can also be selected via the appropriate port pull-high resistor register. Note that even if
the pin is setup as an external interrupt input the I/O
function still remains.
· External Timer/Event Counter Input
T 1
The device contains a single Timer/Event Counter.
The Timer/Event Counter has an external input pin,
known as TMR0 which is pin-shared with the I/O pin
PA2. For the shared pin to be used as a Timer/Event
Counter input, the Timer/Event Counter must be configured to be in the Event Counter or Pulse Width
Measurement Mode. This is achieved by setting the
appropriate bits in the Timer/Event Counter Control
Register. The pin must also be setup as an input by
setting the appropriate bit in the Port Control Register.
Pull-high resistor options can also be selected via the
port pull-high resistor register. Note that even if the pin
is setup as an external timer input the I/O function still
remains.
Rev. 1.10
S y s te m
T 2
T 3
T 4
T 1
T 2
T 3
T 4
C lo c k
P o rt D a ta
W r ite to P o r t
R e a d fro m
P o rt
Read/Write Timing
Pins PA0 to PA7 each have a wake-up functions, selected via the PAWK register. When the device is in the
Power Down Mode, various methods are available to
wake the device up. One of these is a high to low transition of any of the these pins. Single or multiple pins on
Port A can be setup to have this function.
15
August 4, 2008
HT48R01A
V
D D
P A P U 4 ~ P A P U 0
C o n tr o l B it
Q
D
D a ta B u s
W r ite C o n tr o l R e g is te r
C K
W e a k
P u ll- u p
P A
P A
P A
P A
P A
Q
S
C h ip R e s e t
0 /B
1 /B
2 /T
3 /IN
4
Z
Z
M R 0
T
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
Q
S
M
B u z z e r
W a v e fo rm
M
R e a d D a ta R e g is te r
S y s te m
W a k e -u p
U
U
X
B u z z e r
X
P A W K 4 ~ P A W K 0
IN T ( P A 3 o n ly )
T M R 0 ( P A 2 o n ly )
PA0~PA4 Input/Output Ports
V
P A P U 5 , P A P U 6
C o n tr o l B it
D a ta B u s
W r ite C o n tr o l R e g is te r
W e a k
P u ll- u p
Q
D
C K
D D
Q
S
C h ip R e s e t
P A 5 /O S C 2
P A 6 /O S C 1
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
S
O s c illa to r
C o n fig u r a tio n
O p tio n s
Q
M
R e a d D a ta R e g is te r
S y s te m
U
S c h m itt T r ig g e r In p u t
X
W a k e -u p
O s c illa to r
C ir c u it
P A W K 5 /P A W K 6
PA5~PA6 Input/Output Ports
S y s te m
W a k e -u p
P A W K 7
R e a d D a ta
D a ta B u s
P A 7 /R E S
T o R e s e t C ir c u it
R e s e t C o n fig u r a tio n O p tio n
PA7 Input Port
Rev. 1.10
16
August 4, 2008
HT48R01A
Timer/Event Counters
upon the condition of the T0E bit, each high to low, or
low to high transition on the external timer pin will increment the counter by one.
The provision of timers form an important part of any
microcontroller, giving the designer a means of carrying
out time related functions. The device contains one
count-up timer of 8-bit capacity. As the timer has three
different operating modes, it can be configured to operate as a general timer, an external event counter or as a
pulse width measurement device. The provision of an
internal prescaler to the clock circuitry gives added
range to the timer.
Timer Registers - TMR0
The timer registers are special function registers located
in the Special Purpose Data Memory and is the place
where the actual timer value is stored. This register is
known as TMR0. The value in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the external
timer pin. The timer will count from the initial value loaded
by the preload register to the full count of FFH at which
point the timer overflows and an internal interrupt signal is
generated. The timer value will then be reset with the initial preload register value and continue counting.
There are two types of registers related to the
Timer/Event Counters. The first is the register that contains the actual value of the timer and into which an initial value can be preloaded. Reading from this register
retrieves the contents of the Timer/Event Counter. The
second type of associated register is the Timer Control
Register which defines the timer options and determines how the timer is to be used. The device can have
the timer clock configured to come from the internal
clock source. In addition, the timer clock source can also
be configured to come from an external timer pin.
Note that to achieve a maximum full range count of FFH,
the preload register must first be cleared to all zeros. It
should be noted that after power-on, the preload registers will be in an unknown condition. Note that if the
Timer/Event Counters are in an OFF condition and data
is written to their preload registers, this data will be immediately written into the actual counter. However, if the
counter is enabled and counting, any new data written
into the preload data registers during this period will remain in the preload registers and will only be written into
the actual counter the next time an overflow occurs.
An external clock source is used when the timer is in the
event counting mode, the clock source being provided
on the external timer pin, known as TMR0. These external timer pins are pin-shared with other I/O pins. Depending upon the condition of the T0E bit in the Timer
Control Register, each high to low, or low to high transition on the external timer input pin will increment the
counter by one.
Timer Control Registers - TMR0C
Configuring the Timer/Event Counter Input Clock
Source
The flexible features of the Holtek microcontroller
Timer/Event Counters enable them to operate in three
different modes, the options of which are determined by
the contents of their respective control register.
The internal timer¢s clock can originate from various
sources, depending upon which device and which timer
is chosen. The system clock input timer source is used
when the timer is in the timer mode or in the pulse width
measurement mode. For Timer/Event Counter 0 this
system clock timer source is first divided by a prescaler,
the division ratio of which is conditioned by the Timer
Control Register bits T0PSC0~T0PSC2.
The Timer Control Register is known as TMR0C. It is the
Timer Control Register together with its corresponding
timer register that control the full operation of the
Timer/Event Counter. Before the timer can be used, it is
essential that the Timer Control Register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during
program initialisation.
An external clock source is used when the timer is in the
event counting mode, the clock source being provided
on an external timer pin TMR0 or TMR1, depending
upon which device and which timer is used. Depending
To choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode
D a ta B u s
P r e lo a d R e g is te r
fS Y S
R T C O s c illa to r
T 0 S
M
U
T 0 P S C 2 ~ T 0 P S C 0
(1 /2 ~ 1 /2 5 6 )
X
8 - s ta g e p r e s c a le r
T 0 M 1
R e lo a d
T 0 M 0
T im e r /E v e n t C o u n te r
M o d e C o n tro l
O v e r flo w
to In te rru p t
T im e r /E v e n t C o u n te r
T 0 O N
T M R 0
¸
2
B u z z e r
T 0 E
8-bit Timer/Event Counter Structure
Rev. 1.10
17
August 4, 2008
HT48R01A
bit pair, T0M1/T0M0, must be set to 1 and 0 respectively. In this mode the internal clock is used as the timer
clock. The timer input clock source is either fsys or the
RTC oscillator. However, this timer clock source is further divided by a prescaler, the value of which is determined by the bits T0PSC2~T0PSC0 in the Timer
Control Register. The timer-on bit, T0ON must be set
high to enable the timer to run. Each time an internal
clock high to low transition occurs, the timer increments
by one; when the timer is full and overflows, an interrupt
signal is generated and the timer will preload the value
already loaded into the preload register and continue
counting. A timer overflow condition and corresponding
internal interrupt is one of the wake-up sources, however, the internal interrupts can be disabled by ensuring
that the ET0I bits of the INTC0 register are reset to zero.
or the pulse width measurement mode, bits 7 and 6 of
the Timer Control Register, which are known as the bit
pair T0M1/T0M0, must be set to the required logic levels. The timer-on bit, which is bit 4 of the Timer Control
Register and known as T0ON, provides the basic on/off
control of the respective timer. Setting the bit high allows
the counter to run, clearing the bit stops the counter. Bits
0~2 of the Timer Control Register determine the division
ratio of the input clock prescaler. The prescaler bit settings have no effect if an external clock source is used. If
the timer is in the event count or pulse width measurement mode, the active transition edge level type is selected by the logic level of bit 3 of the Timer Control
Register which is known as T0E.
Configuring the Timer Mode
In this mode, the timer can be utilized to measure fixed
time intervals, providing an internal interrupt signal each
time the counter overflows. To operate in this mode, the
b 7
T 0 M 1 T 0 M 0
b 0
T 0 S
T 0 O N
T 0 E
T 0 P S C 2
T 0 P S C 1
T 0 P S C 0
T im e r /E v e n t C o u n te r C o n tr o l R e g is te r
T M R 0 C
T im e r p r e s c a le r r a te s e le c t
T 0 P S C 2 T 0 P S C 1
T 0 P S C 0
0
0
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
1
1
1
0
1
1
1
E v
1 :
0 :
P u
1 :
0 :
e n t C
c o u n
c o u n
ls e W
s ta rt
s ta rt
o u n te r a c tiv e e d g
t o n fa llin g e d g e
t o n r is in g e d g e
id th M e a s u r e m e n
c o u n tin g o n r is in g
c o u n tin g o n fa llin g
T im e r
1 :1
1 :2
1 :4
1 :8
1 :1
1 :3
1 :6
1 :1
4
R a te
2
6
2 8
e s e le c t
t a c tiv e e d g e s e le c t
e d g e , s to p o n fa llin g e d g e
e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r c o u n tin g e n a b le
1 : e n a b le
0 : d is a b le
T im e r c lo c k s o u r c e
1 : R T C
0 : fS Y S
O p e r a tin
T 0 M 1 T
0
0
1
1
g m o d e s e le c t
0 M 0
n o m o d e a v a ila b le
0
e v e n t c o u n te r m o d e
1
tim e r m o d e
0
1
p u ls e w id th m e a s u r e m e n t m o d e
TMR0C Register
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o n tr o lle r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N + 1
Timer Mode Timing Chart
Rev. 1.10
18
August 4, 2008
HT48R01A
Configuring the Event Counter Mode
reset to zero and the timer will stop counting. If the T0E
bit is high, the timer will begin counting once a low to
high transition has been received on the external timer
pin and stop counting when the external timer pin returns to its original low level. As before, the T0ON bit will
be automatically reset to zero and the timer will stop
counting. It is important to note that in the Pulse Width
Measurement Mode, the T0ON bit is automatically reset
to zero when the external control signal on the external
timer pin returns to its original level, whereas in the other
two modes the T0ON bit can only be reset to zero under
program control. The residual value in the timer, which
can now be read by the program, therefore represents
the length of the pulse received on the external timer
pin. As the T0ON bit has now been reset, any further
transitions on the external timer pin, will be ignored. Not
until the T0ON bit is again set high by the program can
the timer begin further pulse width measurements. In
this way, single shot pulse measurements can be easily
made. It should be noted that in this mode the counter is
controlled by logical transitions on the external timer pin
and not by the logic level. As in the case of the other two
modes, when the counter is full, the timer will overflow
and generate an internal interrupt signal. The counter
will also be reset to the value already loaded into the
preload register. If the external timer pin is pin-shared
with other I/O pins, to ensure that the pin is configured to
operate as a pulse width measuring input pin, two things
have to happen. The first is to ensure that the
T0M1/T0M0 bits place the Timer/Event Counter in the
pulse width measuring mode, the second is to ensure
that the port control register configures the pin as an input. It should be noted that a timer overflow and corresponding timer interrupt is one of the wake-up sources.
Note that the timer interrupts can be disabled by ensuring that the ET0I bits in the INTC0 register are reset to
zero.
In this mode, a number of externally changing logic
events, occurring on the external timer pin, can be recorded by the internal timer. For the timer to operate in
the event counting mode, the bit pair, T0M1/T0M0 must
be set to 0 and 1 respectively. The timer-on bit T0ON or
T1ON, depending upon which timer is used, must be set
high to enable the timer to count. If T0E is low, the counter will increment each time the external timer pin receives a low to high transition. If T0E is high, the counter
will increment each time the external timer pin receives
a high to low transition. As in the case of the other two
modes, when the counter is full, the timer will overflow
and generate an internal interrupt signal. The counter
will then preload the value already loaded into the
preload register. As the external timer pins are
pin-shared with other I/O pins, to ensure that the pin is
configured to operate as an event counter input pin, two
things have to happen. The first is to ensure that the
T0M1/T0M0 bits place the Timer/Event Counter in the
event counting mode, the second is to ensure that the
port control register configures the pin as an input. It
should be noted that a timer overflow is one of the interrupt and wake-up sources. Note that the timer interrupts
can be disabled by ensuring that the ET0I bits in the
INTC0 register are reset to zero.
Configuring the Pulse Width Measurement Mode
In this mode, the width of external pulses applied to the
external timer pin can be measured. In the Pulse Width
Measurement Mode the timer clock source is supplied
by the internal clock. For the timer to operate in this
mode, the bit pair, T0M1/T0M0 must both be set high. If
the T0E bit is low, once a high to low transition has been
received on the external timer pin, the timer will start
counting until the external timer pin returns to its original
high level. At this point the T0ON bit will be automatically
E x te rn a l E v e n t
In c re m e n t
T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + 3
Event Counter Mode Timing Chart
E x te r n a l T im e r
P in In p u t
T 0 O N o r T 1 O N
( w ith T 0 E o r T 1 E = 0 )
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o u n te r
+ 1
T im e r
+ 2
+ 3
+ 4
P r e s c a le r O u tp u t is s a m p le d a t e v e r y fa llin g e d g e o f T 1 .
Pulse Width Measure Mode Timing Chart
Rev. 1.10
19
August 4, 2008
HT48R01A
Prescaler
data bit PA1 has no effect on the overall control of the
BZ and BZ pins.
Bits T0PSC0~T0PSC2 of the TMR0C register can be
used to define a division ratio for the internal clock
source of the Timer/Event Counter enabling longer time
out periods to be setup.
Using this method of frequency generation, and if a
crystal oscillator is used for the system clock, very precise values of frequency can be generated.
Buzzer Function
I/O Interfacing
Operating similar to a programmable frequency divider,
the buzzer function within the microcontroller provides a
means of producing a variable frequency output suitable
for applications, such as piezo-buzzer driving or other
interfaces requiring a precise frequency generator.
The Timer/Event Counter, when configured to run in the
event counter or pulse width measurement mode, requires the use of an external timer pin for its operation.
As this pin is a shared pin it must be configured correctly
to ensure that it is setup for use as a Timer/Event Counter input pin. This is achieved by ensuring that the mode
select bits in the Timer/Event Counter control register,
select either the event counter or pulse width measurement mode. Additionally the corresponding PAC Port
Control Register bit must be set high to ensure that the
pin is setup as an input. Any pull-high resistor connected
to this pin will remain valid even if the pin is used as a
Timer/Event Counter input.
BZ and BZ pins are a complimentary pair and pin-shared
with I/O pins, PA0 and PA1. The function is selected via
the CTRL0 register, however, if not selected, the pins can
operate as normal I/O pins. Note that the BZ pin is the inverse of the BZ pin generating a kind of differential output
and supplying more power to connected interfaces such
as buzzers. The CTRL0 register can select a single BZ
pin or the complimentary pair BZ and BZ.
The timer overflow signal is the clock source for the
buzzer circuit. The output frequency is controlled by loading the required values into the timer prescaler and timer
registers to give the required division ratio. The counter
will begin to count-up from this preload register value until
full, at which point an overflow signal is generated, causing both the BZ and BZ outputs to change state. The
counter will then be automatically reloaded with the
preload register value and continue counting- up.
Programming Considerations
When configured to run in the timer mode, the internal
system clock is used as the timer clock source and is
therefore synchronised with the overall operation of the
microcontroller. In this mode when the appropriate timer
register is full, the microcontroller will generate an internal
interrupt signal directing the program flow to the respective internal interrupt vector. For the pulse width measurement mode, the internal system clock is also used as
the timer clock source but the timer will only run when the
correct logic condition appears on the external timer input
pin. As this is an external event and not synchronised
with the internal timer clock, the microcontroller will only
see this external event when the next timer clock pulse
arrives. As a result, there may be small differences in
measured values requiring programmers to take this into
account during programming. The same applies if the
timer is configured to be in the event counting mode,
which again is an external event and not synchronised
with the internal system or timer clock.
If the CTRL0 register has selected the buzzer function,
then for both buzzer outputs to operate, it is essential
that the Port A control register PAC bit 0 and PAC bit 1
are setup as outputs. If only one pin is setup as an output, the other pin can still be used as a normal data input
pin. However, if both pins are setup as inputs then the
buzzer will not function. The buzzer outputs will only be
activated if bit PA0 is set to ²1². This output data bit is
used as the on/off control bit for the buzzer outputs.
Note that the BZ and BZ outputs will both be low if the
PA0 output data bit is cleared to ²0². The condition of
T im e r O v e r flo w
B u z z e r C lo c k
P A 0 D a ta
B Z O u tp u t a t P A 0
B Z O u tp u t a t P A 1
Buzzer Function
Rev. 1.10
20
August 4, 2008
HT48R01A
When the Timer/Event Counter is read, or if data is written to the preload register, the clock is inhibited to avoid
errors, however as this may result in a counting error, this
should be taken into account by the programmer. Care
must be taken to ensure that the timers are properly initialised before using them for the first time. The associated timer enable bits in the interrupt control register must
be properly set otherwise the internal interrupt associated
with the timer will remain inactive. The edge select, timer
mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. It is also
important to ensure that an initial value is first loaded into
the timer registers before the timer is switched on; this is
because after power-on the initial values of the timer registers are unknown. After the timer has been initialised
the timer can be turned on and off by controlling the enable bit in the timer control register.
generate a wake-up signal if the device is in a
Power-down condition. This situation may occur if the
Timer/Event Counter is in the Event Counting Mode and
if the external signal continues to change state. In such
a case, the Timer/Event Counter will continue to count
these external events and if an overflow occurs the device will be woken up from its Power-down condition. To
prevent such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing
the ²HALT² instruction to enter the Power Down Mode.
Timer Program Example
The program shows how the Timer/Event Counter registers are setup along with how the interrupts are enabled
and managed. Note how the Timer/Event Counter is
turned on, by setting bit 4 of the Timer Control Register.
The Timer/Event Counter can be turned off in a similar
way by clearing the same bit. This example program
sets the Timer/Event Counters to be in the timer mode,
which uses the internal system clock as their clock
source.
When the Timer/Event Counter overflows, its corresponding interrupt request flag in the interrupt control
register will be set. If the Timer/Event Counter interrupt
is enabled this will in turn generate an interrupt signal.
However irrespective of whether the interrupts are enabled or not, a Timer/Event Counter overflow will also
:
org 04h
:
; external interrupt vector
org 08h
; Timer Counter 0 interrupt vector
jmp tmr0int
; jump here when Timer 0 overflows
:
:
org 20h
; main program
:
:
;internal Timer 0 interrupt routine
tmr0int:
:
; Timer 0 main program placed here
:
:
begin:
;setup Timer 0 registers
mov a,09bh
; setup Timer 0 preload value
mov tmr0,a
mov a,081h
; setup Timer 0 control register
mov tmr0c,a
; timer mode and prescaler set to /2
;setup interrupt register
mov a,00dh
; enable master interrupt and both timer interrupts
mov intc0,a
:
:
set tmr0c.4
; start Timer 0
:
:
Rev. 1.10
21
August 4, 2008
HT48R01A
Interrupts
Interrupts are an important part of any microcontroller
system. When an external event or an internal function
such as a Timer/Event Counter requires microcontroller
attention, their corresponding interrupt will enforce a
temporary suspension of the main program allowing the
microcontroller to direct attention to their respective
needs. The device contains a single external interrupt
and a single internal interrupt function. The external interrupt is controlled by the action of the external interrupt pin, while the internal interrupt is controlled by the
Timer/Event Counter overflow.
Interrupt Operation
A Timer/Event Counter overflow or an active edge on
the external interrupt pin will all generate an interrupt request by setting their corresponding request flag, if their
appropriate interrupt enable bit is set. When this happens, the Program Counter, which stores the address of
the next instruction to be executed, will be transferred
onto the stack. The Program Counter will then be loaded
with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then
fetch its next instruction from this interrupt vector. The
instruction at this vector will usually be a JMP statement
which will jump to another section of program which is
known as the interrupt service routine. Here is located
the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI
statement, which retrieves the original Program Counter
address from the stack and allows the microcontroller to
continue with normal execution at the point where the interrupt occurred.
Interrupt Register
Overall interrupt control, which means interrupt enabling
and request flag setting, is controlled by a single INTC0
register, which is located in the Data Memory. By controlling the appropriate enable bits in this registers each
individual interrupt can be enabled or disabled. Also
when an interrupt occurs, the corresponding request
flag will be set by the microcontroller. The global enable
flag if cleared to zero will disable all interrupts.
A u to m a tic a lly C le a r e d b y IS R
M a n u a lly S e t o r C le a r e d b y S o ftw a r e
A u to m a tic a lly D is a b le d b y IS R
C a n b e E n a b le d M a n u a lly
E x te rn a l In te rru p t
R e q u e s t F la g E IF
E E I
T im e r /E v e n t C o u n te r 0
In te r r u p t R e q u e s t F la g T 0 F
E T 0 I
E M I
P r io r ity
H ig h
In te rru p t
P o llin g
L o w
Interrupt Scheme
b 7
b 0
T 0 F
E IF
E T 0 I
E E I
E M I
IN T C 0 R e g is te r
M a s te r In te r r u p t G lo b a l E n a b le
1 : g lo b a l e n a b le
0 : g lo b a l d is a b le
E x te r n a l In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
T im e r /E v e n t C o u n te r In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
E x te r n a l In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
T im e r /E v e n t C o u n te r In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
N o t im p le m e n te d , r e a d a s " 0 "
INTC0 Register
Rev. 1.10
22
August 4, 2008
HT48R01A
The various interrupt enable bits, together with their associated request flags, are shown in the following diagram with their order of priority.
The external interrupt pin is pin-shared with the I/O pin
PA3 and can only be configured as an external interrupt
pin if the corresponding external interrupt enable bit in
the INTC0 register has been set and the edge trigger
type has been selected using the CTRL1 register. The
pin must also be setup as an input by setting the corresponding PAC.3 bit in the port control register. When the
interrupt is enabled, the stack is not full and a transition
appears on the external interrupt pin, a subroutine call to
the external interrupt vector at location 04H, will take
place. When the interrupt is serviced, the external interrupt request flag, EIF, will be automatically reset and the
EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor connections on
this pin will remain valid even if the pin is used as an external interrupt input.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting
from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing
while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
Timer/Event Counter Interrupt
For a Timer/Event Counter interrupt to occur, the global
interrupt enable bit, EMI, and the corresponding timer
interrupt enable bit, ET0I, must first be set. An actual
Timer/Event Counter interrupt will take place when the
Timer/Event Counter request flag, T0F, is set, a situation
that will occur when the relevant Timer/Event Counter
overflows. When the interrupt is enabled, the stack is
not full and a Timer/Event Counter 0 overflow occurs, a
subroutine call to the timer interrupt vector at location
08H, will take place. When the interrupt is serviced, the
timer interrupt request flag, T0F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts.
Interrupt Priority
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests, the
following table shows the priority that is applied. These
can be masked by resetting the EMI bit.
Interrupt Source
HT48R01A
External Interrupt
1
Timer/Event Counter 0 Overflow
2
In cases where both external and internal interrupts are
enabled and where an external and internal interrupt occurs simultaneously, the external interrupt will always
have priority and will therefore be serviced first. Suitable
masking of the individual interrupts using the interrupt
registers can prevent simultaneous occurrences.
Programming Considerations
By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however,
once an interrupt request flag is set, it will remain in this
condition in the interrupt register until the corresponding
interrupt is serviced or until the request flag is cleared by
a software instruction.
External Interrupt
For an external interrupt to occur, the global interrupt enable bit, EEI, and external interrupt enable bit, EEI, must
first be set. An actual external interrupt will take place
when the external interrupt request flag, EIF, is set, a situation that will occur when an edge transition appears
on the external INT line. The type of transition that will
trigger an external interrupt, whether high to low, low to
high or both is determined by the INTES0 and INTES1
bits, which are bits 6 and 7 respectively, in the CTRL1
control register. These two bits can also disable the external interrupt function.
INTES1
INTES0
0
0
Disable
0
1
Rising Edge Trigger
1
0
Falling Edge Trigger
1
1
Dual Edge Trigger
Rev. 1.10
It is recommended that programs do not use the ²CALL
subroutine² instruction within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged
once a ²CALL subroutine² is executed in the interrupt
subroutine.
All of these interrupts have the capability of waking up
the processor when in the Power Down Mode.
Edge Trigger Type
Only the Program Counter is pushed onto the stack. If
the contents of the register or status register are altered
by the interrupt service program, which may corrupt the
desired control sequence, then the contents should be
saved in advance.
23
August 4, 2008
HT48R01A
Reset and Initialisation
inhibited. After the RES line reaches a certain voltage
value, the reset delay time tRSTD is invoked to provide
an extra delay time after which the microcontroller will
begin normal operation. The abbreviation SST in the
figures stands for System Start-up Timer.
A reset function is a fundamental part of any
microcontroller ensuring that the device can be set to
some predetermined condition irrespective of outside
parameters. The most important reset condition is after
power is first applied to the microcontroller. In this case,
internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready
to execute the first program instruction. After this
power-on reset, certain important internal registers will
be set to defined states before the program commences. One of these registers is the Program Counter,
which will be reset to zero forcing the microcontroller to
begin program execution from the lowest Program
Memory address.
V D D
0 .9 V
R E S
tR
S T D
S S T T im e - o u t
In te rn a l R e s e t
Power-On Reset Timing Chart
For most applications a resistor connected between
VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES
pin should be kept as short as possible to minimise
any stray noise interference.
In addition to the power-on reset, situations may arise
where it is necessary to forcefully apply a reset condition
when the microcontroller is running. One example of this
is where after power has been applied and the
microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain
unchanged allowing the microcontroller to proceed with
normal operation after the reset line is allowed to return
high. Another type of reset is when the Watchdog Timer
overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup.
V D D
1 0 0 k W
R E S
0 .1 m F
V S S
Basic Reset Circuit
For applications that operate within an environment
where more noise is present the Enhanced Reset Circuit shown is recommended.
Another reset exists in the form of a Low Voltage Reset,
LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage
falls below a certain threshold.
0 .0 1 m F
V D D
1 0 0 k W
R E S
Reset Functions
1 0 k W
There are five ways in which a microcontroller reset can
occur, through events occurring both internally and externally:
0 .1 m F
V S S
Enhanced Reset Circuit
· Power-on Reset
The most fundamental and unavoidable reset is the
one that occurs after power is first applied to the
microcontroller. As well as ensuring that the Program
Memory begins execution from the first memory address, a power-on reset also ensures that certain
other registers are preset to known conditions. All the
I/O port and port control registers will power up in a
high condition ensuring that all pins will be first set to
inputs.
Although the microcontroller has an internal RC reset
function, if the VDD power supply rise time is not fast
enough or does not stabilise quickly at power-on, the
internal reset function may be incapable of providing
proper reset operation. For this reason it is recommended that an external RC network is connected to
the RES pin, whose additional time delay will ensure
that the RES pin remains low for an extended period
to allow the power supply to stabilise. During this time
delay, normal operation of the microcontroller will be
Rev. 1.10
D D
More information regarding external reset circuits is
located in Application Note HA0075E on the Holtek
website.
· RES Pin Reset
This type of reset occurs when the microcontroller is
already running and the RES pin is forcefully pulled
low by external hardware such as an external switch.
In this case as in the case of other reset, the Program
Counter will reset to zero and program execution initiated from this point.
R E S
0 .4 V
0 .9 V
D D
D D
tR
S T D
S S T T im e - o u t
In te rn a l R e s e t
RES Reset Timing Chart
24
August 4, 2008
HT48R01A
· Low Voltage Reset - LVR
Reset Initial Conditions
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is selected via a configuration
option. If the supply voltage of the device drops to
within a range of 0.9V~VLVR such as might occur when
changing the battery, the LVR will automatically reset
the device internally. For a valid LVR signal, a low supply voltage, i.e., a voltage in the range between
0.9V~VLVR must exist for a time greater than that specified by tLVR in the A.C. characteristics. If the low supply voltage state does not exceed this value, the LVR
will ignore the low supply voltage and will not perform
a reset function. The actual VLVR value can be selected via configuration options.
The different types of reset described affect the reset
flags in different ways. These flags, known as PDF and
TO are located in the status register and are controlled
by various microcontroller operations, such as the
Power Down function or Watchdog Timer. The reset
flags are shown in the table:
TO PDF
L V R
tR
RESET Conditions
0
0
RES reset during power-on
u
u
RES or LVR reset during normal operation
1
u
WDT time-out reset during normal operation
1
1
WDT time-out reset during Power Down
Note: ²u² stands for unchanged
S T D
S S T T im e - o u t
The following table indicates the way in which the various components of the microcontroller are affected after
a power-on reset occurs.
In te rn a l R e s e t
Low Voltage Reset Timing Chart
Item
· Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except
that the Watchdog time-out flag TO will be set to ²1².
W D T T im e - o u t
tR
S T D
S S T T im e - o u t
In te rn a l R e s e t
Condition After RESET
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins
counting
Timer/Event
Counter
Timer Counter will be turned off
Prescaler
The Timer Counter Prescaler will
be cleared
Input/Output Ports I/O ports will be setup as inputs
WDT Time-out Reset during Normal Operation
Timing Chart
Stack Pointer
Stack Pointer will point to the top
of the stack
· Watchdog Time-out Reset during Power Down
The Watchdog time-out Reset during Power Down is
a little different from other kinds of reset. Most of the
conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to
²0² and the TO flag will be set to ²1². Refer to the A.C.
Characteristics for tSST details.
W D T T im e - o u t
tS
S T
S S T T im e - o u t
WDT Time-out Reset during Power Down
Timing Chart
Note:
The SST can be chosen to be either 1024 or 2
clock cycles via configuration option if the system clock source is not provided by an external
crystal.
Rev. 1.10
25
August 4, 2008
HT48R01A
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable
continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller
is in after a particular reset occurs. The following table describes how each type of reset affects each of the
microcontroller internal registers.
Reset
(Power-on)
RES or LVR
Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
MP0
1xxx xxxx
uuuu uuuu
1uuu uuuu
1uuu uuuu
MP1
1xxx xxxx
uuuu uuuu
1uuu uuuu
1uuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
WDTS
---- -111
---- -111
---- -111
---- -uuu
STATUS
--00 xxxx
--uu uuuu
--1u uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-uuu uuuu
Register
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
0000 1000
0000 1000
0000 1000
uuuu uuuu
PA
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAPU
-000 0000
-000 0000
-000 0000
-uuu uuuu
PAWK
0000 0000
0000 0000
0000 0000
uuuu uuuu
CTRL0
---- 0000
---- 0000
---- 0000
---- uuuu
CTRL1
10-- 1010
10-- 1010
10-- 1010
uu-- uuuu
Note:
²*² means ²warm reset²
²-² not implemented
²u² means ²unchanged²
²x² means ²unknown²
Rev. 1.10
26
August 4, 2008
HT48R01A
Oscillator
Various oscillator options offer the user a wide range of
functions according to their various application requirements. Four types of system clocks can be selected
while various clock source options for the Watchdog
Timer are provided for maximum flexibility. All oscillator
options are selected through the configuration options.
Crystal Frequency
The four methods of generating the system clock are:
Crystal Oscillator C1 and C2 Values
· External crystal/resonator oscillator
· External RC oscillator
C1
C2
CL
12MHz
TBD
TBD
TBD
8MHz
TBD
TBD
TBD
4MHz
TBD
TBD
TBD
1MHz
TBD
TBD
TBD
Note:
· Internal RC oscillator
· Combined Internal RC oscillator and Real Time Clock
One of these four methods must be selected using the
configuration options.
1. C1 and C2 values are for guidance only.
2. CL is the crystal manufacturer specified
load capacitor value.
Crystal Recommended Capacitor Values
More information regarding the oscillator is located in
Application Note HA0075E on the Holtek website.
Resonator C1 and C2 Values
Resonator Frequency
External Crystal/Resonator Oscillator
The simple connection of a crystal across OSC1 and
OSC2 will create the necessary phase shift and feedback for oscillation, and will normally not require external capacitors. However, for some crystals and most
resonator types, to ensure oscillation and accurate frequency generation, it may be necessary to add two
C1
C2
3.58MHz
TBD
TBD
1MHz
TBD
TBD
455kHz
TBD
TBD
Note:
C1 and C2 values are for guidance only.
Resonator Recommended Capacitor Values
External RC Oscillator
C 1
In te r n a l
O s c illa to r
C ir c u it
O S C 1
R f
R p
C a
C b
T o in te r n a l
c ir c u its
O S C 2
C 2
Using the external system RC oscillator requires that a
resistor, with a value between 24kW and 1.5MW, is connected between OSC1 and VDD, and a capacitor is connected to ground. Although this is a cost effective
oscillator configuration, the oscillation frequency can
vary with VDD, temperature and process variations and
is therefore not suitable for applications where timing is
critical or where accurate oscillator frequencies are required.For the value of the external resistor ROSC refer
to the Holtek website for typical RC Oscillator vs. Temperature and VDD characteristics graphics Here only
the OSC1 pin is used, which is shared with I/O pin PA6,
leaving pin PA5 free for use as a normal I/O pin. Note
that it is the only microcontroller internal circuitry together with the external resistor, that determine the frequency of the oscillator. The external capacitor shown
on the diagram does not influence the frequency of oscillation.
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d .
2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic
c a p a c ita n c e o f a r o u n d 7 p F .
Crystal/Resonator Oscillator
small value external capacitors, C1 and C2. The exact
values of C1 and C2 should be selected in consultation
with the crystal or resonator manufacturer¢s specification. The external parallel feedback resistor, Rp, is normally not required but in some cases may be needed to
assist with oscillation start up.
V
D D
Internal Ca, Cb, Rf Typical Values @ 5V, 25°C
Ca
Cb
Rf
11~13pF
13~15pF
270kW
R
O S C
O S C 1
4 7 0 p F
Oscillator Internal Component Values
P A 5
External RC Oscillator
Rev. 1.10
27
August 4, 2008
HT48R01A
Internal RC Oscillator
Internal Ca, Cb, Rf Typical Values @ 5V, 25°C
The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal
RC oscillator has three fixed frequencies of either
4MHz, 8MHz or 12MHz, the choice of which is indicated
by the suffix marking next to the part number of the device used. Note that if this internal system clock option is
selected, as it requires no external pins for its operation,
I/O pins PA5 and PA6 are free for use as normal I/O
pins. Refer to the Appendix section for more information
on the actual internal oscillator frequency vs. Temperature and VDD characteristics graphics.
P A 5
32768Hz
Note:
O S C 1
C a
O S C 2
1. C1 and C2 values are for guidance only.
2. CL is the crystal manufacturer specified
load capacitor value.
Normal
Running
T o in te r n a l
c ir c u its
Power
Down
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d .
2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic
c a p a c ita n c e o f a r o u n d 7 p F .
System
Clock
0
On
On
RC
Oscillator
1
Off
On
32768Hz
X
Off
On
Stopped
During power up there is a time delay associated with
the RTC oscillator waiting for it to start up. Bit 1 of the
CTRL0 register, known as the QOSC bit, is provided to
give a quick start-up function and can be used to minimize this delay. During a power up condition, this bit will
be cleared to 0 which will initiate the RTC oscillator quick
start-up function. However, as there is additional power
consumption associated with this quick start-up function, to reduce power consumption after start up takes
place, it is recommended that the application program
should set the QOSC bit high about 2 seconds after
power on. It should be noted that, no matter what condition the QOSC bit is set to, the RTC oscillator will always
function normally, only there is more power consumption associated with the quick start-up function.
Internal RC Oscillator + External RTC Oscillator
another clock, independent of the system clock, must be
provided. To do this a configuration option exists to allow
the Internal System RC Oscillator to be used in conjunction with a Real Time Clock - RTC oscillator. Here the
OSC1 and OSC2 pins, which are shared with I/O pins
PA6 and PA5, should be connected to a 32768Hz crystal
to implement this internal RTC oscillator. However, for
some crystals, to ensure oscillation and accurate frequency generation, it may be necessary to add two
small value external capacitors, C1 and C2. The exact
values of C1 and C2 should be selected in consultation
with the crystal or resonator manufacturer¢s specification. The external parallel feedback resistor, Rp, is normally not required but in some cases may be needed to
assist with oscillation start up.
Rev. 1.10
CL
TBD
Operating CLKMOD Internal
RTC
Mode
Bit
RC Osc.
In te r n a l
O s c illa to r
C ir c u it
In te rn a l R C
O s c illa to r
C b
C 2
C2
TBD
For applications using the RTC oscillator, the system
clock can be chosen to be either the Internal System RC
Oscillator or the RTC oscillator itself. This selection is
made using the CLKMOD bit in the CTRL0 register. If
this bit is set high then the 32768Hz external crystal will
also provide the system clock source. If the bit is low
then the system clock source will be the Internal RC Oscillator. When the system enters the Power Down Mode,
the system clock, irrespective of whether the CLKMOD
bit has selected the RTC or Internal RC Oscillator as its
source, will always stop running. The accompanying table shows the relationship between the CLKMOD bit
and the various oscillators.
When the microcontroller enters the Power Down Mode,
the system clock is switched off to stop microcontroller
activity and to conserve power. However, in many
microcontroller applications it may be necessary to keep
the internal timers operational even when the
microcontroller is in the Power Down Mode. To do this,
R f
C1
TBD
32768 Hz Crystal Recommended Capacitor Values
Internal RC Oscillator + External RTC Oscillator
R p
270kW
Crystal Frequency
Internal RC Oscillator
3 2 7 6 8 H z
Rf
RTC Oscillator C1 and C2 Values
N o te : P A 5 /P A 6 u s e d a s n o rm a l I/O s
C 1
Cb
13~15pF
RTC Oscillator Internal Component Values
In te rn a l R C
O s c illa to r
P A 6
Ca
11~13pF
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August 4, 2008
HT48R01A
Watchdog Timer Oscillator
device. All high-impedance input pins must be connected to either a fixed high or low level as any floating
input pins could create internal oscillations and result in
increased current consumption. Care must also be
taken with the loads, which are connected to I/O pins,
which are setup as outputs. These should be placed in a
condition in which minimum current is drawn or connected only to external circuits that do not draw current,
such as other CMOS inputs.
The WDT oscillator is a fully self-contained free running
on-chip RC oscillator with a typical period of 65ms at 5V
requiring no external components. When the device enters the Power Down Mode, the system clock will stop
running but the WDT oscillator continues to free-run and
to keep the watchdog active. However, to preserve
power in certain applications the WDT oscillator can be
disabled via a configuration option.
If the configuration options have enabled the Watchdog
Timer internal oscillator then this will continue to run
when in the Power Down Mode and will thus consume
some power. For power sensitive applications it may be
therefore preferable to use the system clock source for
the Watchdog Timer. The RTC, if configured for use, will
also consume a limited amount of power, as it continues
to run when the device enters the Power Down Mode. To
keep the RTC power consumption to a minimum level
the QOSC bit in the CTRL0 register, which controls the
quick start up function, should be set high.
Power Down Mode and Wake-up
Power Down Mode
All of the Holtek microcontrollers have the ability to enter
a Power Down Mode. When the device enters this
mode, the normal operating current, will be reduced to
an extremely low standby current level. This occurs because when the device enters the Power Down Mode,
the system oscillator is stopped which reduces the
power consumption to extremely low levels, however,
as the device maintains its present internal condition, it
can be woken up at a later stage and continue running,
without requiring a full reset. This feature is extremely
important in application areas where the MCU must
have its power supply constantly maintained to keep the
device in a known condition but where the power supply
capacity is limited such as in battery applications.
Wake-up
After the system enters the Power Down Mode, it can be
woken up from one of various sources listed as follows:
· An external reset
· An external falling edge on PA0 to PA7
· A system interrupt
Entering the Power Down Mode
· A WDT overflow
There is only one way for the device to enter the Power
Down Mode and that is to execute the ²HALT² instruction in the application program. When this instruction is
executed, the following will occur:
If the system is woken up by an external reset, the device will experience a full system reset, however, if the
device is woken up by a WDT overflow, a Watchdog
Timer reset will be initiated. Although both of these
wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog
Timer instructions and is set when executing the ²HALT²
instruction. The TO flag is set if a WDT time-out occurs,
and causes a wake-up that only resets the Program
Counter and Stack Pointer, the other flags remain in
their original status.
· The system oscillator will stop running and the appli-
cation program will stop at the ²HALT² instruction.
· If the RTC oscillator configuration option is enabled
then the RTC clock will keep running.
· The Data Memory contents and registers will maintain
their present condition.
· The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the WDT
or RTC oscillator. The WDT will stop if its clock source
originates from the system clock.
Pins PA0 to PA7 can be setup via the PAWUK register to
permit a negative transition on the pin to wake-up the
system. When a PA0 to PA7 pin wake-up occurs, the
program will resume execution at the instruction following the ²HALT² instruction.
· The I/O ports will maintain their present condition.
· In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related
interrupt is disabled or the interrupt is enabled but the
stack is full, in which case the program will resume execution at the instruction following the ²HALT² instruction.
In this situation, the interrupt which woke-up the device
will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or
when a stack level becomes free. The other situation is
Standby Current Considerations
As the main reason for entering the Power Down Mode
is to keep the current consumption of the MCU to as low
a value as possible, perhaps only in the order of several
micro-amps, there are other considerations which must
also be taken into account by the circuit designer if the
power consumption is to be minimised.
Special attention must be made to the I/O pins on the
Rev. 1.10
29
August 4, 2008
HT48R01A
where the related interrupt is enabled and the stack is
not full, in which case the regular interrupt response
takes place. If an interrupt request flag is set to ²1² before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled.
The Watchdog Timer will be disabled if bits
WDTEN3~WDTEN0 in the CTRL1 register are written
with the binary value 1010B and WDT configuration option is disable. This will be the condition when the device
is powered up. Although any other data written to
WDTEN3~WDTEN0 will ensure that the Watchdog
Timer is enabled, for maximum protection it is recommended that the value 0101B is written to these bits.
No matter what the source of the wake-up event is, once
a wake-up situation occurs, a time period equal to 1024
system clock periods will be required before normal system operation resumes. However, if the wake-up has
originated due to an interrupt, the actual interrupt subroutine execution will be delayed by an additional one or
more cycles. If the wake-up results in the execution of
the next instruction following the ²HALT² instruction, this
will be executed immediately after the 1024 system
clock period delay has ended.
The Watchdog Timer clock can emanate from three different sources, selected by configuration option. These
are its own fully integrated dedicated internal oscillator,
the RTC or fSYS/4. The Watchdog Timer dedicated internal clock source is an internal oscillator which has an
approximate period of 65ms at a supply voltage of 5V.
However, it should be noted that this specified internal
clock period can vary with VDD, temperature and process variations. The other Watchdog Timer clock source
options are the fSYS/4 clock and the RTC. It is important
to note that when the system enters the Power Down
Mode the instruction clock is stopped, therefore if the
configuration options have selected fSYS/4 as the
Watchdog Timer clock source, the Watchdog Timer will
cease to function. For systems that operate in noisy environments, using the internal Watchdog Timer internal
oscillator or the RTC as the clock source is therefore the
recommended choice. No matter which clock source is
selected, it is further divided by 256 via an internal 8-bit
counter and then by a 7-bit prescaler to give longer
time-out periods. The division ratio of the prescaler is
determined by bits 0, 1 and 2 of the WDTS register,
known as WS0, WS1 and WS2. If the Watchdog Timer
internal clock source is selected and with the WS0, WS1
and WS2 bits of the WDTS register all set high, the
prescaler division ratio will be 1:128, which will give a
maximum time-out period of about 2.1s.
Watchdog Timer
The Watchdog Timer, also known as the WDT, is provided to inhibit program malfunctions caused by the program jumping to unknown locations due to certain
uncontrollable external events such as electrical noise.
It operates by providing a device reset when the Watchdog Timer counter overflows. Note that if the Watchdog
Timer function is not enabled, then any instructions related to the Watchdog Timer will result in no operation.
Setting up the various Watchdog Timer options are controlled via the configuration options and two internal registers WDTS and CTRL1. Enabling the Watchdog Timer
can be controlled by both a configuration option and the
WDTEN bits in the CTRL1 internal register in the Data
Memory.
Configuration
Option
CTRL1
Register
WDT
Function
Disable
Disable
OFF
Enable
Disable
ON
Disable
Enable
ON
Enable
Enable
ON
Under normal program operation, a Watchdog Timer
time-out will initialise a device reset and set the status bit
TO. However, if the system is in the Power Down Mode,
when a Watchdog Timer time-out occurs, the device will
be woken up, the TO bit in the status register will be set
and only the Program Counter and Stack Pointer will be
Watchdog Timer On/Off Control
C L R
W D T 1 F la g
C L R
W D T 2 F la g
C le a r W D T T y p e
C o n fig u r a tio n O p tio n
1 o r 2 In s tr u c tio n s
fS
/4
3 2 k H z R T C
W D T O S C O u tp u t
Y S
C L R
C o n fig .
O p tio n
S e le c t
8 - b it C o u n te r
(¸ 2 5 6 )
W D T C lo c k S o u r c e
C L R
7 - b it P r e s c a le r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
Rev. 1.10
30
August 4, 2008
HT48R01A
while for the second option, both ²CLR WDT1² and
²CLR WDT2² must both be executed to successfully
clear the Watchdog Timer. Note that for this second option, if ²CLR WDT1² is used to clear the Watchdog
Timer, successive executions of this instruction will
have no effect, only the execution of a ²CLR WDT2² instruction will clear the Watchdog Timer. Similarly after
the ²CLR WDT2² instruction has been executed, only a
successive ²CLR WDT1² instruction can clear the
Watchdog Timer.
reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is an external
hardware reset, which means a low level on the external
reset pin, the second is using the Clear Watchdog Timer
software instructions and the third is when a HALT instruction is executed. There are two methods of using
software instructions to clear the Watchdog Timer, one
of which must be chosen by configuration option. The
first option is to use the single ²CLR WDT² instruction
while the second is to use the two commands ²CLR
WDT1² and ²CLR WDT2². For the first option, a simple
execution of ²CLR WDT² will clear the Watchdog Timer
b 7
IN T E S 1
IN T E S 0
b 0
W D T E N 3 W D T E N 2 W D T E N 1 W D T E N 0
1
1
0
1
0
X
X
b 7
0
1
0
X
C T R L 1 R e g is te r
W a tc h d o g T im e r F u n c tio n
D is a b le
X
E n a b le - r e c o m m e n d e d v a lu e
O th e r v a lu e s - a ll e n a b le
b 0
W S 2
W S 1
W S 0
W D T S R e g is te r
W D T p r e s c a le r r a te s e le c t
W S 2
W S 1
W S 0
W D T R
0
0
0
1 :1
0
0
1
1 :2
0
1
0
1 :4
0
1
1
1 :8
1 :1
1
0
0
1 :3
1
0
1
1 :6
1
1
0
1 :1
1
1
1
6
a te
2
4
2 8
N o t u s e d
Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the OTP Program Memory device during the programming process. During the development process, these options are selected using the HT-IDE
software development tools. As these options are programmed into the device using the hardware programming tools,
once they are selected they cannot be changed later by the application software. All options must be defined for proper
system function, the details of which are shown in the table.
No.
Options
1
Watchdog Timer: enable or disable
2
Watchdog Timer clock source: WDT internal oscillator, fSYS/4 or RTC
3
CLRWDT instructions: 1 or 2 instructions
4
System oscillator: Internal RC, Internal RC with external RTC, External Crystal, External RC
5
LVR function: enable or disable
6
LVR voltage: 2.1V, 3.15V or 4.2V
7
RES or PA7
8
SST: enable (1024 clocks) or disable (2 clocks)
Rev. 1.10
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August 4, 2008
HT48R01A
Application Circuits
V
D D
V D D
R e s e t
C ir c u it
1 0 0 k W
0 .1 m F
R E S /P A 7
P A 0 /B Z
P A 1 /B Z
P A 2 /T M R 0
0 .1 m F
P A 3 /IN T
V S S
O S C
C ir c u it
P A 4
O S C 1
O S C 2
S e e O s c illa to r
S e c tio n
Rev. 1.10
32
August 4, 2008
HT48R01A
Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
Central to the successful operation of any
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
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Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
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Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
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Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
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Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
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INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
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OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
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RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
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SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
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SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.10
43
August 4, 2008
HT48R01A
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.10
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August 4, 2008
HT48R01A
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.10
45
August 4, 2008
HT48R01A
Device Characteristic Graphics
The following characteristic graphics depicts typical device behavior. The data presented here is a statistical summary
of data gathered from different units. This is for information only and the figures were not tested during manufacturing.
In some of the graphs, the data exceeding the specified operating range are shown for information purposes only. The
device will operate properly only within the specified range.
Noramlized frequency is the ratio of actual frequency(F) to reference frequency(Fr) at VDD=5V, Ta=25°C
4MHZ IRC Frequency vs. VDD
1 .6 0
1 .5 0
-4 5 ° C
N o r m a liz e d F r e q u e n c y ( F / F r )
1 .4 0
1 .3 0
1 .2 0
1 .1 0
2 5 °C
1 .0 0
0 .9 0
0 .8 0
9 0 °C
0 .7 0
0 .6 0
2
2 .5
3
3 .5
4
V
D D
4 .5
5
5 .5
(V )
8MHZ IRC Frequency vs. VDD
1 .6 0
1 .5 0
-4 5 °C
N o r m a liz e d F r e q u e n c y ( F / F r )
1 .4 0
1 .3 0
1 .2 0
1 .1 0
2 5 °C
1 .0 0
0 .9 0
0 .8 0
9 0 °C
0 .7 0
0 .6 0
2
2 .5
3
3 .5
4
V
Rev. 1.10
46
D D
4 .5
5
5 .5
(V )
August 4, 2008
HT48R01A
12MHZ IRC Frequency vs. VDD
1 .6 0
1 .5 0
-4 5 °C
N o r m a liz e d F r e q u e n c y ( F / F r )
1 .4 0
1 .3 0
1 .2 0
1 .1 0
2 5 °C
1 .0 0
0 .9 0
0 .8 0
9 0 °C
0 .7 0
0 .6 0
2
2 .5
3
3 .5
4
V
Rev. 1.10
47
D D
4 .5
5
5 .5
(V )
August 4, 2008
HT48R01A
Package Information
10-pin MSOP Outline Dimensions
1 0
6
E 1
1
5
E
D
L
A 2
A
e
R
0 .1 0
B
C
q
A 1
L 1
(4 C O R N E R S )
Symbol
Rev. 1.10
Dimensions in mm
Min.
Nom.
Max.
A
¾
¾
1.1
A1
0
¾
0.15
A2
0.75
¾
0.95
B
0.17
¾
0.27
C
¾
¾
0.25
D
¾
3
¾
E
¾
4.9
¾
E1
¾
3
¾
e
¾
0.5
¾
L
0.4
¾
0.8
L1
¾
0.95
¾
q
0°
¾
8°
48
August 4, 2008
HT48R01A
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Copyright Ó 2008 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
49
August 4, 2008
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