MP2918 4V to 40V Input, Current Mode, Synchronous, Step-Down Controller DESCRIPTION FEATURES The MP2918 is a high-voltage, synchronous, step-down, switching controller that can directly step down voltages from up to 40V. The MP2918 uses PWM current control architecture with accurate cycle-by-cycle current limit and is capable of driving dual N-channel MOSFET switches. Advanced Asynchronous Mode (AAM) enables non-synchronous operation to optimize lightload efficiency. The operating frequency of the MP2918 can be programmed by an external resistor or synchronized to an external clock for noisesensitive applications. Full protection features include precision output over-voltage protection (OVP), output over-current protection (OCP), and thermal shutdown. The MP2918 is available in TSSOP20-EP and QFN-20 (3mmx4mm) packages. APPLICATIONS Automotive Industrial Control Systems Wide 4V to 40V Operating Input Range Dual N-Channel MOSFET Driver 0.8V Voltage Reference with ±1.5% Accuracy Over Temperature Low Dropout Operation: Maximum Duty Cycle at 99.5% Programmable Frequency Range: 100kHz 1000kHz External Sync Clock Range: 100kHz1000kHz 180°Out-of-Phase SYNCO Pin Programmable Soft Start (SS) Power Good (PG) Output Voltage Monitor Selectable Cycle-by-Cycle Current Limit Output Over-Voltage Protection (OVP) Hiccup Over-Current Protection (OCP) Internal LDO with External Power Supply Option Programmable Forced CCM and AAM Available TSSOP20-EP and QFN-20 (3mmx4mm) Packages All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION 4-40V VIN VCC1 BST IN VCC1 FREQ TG VCC1 SW VOUT PG VCC2 SGND MP2918 EN/SYNC BG SENSE+ SENSE- ILIM CCM/AAM PGND COMP MP2918 Rev. 1.02 5/31/2017 FB SYNCO SS www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 1 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER ORDERING INFORMATION Part Number* Package Top Marking MP2918GF** MP2918GL** TSSOP20-EP QFN-20 (3mm x 4mm) See Below See Below *For Tape & Reel, add suffix –Z (e.g. MP2918GF–Z) ** Under qualification TOP MARKING (TSSOP20-EP) MPS: MPS prefix YY: Year code WW: Week code MP2918: Part number LLLLLLLLL: Lot number TOP MARKING (QFN-20 (3mm x 4mm)) MP: MPS prefix: Y: year code; W: week code: 2918: first four digits of the part number; LLL: lot number; MP2918 Rev. 1.02 5/31/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 2 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER PACKAGE REFERENCE VCC2 3 18 SW VCC1 4 17 BG SGND 5 16 PGND VCC2 1 16 SW VCC1 2 15 SGND 3 MP2918 COMP 7 14 SENSE- FB 8 13 SYNCO CCM/AAM 9 12 ILIM FREQ 10 11 PG TSSOP-20 EP ABSOLUTE MAXIMUM RATINGS (1) Input supply voltage (VIN) ............................. 65V BST supply voltage (VBST) ................. VIN + 6.5V SW .................................................. -0.3V to 65V EN/SYNC ..................................................... 55V BST - SW .................................................... 6.5V Supply voltage (VCC1) ............................... 6.5V External supply voltage (VCC2) ................... 15V SENSE +/- ................................................... 28V Differential sense (SENSE+ to SENSE-) ............ .....................................................-0.7V to +0.7V TG ............................... VSW - 0.3V to VBST + 0.3V BG ................................... -0.3V to VCC1 + 0.3V All other pins ................................-0.3V to +6.5V (2) Continuous power dissipation (TA = +25°C) TSSOP-20 EP ............................................ 3.1W QFN-20 (3mmx4mm) ................................. 2.6W Junction temperature ................................150C Lead temperature .....................................260C Storage temperature ................ -65C to +175C MP2918 Rev. 1.02 5/31/2017 SS 4 13 SENSE+ COMP 5 12 SENSE- FB 6 11 SYNCO ILIM SENSE+ PG 15 FREQ 6 BG 14 PGND MP2918 CCM/AAM SS 17 TG TG 10 19 BST 2 18 EN/SYNC 9 BST IN 20 8 1 7 IN 19 TOP VIEW 20 EN/SYNC TOP VIEW QFN-20 (3mmx4mm) Recommended Operating Conditions (3) Supply voltage (VIN)… ........................ 4V to 40V Output voltage (VOUT) ................................. ≤25V Supply voltage for VCC2… .............. 4.7V to 12V Operating junction temp. (TJ)….-40°C to +125°C Thermal Resistance (4) θJA θJC TSSOP-20 EP ........................ 40 ....... 8.... C/W QFN-20 (3mmx4mm) .............. 48 ...... 10... C/W NOTES: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) Measured on JESD51-7, 4-layer PCB. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 3 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER ELECTRICAL CHARACTERISTICS VIN = 24V, TJ = -40°C to +125°C(4), EN/SYNC = 2V, VILIMIT = 75mV, unless otherwise noted. Parameters Symbol Input Supply VIN UVLO threshold (rising) VIN UVLO threshold (falling) VIN UVLO hysteresis VIN supply current with VCC2 bias VIN supply current without VCC2 bias Condition Min Typ Max Units 4 3.2 4.5 3.7 800 5 3.95 V V mV 25 40 μA 750 1000 μA 250 350 μA 0.5 5 μA 5 5.5 V Load = 0 to 50mA, VCC2 floating or connected to SGND 1 3 % VCC2 > 6V 5 INUV_RISING INUV_FALLING INUV_HYS IQ_VCC2 IQ VIN AAM current IQ_AAM VIN shutdown current VCC Regulator VCC1 regulator output voltage from VIN VCC1 regulator load regulation from VIN ISHDN VCC1_VIN VCC1 regulator output voltage from VCC2 VCC1_VCC2 VCC2 = 12V, external bias, VAAM = 5V, VFB = 0.84V, SENSE+ = SENSE- = 0V, no switching VCC2 = 0V, VFB = 0.84V, VAAM = 5V, SENSE+ = SENSE= 0V, no switching VCC2 = 0V, VAAM = 0.6V, VFB = 0.84V, SENSE+ = SENSE- = 12V, no switching VEN = 0V VIN > 6V, load = 0 to 50mA VCC1 regulator load Load = 0 to 50mA, VCC2 = 12V regulation from VCC2 VCC2 UVLO threshold (rising) VCC2_RISING VCC2 UVLO threshold (falling) VCC2_FALLING VCC2 threshold hysteresis VCC2_HYS VAAM = 5V, VFB = 0.84V, SENSE+ = SENSE- = 12V, VCC2 = 12V, no switching VCC2 supply current IVCC2 VAAM = 0.6V, VFB = 0.84V, SENSE+ = SENSE- =12V, VCC2 = 12V, no switching Feedback (FB) Feedback voltage VFB 4V VIN 40V Feedback current IFB VFB = 0.8V Enable (EN/SYNC) Enable threshold (rising) VEN_RISING Enable threshold (falling) VEN_FALLING Enable threshold hysteresis VEN_TH Enable input current IEN VEN/SYNC = 2V Enable turn-off delay tOFF MP2918 Rev. 1.02 5/31/2017 4.5 V 1 3 % 4.7 4.45 250 4.92 4.75 V V mV 800 1100 μA 200 300 μA 0.788 0.800 10 0.812 V nA 1.16 1.03 1.22 1.09 130 2 20 1.28 1.15 V V mV μA μs 4.3 4.05 10 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 5 40 4 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER ELECTRICAL CHARACTERISTICS (continued) VIN = 24V, TJ = -40°C to +125°C(4), EN/SYNC = 2V, VILIMIT = 75mV, unless otherwise noted. Parameters Symbol Condition Min Typ Max Units RFREQ = 45.3kΩ 340 430 520 kHz Oscillator and Sync Operating frequency Foldback operating frequency Maximum programmable frequency Minimum programmable frequency EN/SYNC frequency range EN/SYNC voltage rising threshold EN/SYNC voltage falling threshold Current Sense Current sense common mode voltage range FSW FSW_FOLDBACK VFB = 0.1V FSWH FSYNC 100 VSYNC_RISING 2 VSENSE+/- Reverse current limit sense voltage VREV_ILIMIT Valley current limit VVAL_ILIMIT Soft Start (SS) Soft-start source current Error Amplifier (EA) Error amp transconductance (5) Error amp open loop DC gain (5) Error amp sink/source current Protection Over-voltage threshold Over-voltage hysteresis Thermal shutdown (5) Thermal shutdown hysteresis (5) MP2918 Rev. 1.02 5/31/2017 kHz ISENSE 0 ILIM = SGND, VSENSE+ = 3.3V ILIM = VCC1, VSENSE+ = 3.3V ILIM = float, VSENSE+ = 3.3V ILIM = SGND, VSENSE+ = 3.3V ILIM = VCC1, VSENSE+ = 3.3V ILIM = float, VSENSE+ = 3.3V ILIM = SGND, VSENSE+ = 3.3V ILIM = VCC1, VSENSE+ = 3.3V ILIM = float, VSENSE+ = 3.3V VSENSE+/-(CM) = 0V VSENSE+/-(CM) = 3.3V VSENSE+/-(CM) > 5V ISS SS = 0.5V Gm AO IEA ∆V = 5mV VOV VOV_HYS 15 40 65 100 kHz 1000 kHz V VSYNC_FALLING VILIMIT FSW 1000 FSWL Current limit sense voltage Input current of sensor 50% 0.35 V 25 V 35 60 85 mV mV mV -70 80 105 25 50 75 8 17 24 22.5 47.5 72.5 -45 115 150 -20 160 205 μA μA μA 2 4 6 μA mV mV μS dB μA 500 70 ±30 FB = 0.7/0.9V 110% 115% 10% 170 20 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 120% VFB VFB °C °C 5 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER ELECTRICAL CHARACTERISTICS (continued) VIN = 24V, TJ = -40°C to +125°C(4), EN/SYNC = 2V, VILIMIT = 75mV, unless otherwise noted. Parameters Symbol Gate Driver TG pull-up resistor TG pull-down resistor BG pull-up resistor BG pull-down resistor Dead time TG maximum duty cycle TG minimum on time (5) BG minimum on time Power Good (PG) Power good low RTG_PULLUP RTG_PULLDN RBG_PULLUP RBG_PULLDN tdead Dmax tON_MIN_TG tON_MIN_BG VPG_Low PG rising threshold PGVth_RSING PG falling threshold PGVth_FALLING PG threshold hysteresis Power good leakage Power good delay AAM/CCM AAM output current CCM required AAM threshold voltage PGVth_HYS IPG_LK tPG_delay IAAM Condition CLoad = 3.3nF VFB = 0.7V Iload = 4mA VOUT rising VOUT falling VOUT falling VOUT rising Min 98 85% 101% 81% 105% PG = 5V Rising Falling 2 1 3 1 60 99.5 92 175 0.1 90% 107% 87% 110% 3% Max Units 250 Ω Ω Ω Ω ns % ns ns 0.3 96.5% 112.5% 92.5% 116.5% 2 RFREQ = 45.3kΩ VCCM_TH Typ V VFB VFB VFB μA 37 28 μs 13.2 μA 2.3 V NOTES: 4) Not tested in production, guaranteed by over-temperature correlation 5) Not tested in production, guaranteed by design and characterization. MP2918 Rev. 1.02 5/31/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 6 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER TYPICAL CHARACTERISTICS VIN = 24V, TJ = -40°C to +125°C, unless otherwise noted. MP2918 Rev. 1.02 5/31/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 7 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER TYPICAL CHARACTERISTICS (continued) VIN = 24V, TJ = -40°C to +125°C, unless otherwise noted. MP2918 Rev. 1.02 5/31/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 8 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER TYPICAL CHARACTERISTICS (continued) VIN = 24V, TJ = -40°C to +125°C, unless otherwise noted. MP2918 Rev. 1.02 5/31/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 9 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER TYPICAL PERFORMANCE CHARACTERISTICS VIN = 24V, VOUT = 5V, L = 4.7µH, AAM, FSW = 500kHz, TA = +25°C, unless otherwise noted. MP2918 Rev. 1.02 5/31/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 10 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 24V, VOUT = 5V, L = 4.7µH, AAM, FSW = 500kHz, TA = +25°C, unless otherwise noted. MP2918 Rev. 1.02 5/31/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 11 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 24V, VOUT = 5V, L = 4.7µH, AAM, FSW = 500kHz, TA = +25°C, unless otherwise noted. MP2918 Rev. 1.02 5/31/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 12 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER TYPICAL PERFORMANCE CHARACTERISTICS (continued) VIN = 24V, VOUT = 5V, L = 4.7µH, AAM, FSW = 500kHz, TA = +25°C, unless otherwise noted. MP2918 Rev. 1.02 5/31/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 13 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER PIN FUNCTIONS TSSOP-20 Pin # QFN-20 Pin # 1 19 2 20 3 1 4 2 5 3 6 4 7 5 8 6 9 7 10 8 11 9 12 10 13 11 14 12 15 13 16 14 MP2918 Rev. 1.02 5/31/2017 Name Description Input supply. The MP2918 operates on a 4V to 40V input range. A ceramic capacitor is needed to prevent large voltage spikes at the input. Enable input. The EN/SYNC threshold is 1.22V with 130mV of hysteresis. EN/SYNC is used to implement an input under-voltage lockout EN/SYNC (UVLO) function externally. If an external sync clock is applied to EN/SYNC, the internal clock follows the sync frequency. External power supply for the internal VCC1 regulator. VCC2 disables the power from VIN for as long as VCC2 is higher than 4.7V. Do not VCC2 connect a power supply greater than 12V to VCC2. Connect VCC2 to an external power supply to reduce power dissipation and increase efficiency. Internal bias supply. A ≥1µF decoupling capacitor is required between VCC1 VCC1 and PGND. Low-noise ground reference. SGND should be connected to the VOUT SGND side of the output capacitors. Soft-start control input. SS is used to program the soft-start period with SS an external capacitor between SS and SGND. Regulation control loop compensation. Connect an R-C network from COMP COMP to SGND to compensate for the regulation control loop. Feedback. FB is the input of the error amplifier. An external resistive FB divider connected between the output and SGND is compared to the internal +0.8V reference to set the regulation voltage. Continuous conduction mode/advanced asynchronous mode. Floating CCM/AAM or connecting CCM/AAM to VCC1 makes the part CCM/AAM operate in CCM. Connecting an appropriate external resistor from CCM/AAM to SGND (so AAM is at a low level) makes the part operate in AAM. The AAM voltage should be no less than 480mV. Frequency. Connect a resistor between FREQ and SGND to set the FREQ switching frequency. PG Power good output. The output of PG is an open drain. Sense voltage limit set. The voltage at ILIM sets the nominal sense ILIM voltage at the maximum output current. There are three fixed options: float, VCC1, and SGND. Frequency synchronous out. SYNCO outputs a 180°out-of-phase clock SYNCO when the part works in CCM for dual-channel operation. Negative input for the current sense. The sensed inductor current limit SENSEthreshold is determined by the status of ILIM. Positive input for the current sense. The sensed inductor current limit SENSE+ threshold is determined by the status of ILIM. High-current ground reference for the internal low-side switch driver PGND and the VCC1 regulator circuit. Connect PGND to the negative terminal of the VCC1 decoupling capacitor directly. IN www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 14 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER PIN FUNCTIONS (continued) TSSOP-20 Pin # QFN-20 Pin # Name 17 15 BG 18 16 SW 19 17 TG 20 18 BST Exposed pad MP2918 Rev. 1.02 5/31/2017 Description Bottom gate driver output. Connect BG to the gate of the synchronous N-channel MOSFET. Switch node. SW is the reference for the VBST supply and high-current returns for the bootstrapped switch. Top gate drive. TG drives the gate of the top N-channel synchronous MOSFET. The TG driver draws power from the BST capacitor and returns to SW, providing a true floating drive to the top N-channel MOSFET. Bootstrap. BST is the positive power supply for the internal, floating, highside MOSFET driver. Connect a bypass capacitor between BST and SW. A diode from VCC1 to BST charges the BST capacitor when the low-side switch is off. Exposed pad. The exposed pad is on the bottom side of the device. It is not connected to SGND or PGND electrically. Connect the exposed pad to SGND and PGND during PCB layout for better thermal performance. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 15 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER BLOCK DIAGRAM SYNCO ILIM IN 4.7V VCC Regulator VCC2 VCC1 VCC1 BST FREQ Oscillator HS Driver VCC1 Current Limit Comparator EN/SYNC Reference Control Vref Error Amplifier LS Driver TG SW BG SS SS PGND FB 12X PG V PG Current Sense Amplifer SENSE+ SENSE- SGND COMP CCM/AAM Figure 1: Functional Block Diagram MP2918 Rev. 1.02 5/31/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 16 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER TIME SEQUENCE VIN 0 SW 0 EN Threshold EN 0 VCC1 Threshold VCC1 110% REF 0 107% REF 105% REF 90%REF 62.5% REF VO 0 15µs 115% REF 90% REF SS IL=ILi mit IL=ILi mit IL= Valley current limit IL 0 IL = Reverse current limit 37µs PG 28µ s 37µ s 28µs Start-Up N o r m al OCP N o r m al 28µs 37µ s 0 OV N or mal Shutdown OC Release Figure 2: Time Sequence MP2918 Rev. 1.02 5/31/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 17 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER OPERATION The MP2918 is a high-performance, step-down, synchronous, DC/DC controller IC with a wide input voltage range. It implements current-mode control and programmable switching frequency control architecture to regulate the output voltage with external N-channel MOSFETs. The MP2918 senses the voltage at FB. The difference between the FB voltage (VFB) and an internal 0.8V reference (VREF) is amplified to generate an error voltage on COMP. This is used as the threshold for the current-sense comparator with a slope compensation ramp. Under normal-load conditions, the controller operates in full pulse-width modulation (PWM) mode (see Figure 3). At the beginning of each oscillator cycle, the top gate driver is enabled. The top gate turns on for a period determined by the duty cycle. When the top gate turns off, the bottom gate turns on after a dead time and remains on until the next clock cycle begins. There is an optional power-save mode for lightload or no-load condition. Advanced Asynchronous Mode (AAM) The MP2918 employs advanced asynchronous mode (AAM) functionality to optimize efficiency during light-load or no-load condition (see Figure 3). AAM is enabled when CCM/AAM is at a low level by connecting an appropriate resistor to SGND to ensure that the AAM voltage (VAAM) is no less than 480mV. See Equation (1): VAAM (mV) = IAAM (μA) x RAAM (kΩ) (1) Where IAAM is the CCM/AAM output current. AAM is disabled when CCM/AAM is floating or connected to VCC1. Calculate the CCM/AAM output current (IAAM) with Equation (2): IAAM (μA) = 600 (mV) / RFREQ (kΩ) (2) If AAM is enabled, the MP2918 first enters nonsynchronous operation for as long as the inductor current approaches zero at light load. If the load decreases further to make the COMP voltage (VCOMP) drop below the CCM/AAM voltage (VAAM), the MP2918 enters AAM. In AAM, the internal clock resets whenever VCOMP crosses over VAAM. The crossover time is taken MP2918 Rev. 1.02 5/31/2017 as the benchmark for the next clock cycle. When the load increases and the DC value of VCOMP is higher than VAAM, the operation mode is discontinuous conduction mode (DCM) or continuous conduction mode (CCM), which have a constant switching frequency. Inductor Current Inductor Current Forced CCM AAM t t Load Load Decreased tDecreased t t t Figure 3: Forced CCM and AAM Floating Driver and Bootstrap Charging The floating top gate driver is powered by an external bootstrap capacitor (CBST), which is refreshed when the high-side MOSFET (HSFET) turns off, typically. This floating driver has its own under-voltage lockout (UVLO) protection. This UVLO’s rising threshold is 3.05V with a hysteresis of 170mV. If the BST voltage is lower than the bootstrap UVLO, the MP2918 enters constant-off-time mode to ensure that the BST capacitor is high enough to drive the HS-FET. VCC1 Regulator and VCC2 Power Supply Both the top and bottom MOSFET drivers and most of the internal circuitries are powered by the VCC1 regulator. An internal, low dropout, linear regulator supplies VCC1 power from VIN. Connect a ≥1μF ceramic capacitor from VCC1 to PGND. If VCC2 is left open or connected to a voltage less than 4.7V, an internal 5V regulator supplies power to VCC1 from VIN. If VCC2 is greater than 4.7V, the internal regulator that supplies power to VCC1 from VCC2 is triggered. If VCC2 is between 4.7V and 5V, the 5V regulator is in dropout, and VCC1 approximately equals VCC2. Using the VCC2 power supply allows the VCC1 power to be derived from a highefficiency external source, such as one of the MP2918’s switching regulator outputs. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 18 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER Error Amplifier (EA) The error amplifier (EA) compares VFB with the internal 0.8V reference and outputs a current proportional to the difference between the two input voltages. This output current is used to charge or discharge the external compensation network to form VCOMP, which is used to control the power MOSFET current. Adjusting the compensation network from COMP to SGND optimizes the control loop for good stability or fast transient response. Current Limit Function The MP2918 has three fixed current limit options: 25mV, when ILIM is connected to SGND; 50mV, when ILIM is connected to VCC1; and 75mV, when ILIM is floating. When the peak value of the inductor current exceeds the set current-limit threshold, the output voltage begins dropping until FB is 37.5% below the reference. The MP2918 enters hiccup mode to restart the part periodically. The frequency is lowered when FB is below 0.4V. This protection mode is especially useful when the output is dead-shorted to ground. The average short-circuit current is reduced greatly to alleviate thermal issues. The MP2918 exits hiccup mode once the over-current condition is removed. Low Dropout Operation In low dropout mode, the MP2918 is designed to operate in high-side fully on mode for as long as the voltage difference across BST - SW is greater than 3.05V, improving dropout. When the voltage from BST to SW drops below 3.05V, a UVLO circuit turns off the HS-FET. At the same time, the low-side MOSFET (LS-FET) turns on to refresh the charge on the BST capacitor. After the BST capacitor voltage is recharged, the HS-FET turns on again to regulate the output. Since the supply current sourced from the BST capacitor is low, the HS-FET can remain on for more switching cycles than are required to refresh the BST capacitor, increasing the effective duty cycle of the switching regulator. Low dropout operation makes the MP2918 suitable for automotive cold-crank applications. MP2918 Rev. 1.02 5/31/2017 Power Good (PG) Function The MP2918 includes an open-drain power good (PG) output that indicates whether the regulator’s output is within ±10% of its nominal value. When the output voltage falls outside of this range, the PG output is pulled low. PG should be connected to a voltage source no more than 5V through a resistor (e.g.: 100kΩ). The PG rising delay time is 37µs, and the PG falling delay time is 28µs. Soft Start (SS) Soft start (SS) is implemented to prevent the converter output voltage from overshooting during start-up. When the chip starts up, the internal circuitry generates a soft-start voltage that ramps up from 0V to 1.2V. When it is lower than REF, SS overrides REF, so the error amplifier uses SS as the reference. When SS is higher than REF, REF regains control. An external capacitor connected from SS to SGND is charged from an internal 4μA current source, producing a ramped voltage. The softstart time (tSS) is set by the external SS capacitor and can be calculated by Equation (3): t SS ms C SS nF VREF V ISS μA (3) Where CSS is the external SS capacitor, VREF is the internal reference voltage (0.8V), and ISS is the 4μA SS charge current. There is no internal SS capacitor. SS is reset when a fault protection other than over-voltage protection (OVP) occurs. Output Over-Voltage Protection (OVP) The output over-voltage is monitored by VFB. If VFB is typically 15% higher than the reference, the MP2918 enters discharge mode. The HSFET turns off, and the LS-FET turns on. The LS-FET remains on until the reverse current limit is triggered. The LS-FET then turns off, and the inductor current increases to 0. The LSFET is turned on again after ZCD is triggered. The MP2918 works in discharge mode until the over-voltage condition is cleared. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 19 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER EN/SYNC Control The MP2918 has a dedicated enable (EN/SYNC) control that uses a bandgapgenerated precision threshold of 1.22V. By pulling EN/SYNC high or low, the IC can be enabled or disabled. To disable the part, EN/SYNC must be pulled low for at least 40µs. Tie EN/SYNC to VIN through a resistor divider (R16 and R17) to program the VIN start-up threshold (see Figure 4). The EN/SYNC threshold is 1.09V (falling edge), so the VIN UVLO threshold is 1.09V x (1 + R16/R17). Otherwise, if VIN ≤ 52V, EN/SYNC can be connected to VIN directly. If VIN ≥ 52V, a ≥50kΩ pull-up resistor is needed to prevent EN/SYNC from breaking down. VIN R16 EN/ SYNC R17 Figure 4: EN/SYNC Resistor Divider Synchronize The MP2918 can be synchronized to an external clock ranging from 100kHz up to 1000kHz through EN/SYNC. The internal clock rising edge is synchronized to the external clock rising edge. The pulse width (both on and off) of the external clock signal should be no less than 100ns. Thermal Protection Thermal protection prevents damage to the IC from excessive temperatures. The die temperature is monitored internally until the thermal limit is reached. When the silicon die temperature is higher than 170°C, the entire chip shuts down. When the temperature is lower than its lower threshold (typically 20°C), the chip is enabled again. Start-Up and Shutdown If both VIN and EN/SYNC are higher than their respective thresholds, the chip starts up. The reference block starts first, generating stable reference voltages and currents. The internal regulator is then enabled. The regulator provides a stable supply for the remaining circuitries. Three events can shut down the chip: EN/SYNC low, VIN low, and thermal shutdown. During the shutdown procedure, the signal path is blocked first to avoid any fault triggering. VCOMP and the internal supply rail are then pulled down. The floating driver is not subject to this shutdown command. Pre-Bias Start-Up If SS is less than FB at start-up, the output has a pre-bias voltage, and neither TG nor BG is turned on until SS is greater than FB. Under-Voltage Lockout (UVLO) Under-voltage lockout (UVLO) is implemented to protect the chip from operating at an insufficient input supply voltage. The MP2918 UVLO rising threshold is about 4.5V, while its falling threshold is a consistent 3.7V. MP2918 Rev. 1.02 5/31/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 20 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER APPLICATION INFORMATION Setting the Output Voltage The external resistor divider is used to set the output voltage (see Figure 5). VOUT R8 FB R9 Figure 5: External Resistor Divider If R8 is known, then R9 can be calculated with Equation (4): R9 R8 (4) VOUT 1 0.8V recommended value for RSENSE is between 7mΩ and 50mΩ. Programmable Switching Frequency Consider different variables when choosing the switching frequency. A high frequency increases switching losses and gate charge losses, while a low frequency requires more inductance and capacitance, resulting in larger real estate and higher cost. Setting the switching frequency is a trade-off between power loss and passive component size. In noise-sensitive applications, the switching frequency should be out of a sensitive frequency band. The MP2918’s frequency can be programmed from 100kHz to 1000kHz with a resistor from FREQ to SGND (see Table 2). The value of RFREQ for a given operating frequency can be calculated with Equation (6): Table 1 lists the recommended feedback resistor values for common output voltages. Table 1: Resistor Selection for Common Output Voltages RFREQ (k) 20000 1 fs (kHz) Table 2: Frequency vs. Resistor VOUT (V) R8 (kΩ) R9 (kΩ) Resistor (kΩ) Frequency (kHz) 3.3 5 12 37.4 (1%) 63.4 (1%) 169 (1%) 12 (1%) 12 (1%) 12 (1%) 65 45.3 39 19 300 430 500 1000 Setting Current Sensing The MP2918 has three fixed current limit options: 25mV, when ILIM is connected to SGND; 50mV, when ILIM is connected to VCC1; and 75mV, when ILIM is floating. Ensure that the application can deliver a full load of current over the full operating temperature range when setting ILIM. (6) VCC Regulator Connection VCC1 can be powered from both VIN and VCC2. If connecting VCC2 to an external power supply to improve the overall efficiency, VCC2 should be larger than 4.7V but smaller than 12V (see Figure 6). VIN The current sense resistor (RSENSE) monitors the inductor current. Its value is chosen based on the current limit threshold. The relationship between the peak inductor current (Ipk) and RSENSE can be calculated with Equation (5): V R SENSE ILIMIT Ipk IN VCC1 VCC2 LDO C Vcc MP2918 INTERNAL Ext . Power Supply (5) A higher RSENSE value increases the power loss across it. Considering the output current, efficiency, and ILIM threshold, the MP2918 Rev. 1.02 5/31/2017 C IN 4.5V Figure 6: Internal Circuitry of VCC2 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 21 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER If VOUT is higher than 4.7V but less than 12V, VCC2 can be connected to VOUT directly (see Figure 7). current capability. The RMS value of the ripple current flowing through the input capacitor can be calculated with Equation (9): VIN IL Rsense C IN IRMS =ILOAD VOUT CO IN VCC1 C Vcc IRMS = ILOAD/2 (10) The input capacitor must be capable of handling this ripple current. 4.5V Figure 7: Configuration of VCC2 Connecting to VOUT Selecting the Inductor An inductor with a DC current rating at least 25% higher than the maximum load current is recommended for most applications. A largervalue inductor results in less ripple current and a lower output ripple voltage. However, the larger-value inductor also has a larger physical size, higher series resistance, and lower saturation current. Choose the inductor ripple current to be approximately 30% of the maximum load current. The inductance value can then be calculated with Equation (7): L (9) The worst-case condition occurs at VIN = 2VOUT, shown in Equation (10): VCC2 LDO MP2918 INTERNAL VOUT V (1- OUT ) VIN VIN VOUT (VIN - VOUT ) VIN ΔIL fS (7) Output Capacitor Selection The output capacitor impedance should be low at the switching frequency. The output voltage ripple can be estimated with Equation (11): ΔVOUT (11) VOUT VOUT 1 1 RESR fS L VIN 8 fS CO Where CO is the output capacitance value, and RESR is the equivalent series resistance (ESR) value of the output capacitor. For tantalum or electrolytic capacitor applications, the ESR dominates the impedance at the switching frequency. The output voltage ripple can be approximated with Equation (12): ΔVOUT VOUT VOUT 1 RESR fS L VIN (12) Where VOUT is the output voltage, VIN is the input voltage, fS is the 300kHz switching frequency, and ∆IL is the peak-to-peak inductor ripple current. Power MOSFET Selection Two N-channel MOSFETs must be selected for the controller: one for the high-side switch, and one for the low-side switch. The maximum inductor peak current can be calculated with Equation (8): The driver level of the HS-FET and LS-FET is 5V, so the threshold voltage (Vth) of the selected MOSFETs must be no higher than this value. IL(MAX) =ILOAD + ΔIL 2 (8) Where ILOAD is the load current. Selecting the Input Capacitor Since the input capacitor absorbs the input switching current, it requires an adequate ripple current rating. The selection of the input capacitor is based mainly on its maximum ripple MP2918 Rev. 1.02 5/31/2017 The input voltage (VDS), continuous drain current (ID), on resistance (RDS(ON)), total gate charge (Qg), and thermal-related parameters should be considered when choosing the power MOSFETs. VDS of the chosen MOSFETs should exceed the maximum applied voltage between the drain www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 22 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER and source in the application, which is VIN(MAX) plus additional rings on the switch node. The MOSFET’s power dissipations can be calculated with Equation (13) and Equation (14): VCC1 RBST External BST diode IN4148 BST VCC1 PHS =IOUT 2 V RON-HS OUT + VIN CBST 1 VIN IOUT t r +t f fSW 2 +Qg-HS fSW Vdriver V PLS =IOUT 2 RON-LS 1 OUT VIN Qg-LS fSW Vdriver + L VOUT SW COUT (13) Figure 8: External Bootstrap Diode and Resistor The recommended external BST diode is IN4148, and the recommended BST capacitor value is 0.1µF to 1μF. + (14) VDROP IOUT t dead1+t dead2 fSW Where RON-HS and RON-LS are the on resistance of the HS-FET and LS-FET, tr and tf are the rising and falling time of the switch, Qg-HS and Qg-LS are the total gate charge of the HS-FET and LS-FET, Vdriver is the gate driver voltage (which is provided by VCC1), VDROP is the LSFET body diode forward voltage, tdead1 is the dead time between the HS-FET turning off and the LS-FET turning on, and tdead2 is the dead time between the LS-FET turning off and the HS-FET turning on. Ensure that the thermal caused by the power loss on the MOSFETs does not exceed the allowed maximum thermal of the selected MOSFETs. Schottky Selection The diode between SW and PGND (shown as D2 in Figure 12) is used to absorb spikes, store charges during dead time, and protect the body diode of the LS-FET. Considering the size and power loss during the dead time, a 1 - 3A Schottky diode is recommended. BST Charge Diode and Resistor Selection An external BST diode can enhance the efficiency of the regulator when the duty cycle is high. A power supply between 2.5V and 5V can be used to power the external bootstrap diode. VCC1 or VOUT is recommended to be this power supply in the circuit (see Figure 8). A resistor in series with the BST capacitor (RBST) can reduce the SW rising rate and voltage spikes. This helps enhance EMI performance and reduce voltage stress at a high VIN. A higher resistance is better for SW spike reduction but compromises efficiency. To make a tradeoff between EMI and efficiency, a ≤20Ω RBST is recommended. Compensation Components The MP2918 employs current-mode control for easy compensation and fast transient response. COMP is the output of the internal error amplifier and controls system stability and transient response. A series resistor-capacitor (R-C) combination sets a pole zero combination to control the control system’s characteristics (see Figure 9). The DC gain of the voltage feedback loop can be calculated with Equation (15): A VDC RLOAD GCS A O VFB VOUT (15) Where AO is the error amplifier voltage gain (3000V/V), GCS is the current sense transconductance 1/(12xRSENSE) (A/V), and RLOAD is the load resistor value. COMP C6 C7 R5 Figure 9: Compensation Network MP2918 Rev. 1.02 5/31/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 23 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER The system has two important poles: one from the compensation capacitor (C6) and the output resistor of the error amplifier, and the other from the output capacitor and the load resistor (see Figure 9). These poles can be calculated with Equation (16) and Equation (17): Gm fP1 2π C6 A O fP2 1 2π Co R LOAD (16) (17) The system has one important zero due to the compensation capacitor and the compensation resistor (R5), which can be calculated with Equation (18): 1 2π C6 R5 (18) The system may have another significant zero if the output capacitor has a large capacitance or high ESR value and can be calculated with Equation (19): fESR 1 2π Co R ESR 1 2π C7 R5 to design the 1. Choose R5 to set the desired crossover frequency with Equation (21): R5 2π Co fC VOUT Gm GCS VFB (21) 2. Choose C6 to achieve the desired phase margin. For applications with typical inductor values, set the compensation zero (fZ1) <0.25 x fC to provide a sufficient phase margin. C6 is then calculated with Equation (22): C6 4 2π R5 fC (22) 3. C7 is required if the ESR zero of the output capacitor is located at <0.5 x fSW, or Equation (23) is valid: f 1 SW 2π Co R ESR 2 (23) If this is the case, use C7 to set the pole (fP3) at the location of the ESR zero. Determine C7 with Equation (24): (19) C7 In this case, a third pole set by the compensation capacitor (C7) and the compensation resistor can compensate for the effect of the ESR zero. This pole is calculated with Equation (20): fP3 below Where fC is the desired crossover frequency. Where Gm is the error amplifier transconductance (500μA/V), and Co is the output capacitor. fZ1 Follow the steps compensation. Co RESR R5 (24) (20) The goal of the compensation design is to shape the converter transfer function for a desired loop gain. The system crossover frequency where the feedback loop has unity gain is important, since lower crossover frequencies result in slower line and load transient responses, and higher crossover frequencies lead to system instability. Set the crossover frequency to ~0.1 x fSW. MP2918 Rev. 1.02 5/31/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 24 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER PCB Layout Guidelines Efficient PCB layout is critical for stable operation, especially for the input capacitor placement. A four-layer layout is strongly recommended to achieve better thermal performance. For best results, refer to Figure 10 and Figure 11 and follow the guidelines below. 1. Place the MOSFETs as close as possible to the device. 2. Make the sense lines (the red lines in Inner Layer 2 of Figure 10 and Figure 11) run close together using a Kelvin connection to reduce the line drop error. 3. Use a large ground plane to connect to PGND directly. 4. Add vias near PGND if the bottom layer is a ground plane. 5. Ensure that the high-current paths at PGND and VIN have short, direct, and wide traces. 6. Place the ceramic input capacitor, especially the small package size (0603) input bypass capacitor, as close to IN and PGND as possible to minimize highfrequency noise. 7. Keep the connection of the input capacitor and IN as short and wide as possible. 8. Place the VCC1 capacitor as close to VCC1 and SGND as possible. 9. Route SW and BST away from sensitive analog areas such as FB. Top Layer Inner Layer 1 Inner Layer 2 10. Place the feedback resistors close to the chip to ensure that the trace which connects to FB is as short as possible. 11. Use multiple vias to connect the power planes to the internal layers. Bottom Layer Figure 10: Recommended PCB Layout for (6) TSSOP Package NOTE: 6) The recommended PCB layout is based on Figure 12. MP2918 Rev. 1.02 5/31/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 25 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER Top Layer Inner Layer 1 Inner Layer 2 Bottom Layer Figure 11: Recommended PCB Layout for QFN (7) Package NOTE: 7) The recommended PCB layout is based on Figure 14. MP2918 Rev. 1.02 5/31/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 26 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER VCC1 C2 1µF 16V PG VCC2 R3 0Ω VOUT SYNCO R15 100kΩ R16 100kΩ EN/SYNC R17 NS CCM R12 0Ω L1 4.7µH R14 10 C11 220pF M2 D2 DFLS 160 15 14 8 R7 0.007Ω R19 R20 0Ω 0Ω C9 NS VOUT R18 10Ω R8 63.4kΩ 3 VCC1 5 PGND SS 6 COUT1 COUT2 COUT3 COUT4 68µF 68µF 22µF NS R10 16V 16V 16V NS C10 NS R9 12kΩ 1 JP2 C7 10nF VOUT 5V/7A C6 680pF C7 NS R5 51kΩ AAM R4 45.3kΩ 17 ILIMIT 12 9 CCM/AAM JP1 3 2 1 VCC1 M1 D1 R13 1N4148WS VCC1 C8 2.2Ω 0.1µF 16V SW 18 FREQ 2 EN/SYNC VIN R11 0Ω BST 20 4 VCC1 R2 MP2918GF 100kΩ BG 11 PG 3 C3 VCC2 SENSE+ 4.7µF 16V SENSE13 SYNCO FB CCM/AAM R1 45.3kΩ TG 19 2 10 PGND 7 COMP C1A C1B 47µF 4.7µF 63V 100V GND SGND U1 1 IN C1C C1 4.7µF 0.47µF 100V 100V VIN 6V-40V 16 TYPICAL APPLICATION CIRCUITS C4 NS Note: Thermal pad should connect to PGND and SGND PGND SYNCO R15 100kΩ EN/SYNC VCC1 C2 1µF 16V PG VCC2 R3 0Ω VOUT PGND 16 2 EN/SYNC VIN R16 100kΩ R17 NS VCC1 9 CCM/AAM JP1 3 2 1 CCM R4 45.3kΩ AAM R11 0Ω M1 D1 R13 1N4148WS VCC1 C8 2.2Ω 0.1µF 16V SW 18 BST 20 4 VCC1 R2 MP2918GF 100kΩ BG 11 PG 3 C3 VCC2 SENSE+ 4.7µF 16V SENSE13 SYNCO FB CCM/AAM R1 45.3kΩ FREQ TG 19 17 R12 0Ω L1 15µH R14 10Ω C11 220pF M2 15 14 8 ILIMIT 12 SS 6 D2 DFLS 160 R7 0.007Ω R19 R20 0Ω 0Ω C9 NS VOUT VCC1 C7 10nF 3 1 JP2 VOUT 12V/7A R18 10Ω R8 169kΩ 2 10 SGND C1A C1B 47µF 4.7µF 63V 100V GND U1 1 IN C1C C1 4.7µF 0.47µF 100V 100V 7 COMP VIN 16V-40V 5 Figure 12: 5V Output Application Circuit for TSSOP Package R10 0Ω COUT1 COUT2 220µF 22µF 16V 16V C10 150pF R9 12kΩ C6 220pF C7 R5 82pF 10kΩ C4 NS Note: Thermal pad should connect to PGND and SGND Figure 13: 12V Output Application Circuit for TSSOP Package MP2918 Rev. 1.02 5/31/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 27 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER TYPICAL APPLICATION CIRCUITS (continued) VIN C1C 4.7µF 100V C1A C1B 47µF 4.7µF 63V 100V GND 3 U1 19 IN C1 0.47µF 100V 6V-40V 14 AGND PGND TG BST 18 8 FREQ R1 45.3kΩ VCC1 VCC2 R3 NS VOUT SYNCO R15 100kΩ 5 COMP VIN R16 100kΩ EN/SYNC SW 16 2 VCC1 R2 MP2918GL 100kΩ BG 9 PG 1 C3 VCC2 4.7µF SENSE+ 16V SENSE11 SYNCO FB 20 EN/SYNC ILIMIT 7 CCM/AAM SS C2 1µF 16V PG R17 NS CCM AAM R4 45.3kΩ 15 R11 0Ω M1 D1 1N4148WS VCC1 R13 C8 0Ω 0.1µF 16V L1 4.7µH R14 10Ω M2 R12 0Ω R7 0.007Ω R19 R20 0Ω 0Ω C9 NS 13 12 6 R8 63.4kΩ 10 VOUT 5V/7A R18 10Ω D2 C11 DFLS160 220pF VOUT COUT1 COUT2 COUT3 COUT4 68µF 68µF 22µF NS 16V 16V R10 16V NS C10 NS 3 2 1 R9 12kΩ VCC1 4 JP2 C5 10nF C6 680pF C7 NS R5 51kΩ JP1 3 2 1 VCC1 17 Note: Thermal pad should connect to PGND and SGND C4 NS Figure 14: 5V Output Application Circuit for QFN Package 16V-40V C1A C1B 47µF 4.7µF 63V 100V GND C1C 4.7µF 100V U1 19 IN C1 0.47µF 100V 14 VIN 3 AGND PGND TG BST 18 8 FREQ R1 45.3kΩ VCC1 VCC2 R15 100kΩ EN/SYNC R3 NS VOUT VIN 5 COMP SYNCO SW 16 2 VCC1 R2 MP2918GL 100kΩ BG 9 PG 1 C3 VCC2 4.7µF SENSE+ 16V SENSE11 SYNCO FB 20 EN/SYNC ILIMIT 7 CCM/AAM SS C2 1µF 16V PG R16 100kΩ R17 NS VCC1 JP1 3 2 1 CCM R4 45.3kΩ AAM C4 NS 17 15 R11 0Ω M1 D1 1N4148WS VCC1 R13 C8 0Ω 0.1µF 16V M2 R12 0Ω L1 15µH R14 10Ω R19 R20 0Ω 0Ω C9 NS 13 12 6 R8 169kΩ 10 VOUT 12V/7A R18 10Ω D2 C11 DFLS160 220pF VOUT R7 0.007Ω R10 0Ω C10 150pF COUT1 COUT2 220µF 68µF 16V 16V 3 2 1 VCC1 4 JP2 R9 12kΩ C5 10nF C6 220pF C7 R5 82pF 10kΩ Note: Thermal pad should connect to PGND and SGND Figure 15: 12V Output Application Circuit for QFN Package MP2918 Rev. 1.02 5/31/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 28 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER PACKAGE INFORMATION TSSOP-20 EP 4.40 TYP 0.40 TYP 6.40 6.60 20 0.65 BSC 11 1.60 TYP 4.30 4.50 PIN 1 ID 1 3.20 TYP 6.20 6.60 5.80 TYP 10 TOP VIEW RECOMMENDED LAND PATTERN 0.80 1.05 1.20 MAX SEATING PLANE 0.19 0.30 0.65 BSC 0.00 0.15 0.09 0.20 SEE DETAIL "A" SIDE VIEW FRONT VIEW GAUGE PLANE 0.25 BSC 3.80 4.30 0o-8o 0.45 0.75 DETAIL “A” 2.60 3.10 BOTTOM VIEW MP2918 Rev. 1.02 5/31/2017 NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH , PROTRUSION OR GATE BURR. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. 4) LEAD COPLANARITY(BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.10 MILLIMETERS MAX. 5) DRAWING CONFORMS TO JEDEC MO-153, VARIATION ACT. 6) DRAWING IS NOT TO SCALE. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 29 MP2918—4V TO 40V SYNCHRONOUS STEP-DOWN CONTROLLER QFN-20 (3mmx4mm) PIN 1 ID SEE DETAIL A PIN 1 ID MARKING PIN 1 ID INDEX AREA BOTTOM VIEW TOP VIEW PIN 1 ID OPTION A 0.30x45°TYP. PIN 1 ID OPTION B R0.20 TYP. DETAIL A SIDE VIEW NOTE: 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX. 4) JEDEC REFERENCE IS MO-220. 5) DRAWING IS NOT TO SCALE. RECOMMENDED LAND PATTERN NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP2918 Rev. 1.02 5/31/2017 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. 30