TI1 MUX50X 36-v, low-capacitance, low-leakage-current, precision analog multiplexer Datasheet

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MUX506, MUX507
SBAS803A – NOVEMBER 2016 – REVISED NOVEMBER 2017
MUX50x 36-V, Low-Capacitance, Low-Leakage-Current, Precision Analog Multiplexers
1 Features
3 Description
•
The MUX506 and MUX507 (MUX50x) are modern
complementary metal-oxide semiconductor (CMOS)
precision analog multiplexers (muxes). The MUX506
offers 16:1 single-ended channels, whereas the
MUX507 offers differential 8:1 or dual 8:1 singleended channels. The MUX506 and MUX507 work
equally well with either dual supplies (±5 V to ±18 V)
or a single supply (10 V to 36 V). These devices also
perform well with symmetric supplies (such as VDD =
12 V, VSS = –12 V), and unsymmetric supplies (such
as VDD = 12 V, VSS = –5 V). All digital inputs have
transistor-transistor logic (TTL) compatible thresholds,
providing both TTL and CMOS logic compatibility
when operating in the valid supply voltage range.
1
•
•
•
•
•
•
•
•
•
•
•
•
Low On-Capacitance
– MUX506: 13.5 pF
– MUX507: 8.7 pF
Low Input Leakage: 1 pA
Low Charge Injection: 0.31 pC
Rail-to-Rail Operation
Wide Supply Range: ±5 V to ±18 V, 10 V to 36 V
Low On-Resistance: 125 Ω
Transition Time: 97 ns
Break-Before-Make Switching Action
EN Pin Connectable to VDD
Logic Levels: 2 V to VDD
Low Supply Current: 45 µA
ESD Protection HBM: 2000 V
Industry-Standard TSSOP/ SOIC Package
The MUX507 and MUX507 have very low on- and offleakage currents, allowing these multiplexers to
switch signals from high input impedance sources
with minimal error. A low supply current of 45 µA
enables use in power-sensitive applications.
Device Information(1)
2 Applications
•
•
•
•
•
•
Factory Automation and Industrial Process Control
Programmable Logic Controllers (PLC)
Analog Input Modules
ATE Test Equipment
Digital Multimeters
Battery Monitoring Systems
PART NUMBER
MUX506
MUX507
PACKAGE
BODY SIZE (NOM)
TSSOP (28)
9.70 mm × 6.40 mm
SOIC (28)
17.9 mm × 7.50 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Simplified Schematic
Leakage Current vs Temperature
1000
±
Thermocouple
MUX507
VINP
ADC
PGA/INA
+
VINM
Current
Sensing
Leakage Current (pA)
Bridge Sensor
ID(OFF)+
0
-500
IS(OFF)-1000
ID(OFF)-
-1500
Photo
LED Detector
Optical Sensor
Analog Inputs
Copyright © 2017, Texas Instruments Incorporated
ID(ON)+
IS(OFF)+
500
-2000
-75
ID(ON)-
-50
-25
0
25
50
75
Temperature (qC)
100
125
150
D006
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MUX506, MUX507
SBAS803A – NOVEMBER 2016 – REVISED NOVEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
1
1
1
2
3
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics: Dual Supply ..................... 7
Electrical Characteristics: Single Supply................... 9
Typical Characteristics ............................................ 11
Parameter Measurement Information ................ 16
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
Truth Tables ............................................................
On-Resistance ........................................................
Off Leakage.............................................................
On-Leakage Current ...............................................
Transition Time .......................................................
Break-Before-Make Delay.......................................
Turn-On and Turn-Off Time ....................................
Charge Injection ......................................................
Off Isolation .............................................................
Channel-to-Channel Crosstalk ..............................
16
17
17
18
18
19
20
21
22
22
7.11 Bandwidth ............................................................. 23
7.12 THD + Noise ......................................................... 23
8
Detailed Description ............................................ 24
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
24
24
25
27
Application and Implementation ........................ 28
9.1 Application Information............................................ 28
9.2 Typical Application ................................................. 28
10 Power Supply Recommendations ..................... 30
11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
11.2 Layout Example .................................................... 31
12 Device and Documentation Support ................. 33
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
33
33
33
33
13 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (November 2016) to Revision A
Page
•
Changed Transition Time From: 85 ns To: 97ns (Typ) in the Features list............................................................................ 1
•
Added SOIC packages to Feature and Device Information .................................................................................................. 1
•
Added the DW (SOIC) package to the Pin Configuration and Functions section .................................................................. 3
•
Added SOIC package to the Thermal Information table ........................................................................................................ 7
•
Changed Transition time Typ value From 85: ns To: 97ns for ±15 V supplies in the Electrical Characteristics: Dual
Supply table ............................................................................................................................................................................ 8
•
Added additional specifications for the SOIC packages (QJ, Off-isolation, and channel-to-channel crosstalk) for ±15
V supplies in Electrical Characteristics: Dual Supply ............................................................................................................. 8
•
Changed Transition time Typ value From: 91 To: 102 ns for 12 V supply in the Electrical Characteristics: Single
Supply table .......................................................................................................................................................................... 10
•
Added additional specifications for the SOIC packages (QJ, Off-isolation, and channel-to-channel crosstalk) for 12 V
supply in Electrical Characteristics: Single Supply............................................................................................................... 10
•
Added NOTE to the Application and Implementation section .............................................................................................. 28
2
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SBAS803A – NOVEMBER 2016 – REVISED NOVEMBER 2017
5 Pin Configuration and Functions
MUX506: PW and DW Packages
28-Pin TSSOP and SOIC
Top View
VDD
1
28
D
NC
2
27
VSS
NC
3
26
S8
S16
4
25
S7
S15
5
24
S6
S14
6
23
S5
S13
7
22
S4
S12
8
21
S3
S11
9
20
S2
S10
10
19
S1
S9
11
18
EN
GND
12
17
A0
NC
13
16
A1
A3
14
15
A2
Not to scale
Pin Functions: MUX506
PIN
NAME
NO.
FUNCTION
DESCRIPTION
A0
17
Digital input
Address line 0
A1
16
Digital input
Address line 1
A2
15
Digital input
Address line 2
A3
14
Digital input
Address line 3
D
28
EN
18
Digital input
GND
Analog input or output Drain pin. Can be an input or output.
Active high digital input. When this pin is low, all switches are turned off. When this pin is
high, the A[3:0] logic inputs determine which switch is turned on.
12
Power supply
NC
2, 3, 13
No connect
Ground (0 V) reference
S1
19
Analog input or output Source pin 1. Can be an input or output.
S2
20
Analog input or output Source pin 2. Can be an input or output.
S3
21
Analog input or output Source pin 3. Can be an input or output.
S4
22
Analog input or output Source pin 4. Can be an input or output.
S5
23
Analog input or output Source pin 5. Can be an input or output.
S6
24
Analog input or output Source pin 6. Can be an input or output.
S7
25
Analog input or output Source pin 7. Can be an input or output.
S8
26
Analog input or output Source pin 8. Can be an input or output.
S9
11
Analog input or output Source pin 9. Can be an input or output.
Do not connect
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Pin Functions: MUX506 (continued)
PIN
NAME
NO.
FUNCTION
DESCRIPTION
S10
10
Analog input or output Source pin 10. Can be an input or output.
S11
9
Analog input or output Source pin 11. Can be an input or output.
S12
8
Analog input or output Source pin 12. Can be an input or output.
S13
7
Analog input or output Source pin 13. Can be an input or output.
S14
6
Analog input or output Source pin 14. Can be an input or output.
S15
5
Analog input or output Source pin 15. Can be an input or output.
S16
4
Analog input or output Source pin 16. Can be an input or output.
VDD
1
Power supply
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD
and GND.
VSS
27
Power supply
Negative power supply. This pin is the most negative power-supply potential. In singlesupply applications, this pin can be connected to ground. For reliable operation, connect a
decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
MUX507: PW and DW Package
28-Pin TSSOP and SOIC
Top View
VDD
1
28
DA
DB
2
27
VSS
NC
3
26
S8A
S8B
4
25
S7A
S7B
5
24
S6A
S6B
6
23
S5A
S5B
7
22
S4A
S4B
8
21
S3A
S3B
9
20
S2A
S2B
10
19
S1A
S1B
11
18
EN
GND
12
17
A0
NC
13
16
A1
NC
14
15
A2
Not to scale
Pin Functions: MUX507
PIN
NAME
NO.
FUNCTION
DESCRIPTION
A0
17
Digital input
Address line 0
A1
16
Digital input
Address line 1
A2
15
Digital input
Address line 2
DA
28
4
Analog input or output Drain pin A. Can be an input or output.
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Pin Functions: MUX507 (continued)
PIN
NAME
NO.
FUNCTION
DB
2
EN
18
Digital input
GND
DESCRIPTION
Analog input or output Drain pin B. Can be an input or output.
Active high digital input. When this pin is low, all switches are turned off. When this pin is
high, the A[2:0] logic inputs determine which pair of switches is turned on.
12
Power supply
NC
3, 13, 14
No connect
Ground (0 V) reference
S1A
19
Analog input or output Source pin 1A. Can be an input or output.
S2A
20
Analog input or output Source pin 2A. Can be an input or output.
S3A
21
Analog input or output Source pin 3A. Can be an input or output.
S4A
22
Analog input or output Source pin 4A. Can be an input or output.
S5A
23
Analog input or output Source pin 5A. Can be an input or output.
S6A
24
Analog input or output Source pin 6A. Can be an input or output.
S7A
25
Analog input or output Source pin 7A. Can be an input or output.
S8A
26
Analog input or output Source pin 8A. Can be an input or output.
S1B
11
Analog input or output Source pin 1B. Can be an input or output.
S2B
10
Analog input or output Source pin 2B. Can be an input or output.
S3B
9
Analog input or output Source pin 3B. Can be an input or output.
S4B
8
Analog input or output Source pin 4B. Can be an input or output.
S5B
7
Analog input or output Source pin 5B. Can be an input or output.
S6B
6
Analog input or output Source pin 6B. Can be an input or output.
S7B
5
Analog input or output Source pin 7B. Can be an input or output.
S8B
4
Analog input or output Source pin 8B. Can be an input or output.
VDD
1
Power supply
Positive power supply. This pin is the most positive power supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD
and GND.
VSS
27
Power supply
Negative power supply. This pin is the most negative power supply potential. In singlesupply applications, this pin can be connected to ground. For reliable operation, connect a
decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
Do not connect
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply
Voltage
MIN
MAX
VDD
–0.3
40
VSS
–40
0.3
VSS – 0.3
VDD + 0.3
VSS – 2
VDD + 2
VDD – VSS
40
Digital pins (2): EN, A0, A1, A2, A3
Analog pins (2): Sx, SxA, SxB, D, DA, DB
Current
(3)
Operating, TA
Temperature
(2)
(3)
V
–30
30
–55
150
Junction, TJ
mA
150
Storage, Tstg
(1)
UNIT
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltage limits are valid if current is limited to ±30 mA.
Only one pin at a time.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
Dual supply
NOM
MAX
5
18
10
36
UNIT
VDD (1)
Positive power-supply voltage
VSS (2)
Negative power-supply voltage (dual supply)
–5
–18
V
VDD – VSS
Supply voltage
10
36
V
Single supply
(3)
V
VS
Source pins voltage
VSS
VDD
V
VD
Drain pins voltage
VSS
VDD
V
VEN
Enable pin voltage
VSS
VDD
V
VA
Address pins voltage
VSS
VDD
V
ICH
Channel current (TA = 25°C)
–25
25
mA
TA
Operating temperature
–40
125
°C
(1)
(2)
(3)
6
When VSS = 0 V, VDD can range from 10 V to 36 V.
VDD and VSS can be any value as long as 10 V ≤ (VDD – VSS) ≤ 36 V.
VS is the voltage on all the S pins.
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6.4 Thermal Information
MUX50x
THERMAL METRIC (1)
PW (TSSOP)
DW (SOIC)
28 PINS
28 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
79.8
53.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
24.0
30.1
°C/W
RθJB
Junction-to-board thermal resistance
37.6
28.5
°C/W
ψJT
Junction-to-top characterization parameter
1.2
9.0
°C/W
ψJB
Junction-to-board characterization parameter
37.1
28.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics: Dual Supply
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD
V
ANALOG SWITCH
Analog signal range
TA = –40°C to +125°C
VSS
VS = 0 V, IS = –1 mA
RON
On-resistance
VS = ±10 V, IS = –1 mA
125
170
145
200
TA = –40°C to +85°C
230
TA = –40°C to +125°C
ΔRON
250
6
On-resistance
mismatch between
channels
VS = ±10 V, IS = –1 mA
On-resistance
flatness
VS = 10 V, 0 V, –10 V
On-resistance drift
IS(OFF)
ID(OFF)
Input leakage current
Output off-leakage
current
14
TA = –40°C to +125°C
16
53
TA = –40°C to +125°C
58
VS = 0 V
0.62
–1
Output on-leakage
current
–0.001
Ω/°C
TA = –40°C to +85°C
–10
10
TA = –40°C to +125°C
–25
25
Switch state is off,
VS = ±10 V, VD = ±10
V (1)
TA = -40°C to +85°C
–10
10
TA = -40°C to +125°C
–25
25
Switch state is on,
VD = ±10 V, VS = floating
TA = –40°C to +85°C
–10
10
TA = –40°C to +125°C
–50
50
–0.01
–0.01
Ω
1
Switch state is off,
VS = ±10 V, VD = ±10
V (1)
–1
Ω
45
TA = –40°C to +85°C
–1
ID(ON)
9
TA = –40°C to +85°C
20
RFLAT
Ω
nA
1
nA
1
nA
LOGIC INPUT
VIH
Logic voltage high
VIL
Logic voltage low
0.8
V
ID
Input current
0.1
µA
(1)
2
V
When VS is positive, VD is negative, and vice versa.
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Electrical Characteristics: Dual Supply (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
82
136
UNIT
SWITCH DYNAMICS (2)
tON
Enable turn-on time
VS = ±10 V, RL = 300 Ω,
CL= 35 pF
TA = –40°C to +85°C
145
TA = –40°C to +125°C
151
63
tOFF
Enable turn-off time
VS = ±10 V, RL = 300 Ω,
CL= 35 pF
tt
Transition time
Break-before-make
time delay
tBBM
89
TA = –40°C to +125°C
97
151
TA = –40°C to +125°C
157
VS = 10 V, RL = 300 Ω, CL= 35 pF, TA = –40°C to +125°C
Charge injection
CL = 1 nF, RS = 0 Ω
VS = –15 V to +15 V
Off-isolation
RL = 50 Ω, VS = 1 VRMS,
f = 1 MHz
Input off-capacitance
TSSOP package
0.31
SOIC package
0.67
TSSOP package
±0.9
SOIC package
±1.1
TSSOP package
–98
SOIC package
–94
Adjacent channel to D, DA,
DB
TSSOP package
–94
RL = 50 Ω, VS = 1 VRMS,
f = 1 MHz
Adjacent channels
CS(OFF)
SOIC package
TSSOP package
Output offcapacitance
f = 1 MHz, VS = 0 V
CS(ON),
CD(ON)
Output oncapacitance
f = 1 MHz, VS = 0 V
ns
ns
pC
dB
–88
–100
SOIC package
–96
TSSOP package
–88
SOIC package
–83
f = 1 MHz, VS = 0 V
CD(OFF)
54
Nonadjacent channel to D,
DA, DB
Nonadjacent channels
Channel-to-channel
crosstalk
30
ns
143
TA = –40°C to +85°C
VS = 0 V
QJ
78
TA = –40°C to +85°C
97
VS = 10 V, RL = 300 Ω,
CL= 35 pF,
ns
dB
2.1
3
MUX506
11.1
12.2
MUX507
6.4
7.5
MUX506
13.5
15
MUX507
8.7
10.2
45
59
pF
pF
pF
POWER SUPPLY
VDD supply current
All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V,
TA = –40°C to +85°C
62
TA = –40°C to +125°C
85
26
VSS supply current
(2)
8
All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V,
µA
34
TA = –40°C to +85°C
37
TA = –40°C to +125°C
58
µA
Specified by design; not subject to production testing.
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6.6 Electrical Characteristics: Single Supply
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD
V
ANALOG SWITCH
Analog signal range
TA = –40°C to +125°C
VSS
235
RON
On-resistance
VS = 10 V, IS = –1 mA
TA = –40°C to +85°C
390
TA = –40°C to +125°C
430
7
ΔRON
On-resistance match
On-resistance drift
IS(OFF)
ID(OFF)
ID(ON)
Input leakage current
Output off leakage
current
Output on leakage
current
VS = 10 V, IS = –1 mA
340
20
TA = –40°C to +85°C
35
TA = –40°C to +125°C
40
VS = 10 V
1.07
–1
0.001
Ω/°C
TA = –40°C to +85°C
–10
10
TA = –40°C to +125°C
–25
25
Switch state is off,
VS = 1 V and VD = 10 V,
or VS = 10 V and VD = 1
V (1)
TA = –40°C to +85°C
–10
10
TA = –40°C to +125°C
–25
25
Switch state is on,
VD = 1 V and 10 V, VS =
floating
TA = –40°C to +85°C
–10
10
TA = –40°C to +125°C
–50
50
–1
0.01
0.02
Ω
1
Switch state is off,
VS = 1 V and VD = 10 V,
or VS = 10 V and VD = 1
V (1)
–1
Ω
nA
1
nA
1
nA
LOGIC INPUT
VIH
Logic voltage high
VIL
Logic voltage low
0.8
V
ID
Input current
0.1
µA
(1)
2.0
V
When VS is 1 V, VD is 10 V, and vice versa.
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Electrical Characteristics: Single Supply (continued)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
90
145
UNIT
SWITCH DYNAMIC CHARACTERISTICS (2)
tON
Enable turn-on time
VS = 8 V, RL = 300 Ω,
CL= 35 pF
TA = –40°C to +85°C
145
TA = –40°C to +125°C
149
66
tOFF
Enable turn-off time
VS = 8 V, RL = 300 Ω,
CL= 35 pF
tt
Transition time
Break-before-make
time delay
tBBM
94
TA = –40°C to +125°C
102
107
TA = –40°C to +85°C
153
VS = 8 V, RL = 300 Ω,
CL= 35 pF,
TA = –40°C to +125°C
155
VS = 8 V, RL = 300 Ω, CL= 35 pF, TA = –40°C to +125°C
Charge injection
CL = 1 nF, RS = 0 Ω
VS = 0 V to 12 V
Off-isolation
RL = 50 Ω, VS = 1 VRMS,
f = 1 MHz
Input off-capacitance
SOIC package
±0.17
SOIC package
±0.48
–97
SOIC package
–94
Adjacent channel to D, DA,
DB
TSSOP package
–94
RL = 50 Ω, VS = 1 VRMS,
f = 1 MHz
TSSOP package
CD(OFF)
Output offcapacitance
f = 1 MHz, VS = 6 V
CS(ON),
CD(ON)
Output oncapacitance
f = 1 MHz, VS = 6 V
pC
dB
–88
–100
SOIC package
–99
TSSOP
-88
SOIC package
-83
f = 1 MHz, VS = 6 V
ns
0.38
TSSOP
SOIC package
ns
0.12
TSSOP package
Adjacent channels
CS(OFF)
TSSOP package
54
Nonadjacent channel to D,
DA, DB
Nonadjacent channels
Channel-to-channel
crosstalk
30
ns
147
VS = 8 V, RL = 300 Ω,
CL= 35 pF,
VS = 6 V
QJ
84
TA = –40°C to +85°C
VS = 8 V, CL= 35 pF
ns
dB
2.4
3.4
MUX506
14
15.4
MUX507
7.8
9.1
MUX506
16.2
18
MUX507
9.9
11.6
41
59
pF
pF
pF
POWER SUPPLY
VDD supply current
All VA = 0 V or 3.3 V,
VS= 0 V, VEN = 3.3 V
TA = –40°C to +85°C
62
TA = –40°C to +125°C
83
22
VSS supply current
(2)
10
All VA = 0 V or 3.3 V,
VS = 0 V, VEN = 3.3 V
µA
34
TA = –40°C to +85°C
37
TA = –40°C to +125°C
57
µA
Specified by design, not subject to production test.
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6.7 Typical Characteristics
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
350
400
TA = 90qC
VDD = 10 V, VSS = -10 V
300
350
TA = 125qC
On Resistance (:)
On Resistance (:)
TA = 25qC
VDD = 16.5 V, VSS = -16.5 V
300
VDD = 13.5 V, VSS = -13.5 V
250
200
150
250
200
150
100
TA = 0qC
50
100
VDD = 18 V, VSS = -18 V
50
-18
-14
-10
TA = -40qC
VDD = 15 V, VSS = -15 V
-6
-2
2
6
10
Source or Drain Voltage (V)
14
0
-18
18
-14
-10
D001
-6
-2
2
6
10
Source or Drain Voltage (V)
14
18
D002
VDD = 15 V, VSS = –15 V
Figure 1. On-Resistance vs Source or Drain Voltage
Figure 2. On-Resistance vs Source or Drain Voltage
700
700
TA = 85qC
VDD = 5 V, VSS = -5 V
On Resistance (:)
VDD = 6 V, VSS = -6 V
On Resistance (:)
TA = 125qC
600
600
500
400
300
200
500
TA = 25qC
400
300
200
100
VDD = 7 V, VSS = -7 V
100
-8
TA = -40qC
TA = 0qC
0
-6
-4
-2
0
2
4
Source or Drain Voltage (V)
6
8
0
2
D003
4
6
8
Source or Drain Voltage (V)
10
12
D004
VDD = 12 V, VSS = 0 V
Figure 3. On-Resistance vs Source or Drain Voltage
Figure 4. On-Resistance vs Source or Drain Voltage
700
250
600
VDD = 14 V, VSS = 0 V
VDD = 33 V, VSS = 0 V
On Resistance (:)
On Resistance (:)
200
150
100
VDD = 36 V, VSS = 0 V
VDD = 30 V, VSS = 0 V
500
400
300
200
VDD = 12 V, VSS = 0 V
50
100
VDD = 10 V, VSS = 0 V
0
0
0
6
12
18
24
Source or Drain Voltage (V)
30
36
0
2
D024
Figure 5. On-Resistance vs Source or Drain Voltage
4
6
8
10
Source or Drain Voltage (V)
12
14
D005
Figure 6. On-Resistance vs Source or Drain Voltage
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Typical Characteristics (continued)
250
250
200
200
On Resistance (:)
On Resistance (:)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
150
100
50
150
100
50
0
0
6
12
18
Source or Drain Voltage (V)
0
-12
24
-6
D025
VDD = 24 V, VSS = 0 V
12
D026
VDD = 12 V, VSS = –12 V
Figure 7. On-Resistance vs Source or Drain Voltage
Figure 8. On-Resistance vs Source or Drain Voltage
1000
900
ID(ON)+
IS(OFF)+
500
0
-500
IS(OFF)-1000
ID(OFF)-
-1500
IS(OFF)+
600
ID(OFF)+
Leakage Current (pA)
Leakage Current (pA)
0
6
Source or Drain Voltage (V)
ID(ON)-
ID(ON)+
300
IS(OFF)-
0
ID(OFF)+
-300
ID(OFF)-
-600
ID(ON)-2000
-75
-50
-25
0
25
50
75
Temperature (qC)
100
125
-900
-75
150
-50
D006
-25
0
25
50
75
Temperature (qC)
100
125
150
D007
Þ
VDD = 15 V, VSS = –15 V
VDD = 12 V, VSS = 0 V
Figure 9. Leakage Current vs Temperature
Figure 10. Leakage Current vs Temperature
2
2
VDD = 5 V, VSS = -5 V
VDD = 12 V, VSS = 0 V
1
Charge Injection (pC)
Charge Injection (pC)
VDD = 5 V, VSS = -5 V
0
VDD = 10 V, VSS = -10 V
-1
1
0
-10
-5
0
5
Source Voltage (V)
VDD = 10 V, VSS = -10 V
-1
VDD = 15 V, VSS = -15 V
VDD = 15 V, VSS = -15 V
-2
-15
10
15
-2
-15
-10
D011
MUX506, source-to-drain
-5
0
5
Source Voltage (V)
10
15
D027
MUX507, source-to-drain
Figure 11. Charge Injection vs Source Voltage
12
VDD = 12 V, VSS = 0 V
Figure 12. Charge Injection vs Source Voltage
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Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
150
9
VDD = 10 V, VSS = -10 V
Turn On and Turn Off Times (ns)
tON (VDD = 12 V, VSS = 0 V)
Charge Injection (pC)
6
VDD = 15 V, VSS = -15 V
3
0
-3
-6
120
tON (VDD = 15 V, VSS = -15 V)
90
60
tOFF (VDD = 12 V, VSS = 0 V)
30
tOFF (VDD = 15 V, VSS = -15 V)
VDD = 12 V, VSS = 0 V
-9
-15
-10
-5
0
5
Drain voltage (V)
10
0
-75
15
-50
-25
D008
0
25
50
75
Temperature (qC)
100
125
150
D010
Drain-to-source
Figure 13. Charge Injection vs Drain Voltage
Figure 14. Turn-On and Turn-Off Times vs Temperature
0
0
-20
Adjacent Channel to D (Output)
Adjacent Channels
-40
-40
Crosstalk (dB)
Off Isolation (dB)
-20
-60
-80
-100
-60
-80
-100
-120
-120
Non-Adjacent Channel to D (Output)
-140
100k
1M
10M
Frequency (Hz)
100M
Non-Adjacent Channels
-140
100k
1G
1M
D012
Figure 15. Off Isolation vs Frequency
10M
Frequency (Hz)
100M
1G
D013
Figure 16. Crosstalk vs Frequency
5
100
0
On Response (dB)
10
THD+N (%)
VDD = 5 V, VSS = -5 V
1
0.1
-5
-10
-15
-20
-25
VDD = 15 V, VSS = -15 V
0.01
10
100
1k
Frequency (Hz)
10k
100k
-30
100k
1M
D014
Figure 17. THD+N vs Frequency
10M
Frequency (Hz)
100M
1G
D021
Figure 18. On Response vs Frequency
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Typical Characteristics (continued)
30
30
24
24
CD(OFF)
Capacitance (pF)
Capacitance (pF)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
18
12
CD(ON)
CS(OFF)
18
CD(OFF)
12
CD(ON)
6
6
CS(OFF)
0
-15
-10
-5
0
5
Source or Drain Voltage (V)
10
0
-15
15
MUX506, VDD = 15 V, VSS = –15 V
24
24
CD(ON)
Capacitance (pF)
Capacitance (pF)
30
12
6
10
15
D016
Figure 20. Capacitance vs Source Voltage
30
18
-5
0
5
Source or Drain Voltage (V)
MUX507, VDD = 15 V, VSS = –15 V
Figure 19. Capacitance vs Source Voltage
CD(OFF)
-10
D015
CS(OFF)
18
CD(ON)
CD(OFF)
12
6
CS(OFF)
0
0
0
6
12
18
Source or Drain Voltage (V)
24
30
0
6
12
18
Source or Drain Voltage (V)
D017
MUX506, VDD = 30 V, VSS = 0 V
24
30
D018
MUX507, VDD = 30 V, VSS = 0 V
Figure 21. Capacitance vs Source Voltage
Figure 22. Capacitance vs Source Voltage
30
30
CD(ON)
24
CD(OFF)
Capacitance (pF)
Capacitance (pF)
24
18
12
CS(OFF)
6
CD(ON)
18
12
6
CS(OFF)
0
0
0
3
6
9
Source or Drain Voltage (V)
MUX506, VDD = 12 V, VSS = 0 V
Figure 23. Capacitance vs Source Voltage
14
CD(OFF)
12
0
3
D019
6
9
Source or Drain Voltage (V)
12
D020
MUX507, VDD = 12 V, VSS = 0 V
Figure 24. Capacitance vs Source Voltage
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Typical Characteristics (continued)
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
25
20
Drain Current (mA)
15
10
5
0
-5
-10
-15
-20
-25
-25
-20
-15
-10
-5
0
5
10
Source Current (mA)
15
20
25
D028
Figure 25. Source Current vs Drain Current
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7 Parameter Measurement Information
7.1 Truth Tables
Table 1. MUX506
(1)
EN
A3
A2
A1
A0
ON-CHANNEL
0
X (1)
X (1)
X (1)
X (1)
All channels are off
1
0
0
0
0
Channel 1
1
0
0
0
1
Channel 2
1
0
0
1
0
Channel 3
1
0
0
1
1
Channel 4
1
0
1
0
0
Channel 5
1
0
1
0
1
Channel 6
1
0
1
1
0
Channel 7
1
0
1
1
1
Channel 8
1
1
0
0
0
Channel 9
1
1
0
0
1
Channel 10
1
1
0
1
0
Channel 11
1
1
0
1
1
Channel 12
1
1
1
0
0
Channel 13
1
1
1
0
1
Channel 14
1
1
1
1
0
Channel 15
1
1
1
1
1
Channel 16
X denotes don't care..
Table 2. MUX507
EN
0
(1)
16
A2
A1
A0
(1)
(1)
(1)
X
X
X
ON-CHANNEL
All channels are off
1
0
0
0
Channels 1A and 1B
1
0
0
1
Channels 2A and 2B
1
0
1
0
Channels 3A and 3B
1
0
1
1
Channels 4A and 4B
1
1
0
0
Channels 5A and 5B
1
1
0
1
Channels 6A and 6B
1
1
1
0
Channels 7A and 7B
1
1
1
1
Channels 8A and 8B
X denotes don't care.
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7.2 On-Resistance
The on-resistance of the MUX50x is the ohmic resistance across the source (Sx, SxA, or SxB) and drain (D, DA,
or DB) pins of the device. The on-resistance varies with input voltage and supply voltage. The symbol RON is
used to denote on-resistance. The measurement setup used to measure RON is shown in Figure 26. Voltage (V)
and current (ICH) are measured using this setup, and RON is computed as shown in Equation 1:
RON = V / ICH
(1)
V
D
S
ICH
VS
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Figure 26. On-Resistance Measurement Setup
7.3 Off Leakage
There are two types of leakage currents associated with a switch during the OFF state:
1. Source off-leakage current
2. Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF).
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF).
The setup used to measure both off-leakage currents is shown in Figure 27
ID (OFF)
Is (OFF)
A
S
D
VS
A
VD
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Figure 27. Off-Leakage Measurement Setup
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7.4 On-Leakage Current
On-leakage current is defined as the leakage current that flows into or out of the drain pin when the switch is in
the ON state. The source pin is left floating during the measurement. Figure 28 shows the circuit used for
measuring the on-leakage current, denoted by ID(ON).
ID (ON)
D
S
A
NC
NC = No Connection
VD
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Figure 28. On-Leakage Measurement Setup
7.5 Transition Time
Transition time is defined as the time taken by the output of the MUX50x to rise or fall to 90% of the transition
after the digital address signal has fallen or risen to 50% of the transition. Figure 29 shows the setup used to
measure transition time, denoted by the symbol tt.
VDD
VSS
VDD
VSS
3V
Address
Signal (VIN)
50%
50%
S1
VS1
A0
0V
A1
VIN
tt
S2-S15
A2
tt
A3
90%
Output
MUX506
Output
2V
VS16
S16
VS1
EN
D
GND
300 Ÿ
35 pF
90%
VS16
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Figure 29. Transition-Time Measurement Setup
18
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7.6 Break-Before-Make Delay
Break-before-make delay is a safety feature that prevents two inputs from connecting when the MUX50x is
switching. The MUX50x output first breaks from the ON-state switch before making the connection with the next
ON-state switch. The time delay between the break and the make is known as break-before-make delay.
Figure 30 shows the setup used to measure break-before-make delay, denoted by the symbol tBBM.
VDD
VSS
VDD
VSS
3V
Address
Signal (VIN)
S1
VS
A0
0V
A1
VIN
S2-S15
A2
S16
A3
Output
80%
Output
MUX506
80%
2V
EN
D
GND
300 Ÿ
35 pF
tBBM
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Figure 30. Break-Before-Make Delay Measurement Setup
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7.7 Turn-On and Turn-Off Time
Turn-on time is defined as the time taken by the output of the MUX50x to rise to 90% final value after the enable
signal has risen to 50% final value. Figure 31 shows the setup used to measure turn-on time. Turn-on time is
denoted by the symbol tON.
Turn off time is defined as the time taken by the output of the MUX50x to fall to 10% initial value after the enable
signal has fallen to 50% initial value. Figure 31 shows the setup used to measure turn-off time. Turn-off time is
denoted by the symbol tOFF.
VDD
VSS
VDD
VSS
3V
Enable
Drive (VIN)
50%
50%
S1
A0
VS
A1
S2-S16
0V
A2
A3
tOFF (EN)
tON (EN)
MUX506
VS
0.9 VS
Output
Output
D
EN
GND
0.1 VS
0V
VIN
300 Ÿ
35 pF
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Figure 31. Turn-On and Turn-Off Time Measurement Setup
20
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7.8 Charge Injection
The MUX50x have a simple transmission-gate topology. Any mismatch in capacitance between the NMOS and
PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the gate
signal. The amount of charge injected into the source or drain of the device is known as charge injection, and is
denoted by the symbol QINJ. Figure 32 shows the setup used to measure charge injection.
VSS
VDD
VDD
VSS
A0
3V
A1
VEN
A2
A3
MUX506
0V
RS
S1
D
VOUT
EN
VOUT
VOUT
CL
1 nF
VS
GND
QINJ = CL ×
VOUT
VEN
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Figure 32. Charge-Injection Measurement Setup
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7.9 Off Isolation
Off isolation is defined as the voltage at the drain pin (D, DA, or DB) of the MUX50x when a 1-VRMS signal is
applied to the source pin (Sx, SxA, or SxB) of an off-channel. Figure 33 shows the setup used to measure off
isolation. Use Equation 2 to compute off isolation.
VDD
VSS
0.1 µF
0.1 µF
Network Analyzer
VSS
VDD
50
S
50 Ÿ
VS
D
VOUT
RL
50 Ÿ
GND
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Figure 33. Off Isolation Measurement Setup
Off Isolation
§V
·
20 ˜ Log ¨ OUT ¸
© VS ¹
(2)
7.10 Channel-to-Channel Crosstalk
Channel-to-channel crosstalk is defined as the voltage at the source pin (Sx, SxA, or SxB) of an off-channel,
when a 1-VRMS signal is applied at the source pin of an on-channel. Figure 34 shows the setup used to measure
channel-to-channel crosstalk. Use Equation 3 to compute, channel-to-channel crosstalk.
VSS
VDD
0.1 µF
0.1 µF
VSS
VDD
Network Analyzer
VOUT
S1
RL
50 Ÿ
R
50 Ÿ
S2
VS
GND
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Figure 34. Channel-to-Channel Crosstalk Measurement Setup
Channel-to-Channel Crosstalk
22
§V
·
20 ˜ Log ¨ OUT ¸
© VS ¹
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7.11 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin of an on-channel, and the output measured at the drain pin of the MUX50x. Figure 35 shows
the setup used to measure bandwidth of the mux. Use Equation 4 to compute the attenuation.
VSS
VDD
0.1 µF
0.1 µF
VSS
VDD
Network Analyzer
V1
50
S
VS
V2
D
VOUT
RL
50 Ÿ
GND
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Figure 35. Bandwidth Measurement Setup
Attenuation
§V ·
20 ˜ Log ¨ 2 ¸
© V1 ¹
(4)
7.12 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as the
ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the mux
output. The on-resistance of the MUX50x varies with the amplitude of the input signal and results in distortion
when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as
THD+N. Figure 36 shows the setup used to measure THD+N of the MUX50x.
VSS
VDD
0.1 µF
0.1 µF
Audio Precision
VSS
VDD
RS
S
IN
VS
VIN
D
5 VRMS
VOUT
RL
10 NŸ
GND
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Figure 36. THD+N Measurement Setup
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8 Detailed Description
8.1 Overview
The MUX50x are a family of analog multiplexers. The Functional Block Diagram section provides a top-level
block diagram of both the MUX506 and MUX507. The MUX506 is a 16-channel, single-ended, analog mux. The
MUX507 is an 8-channel, differential or dual 8:1, single-ended, analog mux. Each channel is turned on or turned
off based on the state of the address lines and enable pin.
8.2 Functional Block Diagram
MUX507
MUX506
S1
S1A
S2
S2A
S3
S7A
S8
D
S9
S8A
DA
S1B
DB
S2B
S14
S7B
S15
S16
S8B
1-of-8
Decoder
1-of-16
Decoder
A0
A1
A2
A3
EN
A0
A1
A2
EN
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8.3 Feature Description
8.3.1 Ultralow Leakage Current
The MUX50x provide extremely low on- and off-leakage currents. The MUX50x are capable of switching signals
from high source-impedance inputs into a high input-impedance op amp with minimal offset error because of the
ultra-low leakage currents. Figure 37 shows typical leakage currents of the MUX50x versus temperature.
1000
Leakage Current (pA)
ID(ON)+
IS(OFF)+
500
ID(OFF)+
0
-500
IS(OFF)-1000
ID(OFF)-
-1500
-2000
-75
ID(ON)-
-50
-25
0
25
50
75
Temperature (qC)
100
125
150
D006
Figure 37. Leakage Current vs Temperature
8.3.2 Ultralow Charge Injection
The MUX50x have a simple transmission gate topology, as shown in Figure 38. Any mismatch in the stray
capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is
opened or closed.
OFF ON
CGSN
CGDN
S
D
CGSP
CGDP
OFF ON
Copyright © 2017, Texas Instruments Incorporated
Figure 38. Transmission Gate Topology
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Feature Description (continued)
The MUX50x have special charge-injection cancellation circuitry that reduces the source-to-drain charge injection
to as low as 0.31 pC at VS = 0 V, and ±0.9 pC in the full signal range, as shown in Figure 39.
2
Charge Injection (pC)
VDD = 5 V, VSS = -5 V
VDD = 12 V, VSS = 0 V
1
0
VDD = 10 V, VSS = -10 V
-1
VDD = 15 V, VSS = -15 V
-2
-15
-10
-5
0
5
Source Voltage (V)
10
15
D011
Figure 39. Source-to-Drain Charge Injection
The drain-to-source charge injection becomes important when the device is used as a demultiplexer (demux),
where D becomes the input and Sx becomes the output. Figure 40 shows the drain-to-source charge injection
across the full signal range.
9
VDD = 10 V, VSS = -10 V
Charge Injection (pC)
6
3
VDD = 15 V, VSS = -15 V
0
-3
-6
VDD = 12 V, VSS = 0 V
-9
-15
-10
-5
0
5
Drain voltage (V)
10
15
D008
Figure 40. Drain-to-Source Charge Injection
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Feature Description (continued)
8.3.3 Bidirectional Operation
The MUX50x are operable as both a mux and demux. The source (Sx, SxA, SxB) and drain (D, DA, DB) pins of
the MUX50x are used either as input or output. Each MUX50x channel has very similar characteristics in both
directions.
8.3.4 Rail-to-Rail Operation
The valid analog signal for the MUX50x ranges from VSS to VDD. The input signal to the MUX50x swings from VSS
to VDD without any significant degradation in performance. The on-resistance of the MUX50x varies with input
signal, as shown in Figure 41
400
VDD = 10 V, VSS = -10 V
On Resistance (:)
350
300
VDD = 16.5 V, VSS = -16.5 V
VDD = 13.5 V, VSS = -13.5 V
250
200
150
100
VDD = 18 V, VSS = -18 V
50
-18
-14
-10
VDD = 15 V, VSS = -15 V
-6
-2
2
6
10
Source or Drain Voltage (V)
14
18
D001
Figure 41. On-resistance vs Source or Drain Voltage
8.4 Device Functional Modes
When the EN pin of the MUX50x is pulled high, one of the switches is closed based on the state of the address
lines. When the EN pin is pulled low, all the switches are in an open state irrespective of the state of the address
lines. The EN pin can be connected to VDD (as high as 36 V).
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The MUX50x family offers outstanding input/output leakage currents and ultra-low charge injection. These
devices operate up to 36 V, and offer true rail-to-rail input and output. The on-capacitance of the MUX50x is very
low. These features makes the MUX50x a family of precision, robust, high-performance analog multiplexer for
high-voltage, industrial applications.
9.2 Typical Application
Figure 42 shows a 16-bit, differential, 8-channel, multiplexed, data-acquisition system. This example is typical in
industrial applications that require low distortion and a high-voltage differential input. The circuit uses the
ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along
with a precision, high-voltage, signal-conditioning front end, and a 4-channel differential mux. This TI Precision
Design details the process for optimizing the precision, high-voltage, front-end drive circuit using the MUX507,
OPA192 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864.
Analog Inputs
REF3140
Bridge Sensor
Thermocouple
MUX507
OPA192
+
OPA140
Photo
Detector
+
Gain Network
Gain Network
Current Sensing
LED
High-Voltage Multiplexed Input
OPA350
RC Filter
Reference Driver
+
OPA192
Optical Sensor
Gain Network
Gain Network
RC Filter
High-Voltage Level Translation
REF
Charge
Kickback
Filter
VINP
ADS8864
VINM
VCM
Copyright © 2016, Texas Instruments Incorporated
Figure 42. 16-Bit Precision Multiplexed Data-Acquisition System for High-Voltage Inputs With Lowest
Distortion
9.2.1 Design Requirements
The primary objective is to design a ±20 V, differential, 8-channel, multiplexed, data-acquisition system with
lowest distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10-kHz, full-scale, pure, sine-wave
input. The design requirements for this block design are:
• System supply voltage: ±15 V
• ADC supply voltage: 3.3 V
• ADC sampling rate: 400 kSPS
• ADC reference voltage (REFP): 4.096 V
• System input signal: A high-voltage differential input signal with a peak amplitude of 20 V and frequency
(fIN) of 10 kHz are applied to each differential input of the mux.
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Typical Application (continued)
9.2.2 Detailed Design Procedure
The purpose of this precision design is to design an optimal, high-voltage, multiplexed, data-acquisition system
for highest system linearity and fast settling. The overall system block diagram is illustrated in Figure 42. The
circuit is a multichannel, data-acquisition signal chain consisting of an input low-pass filter, mux, mux output
buffer, attenuating SAR ADC driver, and the reference driver. The architecture allows fast sampling of multiple
channels using a single ADC, providing a low-cost solution. This design systematically approaches each analog
circuit block to achieve a 16-bit settling for a full-scale input stage voltage and linearity for a 10-kHz sinusoidal
input signal at each input channel. Detailed design considerations and component selection procedure can be
found in the TI Precision Design TIPD151, 16-Bit, 400-kSPS, 4-Channel Multiplexed Data-Acquisition System for
High-Voltage Inputs with Lowest Distortion.
9.2.3 Application Curve
1.0
Integral Non-Linearity (LSB)
0.8
0.6
0.4
0.2
0.0
±0.2
±0.4
±0.6
±0.8
±1.0
±20
±15
±10
±5
0
5
10
ADC Differential Peak-to-Peak Input (V)
15
20
C030
Figure 43. ADC 16-Bit Linearity Error for the Multiplexed Data-Acquisition Block
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10 Power Supply Recommendations
The MUX50x operates across a wide supply range of ±5 V to ±18 V (10 V to 36 V in single-supply mode). The
devices also perform well with unsymmetric supplies such as VDD = 12 V and VSS= –5 V. For reliable operation,
use a supply decoupling capacitor ranging between 0.1 µF to 10 µF at both the VDD and VSS pins to ground.
The on-resistance of the MUX50x varies with supply voltage, as illustrated in Figure 44
400
VDD = 10 V, VSS = -10 V
On Resistance (:)
350
300
VDD = 16.5 V, VSS = -16.5 V
VDD = 13.5 V, VSS = -13.5 V
250
200
150
100
VDD = 18 V, VSS = -18 V
50
-18
-14
-10
VDD = 15 V, VSS = -15 V
-6
-2
2
6
10
Source or Drain Voltage (V)
14
18
D001
Figure 44. On-Resistance Variation With Supply and Input Voltage
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11 Layout
11.1 Layout Guidelines
Figure 45 illustrates an example of a PCB layout with the MUX506IPW, and Figure 46 illustrates an example of a
PCB layout with MUX507IPW.
Some key considerations are:
1. Decouple the VDD and VSS pins with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure
that the capacitor voltage rating is sufficient for the VDD and VSS supplies.
2. Keep the input lines as short as possible. In case of the differential signal, make sure the A inputs and B
inputs are as symmetric as possible.
3. Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
4. Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
11.2 Layout Example
C
Via to
GND Plane
VDD
D
NC
VSS
NC
S8
S16
S7
S15
S6
S14
S5
C
Via to
GND Plane
S4
S13
MUX506IPW
Via to
GND Plane
S12
S3
S11
S2
S10
S1
S9
EN
GND
A0
NC
A1
A3
A2
Figure 45. MUX506IPW Layout Example
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Layout Example (continued)
C
Via to
GND Plane
VDD
DA
DB
VSS
NC
S8A
S8B
S7A
S7B
S6A
S6B
S5A
C
Via to
GND Plane
S4A
S5B
MUX507IPW
Via to
GND Plane
S4B
S3A
S3B
S2A
S2B
S1A
S1B
EN
GND
A0
NC
A1
NC
A2
Figure 46. MUX507IPW Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• ADS8864 16-Bit, 400-kSPS, Serial Interface, microPower, Miniature, Single-Ended Input, SAR Analog-toDigital Converter (SBAS572)
• OPAx192 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage, Low Input Bias Current Op Amp with
e-trim (SBOS620)
• OPAx140 High-Precision, Low-Noise, Rail-to-Rail Output, 11-MHz JFET Op Amp (SBOS498)
12.2 Related Links
The following table lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MUX506
Click here
Click here
Click here
Click here
Click here
MUX507
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Nov-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MUX506IDWR
ACTIVE
SOIC
DW
28
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
MUX506DA
MUX506IPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
MUX506A
MUX506IPWR
ACTIVE
TSSOP
PW
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
MUX506A
MUX507IDWR
ACTIVE
SOIC
DW
28
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
MUX507DA
MUX507IPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
MUX507A
MUX507IPWR
ACTIVE
TSSOP
PW
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
MUX507A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Nov-2017
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Nov-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
MUX506IDWR
SOIC
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
DW
28
1000
330.0
32.4
11.35
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
18.67
3.1
16.0
32.0
Q1
MUX506IPWR
TSSOP
PW
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
MUX507IDWR
SOIC
DW
28
1000
330.0
32.4
11.35
18.67
3.1
16.0
32.0
Q1
MUX507IPWR
TSSOP
PW
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Nov-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MUX506IDWR
SOIC
DW
28
1000
367.0
367.0
55.0
MUX506IPWR
TSSOP
PW
28
2000
367.0
367.0
38.0
MUX507IDWR
SOIC
DW
28
1000
367.0
367.0
55.0
MUX507IPWR
TSSOP
PW
28
2000
367.0
367.0
38.0
Pack Materials-Page 2
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ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
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