ON LC786820E Compressed audio signal processor ic Datasheet

LC786820E
Compressed Audio Signal Processor IC
with USB Host Controller
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Overview
The LC786820E integrates ARM7TDMI-S™, USB host processing, SD
memory card host processing, compressed audio decode processing, audio
signal processing and a flash memory which stores the program for
ARM7TDMI-S™ and the various data. The sophisticated programs in the
flash memory for the USB host processing for the SD memory card
processing or audio signal processing etc. make the process of external main
microcontroller easier and very helpful to develop a much features / high
performance audio player system.
Main Features
1. USB host / device function (Full speed : 12 M bps),
SD memory card host function
2. MP3*, WMA*, AAC*, FLAC* decoder processing function
3. Audio input functions such as Analog (stereo 3-ch) / digital 3-ch input
(Sampling rate convertible)
4. Audio processing functions such as 20 bands equalizer (stereo 1-ch),
subwoofer processing, high-frequency range extendable filter and etc.
5. Audio output functions such as Electronical Volume output 5-ch
(for LF, LR, RF, RR, SW), or DAC output 3-ch (Lch, Rch, SW)
6. ARM7TDMI-S™ as internal CPU core, flash memory for program and
various data storage
7. Operational voltage source : 3.3 V single power supply
8. Operational temperature : 40 to +85C
9. Package : QIP100E (1420) Pb-Free and Halogen Free type
PQFP100 14x20 / QIP100E
* MP3
MPEG Layer-3 Audio Coding
* WMA
Windows Media Audio
* AAC
Advanced Audio Coding
* FLAC
Free Lossless Audio Codec
* This product is licensed from Silicon Storage Technology, Inc. (USA).
© Semiconductor Components Industries, LLC, 2016
November 2016 - Rev. 2
1
Publication Order Number :
LC786820E/D
LC786820E
Detail Functions
[ Compressed audio functions ]
<Audio processing block>
 MP3 decode (ISO/IEC 11172-3, ISO/IEC 13818-3)
Supported sampling rate : MPEG1-Layer1/2/3 (32 kHz, 44.1 kHz, 48 kHz)
MPEG2-Layer1/2/3 (16 kHz, 22.05 kHz, 24 kHz)
MPEG2.5-Layer3
( 8 kHz, 11.025 kHz, 12 kHz)
Supported bit rate
: All Bit Rate (Variable Bit Rate support)
MPEG header read supported
 WMA decode (Version 9.2 standard)
Supported sampling rate : 8 kHz, 11.025 kHz, 16 kHz, 22.05 kHz, 32 kHz, 44.1 kHz, 48 kHz
Supported bit rate
: 5k bps to 384k bps (Variable Bit Rate support)
 AAC decode (ISO/IEC 14496-3, ISO/IEC 13818-7)
Profile
: MPEG4-AAC-LowComplexity
Supported sampling rate : 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz
Supported bit rate
: Monaural 8k bps to 160k bps (Variable bit rate support)
Stereo
16k bps to 320k bps (Variable bit rate support)
* Depending on the condition, sampling rate can be supported up to 96 kHz.
 FLAC decode (FLAC 1.3.0)
Supported format
: Block size : up to 4608
Quantized number of bits : 8 / 16 / 24-bit per sample
Supported sampling rate : 8 kHz to 48 kHz
Supported channel
: 1/2-ch
[ Audio processing functions ]
<Audio data digital processing block>
 Equalizer function
Supports max of 20-band (stereo 1-ch) and unused band can be used for not only the voice output but also
used for other processing
 Supports signal processing for subwoofer
 Sampling conversion (Fs = 32 / 44.1 / 48 kHz) when playing compressed audio, High band extended
processing supported
 Mute (/12 dB), attenuator
 De-emphasis filter
 Embedded level/peak hold circuit and can hold up to 8 data
 Noise cancel/Echo cancel function
Supports noise cancel/echo cancel at Fs = 8 kHz
 Supports input/output of Fs = 16 kHz voice data
<Audio input processing block>
 Analog Audio data input (3 channels by stereo)
Single Ended input
: 2 channels
Differential input
: 1 channel
Input Gain
: 12.5 dB to +18.5 dB (1 dB step)
24-bit accuracy AD converter
 Digital audio input (Stereo input: Max of 3 channels)
Supports digital 3-line (LR clock, bit clock, audio data) connection and clock can be master or slave
Data format supports IIS/MSB first right justified and etc.
Input data can support 8 kHz to 96 kHz, and by sampling conversion, converts to the suitable Fs
(Playback Fs = 32 / 44.1 / 48 kHz etc.)
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2
LC786820E
<Audio output processing block>
 Analog Audio data output (One channel for stereo, and one channel for Sub-Woofer)
Eight-fold over-sampling digital filter (24-bit)
Secondary LPF for audio output
 Electronic Volume/Fader
5ch outputs (Lch-Front (LF)/Rear(LR), Rch-Front (RF)/Rear (RR), Sub-Woofer)
Output Range : 0 dB to 0 dB, 
0 dB to 32 dB
: Analog control, 0.25 dB step
32 dB to 70 dB
: Analog control, 1.0 dB step
70 dB to 90 dB
: Digital attenuator control
Decrease the noise at the volume change timing by the digital and analog composite control.
Individual output for 5 channels control is available
 Digital Audio data output
Digital 3-line interface with IIS/MSB first right justification and etc.
LR clock, Bit clock, Data 1
Clock can be master or slave
Capable of outputting 384Fs clock
[ External interface functions ]
<USB host/device control block>
 Open Host Controller Interface 1.0a
 Universal Serial Bus Specification 2.0 Full Speed
 Supports four kinds of transfer type (Control / Bulk / Interrupt / Isochronous)
 Supports 2 Ports. USB1 = Host or Device, USB2 = Host only
 USB Charger (USB1 only)
Supports detection of CDP (Charging Downstream Port) of USB Charger Specification 1.2
Charge (supplying current) is not supported
 PHY block: Internal Pull-Down/Pull-Up resisters built-in
<SD memory card host control block>
 Multimedia Card Specification v2.11
 Secure Digital Memory Card Physical Layer Specification v0.96
* Individual contract is necessary to use SD memory card controller.
[ Internal Microcontroller functions ]
<Sequencer control>
 USB, SD memory card playback/write control
USB/SD files analysis, etc.
 Audio playback control
Compressed audio playback control, various filter control and etc.
<Communication control between main controller>
 Main communication format is SIO (4-line)
 Capable of direct control of oscillation stop/start from main microcontroller
 Capable of some special command can be used even when oscillation is stopped
<Peripheral interface block>
 GPIO ports
37 ports maximum
(Shared with other functions. Some part of pins can be used even when the clock is halted)
 External interrupt pins 4 pins maximum (Shared with other functions)
 Serial interface
SIO
clock synchronized full duplex (3 lines)
3 channels
UART
full duplex
2 channels
IIC
master function
1 channel
<Program memory block>
 Program memory for the internal sequencer built-in
Program version up from the external media (USB and etc.) or main controller is available.
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LC786820E
<Others>
 Watch Dog Timer
Notify to outside from the pin or internal reset.
 Sleep Mode (2 kinds)
(1) Only CPU core operates at slow clock and clocks for other blocks are stopped.
(2) All clocks are stopped by the main microcontroller control.
[ Useful functions for CD-DSP IC connection usage ]
<CD TEXT processing block>
 Buffers CD-TEXT data
 Starts buffering from desired ID3/ID4 of CD-TEXT data.
* Necessary to connect subcode synchronization signals (SBSY and SFSY), shift clock (SBCK) and data (PW).
<CD-ROM processing block>
 Up to 4 speed operation available
 Supports CD-ROM decoding (Mode1, Mode2 <form1, form2>)
 Supports output of CD-ROM decoded data
* Necessary to connect three signals (LRCK, BCK and DATA).
It is possible if desired to connect C2 error flag.
[ Others ]
<Internal power supply>
 Regulator for internal blocks (VDD for internal = 1.2 V, VDD for Flash = 1.8 V) built-in
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LC786820E
Absolute Maximum at Ta = 25C, DVSS = AVSS1 = AVSS2 = XVSS = 0 V
Item
Maximum
supply voltage
Input voltage
Output voltage
Allowable
power
dissipation
Symbol
VDD max
VIN
VOUT
Pin Name
DVDD, AVDD1, AVDD2, XVDD,
VVDD2
All digital input pins
All digital output/input-output pins
Condition
Ratings
Unit
0.3 to +3.95
0.3 to DVDD+0.3
0.3 to DVDD+0.3
V
519
mW
Ta  85C
Mounted
reference
PCB(*)
Pd max
Operating
Topr
temperature
Storage
Tstg
temperature
(*) Reference PCB : 114.3 mm  76.1 mm  1.6 mm, glass epoxy resin
40 to +85
40 to +125
C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Allowable Operating Ranges at Ta = 40C to 85C, DVSS = AVSS1 = AVSS2 = XVSS = 0 V
Item
Symbol
Supply voltage
VDD1
High-level input
voltage
VIH
Low-level input
voltage
VIL
Oscillator Frequency
FX
Pin Name
DVDD, AVDD1, AVDD2,
XVDD, VVDD2
RESB, SIFCK, SIFDI,
SIFDO, SIFCE, BUSYB,
GP03, GP04, GP05, GP06,
GP07, GP10, GP11, GP12,
GP13, GP14, GP15, JTMS,
JTRSTB, JTCK, JTDI,
GP30, GP31, GP32, GP33,
GP34, GP35, GP36, GP37,
GP40, GP41, GP42, GP43,
GP44, GP45, GP46, GP47,
GP50, GP51, GP52, GP53
RESB, SIFCK, SIFDI,
SIFDO, SIFCE, BUSYB,
GP03, GP04, GP05, GP06,
GP07, GP10, GP11, GP12,
GP13, GP14, GP15, JTMS,
JTRSTB, JTCK, JTDI,
GP30, GP31, GP32, GP33,
GP34, GP35, GP36, GP37,
GP40, GP41, GP42, GP43,
GP44, GP45, GP46, GP47,
GP50, GP51, GP52, GP53,
TEST0, TEST1
Condition
XIN
Schmitt
TYP
MAX
3.00
3.60
2.00
VDD1
Unit
V
Schmitt
Oscillator
circuit
XOUT
MIN
0.00
0.80
12.0000
MHz
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
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LC786820E
Electrical Characteristics at Ta = 40C to 85C, VDD1 = 3.0 V to 3.6 V, DVSS = AVSS1 = AVSS2 = XVSS = 0 V
Item
Symbol
Current drain
IDD1
High-level
input current
Low-level
input current
IIH
IIL
VOH(1)
High-level
output voltage
VOH(2)
VOL(1)
Low-level
output voltage
VOL(2)
Built-in Pulldown resistor
RPD
Pin Name
DVDD, AVDD1, AVDD2,
XVDD, VVDD2
RESB, SIFCK, SIFDI,
SIFDO, SIFCE, BUSYB,
GP03, GP04, GP05, GP06,
GP07, GP10, GP11, GP12,
GP13, GP14, GP15, JTMS,
JTRSTB, JTCK, JTDI,
GP30, GP31, GP32, GP33,
GP34, GP35, GP36, GP37,
GP40, GP41, GP42, GP43,
GP44, GP45, GP46, GP47,
GP50, GP51, GP52, GP53
RESB, SIFCK, SIFDI,
SIFDO, SIFCE, BUSYB,
GP03, GP04, GP05, GP06,
GP07, GP10, GP11, GP12,
GP13, GP14, GP15, GP30, GP31,
GP32, GP33, GP34, GP35,
GP36, GP37, GP40, GP41,
GP42, GP43, GP44, GP45,
GP46, GP47, GP50, GP51,
GP52, GP53, JTMS,
JTRSTB, JTCK, JTDI,
TEST0, TEST1
GP04, GP05, GP06, GP07,
GP12, GP13, GP14, GP15, GP30,
GP31, GP32, GP33, GP34,
GP35, GP36, GP37, GP40,
GP41, GP42, GP43, GP44,
GP45, GP46, GP47, GP50,
GP51, GP52, GP53
SIFDI, SIFDO, SIFCE,
BUSYB, GP03, GP10, GP11,
JTDO, JTRTCK
GP04, GP05, GP06, GP07,
GP12, GP13, GP14, GP15, GP30,
GP31, GP32, GP33, GP34,
GP35, GP36, GP37, GP40,
GP41, GP42, GP43, GP44,
GP45, GP46, GP47, GP50,
GP51, GP52, GP53
SIFDI, SIFDO, SIFCE,
BUSYB, GP03, GP10, GP11,
JTDO, JTRTCK
SIFDO, SIFCE, BUSYB,
GP03, GP04, GP05, GP06,
GP07, GP10, GP11, GP12,
GP13, GP14, GP15, GP30, GP31,
GP32, GP33, GP34, GP35,
GP36, GP37, GP40, GP41,
GP42, GP43, GP44, GP45,
GP46, GP47, GP50, GP51,
GP52, GP53
Condition
MIN
TYP
MAX
Unit
100
150
mA
Schmitt
VIN = VDD1
10.00
Built-in Pulldown resistor
OFF
μA
Schmitt
VIN = 0 V
CMOS
IOH = 2 mA
10.00
VDD1
0.6
V
CMOS
IOH = 4 mA
CMOS
IOL = 2 mA
0.40
V
CMOS
IOL = 4 mA
0.40
V
200
kΩ
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50
100
LC786820E
Item
Output offleakage
current
Charge
pump output
current
Symbol
IOFF
(1)
IOFF
(2)
Pin Name
Condition
MIN
TYP
MAX
AFILT
Hi-Z Out
10.00
10.00
SIFDO
Hi-Z Out
10.00
10.00
Unit
μA
IAFH
AFILT
195.0
IAFL
AFILT
195.0
μA
<Note>
 Place an internal pull-down resistor or external pull-down resistor or external pull-up resistor to the SIFDO pin if its
output condition is set to 3-State mode.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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7
LC786820E
■ Package Dimensions
unit : mm
PQFP100 14x20 / QIP100E
CASE 122BV
ISSUE A
0.80.2
23.20.2
17.20.2
100
14.00.1
20.00.1
12
0.65
0.30.05
0.10.1 (2.7)
3.0 MAX
(0.58)
0.15
0.13
0 to10
0.10
SOLDERING FOOTPRINT*
22.30
GENERIC
MARKING DIAGRAM*
0.65
0.43
1.30
16.30
(Unit: mm)
NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
XXXXXXXXX
YMDDD
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
*This information is generic. Please refer to
device data sheet for actual part marking.
LC786820E
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DVDD
DVSS
GP30
GP31
GP32
GP33
GP34
GP35
GP36
GP37
DVDD
DVSS
REG1EXTR
DVDD12_2
GP10
GP11
GP12
GP13
DVDD
DVSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LC786820
NC
AVDD1
AVSS1
LRREF
DACOUTR
RVRIN
RROUT
RFOUT
DACOUTS
SWIN
SWOUT
VREF_ADC
AVSS2
AVDD2
L3INP
L3INN
R3INP
R3INN
L2IN
R2IN
L1IN
R1IN
TEST0
TEST1
DVDD18_2
GP15
GP50
GP51
GP52
GP53
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DACOUTL
LVRIN
LROUT
LFOUT
JTRTCK
JTDO
JTMS
JTDI
JTCK
JTRSTB
DVDD18_1
DVSS
DVDD
DVDD12_1
GP14
GP07
GP06
GP05
GP04
DVDD
■ PIN Assignment
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80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DVSS
VVDD2
NC
AFILT
XVSS
XOUT
XIN
XVDD
UDP1
UDM1
DVSS
UDP2
UDM2
DVDD
DVSS
GP47
GP46
GP45
GP44
GP43
GP42
GP41
GP40
GP03
BUSYB
SIFCE
SIFDO
SIFDI
SIFCK
RESB
LC786820E
■ Pin Description
Pin
No.
Pin name
I/O
State when
"Reset"
1
2
3
NC
AVDD1
AVSS1






4
LRREF
AO
AVDD1/2
5
6
7
8
9
10
11
12
13
14
DACOUTR
RVRIN
RROUT
RFOUT
DACOUTS
SWIN
SWOUT
VREF_ADC
AVSS2
AVDD2
AO
AI
AO
AO
AO
AI
AO
AO


Unknown
Input
Unknown
Unknown
Unknown
Input
Unknown
AVDD2/2


15
L3INP
AI
Input
16
L3INN
AI
Input
17
R3INP
AI
Input
18
19
20
21
22
23
24
25
R3INN
L2IN
R2IN
L1IN
R1IN
TEST0
TEST1
DVDD18_2
AI
AI
AI
AI
AI
I
I
AO
Input
Input
Input
Input
Input
Input
Input
H
26
GP15
I/O
Input(L)
27
GP50
I/O
Input(L)
28
GP51
I/O
Input(L)
29
GP52
I/O
Input(L)
30
GP53
I/O
Input(L)
31
32
DVDD
DVSS




Function
NC pin. This pin must be left open.
Analog system (ADC) power supply
Analog system (ADC) ground. This pin must be connected to the 0 V level.
Capacitor connection pin for reference voltage for Audio DAC and
Electronic Volume.
Audio DAC : Right channel output
Electronic Volume : Right channel volume input
Electronic Volume : Right channel Rear output
Electronic Volume : Right channel Front output
Audio DAC : Sub-Woofer output
Electronic Volume : Sub-Woofer volume input
Electronic Volume : Sub-Woofer output
Capacitor connection pin for audio ADC reference voltage
Analog system (ADC) ground. This pin must be connected to the 0 V level.
Analog system (ADC) power supply
Analog stereo Left channel Differential input (Positive) /
Analog stereo Left channel Single Ended input
Analog stereo Left channel Differential input (Negative)
Analog stereo Right channel Differential input (Positive) /
Analog stereo Right channel Single Ended input
Analog stereo Right channel Differential input (Negative)
Analog stereo Left channel Single Ended input
Analog stereo Right channel Single Ended input
Analog stereo Left channel Single Ended input
Analog stereo Right channel Single Ended input
Test input. This pin must be connected to the 0 V level.
Test input. This pin must be connected to the 0 V level.
Capacitor connection pin for internal regulator (1.8 V for Flash)
General purpose I/O port with pull down resistor
Various signal monitoring output
General purpose I/O port with pull down resistor
LR clock input/output 1 for Audio interface
LR clock input 1 for Stream data interface
Transmit data output for serial communication 3 (exclusive with GP34)
Over current detection signal input for USB 1 (exclusive with GP44)
General purpose I/O port with pull down resistor
Bit clock input/output 1 for Audio interface
Bit clock input/output 1 for Stream data interface
Master clock output for serial communication 3 (exclusive with GP35)
Power supply signal output for USB 1 (exclusive with GP45)
General purpose I/O port with pull down resistor
Data input/output 1 for Audio interface
Data input 1 for Stream data interface
Receive data input for serial communication 3 (exclusive with GP36)
Over current detection signal input for USB 2 (exclusive with GP46)
General purpose I/O port with pull down resistor
Clock (Fs384) input/output 1 for Audio DAC
Request flag input/output 1 for Stream data interface
Power supply signal output for USB 2 (exclusive with GP47)
Digital system power supply
Digital system ground. This pin must be connected to the 0 V level.
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LC786820E
Pin
No.
Pin name
I/O
State when
"Reset"
33
GP30
I/O
Input(L)
34
GP31
I/O
Input(L)
35
GP32
I/O
Input(L)
36
GP33
I/O
Input(L)
37
GP34
I/O
Input(L)
38
GP35
I/O
Input(L)
39
GP36
I/O
Input(L)
40
GP37
I/O
Input(L)
41
42
43
44
DVDD
DVSS
REG1EXTR
DVDD12_2


AO
AO


Unknown
H
45
GP10
I/O
Input(L)
46
GP11
I/O
Input(L)
47
GP12
I/O
Input(L)
48
GP13
I/O
Input(L)
Function
General purpose I/O port with pull down resistor
UART2 data transmit (exclusive with GP46)
External interruption function 3
(exclusive with GP13, GP31, GP43 and GP47)
LR clock input/output 2 for Audio interface
LR clock input 2 for Stream data interface
General purpose I/O port with pull down resistor
UART2 data receive (exclusive with GP47)
External interruption function 3
(exclusive with GP13, GP30, GP43 and GP47)
Bit clock input/output 2 for Audio interface
Bit clock input/output 2 for Stream data interface
General purpose I/O port with pull down resistor
Data 1 input/output for SD memory card
Data input/output 2 for Audio interface
Data input/output 2 for Stream data interface
General purpose I/O port with pull down resistor
Data 0 input/output for SD memory card
Clock(Fs384) input/output 2 for Audio DAC
Request flag input/output 2 for Stream data interface
General purpose I/O port with pull down resistor
Clock output for SD memory card
Transmit data output for serial communication 3 (exclusive with GP50)
Block synchronization signal (SBSY) input for CD subcode
(exclusive with GP44)
General purpose I/O port with pull down resistor
Command input/output for SD memory card
Master clock output for serial communication 3 (exclusive with GP51)
Frame synchronization signal (SFSY) input for CD subcode
(exclusive with GP45)
General purpose I/O port with pull down resistor
Data 3 input/output for SD memory card
Receive data input for serial communication 3 (exclusive with GP52)
Data (PW) input for CD subcode (exclusive with GP46)
General purpose I/O port with pull down resistor
Data 2 input/output for SD memory card
Data transmit clock (SBCK) output for CD subcode (exclusive with GP47)
Digital system power supply
Digital system ground. This pin must be connected to the 0 V level.
Reserved pin for internal regulator. This pin must be left open.
Capacitor connection pin for internal regulator (1.2 V for internal)
General purpose I/O port with pull down resistor
UART1 data transmit (exclusive with GP06)
IIC (master) clock output (exclusive with GP04 and GP40)
General purpose I/O port with pull down resistor
UART1 data receive (exclusive with GP07)
IIC (master) data input/output (exclusive with GP05 and GP41)
General purpose I/O port with pull down resistor
External interruption function 2 (exclusive with GP42 and GP46)
Clock control input 1
Watch Dog Timer state monitor output
General purpose I/O port with pull down resistor
External interruption function 3
(exclusive with GP30, GP31, GP43 and GP47)
Clock control input 2
Watch Dog Timer state monitor output
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LC786820E
Pin
No.
Pin name
I/O
State when
"Reset"
49
50
DVDD
DVSS




51
RESB
I

52
SIFCK
I
Input
53
SIFDI
I/O
Input
54
SIFDO
I/O
Input
55
SIFCE
I/O
Input
56
BUSYB
I/O
Input(L)
57
GP03
I/O
Input(L)
58
GP40
I/O
Input(L)
59
GP41
I/O
Input(L)
60
GP42
I/O
Input(L)
61
GP43
I/O
Input(L)
62
GP44
I/O
Input(L)
63
GP45
I/O
Input(L)
Function
Digital system power supply
Digital system ground. This pin must be connected to the 0 V level.
IC reset input ("L"-active)
This pin must be set low once after power is first applied.
Host-I/F
Data transmit clock input for serial communication 1
Data transmit clock input for IIC communication
Host-I/F
Data input for serial communication 1
Data input/output for IIC communication
Host-I/F
Data output for serial communication 1 (CMOS or 3-State output)
General purpose I/O port with pull down resistor (GP00)
Host -I/F
Enable signal input for serial communication 1 ("H"-active)
General purpose I/O port with pull down resistor (GP01)
Host -I/F
System busy signal output ("L"-active)
General purpose I/O port with pull down resistor (GP02)
External interruption function 0 (exclusive with GP40 and GP44)
General purpose I/O port with pull down resistor
Watch Dog Timer state monitor output
USB device detection flag output
External interruption function 1 (exclusive with GP14, GP41 and GP45)
General purpose I/O port with pull down resistor
External interruption function 0 (exclusive with GP02 and GP44)
IIC (master) clock output (exclusive with GP04 and GP10)
LR clock input/output 3 for Audio interface
LR clock input 3 for Stream data interface
General purpose I/O port with pull down resistor
External interruption function 1 (exclusive withGP03, GP14 and GP45)
IIC (master) data input/output (exclusive with GP05 and GP11)
Bit clock input/output 3 for Audio interface
Bit clock input/output 3 for Stream data interface
General purpose I/O port with pull down resistor
External interruption function 2 (exclusive with GP12 and GP46)
Watch Dog Timer state monitor output
Data input/output 3 for Audio interface
Data input/output 3 for Stream data interface
General purpose I/O port with pull down resistor
External interruption function 3
(exclusive with GP13, GP30, GP31 and GP47)
Clock (Fs384) input/output 3 for Audio DAC
Request flag input/output 3 for Stream data interface
General purpose I/O port with pull down resistor
External interruption function 0 (exclusive with GP02 and GP40)
Over current detection signal input for USB 1(exclusive with GP50)
Block synchronization signal (SBSY) input for CD subcode
(exclusive with GP34)
General purpose I/O port with pull down resistor
External interruption function 1 (exclusive withGP03, GP14 and GP41)
Power supply signal output for USB 1(exclusive with GP51)
Frame synchronization signal (SFSY) input for CD subcode
(exclusive with GP35)
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12
LC786820E
Pin
No.
Pin name
I/O
State when
"Reset"
64
GP46
I/O
Input(L)
65
GP47
I/O
Input(L)
66
67
68
69
70
DVSS
DVDD
UDM2
UDP2
DVSS


I/O
I/O






71
UDM1
I/O

72
UDP1
I/O

73
74
75
76
77
78
79
80
81
XVDD
XIN
XOUT
XVSS
AFILT
NC
VVDD2
DVSS
DVDD

I
O

AO





Oscillation
Oscillation

Unknown




82
GP04
I/O
Input(L)
83
GP05
I/O
Input(L)
84
GP06
I/O
Input(L)
85
GP07
I/O
Input(L)
86
GP14
I/O
Input(L)
87
88
89
90
DVDD12_1
DVDD
DVSS
DVDD18_1
AO


AO
H


H
Function
General purpose I/O port with pull down resistor
UART2 data transmit (exclusive with GP30)
External interruption function 2 (exclusive with GP12 and GP42)
Over current detection signal input for USB 2 (exclusive with GP52)
Emphasis flag input/output for Audio (exclusive with GP14)
Data (PW) input for CD subcode (exclusive with GP36)
General purpose I/O port with pull down resistor
UART2 data receive (exclusive with GP31)
External interruption function 3
(exclusive with GP13, GP30, GP31 and GP43)
Power supply signal output for USB 2 (exclusive with GP53)
CD_C2 error flag input (exclusive with GP14)
Data transmit clock (SBCK) output for CD subcode (exclusive with GP37)
Digital system ground. This pin must be connected to the 0 V level.
Digital system power supply
USB data input/output 2 D signal connection
USB data input/output 2 D+ signal connection
Digital system ground. This pin must be connected to the 0 V level.
USB data input/output 1 D signal connection
Charge detection (CDP detection) input/output 1
USB data input/output 1 D+ signal connection
Charge detection (CDP detection) input/output 1
Oscillator power supply
X'tal oscillator connection
X'tal oscillator connection
Oscillator ground. This pin must be connected to the 0 V level.
PLL2 charge pump output (for filter connection)
NC pin. This pin must be left open.
PLL2 power supply
Digital system ground. This pin must be connected to the 0 V level.
Digital system power supply
General purpose I/O port with pull down resistor
Master clock output for serial communication 2
IIC (master) clock output (exclusive with GP10 and GP40)
General purpose I/O port with pull down resistor
Receive data input for serial data communication 2
IIC (master) data input/output (exclusive with GP11 and GP41)
General purpose I/O port with pull down resistor
Transmit data output for serial communication 2
UART1 data transmit (exclusive with GP10)
General purpose I/O port with pull down resistor
UART1 data receive (exclusive with GP11)
General purpose I/O port with pull down resistor
External interruption function 1 (exclusive withGP03, GP41 and GP45)
Watch Dog Timer state monitor output
USB device detection flag output
Emphasis flag input/output for Audio (exclusive with GP46)
CD_C2 error flag input (exclusive with GP47)
Capacitor connection pin for internal regulator (1.2 V for internal)
Digital system power supply
Digital system ground. This pin must be connected to the 0 V level.
Capacitor connection pin for internal regulator (1.8 V for Flash)
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13
LC786820E
Pin
No.
Pin name
I/O
State when
"Reset"
91
JTRSTB
I
Input
92
JTCK
I
Input
93
JTDI
I
Input
94
JTMS
I
Input
95
96
97
98
99
100
JTDO
JTRTCK
LFOUT
LROUT
LVRIN
DACOUTL
O
O
AO
AO
AI
AO
L
L
Unknown
Unknown
Input
Unknown
Function
JTAG reset input
(Connect to pull-down resistor or 0 V level in normal mode.)
JTAG clock input
(Connect to pull-down resistor or 0 V level in normal mode.)
JTAG data input
(Connect to pull-down resistor or 0 V level in normal mode.)
JTAG mode input
(Connect to pull-down resistor or DVDD level in normal mode.)
JTAG data output (Leave open in normal mode.)
JTAG return clock output (Leave open in normal mode.)
Electronic Volume : Left channel Front output
Electronic Volume : Left channel Rear output
Electronic Volume : Left channel volume input
Audio DAC : Left channel output
<Notes>
(1) For unused pins :
 The unused input pins must be connected to the GND(0V) level if there is no individual note in the above table.
 The unused output pins must be left open(No connection) if there is no individual note in the above table.
 The unused input/output pins must follow the below conditions if there is no individual note in the above table:
Input setting
Leave open with internal pull-down resister ON.
With using internal pull-down resistor OFF, connect to GND (0 V) or connect to power
pins for I/O.
However, use of individual pull-up or pull-down resistor is recommended as fail-safe.
Output setting
Leave them open.
(2) For power supply pins:
 Same voltage level must be supplied to DVDD, AVDD1, AVDD2, XVDD and VVDD2 power supply pins.
(Refer to “Allowable operating ranges”)
(3) For “Reset” condition:
 This IC is not reset only by making the RESB pin “Low”.
Refer to “Power on and Reset control” for detail of “Reset” condition.
(4) For “Analog Source” unused pins (15 pin to 22 pin) :
 The “Analog Source” unused pins (15 pin to 22 pin) must be connected to the GND (0 V) level through the input
coupling capacitor or be left open (No connection).
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14
LC786820E
■ Block Diagram
X'tal
(12MHz)
PLL1
PLL2
CDROM
Decoder
Buffer
SRAM
CDTEXT
Decoder
DATA
Trans
Controller
External Input
Data Interface
ASS
&
ADC
MP3/WMA/AAC
FLAC
/Decoder
ARM7 Core
Flash
memory
BUFRAM
I/F
Cache
USB
Host
/Device
Controller
Work
RAM
Boot
ROM
Watch
Dog
USB-I/F
(CDP-Det)
Interrupt
SD
Memory
Card
Controller
Audio
Data-I/F
SRC
&
HFCAudio Control
20Band-EQ/
Sub-Woofer/
(Loudness/)
ATT/MUTE
Level/Peak
8Fs Digital Filter
Audio DAC
Analog LPF
UART
IIC
EVR
Host-I/F
(SIO/IIC)
SIO
GPIO
EVR
EVR
EVR
Regulator
1.2 V
EVR
1.8 V
3.3 V
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15
LC786820E
Power-ON/Reset Control
- Notes on Power-On
(1) Regarding Reset Pin
To stabilize the operation condition of the internal FlashROM, RESB pin must need to be “L”.
If RESB pin is “H” at the Power-On, operation condition of the Flash memory becomes unstable and the operation
of this LSI becomes unstable. In this case, Reset by RESET pin control does not return to the normal state, RESB
pin must be “L” at the Power-On.
(2) Regarding Volume Out
Volume output becomes unknown state when Power-On, external circuit must care by muting/etc. from external
circuit.
- Power-On/Power-Down/Reset Timing
3.3 V Power supply
VDD1
vBOT
0V
tPWD
3.3 V Power supply
VDD1
tRESW2
tRESW1
RESB Pin
Normal Operation
(Clock oscillation stable)
At the Power-On
Parameter
Power-On rise time
Power-Down fall time
Reset period (at Power-On)
Symbol
Min
tPWD
10
vBOT
0
tRESW1
20
Typ
Reset period (When normal
tRESW2
1
operation) (*1)
*1 : Reset period at normal operation is the period that clock is stablely oscillating.
Need to care about clock stable time when making clock OFF by commands.
Max
Unit
ms
0.2
V
ms
ms
- Regarding RESB pin control and internal Flash memory
As stated above, reset of the operation state of the flash memory in this LSI cannot be controlled by only RESB pin,
and needs Poer-On-Reset. Therefore, when flash memory goes to runaway state during the power is on, Power-OnReset must be done. In this case, users must power off the LSI and execute the Power-On-Reset.
On the other hand, reset control by RESB pin is effective to the circuit other than the flash memory. By making RESB
pin to “L” for the time period stated above with the stable clock, the circuit except flash memory is initialized. Also, by
this operation, flash memory becomes stand-by state and states of the memory cells are kept.
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16
LC786820E
Microcontroller Interface
Reception/Transmission from the host microcontroller is done by the SPI synchronous SIO communication.
The format of the data transmission is as below.
- Code of M5 to M0 at the ModeCode transmission must be followed by the specification of the internal software inside
this LSI.
When data input in M5 to M0 and value in the internal register matches, SIFDO becomes “L” (Ack) and communication
will be enabled. If no match, SIFDO becomes “H” (Nack) and communication will not be enabled.
- Judgement whether command transmission or reception will be done by the 7th bit data of the ModeCode transmission.
“L” means command transmission and “H” means data reception.
- Need to care the communication timing specification because the specification differs by operational mode (normal /
low speed) of the internal microcontroller.
- Communication interface with the host microcontroller
SIFCE
SIFCK
SIFDI
MODE
(Send)
Command
1
Command
2
Command
N
MODE
(Receive)
SIFDO
Ack
Data
2
Data
1
Ack
Data
N
BUSYB
- Transmission/Reception format with the host microcontroller
(1) Host : Command transmission
SIFCE
1
2
3
4
5
6
7
M5
M4
M3
M2
M1
M0
WR
8
1
2
3
6
7
8
D7
D6
D5
D2
D1
D0
SIFCK
SIFDI
Mode Code
byte
Nack
SIFDO
1st-data
byte
Last-data
byte
Ack
BUSYB
(2) Host : Data reception
SIFCE
1
2
3
4
5
6
7
M5
M4
M3
M2
M1
M0
RD
8
1
2
3
6
7
8
SIFCK
SIFDI
Mode Code
byte
SIFDO
Nack
Ack D7
D6 D5
1st-data
byte
BUSYB
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17
D2 D1 D0
Last-data
byte
LC786820E
- Characteristics of Communication Timing With Host Microcontroller
SIFCE
(Input)
1/fCLK
tCSU
tCKH
SIFCK
(Input)
tCKL
tCHD
tCE
tCWSU tCWHD
SIFDI
(Input)
tCDOF
tCRAS
SIFDO
(Output)
BUSYB
(Output)
tCDON
tCDOH
tCBST
Parameter
Symbol
Communication Clock Frequency
fCLK
SIFCK
Communication Clock “H” Period
tCKH
SIFCK
Communication Clock “L” Period
tCKL
SIFCK
Communication Start Allowable
Time
Communication Start Set Up
Time
Pin Names
tCE
BUSYB, SIFCE
tCSU
SIFCE, SIFCK
tCHD
SIFCE, SIFCK
Data Input Set Up Time
tCWSU
SIFDI, SIFCK
Data Input Hold Time
tCWHD
SIFDI, SIFCK
Communication End Hold Time
Data Output “H” Level Rise Time tCDOH
SIFDO, SIFCK
Data Output Settle Time
tCRAS
SIFDO, SIFCK
Output ON Settle Timer *1
tCDON
SIFDO, SIFCE
Output OFF Settle Timer *1
tCDOF
SIFDO, SIFCE
BUSYB "L" Level Settle Time
tCBST
BUSYB
Min
Typ
150
690
150
690
0
0
100
200
100
200
75
75
75
200
*Internal Microcontroller Operation Mode Upper Value : Normal Mode
Lower Value : Low Speed Mode
Note1 : tCDON/tCDOF are available only when setting SIFDO pin to 3-State output.
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18
Max
3.3
0.725
Unit
MHz
ns
100
350
100
350
100
100
150
150
150
350
LC786820E
IIC can be used for the transmission/reception from the host microcontroller.
Supported modes are;
Normal Mode
: 100k bps
High Speed Mode : 400k bps
Slave address is 0x16 (7-bit value).
- Condition for Communication (IIC) Timing With Host Microcontroller
SDA
[SIFDI]
(Inout)
SCL
[SIFCK]
(Input)
tF
tBUF
tLOW
tR
tHD;STA
tSU;DAT
tR
tHD;STA
tHIGH
tHD;DAT
tSU;STA
Start Condition
ReStart Condition
tSU;STO
Stop Condition
Normal (100k bps) High Speed (400k bps)
Unit
Min
Max
Min
Max
SCL Frequency
fSCL
0
100
0
400
kHz
Bus Open Time
tBUF
4.7
1.3
s
SCL "L" Period
tLOW
4.7
1.3
s
SCL "H" Period
tHIGH
4.0
0.6
s
Start/ReStart Condition Hold Time
tHD;STA
4.0
0.6
s
Start/ReStart Condition Set-Up Time
tSU;STA
4.7
0.6
s
SDA Hold Time
tHD;DAT
0
0
s
SDA Set-Up Time
tSU;DAT
250
100
ns
SDA, SCL Rise Time
tR
1000 20+0.1Cb
300
ns
SDA, SCL Fall Time
tF
300
20+0.1Cb
300
ns
Stop Condition Set-Up Time
tSU;STO
4.0
0.6
s
Note : Cb is the total capacity added to each bus (Unit : pF)
Parameter
Symbol
When using IIC, SIFDO/SIFCE/BUSYB pins can be used as GPIOs as below ;
SIFDO : GP00
SIFCE : GP01
BUSYB : GP02
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19
LC786820E
Serial Communication Ports
- Characteristics of Serial Communication (SIO) Master Mode Input/Output Timing
1/fSCF
tSCL tSCH
SSPCK
[GP04/GP35/GP51]
(Output)
tSDO
SSPDO
[GP06/GP34/GP50]
(Output)
SSPDI
[GP05/GP36/GP52]
(Input)
tSDS
tSDH
Parameter
Symbol
Signal Names
Min
SIO Clock Frequency
fSCF
SSPCK
0.008
SIO Clock “H” Period
tSCH
SSPCK
100
SIO Clock "L" Period
tSCL
SSPCK
100
Data Output Settle Time
tSDO
SSPDO, SSPCK
Data Input Set-Up Time
tSDS
SSPDI, SSPCK
50
Data Input Hold Time
tSDH
SSPDI, SSPCK
75
Note : In the case that internal microcontroller operates in normal mode.
Typ
Max
5.0
62500
62500
90
Unit
MHz
ns
- Conditions for Input/Output Timing of Serial Communication (IIC) Master Mode
SDA
[GP05/GP11/GP41]
(Inout)
tF
tBUF
tLOW
SCL
[GP04/GP10/GP40]
(Output)
tR
tHD;STA
tSU;DAT
tHIGH
tHD;DAT
Start Condition
tR
tHD;STA
tSU;STA
tSU;STO
ReStart Condition
Normal (100k bps) High Speed (400k bps)
Min
Max
Min
Max
SCLFrequency
fSCL
0
100
0
400
Bus Open Time
tBUF
4.7
1.3
SCL "L" Period
tLOW
4.7
1.3
SCL "H" Period
tHIGH
4.0
0.6
Start/ReStart Condition Hold Time
tHD;STA
4.0
0.6
Start/ReStart Condition Set-Up Time
tSU;STA
4.7
0.6
SDA Hold Time
tHD;DAT
0
0
SDA Set-Up Time
tSU;DAT
250
100
SDA,SCL Rise Time
tR
1000 20+0.1Cb
300
SDA,SCL Fall Time
tF
300
20+0.1Cb
300
Stop Condition Set-Up Time
tSU;STO
4.0
0.6
Note : Cb is the total capacity added to each bus (Unit : pF)
Parameter
Symbol
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20
Stop Condition
Unit
kHz
s
s
s
s
s
s
ns
ns
ns
s
LC786820E
USB Specification at Ta = 40 to 85C, VDD1 = 3.0 to 3.6 V, DVSS = AVSS1 = AVSS2 = XVSS = 0 V
Parameter
High-level input voltage
Low-level input voltage
Input leakage current
Differential input sensitivity
Common mode voltage range
High-level output voltage
Low-level output voltage
Output signal
Crossover voltage
USB data rising time
USB data falling time
D+/D Pull-Down resistor
D+ Pull-Up resistor
D source voltage
Symbol
VIH(USB)
VIL(USB)
ILI
VDI
VCM
VOH(USB)
VOL(USB)
Pin Names
Conditions
Output : OFF
|(UDP)  (UDM)|
Includes VDI range
UDM1, UDP1,
UDM2, UDP2
VCR
TUR
TUF
RPD
RPUI
RPUR
VDMSRC
VLGC_SRC
CL = 50 pF
UDP1
UDM1
Idle
Reception
MIN
2.0
10.0
0.2
0.8
2.8
0.0
TYP
MAX
0.8
10.0
2.5
3.6
0.3
1.3
2.0
V
4.0
4.0
14.25
0.9
1.425
0.5
0.8
20.0
20.0
24.8
1.575
3.09
0.7
2.0
LC786820E
15 Ω
UDP1
* The value of resistors in this circuit might be
needed to be adjusted for each application.
15 Ω
UDM1
/UDM2
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21
V
μA
V
V
V
V
 USB port peripheral circuit application
/UDP2
Unit
ns
kΩ
kΩ
V
V
LC786820E
SD Memory Card Interface
- Characteristics of SD Memory Card Input/Output Timing
tSDCKL tSDCKH
1/fSDCKF
SDCCLK
(Output)
SDCMDIO
(Inout)
SDCDAT[3:0]
(Inout)
tSDCMS
tSDCMO
tSDCMH
tSDCDO
tSDCDS
tSDCDH
*Relationship between signal name and pin
SDCCLK
: GP34
SDCMDIO
SDCDAT[2] : GP37
SDCDAT[1]
Parameter
SDCCLK Clock Frequency
SDCCLK "H" Period
SDCCLK "L" Period
Command Input Set-Up Time
Command Input Hold Time
Command Output Settle Time
Data Input Set-Up Time
Data Input Hold Time
Data Output Settle Time
Symbol
fSDCKF
tSDCKH
tSDCKL
tSDCMS
tSDCMH
tSDCMO
tSDCDS
tSDCDH
tSDCDO
: GP35
: GP32
SDCDAT[3]
SDCDAT[0]
Signal Names
SDCCLK
SDCCLK
SDCCLK
SDCMDIO, SDCCLK
SDCMDIO, SDCCLK
SDCMDIO, SDCCLK
SDCDAT[3:0], SDCCLK
SDCDAT[3:0], SDCCLK
SDCDAT[3:0], SDCCLK
Min
: GP36
: GP33
Typ
6.0
83.3
83.3
Max
30.0
30.0
30.0
30.0
30.0
30.0
Note : Internal microcontroller (ARM7) must be used in normal mode. It cannot be used in low speed mode.
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22
Unit
MHz
ns
LC786820E
Audio Data Input/Output Function
 AC Electrical Characteristics
at Ta = 25C, VDD1 = 3.3 V, DVSS = AVSS1 = AVSS2 = XVSS = 0 V
Fs = 44.1 kHz, Audio Signal Frequency : 1 kHz, Measurement Range : 10 Hz to 20 kHz
Parameter
Symbol
Pin
Names
Conditions
Min
Typ
Max
Unit
3.005
Vpp
(Input selector+ADC)
Full scale Analog Input Level
2.605
Input Impedance
Gain Setting Level
Gain Setting Step
Gain Setting Step Error
20
12
Signal to Noise Ratio
S/N
Dynamic Range
DR
Total Harmonic
Distortion
THD+N
Cross Talk1
Cross Talk2
(ADC Digital Filter)
Passband Frequency
Stopband Frequency
Passband Ripple
Stopband Attenuation
HPF Cut Off Frequency for DC
Offset cancelation
(Audio DAC)
L1IN,
R1IN,
L2IN,
R2IN,
L3INP,
L3INN,
R3INP,
R3INN
19
1
0.5
0 dB Data,
20 kHz-LPF,
A-filter
60 dB Data,
20 kHz-LPF,
A-filter
Input condition :
3 dBFS
0.5
kΩ
dB
dB
dB
90
95
dB
90
95
dB
85
80
dB
CT1
Between Channels
100
85
dB
CT2
Between Sources
100
85
dB
0.4535
Fs
Fs
dB
dB
±0.04 dB
0
0.5465
>24.1 kHz
69
±0.04
0.00002
Full scale Analog Output Level
Signal to Noise Ratio
2.805
(0.85VDD1)
30
2.605
S/N
DACOUTL,
DACOUTR,
DACOUTS
2.805
(0.85VDD)
Fs
3.005
Vpp
0 dB Data,
20 kHz-LPF,
A-filter
106
dB
60 dB Data,
20 kHz-LPF,
A-filter
106
dB
Dynamic Range
DR
Total Harmonic
Distortion
THD+N
0 dB Data,
20 kHz-LPF
85
80
dB
CT
0 dB Data,
20 kHz-LPF
100
85
dB
0.4535
Fs
Fs
±0.015
dB
Cross Talk
(DAC Digital Filter)
Passband Frequency
Stopband Frequency
±0.015 dB
0
0.5465
Passband Ripple
Stopband Attenuation
HPF Cut Off Frequency for DC
Offset cancelation
62
3 dB
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dB
0.0000385
Fs
LC786820E
Parameter
Symbol
Pin
Names
Conditions
Min
Typ
Max
Unit
LVRIN,
RVRIN,
7.5
10
kΩ
SWIN
15
20
kΩ
70
80
90
dB
0 to 32 dB
0.25
dB
32 to 70 dB
0 to 32 dB
32 to 70 dB
1.0
(Electronic Volume)
Input Impedance
Volume Setting range
LFOUT,
LROUT,
RFOUT,
RROUT,
SWOUT
Mute Level
Volume Setting Step
Volume Setting Step Error
0
0.125
0.5
0.125
0.5
dB
dB
dB
dB
- Audio Digital Data Input/Output Function
- Audio Input/Output Supported Format
Mode
IIS
Input
MSB First Right Aligned
MSB First Left Aligned
IIS
Output
MSB First Right Aligned
MSB First Left Aligned
Bit Length
Slot Length
Fs384 Clock
16-bit
24-bit
32 fs, 48 fs, 64 fs
Internal Clock
External Clock
16-bit
24-bit
32 fs, 48 fs, 64 fs
Fs384 Clock Output
- Applied Pins
LRCK
BCK
DATA
Fs384 Clock
GP30
GP31
GP32
GP33
Input
GP40
GP41
GP42
GP43
GP50
GP51
GP52
GP53
GP30
GP31
GP32
GP33
Output
GP40
GP41
GP42
GP43
GP50
GP51
GP52
GP53
Note : When each pin is set as audio input simultaneously, they will be processed as below priority;
(1) GP30 to 33, (2) GP40 to 43, (3) GP50 to 53
For example, if set all pins to audio input mode, audio data will be processed on only data in GP30 to 33.
Data in GP40 to 43, GP 50 to 53 will not be processed in the LSI.
- Other
- Audio output can be supported in 3 kinds of Fs (32 kHz / 44.1 kHz / 48 kHz).
- When inputting external audio, GP14 / GP46 can support input of emphasis signals.
- Characteristics of Audio Data Input Timing
tFCKIH
Fs384ck
(= Fs384 clock)
tFCKIL
tALRIH
1/fFCKI
tALRIS
LRCK
tABKIH
1/fABCKI
tABKIL
BCK
DATA
tADTIS
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tADTIH
LC786820E
Parameter
Fs384 Clock Frequency
Fs384 Clock "H" Period
Fs384 Clock "L" Period
Bit Clock Frequency
Bit Clock "H" Period
Bit Clock "L" Period
LRCK Input Set-Up Time
LRCK Input Hold Time
DATA Input Set-Up Time
DATA Input Hold Time
Symbol
fFCKI
tFCKIH
tFCKIL
fABCKI
tABKIH
tABKIL
tALRIS
tALRIH
tADTIS
tADTIH
Signal Names
Fs384ck
Fs384ck
Fs384ck
BCK
BCK
BCK
LRCK, BCK
LRCK, BCK
DATA, BCK
DATA, BCK
Min
Typ
Max
20.0
unit
MHz
ns
ns
MHz
ns
ns
ns
ns
ns
ns
20
20
3.3
120
120
30
30
30
30
- Characteristics of Audio Data Output Timing
tFCKOH
tFCKOL
1/fFCKO
Fs384ck
(= Fs384 clock)
tDL1
LRCK
tABKOH
tDL2
tABKOL
1/fABCKO
BCK
DATA
tDL3
Parameter
Symbol
Fs384 Clock Frequency
fFCKO
Fs384 Clock "H" Period
tFCKOH
Fs384 Clock "L" Period
tFCKOL
Bit Clock Frequency
fABCKO
Bit Clock "H" Period
tABKOH
Bit Clock "L" Period
tABKOL
LRCK Output Delay Time
BCK Output Delay Time
DATA Output Delay Time
tDL1
tDL2
tDL3
Signal Names
Fs384ck
Min
Fs384ck
Fs384ck
BCK
BCK
BCK
LRCK, Fs384ck
BCK, Fs384ck
DATA, Fs384ck
*1 : In the case that output Fs = 44.1 kHz and slot length of output format 48 fs.
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0
0
0
Typ
16.9344
*1
29.5
*1
29.5
*1
2.1168
*1
236.2
*1
236.2
*1
Max
unit
MHz
ns
ns
MHz
ns
ns
50
50
50
ns
ns
ns
LC786820E
Stream Data Input/Output Function
There are 2 ways to input/output the stream data.
(1) 4-wire method
Stream Input
: During STREQO = "H" output, input STLRCKI/STBCKI/STDATI.
In the case of 4-wire method, STLRCKI/STBCKI/STDATI (input state) are normal audio
inputs/outputs. As same as the format, 4 byte (32-bit) data transmission/reception is done in
one period of STLRCKI (input state).
(2) 3-wire method
Stream Input
: Input STBCKI/STDATI while STREQO="H" output.
Stream Output : Output STBCKO/STDATO while STREQI="H" input.
In the case of 3-wire method, depending on the state of STREQO, only inputs the bit clock and
data, or depending on the state of STREQI, only outputs the bit clock and data, and data
communication unit becomes 2 byte (16-bit). Also in the 3-wire method of the stream output, it is
possible that users just input the clock (STBCKI) and it will output the data only.
- Characteristics of Stream Data Input Timing
STREQO
tSLRH
(Output)
tSLRS
STLRCKI
(Input)
tSTCKIN
tSTCKL tSTCKH
1/fSCI
STBCKI
(Input)
STDATI
(Input)
tSTDSU
tSTDHD
*Relationship between signal name and pin
STREQO : GP33/GP43/GP53
STLRCKI : GP30/GP40/GP50
STBCKI
: GP31/GP41/GP51
STDATI
: GP32/GP42/GP52
Note : When each pin is set as stream input simultaneously, they will be processed as below priority;
(1) GP30 to 33, (2) GP40 to 43, (3) GP50 to 53
For example, if set all pins to stream input mode, stream data will be processed on only data in GP30 to 33.
Data in GP40 to 43, GP 50 to 53 will not be processed in the LSI.
Parameter
STBCKI Clock Frequency
Symbol
fSCI
Stream Input Start Time
tSTCKIN
STBCKI "H" Period
STBCKI "L" Period
STLRCKI Set-Up Time
STLRCKI Hold Time
STDATI Set-Up Time
STDATI Hold Time
tSTCKH
tSTCKL
tSLRS
tSLRH
tSTDSU
tSTDHD
Signal Names
STBCKI
STREQO,
STBCKI, STLRCKI
STBCKI
STBCKI
STLRCKI, STBCKI
STLRCKI, STBCKI
STDATI, STBCKI
STDATI, STBCKI
Min
Typ
Max
4.24
unit
MHz
50
ns
100
100
75
75
75
75
ns
ns
ns
ns
ns
ns
Note : Above diagram shows the case of data input at rising edge of STBCKI. The timing is the same if using falling
edge synchronization.
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LC786820E
- Characteristics of Stream Data Output Timing: STBCK Output Mode
tSTOFF
STREQI
tSTCOH tSTCOL
(Input)
1/fSCO
tSTOAT
STBCKO
(Output)
STDATO
(Output)
tSDODL
*Relationship between signal name and pin
STREQI
: GP33/GP43/GP53
STBCKO : GP31/GP41/GP51
Parameter
STBCKO Clock Frequency
Symbol
fSCO
Stream Output Start Time
tSTOAT
Stream Output Stop Time
tSTOFF
STBCKO "H" Period
STBCKO "L" Period
STDATO Output Delay Time
tSTCOH
tSTCOL
tSDODL
STDATO
Signal Names
STBCKO
STREQI, STBCKO
: GP32/GP42/GP52
Min
STREQI, STBCKO
STBCKO
STBCKO
STDATO, STBCKO
100
100
0
Typ
Max
4.24
(1/fSCO)
48
(1/fSCO)
48
50
unit
MHz
ns
ns
ns
ns
ns
Note : Above diagram shows the case of data input at rising edge of STBCKO. The timing is the same if using falling
edge synchronization.
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LC786820E
- Characteristics of Stream Data Output Timing : STBCK Input Mode
STREQI
(Input)
tSTBCKL tSTBCKH
tSTBCKIN
1/fSTBCI
STBCKI
(Input)
STDATO
(Output)
tSTDODL
*Relationship between signal name and pin
STREQI
: GP33/GP43/GP53
STBCKI
: GP31/GP41/GP51
Parameter
STBCKI Clock Frequency
Symbol
fSTBCI
STBCKI Input Start Time
tSTBCKIN
STBCKI "H" Period
STBCKI "L" Period
STDATO Output Delay
Time
tSTBCKH
tSTBCKL
tSTDODL
STDATO
Signal Names
STBCKI
STREQI,
STBCKI
STBCKI
STBCKI
STBCKI,
STDATO
: GP32/GP42/GP52
Min
Typ
Max
1.25
1000
ns
400
400
ns
ns
250
Note : Above diagram shows STBCKI is starting from “L”.
<Additional Information>
Clock input mode supports 2 types and data output timing changes as below accordingly ;
(1) Starting from STBCKI = "L"
STDATO will be output synchronizing with the rising edge of STBCKI.
(2) Starting from STBCKI = "H".
STDATO will be output synchronizing with the falling edge of SBCKI.
Using each mode of (1) or (2) does not change the output characteristics.
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unit
MHz
ns
LC786820E
Internal Voltage Regulator at Ta = 40 to 85C, DVSS = AVSS1 = AVSS2 = XVSS = 0 V
Parameter
Output Voltage
Load current
Symbol
DVDD12
Iope
Condition
VDD1 = 3.0 to 3.6 V
VDD1 = 3.3 V
Min
1.08
Typ
1.20
Max
1.32
200
Unit
V
mA
Note : The specification of “load current” above is sum of the load current of two internal voltage regulator.
Example of 1.2 V regulator circuit
LC786820E
* Same circuit need to be mounted both for two regulator pins.
(No.44 and No.87)
DVDD
* C1 is for capacitor to stop oscillation.
DVSS
DVDD12
There is a possibility of oscillation due to temperature change and etc., so C1
100 F
must be greater than 50 F and low ESR at the operational temperature.
(The recommended value is 100 F)
C1
Parameter
Output Voltage
Load current
Symbol
DVDD18
Iope
Condition
VDD1 = 3.0 to 3.6 V
VDD1 = 3.3 V
Min
Typ
Max
Unit
1.65
1.80
1.95
V
50
mA
Example of 1.8 V regulator circuit
LC786820E
* Build a circuit shown at left for the regulator pin No. 90.
* C1 is for capacitor to stop oscillation.
DVDD
There is a possibility of oscillation due to temperature change and etc., so C1
must be greater than 50 F and low ESR at the operational temperature.
DVSS
DVDD18
100 F
(The recommended value is 100 F)
C1
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29
LC786820E
Oscillator
Example circuit for Oscillator
LC786820E
XVDD
XIN
Rd1
XOUT
XVSS
C1
C1
 XIN / XOUT : 12.0000 MHz
 For System Main clock and USB control
 Recommended Oscillator
Nihon Dempa Kogyo Co., Ltd.
Type
NX3225GA
Frequency
12 MHz
Recommended constants
Rd1 = 1 kΩ, C1 = 12 pF
<Notes>
 Because the characteristics of oscillator could be changed according to the circuit board, ask evaluation with the
individual original circuit board to the oscillator maker.
 The precision of oscillator used in XIN / XOUT should meet the USB standard.
 If oscillation clock is disturbed by noise or by the other factors, it may lead to operation failure. Hence, make
sure to connect resistor and capacitor for oscillation circuit as close as XIN / XOUT and the wire should be as
short as possible. Also needs to select parts with caution so as to obtain stable external constant value within the
guaranteed operating temperature range because the variation of external constant due to temperature change
could affect the oscillation precision
 About internal circuit for XIN / XOUT, refer to the "Analog Pin Internal Equivalent Circuits" section
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30
LC786820E
PLL Circuit
Example of PLL circuit
LC786820E
VVDD2
AFILT
Rp1
Cp2
Cp1
 About PLL
LC786820E includes PLL1 and PLL2.
PLL1 is for generating system clock and PLL2 is for generating Audio clock.
 External filter constant for PLL2
PLL2 constant
Rp1 = 3.3 kΩ / Cp1 = 3300 pF / Cp2 = 220 pF
<Notes>
 This PLL filter circuit of resistor (Rp1) and capacitance (Cp1, Cp2), are for audio generation/system clock
generation connected to AFILT. If oscillation clock is disturbed by noise or by the other factors, it may lead
to operation failure. Hence, make sure to connect resistor and capacitor that constitute filter circuit as close as
AFILT and the wire should be as short as possible. Also if filter constant changes due to temperature change,
oscillation of PLL may become unstable and the following problem may occur:
Due to unstable audio playback clock, audio playback is affected with unstable audio signal input (ADC
operation) and output (various filter, DAC operation). Hence, needs to select parts with caution so as to obtain
stable filter constant value within the guaranteed operating temperature range.
 See section on "Analog Pin Internal Equivalent Circuits" for the internal configuration of AFILT
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LC786820E
Analog Pins Internal Equivalent Circuit
Pin Name
( ) shows pin #
Internal Equivalent Circuit
LFOUT (97)
LROUT (98)
RROUT (7)
RFOUT (8)
SWOUT (11)
LVRIN (99)
RVRIN (6)
SWIN (10)
DACOUTL (100)
DACOUTR (5)
DACOUTS (9)
L1IN (21)
R1IN (22)
L2IN (19)
R2IN (20)
L3INP (15)
L3INN (16)
R3INP (17)
R3INN (18)
VREF_ADC (12)
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LC786820E
Pin Name
( ) shows pin #
Internal Equivalent Circuit
XIN (74)
XOUT (75)
VVDD2
VVDD2
AFILT (77)
XVSS
LRREF (4)
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XVSS
LC786820E
Reference Circuit
VDD1
DVDD
DVSS
GP30
GP31
GP32
GP33
GP34
GP35
GP36
GP37
DVDD
DVSS
REG1EXTR
DVDD12_2
GP10
GP11
GP12
GP13
DVDD
DVSS
Host-I/F
Digital Audio
INPUT
To
USB2
From
Tuner,AUX
etc
DVSS
VVDD3
VVDD2
AFILT
XVSS
XOUT
XIN
XVDD
UDP1
UDM1
DVSS
UDP2
UDM2
DVDD
DVSS
GP47
GP46
GP45
GP44
GP43
GP42
GP41
GP40
GP03
BUSYB
SIFCE
SIFDO
SIFDI
SIFCK
RESB
To
USB1
NC
AVDD1
AVSS1
LRREF
DACOUTR
RVRIN
RROUT
RFOUT
DACOUTS
SWIN
SWOUT
VREF_ADC
AVSS2
AVDD2
L3INP
L3INN
R3INP
R3INN
L2IN
R2IN
L1IN
R1IN
TEST0
TEST1
DVDD18_2
GP15
GP50
GP51
GP52
GP53
LC786820
To PowerAMP
(Rch, SWch)
LVRIN
LROUT
LFOUT
JTRTCK
JTDO
JTMS
JTDI
JTCK
JTRSTB
DVDD18_1
DVSS
DVDD
DVDD12_1
GP14
GP07
GP06
GP05
GP04
DVDD
To PowerAMP
(Lch)
Serial-I/F
To SD-Card
GND


For analog audio input, it is necessary to consider the input level.
Please refer Page 21, Page 29 to 31 for the detail of USB/Regulator/oscillator reference circuit.
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34
LC786820E
ARM and the ARM logo are registered trademarks, and ARM7TDMI-S is a trademark of ARM Limited (or its subsidiaries) in the
EU and/or elsewhere.
* MP3 (MPEG Layer-3 Audio Coding)
MPEG Layer-3 audio coding technology licensed from Fraunhofer IIS and Thomson.
Supply of this product does not convey license under the relevant intellectual property of Thomson and/or Fraunhofer Gesellschaft nor
imply any right to use this product in any finished end user or ready-to-use final product. An independent license for such use is required.
For details, please visit http://mp3licensing.com/.
* WMA (Windows Media Audio)
TM
Windows Media is a trademark and a registered trademark in the United States and other countries of United States
Microsoft Corporation.
ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries
in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other
intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON
Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or
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responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or
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35