Microchip MCP2003BT-E/MC Lin transceiver Datasheet

MCP2003B
LIN Transceiver
Features
Description
• The MCP2003B is Compliant with Local
Interconnect Network (LIN) Bus Specifications
1.3, 2.0, 2.1, 2.2, SAE J2602, and ISO17987
• Supports Baud Rates up to 20 Kbaudwith
LIN-Compatible Output Driver
• 60V Load Dump Protected
• Very High Electromagnetic Immunity (EMI) Meets
Stringent Original Equipment Manufacturers
(OEM) Requirements
• Direct Capacitor Coupling Robustness without
Transient Voltage Suppressor (TVS):
- ±35V on LBUS (SAE J2962-1)
- ±85V on LBUS (SAE J2962-1)
• High Electrostatic Discharge (ESD)
Immunity without TVS:
- >25 kV on LBUS (SAE J2962-1)
- >15 kV on VBB (IEC 61000-4-2)
- >6 kV on LBUS (IEC 61000-4-2)
• Very High Immunity to RF Disturbances Meets
Stringent OEM Requirements
• Wide Supply Voltage: 5.5V – 30.0V Continuous
• Extended (E) Temperature Range: -40°C to +125°C
• High (H) Temperature Range: -40°C to +150°C
• Interfaces to PIC® MCU EUSART and Standard
USARTs
• LIN Bus Pin:
- Internal pull-up resistor and diode
- Protected against battery shorts
- Protected against loss of ground
- High current drive: >40 mA
• Automatic Thermal Shutdown
• Low-Power Mode:
- Receiver monitoring bus and transmitter off:
( 5 µA)
This device provides a bidirectional, half-duplex
communication, physical interface to automotive and
industrial LIN systems to meet the LIN Bus
Specification Revision 2.2, SAE J2602, and ISO
17987. The device is both short-circuit and
overtemperature protected by internal circuitry. The
device has been specifically designed to operate in the
automotive operating environment and will survive all
specified transient conditions while meeting all of the
stringent quiescent current requirements.
Package Types
MCP2003B
SOIC
RXD 1
8 VREN
CS 2
7 VBB
6 LBUS
5 VSS
WAKE 3
TXD 4
MCP2003B
2x3 DFN*
RXD 1
8 VREN
CS 2
7 VBB
EP
9
WAKE 3
TXD 4
6 LBUS
5 VSS
MCP2003B
3x3 DFN*
RXD 1
CS 2
WAKE 3
TXD 4
8 VREN
EP
9
7 VBB
6 LBUS
5 VSS
* Includes Exposed Thermal Pad (EP); see Table 1-2.
 2015-2016 Microchip Technology Inc.
DS20005463C-page 1
MCP2003B
MCP2003B Block Diagram
DS20005463C-page 2
 2015-2016 Microchip Technology Inc.
MCP2003B
1.0
DEVICE OVERVIEW
The MCP2003B devices provide a physical interface
between a microcontroller and a LIN bus. These
devices will translate the CMOS/TTL logic levels to LIN
logic level, and vice versa. It is intended for automotive
and industrial applications with serial bus speeds up to
20 Kbaud.
LIN Bus Specification Revision 2.2 requires that the
transceiver of all nodes in the system is connected via
the LIN pin, referenced to ground and with a maximum
external termination resistance load of 510 from LIN
bus to battery supply. The 510 corresponds to
1 master and 15 slave nodes.
The VREN pin can be used to drive the logic input of an
external voltage regulator. This pin is high in all modes
except for Power-Down mode.
1.1
1.1.1
External Protection
REVERSE BATTERY PROTECTION
An external reverse-battery-blocking diode should be
used to provide polarity protection (see Example 1-1).
1.1.2
TRANSIENT VOLTAGE
PROTECTION (LOAD DUMP)
An external 60V transient suppressor (TVS) diode,
between VBB and ground, with a 50 transient
protection resistor (RTP) in series with the battery
supply and the VBB pin serve to protect the device from
power transients (see Example 1-1) and ESD events.
While this protection is optional, it is considered good
engineering practice.
1.2
1.2.1
Internal Protection
ESD PROTECTION
For component-level ESD ratings, please refer to the
maximum operation specifications.
1.2.2
GROUND LOSS PROTECTION
The LIN Bus specification states that the LIN pin must
transition to the recessive state when ground is
disconnected. Therefore, a loss of ground effectively
forces the LIN line to a high-impedance level.
1.2.3
THERMAL PROTECTION
The thermal protection circuit monitors the die
temperature and is able to shut down the LIN
transmitter.
There are two causes for a thermal overload. A thermal
shutdown can be triggered by either, or both, of the
following thermal overload conditions.
• LIN bus output overload
• Increase in die temperature due to increase in
environment temperature
Driving the TXD and checking the RXD pin makes it
possible to determine whether there is a bus contention
(RX = low, TX = high) or a thermal overload condition
(RX = high, TX = low). After a thermal overload event,
the device will automatically recover once the die
temperature has fallen below the recovery temperature
threshold (see Figure 1-1).
FIGURE 1-1:
THERMAL SHUTDOWN
STATE DIAGRAM
Shorted LIN bus
to VBB
Operation
Transmitter
Mode
Shutdown
Temp < ShutdownTEMP
 2015-2016 Microchip Technology Inc.
DS20005463C-page 3
MCP2003B
1.3
Modes of Operation
For an overview of all operational modes, refer to
Table 1-1.
1.3.1
The device will go into Power-Down mode on the falling
edge of CS, or return to Operation mode if all faults are
resolved.
POWER-DOWN MODE
In Power-Down mode, everything is off except the
wake-up section. The internal 30 k pull-up resistor
switch is open, which enables the high ohmic pull-up
resistor (900 k typical). This is the lowest power
mode. The receiver is off, thus its output is open-drain.
On CS going to a high level or a falling edge on WAKE,
the device will enter Ready mode as soon as internal
voltage stabilizes. Refer to Section 2.4 “AC
Specifications” for further information. In addition, LIN
bus activity will change the device from Power-Down
mode to Ready mode; The MCP2003B wakes up on a
rising edge on LBUS preceded by a low level lasting at
least 70 µs typically. See Figure 1-2 about remote
wake-up. If CS is held high as the device transitions
from Power-Down to Ready mode, the device will
transition to either Operation or Transmitter Off mode,
depending on TXD input, as soon as internal voltages
stabilize.
1.3.2
READY MODE
Transitioning from POR into Ready mode is achieved
when VBB > VBBUV_RISE. Upon entering Ready mode,
VREN is enabled and the receiver detect circuit is
powered-up. The transmitter remains disabled and the
device is ready to receive data but not to transmit.
Upon VBB supply pin power-on, the device will remain
in Ready mode as long as CS is low. When CS
transitions high, the device will either enter Operation
mode if the TXD pin is held high, or the device will enter
Transmitter Off mode if the TXD pin is held low.
1.3.3
OPERATION MODE
In this mode, all internal modules are operational. Note
that the part cannot transmit if the pull-up resistance is
missing on RX pin. See Section 1.5.1.1 “RXD
Monitoring” for details.
The device will go into Power-Down mode on the falling
edge of CS and the TXD pin is held high. The device will
enter Transmitter Off mode in the event of a Fault condition such as thermal overload, bus contention or TXD
timer expiration.
The VBB to LBUS ~30 kΩ pull-up resistor (RSLAVE) is
connected only in Operation mode.
1.3.4
TRANSMITTER OFF MODE
Transmitter Off mode is reached whenever the
transmitter is disabled due to a Fault condition. Fault
conditions include thermal overload, bus contention,
RXD monitoring and TXD timer expiration.
DS20005463C-page 4
 2015-2016 Microchip Technology Inc.
MCP2003B
FIGURE 1-2:
OPERATIONAL MODES STATE DIAGRAM – MCP2003B
POR
VREN OFF
RX OFF
TX OFF
RPU switch OFF
Rising Edge on LBUS or
CS = 1 or
Falling Edge on WAKE pin
V BAT > V BBUV_RISE
Ready Mode
VREN ON
RX ON
TX OFF
RPU switch OFF
TOFF Mode
VREN ON
RX ON
TX OFF
RPU switch OFF
TXD = 1 And CS = 1
NO Fault,
And RXD > 2.5V while LBUS recessive(1)
Fault:
Thermal or Timer
Operation Mode
VREN ON
RX ON
TX ON
RPU switch ON
Power-Down
Mode
VREN OFF
RX OFF
TX OFF
RPU switch OFF
Note 1: Achieved via pull-up resistor on RXD (See Example 1-1)
TABLE 1-1:
State
OVERVIEW OF OPERATIONAL MODES
Transmitter Receiver VREN
Operation
Comments
POR
OFF
OFF
OFF
Check CS: if low, then proceed to Ready mode;
If high, transition to either TOFF or Operation mode,
depending on TXD.
VBB > VBB(MIN) and
Internal Supply stable.
High ohmic pull-up resistor
enabled (900 k typical).
Ready
OFF
ON
ON
On CS high level, proceed to Operation or TOFF mode.
Bus Off state.
High ohmic pull-up resistor
enabled (900 k typical).
Operation
ON
ON
ON
On CS low level, proceed to Power-Down.
On a fault condition, proceed to TOFF mode.
Normal Operation mode.
RXD has to be at a high
level (>2.5V typical) while
LBUS is recessive.
Power-Down
OFF
Activity
Detect
OFF
On CS high level, proceed to Ready mode then
proceed to either Operation or TOFF mode.
Falling edge on WAKE will put the device into
Ready mode.
Rising edge on LIN bus will put the device into
Ready mode.
Low-Power mode.
High ohmic pull-up resistor
enabled (900 k typical).
Transmitter
Off
OFF
ON
ON
On CS low level, proceed to Power-Down mode;
On TXD high and no fault condition, proceed to
Operation mode.
High ohmic pull-up resistor
enabled (900k typical).
 2015-2016 Microchip Technology Inc.
DS20005463C-page 5
MCP2003B
1.4
Typical Applications
EXAMPLE 1-1:
TYPICAL MCP2003B APPLICATION
VBAT
optional resistor and transient suppressor
VBAT
50
60V
(Note 1)
3.9 k
VDD
(2)
4.7 k
1.0 µF
Voltage Reg
VREN
TXD
TXD
RXD
RXD
I/O
Master Node Only
VBAT
VBB
1 k
LIN Bus
LBUS
CS
33 k
WAKE
220 pF
Wake-up
VSS
Note 1: For applications with current requirements of less than 20 mA, the connection to VBAT can be
deleted, and voltage to the regulator supplied directly from the VREN pin.
2: Required for transmission.
3: A Transient Voltage Suppressor on the LIN Bus is not required to sustain SAE J2962-1 ESD
and Direct Capacitor Coupling tests.
EXAMPLE 1-2:
TYPICAL LIN NETWORK CONFIGURATION
40m
+ Return
LIN bus
VBB
1 k
LIN bus
MCP2003B
LIN bus
MCP2003B
Slave 1
(MCU)
LIN bus
MCP2003B
LIN bus
MCP2003B
Slave 2
(MCU)
Slave n <23
(MCU)
Master
(MCU)
DS20005463C-page 6
 2015-2016 Microchip Technology Inc.
MCP2003B
1.5
Pin Descriptions
TABLE 1-2:
PINOUT DESCRIPTIONS
Pin Name
8-Lead
SOIC
2x3 DFN
3x3 DFN
1
1
1
RXD
Normal Operation
Receive Data Output (OD), HV tolerant
CS
2
2
2
Chip Select (TTL), HV tolerant
WAKE
3
3
3
Wake-up, HV tolerant
TXD
4
4
4
Transmit Data Input (TTL), HV tolerant
VSS
5
5
5
Ground
LBUS
6
6
6
LIN Bus (bidirectional)
VBB
7
7
7
Battery Positive
VREN
8
8
8
Voltage Regulator Enable Output
EP
—
9
9
Exposed Thermal Pad. Do not electrically
connect or connect to Vss.
Legend: TTL = TTL Input Buffer; OD = Open-Drain Output
1.5.1
RECEIVE DATA OUTPUT (RXD)
The Receive Data Output pin is an open-drain (OD)
output and follows the state of the LIN pin, except in
Power-Down mode.
1.5.1.1
RXD Monitoring
The RXD pin is internally monitored. It has to be at a
high level (> 2.5V typical) while LBUS is recessive in
Operation mode. Otherwise, an internal fault will be
created and the device will transition to Transmitter Off
mode.
Note:
1.5.2
A voltage regulator sensing circuit is
connected to RXD. This sensing circuit
internally monitors the RXD pin when
LBUS is recessive (RXD = 1). It will not
allow the device to switch (or stay) in
Operation Mode if the RXD pin is left
open. The RXD pin must be connected to
a valid supply through a pull-up resistor as
RXD is an open drain pin.
If CS = 1 when the VBB supply is turned on, the device
will proceed to Operation mode, or TXOFF (refer to
Figure 1-2), as soon as internal voltages stabilize.
This pin may also be used as a local wake-up input
(refer to Example 1-1). In this implementation, the
microcontroller I/O controlling the CS should be
converted to a high-impedance input allowing the
internal pull-down resistor to keep CS low. An external
switch, or other source, can then wake-up both the
transceiver and the microcontroller (if powered). Refer
to Section 1.3 “Modes of Operation”, for detailed
operation of CS.
Note:
CHIP SELECT (CS)
This is the Chip Select Input pin. An internal pull-down
resistor will keep the CS pin low. This is done to ensure
that no disruptive data will be present on the bus while
the microcontroller is executing a Power-on Reset and
an I/O initialization sequence. The pin must detect a
high level to activate the transmitter. An internal LowPass filter, with a typical time constant of 10 µs,
prevents unwanted wake-up (or transition to PowerDown mode) on glitches.
If CS = 0 when the VBB supply is turned on, the device
goes to Ready mode as soon as internal voltages stabilize, and stays there as long as the CS pin is held low
(0). In Ready mode, the receiver is on and the LIN
transmitter driver is off.
 2015-2016 Microchip Technology Inc.
1.5.3
It is not recommended to tie CS high, as
this can result in the device entering
Operation
mode
before
the
microcontroller is initialized and may
result in unintentional LIN traffic. The CS
pin is internally pulled down to ground with
190 k when CS is less than VIL, and
2 M when CS is greater than VIH. The
current on CS is limited to about 2 µA
when CS is greater than VIH.
WAKE-UP INPUT (WAKE)
The WAKE pin has an internal 800 kΩ pull-up to VBB.
A falling edge on the WAKE pin causes the device to
wake from Power-Down mode. Upon waking, the
MCP2003B will enter Ready mode.
1.5.4
TRANSMIT DATA INPUT (TXD)
The Transmit Data Input pin has an internal pull-up.
The LIN pin is low (dominant) when TXD is low, and high
(recessive) when TXD is high.
For extra bus security, TXD is internally forced to ‘1’
whenever the transmitter is disabled, regardless of
external TXD voltage.
DS20005463C-page 7
MCP2003B
1.5.4.1
TXD Dominant Timeout
If TXD is driven low for longer than approximately
25 ms, the LBUS pin is switched to Recessive mode and
the part enters TOFF Mode. This is to prevent the LIN
node from permanently driving the LIN Bus dominant.
The transmitter is reenabled on TXD rising edge.
1.5.5
GROUND (VSS)
This is the Ground pin.
1.5.6
LIN BUS (LBUS)
The bidirectional LIN Bus pin (LBUS) is controlled by the
TXD input. LBUS has a current limited open collector
output. To reduce EMI, the edges during the signal
changes are slope controlled and include corner
rounding control for both falling and rising edges.
The internal LIN receiver observes the activities on the
LIN bus, and matches the output signal RXD to follow
the state of the LBUS pin.
1.5.6.1
Bus Dominant Timer
The Bus Dominant Timer is an internal timer that
deactivates the LBUS transmitter after approximately
25 ms of dominant state on the LBUS pin. The timer is
reset on any recessive LBUS state.
The LIN bus transmitter will be reenabled after a
recessive state on the LBUS pin as long as CS is high.
Disabling can be caused by the LIN bus being
externally held dominant, or by TXD being driven low.
1.5.7
BATTERY (VBB)
This is the Battery Positive Supply Voltage pin.
1.5.8
VOLTAGE REGULATOR ENABLE
OUTPUT (VREN)
This is the External Voltage Regulator Enable pin.
Open-drain output is pulled high to VBB in all modes
except Power-Down.
1.5.9
EXPOSED THERMAL PAD (EP)
Do not electrically connect, or connect to VSS.
DS20005463C-page 8
 2015-2016 Microchip Technology Inc.
MCP2003B
2.0
ELECTRICAL CHARACTERISTICS
2.1
Absolute Maximum Ratings†
VIN DC Voltage on RXD, TXD, CS ...................................................................................................................-0.3 to +50V
VIN DC Voltage on WAKE and VREN ..............................................................................................................-0.3 to +VBB
VBB Battery Voltage, continuous, non-operating(1) ........................................................................................-0.3 to +50V
VBB Battery Voltage, non-operating (LIN bus recessive)(2) ............................................................................-0.3 to +60V
VBB Battery Voltage, transient ISO 7637 Test 1 ......................................................................................................-200V
VBB Battery Voltage, transient ISO 7637 Test 2a ...................................................................................................+150V
VBB Battery Voltage, transient ISO 7637 Test 3a ....................................................................................................-300V
VBB Battery Voltage, transient ISO 7637 Test 3b ...................................................................................................+200V
VLBUS Bus Voltage, continuous.......................................................................................................................-18 to +50V
VLBUS Bus Voltage, transient(3) .......................................................................................................................-27 to +60V
VLBUS Bus Voltage, Direct Capacitor Coupling without TVS (SAE J2962-1) ........................................... ±35V and ±85V
ILBUS Bus Short-Circuit Current Limit....................................................................................................................200 mA
ESD protection on LIN, without TVS (SAE J2962-1) ............................................................................................. ±25 kV
ESD protection on LIN, VBB, WAKE (IEC 61000-4-2)(4) .......................................................................................... ±6 kV
ESD protection on LIN, VBB, WAKE, CS (Human Body Model)(5) ........................................................................... ±8 kV
ESD protection on all other pins (Human Body Model)(5) ........................................................................................ ±4 kV
ESD protection on all pins (Charge Device Model)(6) .............................................................................................. ±2 kV
ESD protection on all pins (Machine Model)(7) .......................................................................................................±400V
Maximum Junction Temperature ........................................................................................................................... +150C
Storage Temperature .................................................................................................................................. -65 to +150C
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device, at those or any other conditions above those
indicated in the operational listings of this specification, is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note 1: LIN 2.x compliant specification.
2: SAE J2602 compliant specification.
3: ISO 7637/1 load dump compliant (t < 500 ms).
4: According to IEC 61000-4-2, 330, 150 pF and Transceiver EMC Test Specifications [2] to [4]. For WAKE
pin to meet the specification, series resistor must be in place (refer to Example 1-2).
5: According to AEC-Q100-002/JESD22-A114.
6: According to AEC-Q100-011B.
7: According to AEC-Q100-003/JESD22-A115.
 2015-2016 Microchip Technology Inc.
DS20005463C-page 9
MCP2003B
2.2
Nomenclature Used in This Document
Some terms and names used in this data sheet deviate from those referred to in the LIN specifications. Equivalent
values are shown in Table 2-1.
TABLE 2-1:
EQUIVALENT VALUES
LIN specifications Name
Term used in the following tables
VBAT
not used
VSUP
VBB
Supply voltage at device pin
IBUS_LIM
ISC
Current Limit of driver
VBUSREC
VIH(LBUS)
Recessive state
VBUSDOM
VIL(LBUS)
Dominant state
2.3
Definition
ECU operating voltage
DC Specifications
DC Specifications
Parameter
Electrical Characteristics: Unless otherwise indicated, all limits are specified for
VBB = 5.5V to 30.0V
Extended (E): TA = -40°C to +125°C
High (H): TA = -40°C to +150°C
Sym.
Min.
Typ.
Max.
Units
Conditions
IBBQ
—
65
150
µA
Operating Mode,
bus recessive
—
—
160
µA
VBB > 18V
—
60
120
µA
Transmitter off,
bus recessive
—
—
130
µA
VBB > 18V
—
6
15
µA
—
—
20
µA
VBB > 18V
—
14
20
µA
LIN bus shorted to GND
VLIN = 0V, VBB < 12V
IBBNOGND
-1
—
1
mA
VBB = 12V, GND to VBB,
VLIN = 0-27V
VBB Undervoltage
Threshold (switching from
Operation mode to TOFF
and VREN OFF)
VBBUV_FALL
3.8
4
4.4
V
VBB falling (Note 3)
VBB Undervoltage
Recovery Threshold
(switching from POR to
Ready mode)
VBBUV_RISE
5.5
5.6
6.0
V
VBB rising (Note 3)
High-Level Input Voltage
(TXD)
VIH
2.0
—
30
V
Low-Level Input Voltage
(TXD)
VIL
-0.3
—
0.8
V
High-Level Input Current
(TXD)
IIH
-5
—
—
µA
Power
VBB Quiescent Operating
Current
VBB Transmitter-off Current
VBB Power-Down Current
VBB Current
with VSS Floating
IBBTO
IBBPD
Microcontroller Interface
Note 1:
2:
3:
Input voltage = 4.0V
Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0.4 VREG, VLBUS = VBB).
Node has to sustain the current that can flow under this condition; bus must be operational under this
condition.
Characterized; not 100% tested.
DS20005463C-page 10
 2015-2016 Microchip Technology Inc.
MCP2003B
2.3
DC Specifications (Continued)
DC Specifications
Parameter
Electrical Characteristics: Unless otherwise indicated, all limits are specified for
VBB = 5.5V to 30.0V
Extended (E): TA = -40°C to +125°C
High (H): TA = -40°C to +150°C
Sym.
Min.
Typ.
Max.
Units
IIL
-12
—
—
µA
High-Level Voltage (VREN)
VHVREN
-0.3
—
VBB + 0.3
V
High-Level Output Current
(VREN)
IHVREN
-40
—
-5
mA
Low-Level Input Current
(TXD)
Conditions
Input voltage = 0.5V
Output voltage = VBB - 0.5V
-120
—
-20
High-Level Input Voltage
(CS)
VIH
2.0
—
30
V
Output voltage = VBB - 2.0V
Low-Level Input Voltage
(CS)
VIL
-0.3
—
0.8
V
High-Level Input Current
(CS)
IIH
—
—
10.0
µA
Input voltage = 4.0V
Low-Level Input Current
(CS)
IIL
—
—
7.0
µA
Input voltage = 0.5V
Low-Level Input Voltage
(WAKE)
VIL
VBB - 4.0V
—
—
V
High-Level Input Current
(WAKE)
IIH
-12
—
—
µA
-15
—
—
µA
Low-Level Input Current
(WAKE)
IIL
-30
—
—
µA
Through a current limiting
resistor
VBB > 18V
-45
—
—
µA
VBB > 18V
VOL
—
—
0.4
V
IIN = 2 mA
VTH(RXD)
—
2.5
—
V
RXD > VTH;
LBUS recessive in
Operating mode
IOH
-1
—
-1
µA
VLIN = VBB, VRXD = 5.5V
High-Level Input Voltage
VIH(LBUS)
0.6 VBB
—
—
V
Recessive state
Low-Level Input Voltage
VIL(LBUS)
-8
—
0.4 VBB
V
Dominant state
VHYS
—
—
0.175 VBB
V
VIH(LBUS) - VIL(LBUS)
IOL(LBUS)
40
—
200
mA
Output voltage = 0.2 VBB,
VBB = 12V
16.5
—
—
mA
Output voltage = 0.2 VBB,
VBB = 18V
—
—
20
µA
Low-Level Output Voltage
(RXD)
Input Threshold Level
(RXD)
High-Level Output Current
(RXD)
Bus Interface
Input Hysteresis
Low-Level Output Current
High-Level Output Current
IOH(LBUS)
Short-Circuit Current Limit
ISC
50
—
200
mA
High-Level Output Voltage
VOH(LBUS)
0.8 VBB
—
VBB
V
V_LOSUP
—
—
1.2
V
IBUS_PAS_DO
-1
-0.4
—
mA
Driver Dominant Voltage
Input Leakage Current
(at the receiver during
dominant bus level)
Note 1:
2:
3:
M
(Note 1)
RLOAD = 500
Driver off,
VBUS = 0V,
VBB = 12V
Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0.4 VREG, VLBUS = VBB).
Node has to sustain the current that can flow under this condition; bus must be operational under this
condition.
Characterized; not 100% tested.
 2015-2016 Microchip Technology Inc.
DS20005463C-page 11
MCP2003B
2.3
DC Specifications (Continued)
DC Specifications
Parameter
Electrical Characteristics: Unless otherwise indicated, all limits are specified for
VBB = 5.5V to 30.0V
Extended (E): TA = -40°C to +125°C
High (H): TA = -40°C to +150°C
Sym.
Min.
Typ.
Max.
Units
IBUS_PAS_REC
—
12
20
µA
Driver off,
8V < VBB < 18V
8V < VBUS < 18V
VBUS  VBB
Leakage Current
IBUS_NO_GND
(disconnected from ground)
-10
1.0
+10
µA
GNDDEVICE = VBB,
0V < VBUS < 18V,
VBB = 12V
Leakage Current
(disconnected from VBB)
IBUS_NO_VBB
—
—
10
µA
VBB = GND,
0 < VBUS < 18V,
(Note 2)
Receiver Center Voltage
VBUS_CNT
0.525 VBB
V
VBUS_CNT = (VIL (LBUS) +
VIH (LBUS))/2
Input Leakage Current
(at the receiver during
recessive bus level)
0.475 VBB 0.5 VBB
Slave Termination
RSLAVE
20
30
60
k
Capacitance of Slave Node
CSLAVE
—
—
100
pF
Note 1:
2:
3:
Conditions
(Note 3)
Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0, TX = 0.4 VREG, VLBUS = VBB).
Node has to sustain the current that can flow under this condition; bus must be operational under this
condition.
Characterized; not 100% tested.
DS20005463C-page 12
 2015-2016 Microchip Technology Inc.
MCP2003B
2.4
AC Specifications
AC Characteristics
Electrical Characteristics: Unless otherwise indicated, all limits are specified for
VBB = 5.5V to 27.0V
Extended (E): TA = -40°C to +125°C
High (H): TA = -40°C to +150°C
Parameter
Sym.
Min.
Typ.
Max.
Units
Test Conditions
Bus Interface – Constant Slope Time Parameters
Slope Rising and Falling Edges
Propagation Delay of
Transmitter
tSLOPE
3.5
—
22.5
µs
7.3V ≤ VBB ≤ 18V
tTRANSPD
—
—
4.0
µs
tTRANSPD = max (tTRANSPDR or
tTRANSPDF)
Propagation Delay of Receiver
tRECPD
—
—
6.0
µs
tRECPD = max (tRECPDR or tRECPDF)
Symmetry of Propagation
Delay of Receiver Rising Edge
w.r.t. Falling Edge
tRECSYM
-2.0
—
2.0
µs
tRECSYM = max (tRECPDF - tRECPDR)
RRXD 2.4 to VCC, CRXD 20 pF
tTRANSSYM
-2.0
—
2.0
µs
tTRANSSYM = max (tTRANSPDF - tTRANSPDR)
Duty Cycle 1 @20.0 kbit/sec
0.396
—
—
—
CBUS; RBUS conditions:
1 nF; 1 k | 6.8 nF; 660 | 10 nF; 500
THREC(MAX) = 0.744 × VBB,
THDOM(MAX) = 0.581 × VBB,
VBB =7.0V - 18V; tBIT = 50 µs
D1 = tBUS_REC(MIN)/2 × tBIT)
Duty Cycle 2 @20.0 kbit/sec
—
—
0.581
—
CBUS; RBUS conditions:
1 nF; 1 k | 6.8 nF; 660 | 10 nF; 500
THREC(MAX) = 0.284 × VBB,
THDOM(MAX) = 0.422 × VBB,
VBB =7.6V - 18V; tBIT = 50 µs
D2 = tBUS_REC(MAX)/2 × tBIT)
Duty Cycle 3 @10.4 kbit/sec
0.417
—
—
—
CBUS; RBUS conditions:
1 nF; 1 k | 6.8 nF; 660 | 10 nF; 500
THREC(MAX) = 0.778 × VBB,
THDOM(MAX) = 0.616 × VBB,
VBB =7.0V – 18V; tBIT = 96 µs
D3 = tBUS_REC(MIN)/2 × tBIT)
Duty Cycle 4 @10.4 kbit/sec
—
—
0.590
—
CBUS; RBUS conditions:
1 nF; 1 k | 6.8 nF; 660 | 10 nF; 500
THREC(max) = 0.251 × VBB,
THDOM(MAX) = 0.389 × VBB,
VBB =7.6V – 18V; tBIT = 96 µs
D4 = tBUS_REC(MAX)/2 × tBIT)
tBDB
30
70
125
µs
tBACTVE
10
60
110
µs
WAKE to VREN on
tWAKE
—
—
150
µs
Chip Select to VREN on
tCSOR
—
—
150
µs
VREN floating
Chip Select to VREN off
tCSPD
—
—
200
µs
VREN floating
Symmetry of Propagation
Delay of Transmitter Rising
Edge w.r.t. Falling Edge
Wake-up Timing
Bus Activity Debounce time
Bus Activity to VREN on
 2015-2016 Microchip Technology Inc.
DS20005463C-page 13
MCP2003B
2.5
Thermal Specifications
Parameter
Symbol
Typ.
Max.
Units
Recovery Temperature
RECOVERY
+160
—
C
Shutdown Temperature
SHUTDOWN
+180
—
C
tTHERM
1.5
5.0
ms
Thermal Resistance, 2x3 8L-DFN
JA
75
—
C/W
Thermal Resistance, 3x3 8L-DFN
JA
56.7
—
C/W
Thermal Resistance, 8L-SOIC
JA
149.5
—
C/W
Short-Circuit Recovery Time
Test Conditions
Thermal Package Resistances
Note 1:
The maximum power dissipation is a function of TJMAX, JA and ambient temperature TA. The maximum
allowable power dissipation at an ambient temperature is PD = (TJMAX - TA)JA. If this dissipation is
exceeded, the die temperature will rise above 150C and the device will go into thermal shutdown.
DS20005463C-page 14
 2015-2016 Microchip Technology Inc.
MCP2003B
2.6
Typical Performance Curves
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VBB = 5.5V to 18.0V, Extended (E): TA = -40°C to +125°C and
High (H): TA = -40°C to +150°C.
150
Current (μA)
125
-45
-10
130
150
25
5.5
6
100
75
50
25
0
7
12
VBB (V)
FIGURE 2-1:
15.0
Current (μA)
12.5
-45
130
18
27
30
27
30
Typical IBBQ.
-10
150
25
10.0
7.5
5.0
2.5
0.0
5.5
6
7
12
VBB (V)
FIGURE 2-2:
120
Current (μA)
100
-45
130
18
Typical IBBPD.
-10
150
25
80
60
40
20
0
5.5
FIGURE 2-3:
6
7
12
VBB (V)
18
27
30
Typical IBBTO.
 2015-2016 Microchip Technology Inc.
DS20005463C-page 15
MCP2003B
2.7
Timing Diagrams and Specifications
FIGURE 2-4:
BUS TIMING DIAGRAM
TXD
50%
50%
LBUS
.95VLBUS
.50VBB
0.05VLBUS
TTRANSPDR
TTRANSPDF
TRECPDF
0.0V
TRECPDR
RXD
50%
50%
CS TO VREN TIMING DIAGRAM
FIGURE 2-5:
CS
TCSOR
VBB
VREN
OFF
TCSPD
FIGURE 2-6:
REMOTE WAKE-UP
LBUS
0.4VBB
tBDB
tBACTIVE
VBB
VREN
DS20005463C-page 16
 2015-2016 Microchip Technology Inc.
MCP2003B
3.0
PACKAGING INFORMATION
3.1
Package Marking Information
Examples:
8-Lead DFN (2x3)
Device
Code
MCP2003B-E/MC
ADP
MCP2003BT-E/MC
ADP
MCP2003B-H/MC
ADR
MCP2003BT-H/MC
ADR
ADP
613
25
Examples:
8-Lead DFN (3x3)
8-Lead SOIC (150 mil)
Device
Code
MCP2003B-E/MF
DAEC
MCP2003BT-E/MF
DAEC
MCP2003B-H/MF
DAEE
MCP2003BT-H/MF
DAEE
DAEC
1613
256
Examples:
MCP2003B
SN^^^1613
e3
256
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
NNN
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
 2015-2016 Microchip Technology Inc.
DS20005463C-page 17
MCP2003B
'
!""#$%&
2% & %! % *
%% 133)))& &3
" )
* ' % *
$ % % " %
e
D
b
N
N
L
K
E2
E
EXPOSED PAD
NOTE 1
NOTE 1
2
1
2
1
D2
BOTTOM VIEW
TOP VIEW
A
A3
A1
NOTE 2
4%
& 5&%
6!&( $
55,,
6
6
67
8
9
%
./0
7 : %
9
% "$$
.
0% %*
+
,2
7 5 %
/0
7 ;"%
,
,# " "5 %
+
<
,# " ";"%
,
.
<
.
(
.
+
5
+
.
=
<
<
0% %;"%
0% %5 %
0% % % ,# " "
+/0
'
! " #$ %! & '(!%&! %( % ")%% % " *
& & # "% ( % " + *
) ! % "
& "% ,-.
/01 / & % # % ! ))%!%% ,21 $ & '! ! )%!%% '$$& % ! ..
) 0 +0
DS20005463C-page 18
 2015-2016 Microchip Technology Inc.
MCP2003B
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2015-2016 Microchip Technology Inc.
DS20005463C-page 19
MCP2003B
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005463C-page 20
 2015-2016 Microchip Technology Inc.
MCP2003B
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2015-2016 Microchip Technology Inc.
DS20005463C-page 21
MCP2003B
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005463C-page 22
 2015-2016 Microchip Technology Inc.
MCP2003B
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2015-2016 Microchip Technology Inc.
DS20005463C-page 23
MCP2003B
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005463C-page 24
 2015-2016 Microchip Technology Inc.
MCP2003B
'
(" ) *(++, !""#$%()-&
2% & %! % *
%% 133)))& &3
 2015-2016 Microchip Technology Inc.
" )
* ' % *
$ % % " %
DS20005463C-page 25
MCP2003B
NOTES:
DS20005463C-page 26
 2015-2016 Microchip Technology Inc.
MCP2003B
APPENDIX A:
REVISION HISTORY
Revision C (April 2016)
The following is the list of modifications:
•
•
•
•
•
Updated MCP2003B Block Diagram.
Updated Section 1.3.1, Power-Down Mode.
Updated Figure 1-2.
Updated Table 1-1.
Added VBBUV_FALL, VBBUV_RISE and updated
IBBPD.
Revision B (December 2015)
The following is the list of modifications:
• Included Features and Electrical Characteristics
for the SAE J2962-1.
• Minor typographical changes.
Revision A (November 2015)
• Original release of this document.
 2015-2016 Microchip Technology Inc.
DS20005463C-page 27
MCP2003B
NOTES:
DS20005463C-page 28
 2015-2016 Microchip Technology Inc.
MCP2003B
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
/XX
Device
Temperature
Range
Package
Device:
MCP2003B: LIN Transceiver
MCP2003BT: LIN Transceiver (Tape and Reel)
Temperature Range: E
H
Package:
= -40°C to +125°C (Extended)
= -40°C to +150°C (High)
MC = 8-Lead Plastic Dual Flat, No Lead Package –
2x3x0.9 mm Body (DFN)
MF = 8-Lead Plastic Dual Flat, No Lead Package –
3x3x0.9 mm Body (DFN)
SN = 8-Lead Plastic Small Outline – Narrow 3.90 mm Body
(SOIC)
 2015-2016 Microchip Technology Inc.
Examples:
a)
MCP2003B-E/MC: Extended Temperature,
8LD 2x3 DFN package
b)
MCP2003B-E/MF:
Extended Temperature,
8LD 3x3 DFN package
c)
MCP2003B-E/SN:
Extended Temperature,
8LD SOIC package
d)
MCP2003BT-H/MC: Tape and Reel,
High Temperature,
8LD 2x3 DFN package
e)
MCP2003BT-H/MF: Tape and Reel,
High Temperature,
8LD 3x3 DFN package
f)
MCP2003BT-H/SN: Tape and Reel,
High Temperature,
8LD SOIC package
DS20005463C-page 29
MCP2003B
NOTES:
DS20005463C-page 30
 2015-2016 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2015-2016 Microchip Technology Inc.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2015-2016, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0505-4
DS20005463C-page 31
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
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Tel: 86-592-2388138
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Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
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Tel: 33-1-69-53-63-20
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Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
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Tel: 852-2943-5100
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Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
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Fax: 86-10-8528-2104
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Tel: 949-462-9523
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Tel: 49-89-627-144-0
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Tel: 39-0331-742611
Fax: 39-0331-466781
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Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
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Tel: 39-049-7625286
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Tel: 82-53-744-4301
Fax: 82-53-744-4302
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
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Tel: 86-532-8502-7355
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Malaysia - Penang
Tel: 60-4-227-8870
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Tel: 86-21-5407-5533
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Tel: 65-6334-8870
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Tel: 86-755-8864-2200
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Tel: 886-3-5778-366
Fax: 886-3-5770-955
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Tel: 86-27-5980-5300
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Taiwan - Kaohsiung
Tel: 886-7-213-7828
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Tel: 86-29-8833-7252
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Poland - Warsaw
Tel: 48-22-3325737
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Tel: 34-91-708-08-90
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Tel: 44-118-921-5800
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Fax: 66-2-694-1350
07/14/15
DS20005463C-page 32
 2015-2016 Microchip Technology Inc.