Sample & Buy Product Folder Technical Documents Support & Community Tools & Software SN54LVC08A, SN74LVC08A SCAS283S – JANUARY 1993 – REVISED AUGUST 2015 SN74LVC08A Quadruple 2-Input Positive-AND Gates 1 Features 2 Applications • • • • • • • 1 • • • • • • • Operate From 1.65 V to 3.6 V Specified From –40°C to 85°C, –40°C to 125°C, and –55°C to 125°C Inputs Accept Voltages to 5.5 V Max tpd of 4.1 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C Ioff Support Live Insertion, Partial-Power-Down Mode and Back-Drive Protection Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) – On Products Compliant to MIL-PRF-38535, All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters. Servers LED Displays Network Switches I/O expanders Base station processor board 3 Description The SN54LVC08A gate is designed for the SN74LVC08A gate is designed for quadruple 2-input positive-AND 2.7-V to 3.6-V VCC operation, and quadruple 2-input positive-AND 1.65-V to 3.6-V VCC operation. The LVC08A devices perform the Boolean function Y + A • B or Y + A ) B in positive logic. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. Device Information(1) PART NUMBER SNJ54LVC08A SN74LVC08A PACKAGE BODY SIZE (NOM) CFP (14) 9.21 mm × 5.97 mm CDIP (14) 19.56 mm × 6.92 mm LCCC (20) 8.89 mm × 8.89 mm VQFN (14) 3.50 mm × 3.50 mm TSSOP (14) 5.00 mm × 4.40 mm SOP (14) 10.30 mm × 5.30 mm SOIC (14) 8.65 mm × 3.91 mm SSOP (14) 6.20 mm × 5.30 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram, Each Gate (Positive Logic) A B Y 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN54LVC08A, SN74LVC08A SCAS283S – JANUARY 1993 – REVISED AUGUST 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Options....................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 5 7.1 Absolute Maximum Ratings ..................................... 7.2 ESD Ratings.............................................................. 7.3 Recommended Operating Conditions for SN54LVC08A ............................................................ 7.4 Recommended Operating Conditions for SN74LVC08A ............................................................ 7.5 Thermal Information .................................................. 7.6 Electrical Characteristics for SN54LVC08A .............. 7.7 Electrical Characteristics for SN74LVC08A .............. 7.8 Switching Characteristics for SN54LVC08A ............. 7.9 Switching Characteristics for SN74LVC08A ............. 7.10 Operating Characteristics........................................ 7.11 Typical Characteristics ............................................ 5 5 9 Detailed Description ............................................ 10 9.1 9.2 9.3 9.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 10 10 10 10 10 Application and Implementation........................ 11 10.1 Application Information.......................................... 11 10.2 Typical Application ............................................... 11 11 Power Supply Recommendations ..................... 12 12 Layout................................................................... 12 5 12.1 Layout Guidelines ................................................. 12 12.2 Layout Examples................................................... 12 6 6 7 7 7 8 8 8 13 Device and Documentation Support ................. 13 13.1 13.2 13.3 13.4 13.5 Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 13 13 13 13 13 14 Mechanical, Packaging, and Orderable Information ........................................................... 13 Parameter Measurement Information .................. 9 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision R (June 2015) to Revision S • Page Added TJ junction temperature spec to Abs Max Ratings ..................................................................................................... 5 Changes from Revision Q (November 2010) to Revision R Page • Updated document to new TI data sheet format - no specification changes. ........................................................................ 1 • Added Applications, Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ...................................................................................................................... 1 • Added Military Disclaimer to Features.................................................................................................................................... 1 • Added Thermal Information table ........................................................................................................................................... 6 2 Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: SN54LVC08A SN74LVC08A SN54LVC08A, SN74LVC08A www.ti.com SCAS283S – JANUARY 1993 – REVISED AUGUST 2015 5 Device Options PACKAGE BODY SIZE SNJ54LVC08AW PART NUMBER CFP (14) 9.21 mm × 5.97 mm SNJ54LVC08AJ CDIP (14) 19.56 mm × 6.92 mm SNJ54LVC08AFK LCCC (20) 8.89 mm × 8.89 mm SN74LVC08ARGYR VQFN (14) 3.50 mm × 3.50 mm TSSOP (14) 5.00 mm × 4.40 mm SOP (14) 10.30 mm × 5.30 mm SOIC (14) 8.65 mm × 3.91 mm SSOP (14) 6.20 mm × 5.30 mm SN74LVC08APW SN74LVC08APWT SN74LVC08APWG3 SN74LVC08ANSR SN74LVC08AD SN74LVC08ADT SN74LVC08ADRG3 SN74LVC08ADBR Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: SN54LVC08A SN74LVC08A Submit Documentation Feedback 3 SN54LVC08A, SN74LVC08A SCAS283S – JANUARY 1993 – REVISED AUGUST 2015 www.ti.com 6 Pin Configuration and Functions D, DB, NS, J, W, or PW Package 14-Pin SOIC, SSOP, SOP, CDIP, or TSSOP Top View 3 12 4 5 11 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y 2A 2B 2Y VCC 13 1 14 2 13 4B 3 12 4A 4 11 4Y 5 10 3B 9 3A 6 7 8 3Y 14 2 1A 1 GND 1A 1B 1Y 2A 2B 2Y GND RGY Package 14-Pin VQFN Top View 1B 1A NC VCC 4B FK Package 20-Pin LCCC Top View 3 2 4 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A 1Y NC 2A NC 2B Pin Functions PIN SOIC, SSOP, SOP, CDIP, or TSSOP LCCC 1A 1 2 I AND Gate Input 1B 2 3 I AND Gate Input 1Y 3 4 O AND Gate Output 2A 4 6 I AND Gate Input 2B 5 8 I AND Gate Input 2Y 6 9 O AND Gate Output GND 7 10 Ground 3Y 8 12 O AND Gate Output 3A 9 13 I AND Gate Input 3B 10 14 I AND Gate Input 4Y 11 16 O AND Gate Output 4A 12 18 I AND Gate Input 4B 13 19 I AND Gate Input VCC 14 20 Power NAME 4 Submit Documentation Feedback TYPE DESCRIPTION Ground pin for the device Power pin for the device Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: SN54LVC08A SN74LVC08A SN54LVC08A, SN74LVC08A www.ti.com SCAS283S – JANUARY 1993 – REVISED AUGUST 2015 Pin Functions (continued) PIN NAME SOIC, SSOP, SOP, CDIP, or TSSOP TYPE LCCC DESCRIPTION 1 5 NC (1) 7 — — 11 No connect 15 17 (1) NC – No internal connection 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC MIN MAX UNIT Supply voltage –0.5 6.5 V (2) –0.5 6.5 V –0.5 VCC + 0.5 V VI Input voltage VO Output voltage (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA Continuous current through VCC or GND ±100 mA 500 mW Ptot Power dissipation (4) (5) TJ Junction temperature –65 150 °C Tstg Storage temperature –65 150 °C (1) (2) (3) (4) (5) TA = –40°C to 125°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the Recommended Operating Conditions table. For the D package: above 70°C, the value of Ptot derates linearly with 8 mW/K. For the DB, NS, and PW packages: above 60°C, the value of Ptot derates linearly with 5.5 mW/K. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions for SN54LVC08A (1) SN54LVC08A –55°C to 125°C Operating VCC Supply voltage VIH High-level input voltage VCC = 2.7 V to 3.6 V VIL Low-level input voltage VCC = 2.7 V to 3.6 V (1) Data retention only MIN MAX 2 3.6 UNIT 1.5 2 V V 0.8 V All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004. Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: SN54LVC08A SN74LVC08A Submit Documentation Feedback 5 SN54LVC08A, SN74LVC08A SCAS283S – JANUARY 1993 – REVISED AUGUST 2015 www.ti.com Recommended Operating Conditions for SN54LVC08A(1) (continued) SN54LVC08A –55°C to 125°C MIN UNIT MAX VI Input voltage 0 5.5 V VO Output voltage 0 VCC V IOH High-level output current IOL Low-level output current Δt/Δv Input transition rise or fall rate VCC = 2.7 V –12 VCC = 3 V –24 VCC = 2.7 V 12 VCC = 3 V 24 mA mA 8 ns/V 7.4 Recommended Operating Conditions for SN74LVC08A (1) SN74LVC08A TA = 25°C VCC Supply voltage VIH High-level input voltage Operating Data retention only VCC = 1.65 V to 1.95 V –40°C to 125°C UNIT MAX MIN MAX MIN MAX 1.65 3.6 1.65 3.6 1.65 3.6 1.5 1.5 1.5 0.65 × VCC 0.65 × VCC 0.65 × VCC VCC = 2.3 V to 2.7 V 1.7 1.7 1.7 VCC = 2.7 V to 3.6 V 2 2 2 VCC = 1.65 V to 1.95 V Low-level input voltage VIL –40°C to 85°C MIN V V 0.35 × VCC 0.35 × VCC 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 0.7 0.7 VCC = 2.7 V to 3.6 V 0.8 0.8 0.8 V VI Input voltage 0 5.5 0 5.5 0 5.5 V VO Output voltage 0 VCC 0 VCC 0 VCC V High-level output current IOH VCC = 1.65 V –4 –4 –4 VCC = 2.3 V –8 –8 –8 VCC = 2.7 V –12 –12 –12 VCC = 3 V –24 –24 –24 4 4 4 VCC = 1.65 V Low-level output current IOL VCC = 2.3 V 8 8 8 VCC = 2.7 V 12 12 12 VCC = 3 V 24 24 24 8 8 8 Δt/Δv Input transition rise or fall rate (1) mA mA ns/V All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004. 7.5 Thermal Information SN74LVC08A THERMAL METRIC (1) RθJA (1) 6 Junction-to-ambient thermal resistance D (SOIC) DB (SSOP) NS (SOP) PW (TSSOP) RGY (LCCC) 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS 86 96 76 113 47 UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: SN54LVC08A SN74LVC08A SN54LVC08A, SN74LVC08A www.ti.com SCAS283S – JANUARY 1993 – REVISED AUGUST 2015 7.6 Electrical Characteristics for SN54LVC08A over recommended operating free-air temperature range (unless otherwise noted) SN54LVC08A PARAMETER TEST CONDITIONS VCC –55°C to 125°C MIN IOH = –100 μA VOH 3V 2.4 IOH = –24 mA 3V 2.2 IOL = 100 μA 2.7 V to 3.6 V IOL = 12 mA 2.7 V 0.4 IOL = 24 mA 3V 0.55 VI = 5.5 V or GND ICC VI = VCC or GND, IO = 0 One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VCC – 0.2 2.2 II ΔICC UNIT MAX 2.7 V IOH = –12 mA VOL (1) 2.7 V to 3.6 V TYP (1) V 0.2 V ±5 μA 3.6 V 10 μA 2.7 V to 3.6 V 500 μA 3.6 V VI = VCC or GND 3.3 V 5 pF TA = 25°C 7.7 Electrical Characteristics for SN74LVC08A over recommended operating free-air temperature range (unless otherwise noted) SN74LVC08A PARAMETER TEST CONDITIONS VCC TA = 25°C MIN IOH = –100 μA VOH 1.65 V to 3.6 V UNIT MIN MAX VCC – 0.2 VCC – 0.3 1.65 V 1.29 1.2 1.05 2.3 V 1.9 1.7 1.55 2.7 V 2.2 2.2 2.05 3V 2.4 2.4 2.25 IOH = –24 mA 3V 2.3 2.2 2 IOL = 100 μA V 1.65 V to 3.6 V 0.1 0.2 IOL = 4 mA 1.65 V 0.24 0.45 0.6 IOL = 8 mA 2.3 V 0.3 0.7 0.75 IOL = 12 mA 2.7 V 0.4 0.4 0.6 IOL = 24 mA 3V 0.55 0.55 0.8 3.6 V ±1 ±5 ±20 μA 3.6 V 1 10 40 μA 500 500 5000 μA VI = 5.5 V or GND ICC VI = VCC or GND, IO = 0 One input at VCC – 0.6 V, Other inputs at VCC or GND Ci MIN MAX VCC – 0.2 IOH = –8 mA II ΔICC TYP MAX –40°C to 125°C IOH = –4 mA IOH = –12 mA VOL –40°C to 85°C 2.7 V to 3.6 V VI = VCC or GND 3.3 V 0.3 5 V pF 7.8 Switching Characteristics for SN54LVC08A over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) SN54LVC08A PARAMETER FROM (INPUT) TO (OUTPUT) VCC –55°C to 125°C MIN tpd A or B Y 2.7 V 3.3 V ± 0.3 V Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: SN54LVC08A SN74LVC08A 4.8 1 UNIT MAX 4.1 Submit Documentation Feedback ns 7 SN54LVC08A, SN74LVC08A SCAS283S – JANUARY 1993 – REVISED AUGUST 2015 www.ti.com 7.9 Switching Characteristics for SN74LVC08A over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) SN74LVC08A PARAMETER FROM (INPUT) TO (OUTPUT) VCC TA = 25°C MIN tpd A or B Y tsk(o) –40°C to 85°C TYP MAX –40°C to 125°C MIN MAX MIN MAX 1.8 V ± 0.15 V 1 5 9.3 1 9.8 1 11.3 2.5 V ± 0.2 V 1 2.9 6.4 1 6.9 1 9 2.7 V 1 3 4.6 1 4.8 1 6 3.3 V ± 0.3 V 1 2.6 3.9 1 4.1 1 5.5 3.3 V ± 0.3 V 1 1.5 UNIT ns ns 7.10 Operating Characteristics TA = 25°C TEST CONDITIONS PARAMETER Cpd Power dissipation capacitance per gate f = 10 MHz VCC TYP 1.8 V 7 2.5 V 9.8 3.3 V 10 UNIT pF 7.11 Typical Characteristics 10 14 12 VCC = 3 V, TA = 25°C tpd – Propagation Delay Time – ns tpd – Propagation Delay Time – ns VCC = 3 V, TA = 25°C One Output Switching Four Outputs Switching Eight Outputs Switching 10 8 6 4 6 4 2 2 0 50 100 150 200 250 300 CL – Load Capacitance – pF Figure 1. Propagation Delay (Low to High Transition) vs Load Capacitance 8 One Output Switching Four Outputs Switching Eight Outputs Switching 8 Submit Documentation Feedback 0 50 100 150 200 250 300 CL – Load Capacitance – pF Figure 2. Propagation Delay (High to Low Transition) vs Load Capacitance Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: SN54LVC08A SN74LVC08A SN54LVC08A, SN74LVC08A www.ti.com SCAS283S – JANUARY 1993 – REVISED AUGUST 2015 8 Parameter Measurement Information VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VM VM VOL VM 0V VLOAD/2 VM tPZH VOH Output VM tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPHL VM tPZL tPHL VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + VD VOL tPHZ Output Waveform 2 S1 at GND (see Note B) VM VOH - VD VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. t PZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: SN54LVC08A SN74LVC08A Submit Documentation Feedback 9 SN54LVC08A, SN74LVC08A SCAS283S – JANUARY 1993 – REVISED AUGUST 2015 www.ti.com 9 Detailed Description 9.1 Overview The SN74LVC08 device contains quadruple 2-input positive AND gate device and performs the Boolean function Y= A ·B. This device is useful when multiple AND function is used in the system. 9.2 Functional Block Diagram A Y B Figure 4. Logic Diagram, Each Gate (Positive Logic) 9.3 Feature Description The device can operate from 1.65 V to 3.6 V, allowing to be used in low voltage systems. The device can accept voltages to 5.5 V make this device flexible to connect and work seamlessly with wide voltage range systems. The maximum tpd of 4.1 ns at 3.3 V is beneficial for use in high speed applications. The device has a Ioff support live insertion, a partial-power-down mode, and a back-drive protection. 9.4 Device Functional Modes Table 1 lists the functional modes for the SN54LVC08A and SN74LVC08A devices. Table 1. Truth Table INPUTS 10 OUTPUT A B Y H H H L X L X L L Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: SN54LVC08A SN74LVC08A SN54LVC08A, SN74LVC08A www.ti.com SCAS283S – JANUARY 1993 – REVISED AUGUST 2015 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The SN74LVC08A is used to drive CMOS device and used for implementing AND logic. LVC famiy can support current drive of about 24 mA at 3-V VCC. The inputs for SN74LVC08 are 5.5-V tolerant allowing it to translate down to VCC. 10.2 Typical Application A Y B R C Figure 5. Three Input AND Gate Implementation and Driving LED 10.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads so routing and load conditions should be considered to prevent ringing. 10.2.2 Detailed Design Procedure SN74LVC08A contains four AND gates in one package which can be used for individual AND function or to implement complex Bolean logic. Figure 5 shows an example of implementing 3input AND function. AB are inputs for AND gate which are connected to another AND gate. Z= A·B·C. SN74LVC08A support high drive current of 24 mA which can be used to drive LED's of even Drive low current signal FETs, an example is shown in Figure 5 TI recommends to use a series resistance to limit the current. If VCC is 3 V, and LED current should be 10 mA, and the forward-voltage of LED is 2.5 V, then R as shown in Figure 5 is calculated using Equation 1 below: R = (VCC – VLED) / I R = (3 – 2.5) / 0.01 = 50 Ω (1) Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: SN54LVC08A SN74LVC08A Submit Documentation Feedback 11 SN54LVC08A, SN74LVC08A SCAS283S – JANUARY 1993 – REVISED AUGUST 2015 www.ti.com Typical Application (continued) 10.2.3 Application Curves 60 100 80 TA = 25°C, VCC = 3 V, VIH = 3 V, VIL = 0 V, All Outputs Switching 40 TA = 25°C, VCC = 3 V, VIH = 3 V, VIL = 0 V, All Outputs Switching 20 I OH – mA I OL – mA 60 40 0 –20 –40 20 –60 0 –80 –20 –0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 –100 –1 –0.5 0.0 VOL – V Figure 6. Output Drive Current (IOL) vs LOW-level Output Voltage (VOL) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VOH – V Figure 7. Output Drive Current (IOH) vs HIGH-level Output Voltage (VOH) 11 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions table. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, a 0.1-μF capacitor is recommended and if there are multiple VCC pins then 0.01-μF or 0.022-μF capacitor is recommended for each power pin. It is ok to parallel multiple bypass capacitors to reject different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 12 Layout 12.1 Layout Guidelines When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more convenient. 12.2 Layout Examples VCC Unused Input Input Output Output Unused Input Input Figure 8. Layout Examples 12 Submit Documentation Feedback Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: SN54LVC08A SN74LVC08A SN54LVC08A, SN74LVC08A www.ti.com SCAS283S – JANUARY 1993 – REVISED AUGUST 2015 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 2. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY SN54LVC08A Click here Click here Click here Click here Click here SN74LVC08A Click here Click here Click here Click here Click here 13.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 13.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 13.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser based versions of this data sheet, refer to the left hand navigation. Copyright © 1993–2015, Texas Instruments Incorporated Product Folder Links: SN54LVC08A SN74LVC08A Submit Documentation Feedback 13 PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 5962-9753401Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629753401Q2A SNJ54LVC 08AFK 5962-9753401QCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9753401QC A SNJ54LVC08AJ 5962-9753401QDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9753401QD A SNJ54LVC08AW HVAL02231ARGYR ACTIVE VQFN RGY 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LC08A SN74LVC08AD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A SN74LVC08ADBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08ADBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08ADBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08ADE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A SN74LVC08ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A SN74LVC08ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LVC08A SN74LVC08ADRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A SN74LVC08ADRG3 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LVC08A SN74LVC08ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A SN74LVC08ADT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 15-Apr-2017 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SN74LVC08ANSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A SN74LVC08ANSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LVC08A SN74LVC08APW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08APWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08APWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08APWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08APWRG3 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08APWT ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08APWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 LC08A SN74LVC08ARGYR ACTIVE VQFN RGY 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LC08A SN74LVC08ARGYRG4 ACTIVE VQFN RGY 14 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 LC08A SNJ54LVC08AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629753401Q2A SNJ54LVC 08AFK SNJ54LVC08AJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9753401QC A SNJ54LVC08AJ SNJ54LVC08AW ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9753401QD A SNJ54LVC08AW Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2017 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54LVC08A, SN74LVC08A : • Catalog: SN74LVC08A • Automotive: SN74LVC08A-Q1, SN74LVC08A-Q1 Addendum-Page 3 PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2017 • Enhanced Product: SN74LVC08A-EP, SN74LVC08A-EP • Military: SN54LVC08A NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects • Enhanced Product - Supports Defense, Aerospace and Medical Applications • Military - QML certified for Military and Defense Applications Addendum-Page 4 PACKAGE MATERIALS INFORMATION www.ti.com 30-May-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVC08ADBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74LVC08ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LVC08ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LVC08ADR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 SN74LVC08ADRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 SN74LVC08ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LVC08ADRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LVC08ADT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LVC08ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74LVC08APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC08APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC08APWRG3 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC08APWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC08APWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC08ARGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-May-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC08ADBR SSOP DB 14 2000 367.0 367.0 38.0 SN74LVC08ADR SOIC D 14 2500 367.0 367.0 38.0 SN74LVC08ADR SOIC D 14 2500 333.2 345.9 28.6 SN74LVC08ADR SOIC D 14 2500 364.0 364.0 27.0 SN74LVC08ADRG3 SOIC D 14 2500 364.0 364.0 27.0 SN74LVC08ADRG4 SOIC D 14 2500 367.0 367.0 38.0 SN74LVC08ADRG4 SOIC D 14 2500 333.2 345.9 28.6 SN74LVC08ADT SOIC D 14 250 367.0 367.0 38.0 SN74LVC08ANSR SO NS 14 2000 367.0 367.0 38.0 SN74LVC08APWR TSSOP PW 14 2000 364.0 364.0 27.0 SN74LVC08APWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74LVC08APWRG3 TSSOP PW 14 2000 364.0 364.0 27.0 SN74LVC08APWRG4 TSSOP PW 14 2000 367.0 367.0 35.0 SN74LVC08APWT TSSOP PW 14 250 367.0 367.0 35.0 SN74LVC08ARGYR VQFN RGY 14 3000 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will thoroughly test such applications and the functionality of such TI products as used in such applications. TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource solely for this purpose and subject to the terms of this Notice. TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2017, Texas Instruments Incorporated