ON NCP1560HDR2 Full featured voltage mode pwm controller Datasheet

NCP1560
Full Featured Voltage Mode
PWM Controller
The NCP1560 PWM controller contains all the features and
flexibility needed to implement voltage−mode control in high
performance single ended DC−DC converters. This device cost
effectively reduces system part count with the inclusion of a high
voltage startup regulator that operates over a wide input range of
21.5 V to 150 V. The NCP1560 provides two control outputs, OUT1
which controls the main PWM switch and OUT2 with adjustable
overlap delay, which can control a synchronous rectifier switch or an
active clamp/reset switch. Other distinctive features include: two
mode over current protection, line under/overvoltage lockout, fast line
feedforward, soft−start and a maximum duty cycle limit.
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MARKING DIAGRAM
SO−16
D SUFFIX
CASE 751B
PIN CONNECTIONS
Vin
UV/OV
NC
FF
CS
CSKIP
RT
DCMAX
Device
NCP1560HDR2
NCP1560HDR2G
16
VAUX
OUT1
GND
OUT2
tD
VREF
VEA
SS
TX
Startup
SR
Drive
Feedforward
Vin FF
UV/OV
OUT1
OUT2
Shipping†
SO−16
2500/Tape & Reel
SO−16
(Pb−Free)
2500/Tape & Reel
Cout
+
−
Vout
Cclamp
M1
NCP1560
Package
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Lout
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Overlap
Delay
1
ORDERING INFORMATION
Telecommunication Power Converters
Industrial Power Converters
High Voltage Power Modules
+42 V Automotive Systems
Control Driven Synchronous Rectifier Power Converters
+
Vin
−
1
NCP1560 = Device Code
A
= Assembly Location
WL
= Wafer Lot
Y
= Year
WW
= Work Week
Minimum Operating Voltage of 21.5 V
Internal High Voltage Startup Regulator
Dual Control Outputs with Adjustable Overlap Delay
Single Resistor Oscillator Frequency Setting
Fast Line Feedforward
Line Under/Overvoltage Lockout
Dual Mode Overcurrent Protection
Programmable Maximum Duty Cycle Control
Maximum Duty Cycle Proportional to Line Voltage
Programmable Soft−Start
Precision 5.0 V Reference
Pb−Free Package is Available*
Typical Applications
•
•
•
•
•
NCP1560
AWLYWW
1
Features
•
•
•
•
•
•
•
•
•
•
•
•
16
16
Driver
Mclamp
tD
Opto
Error
Amplifier
Figure 1. Active−Clamp Forward Converter
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 7
1
Publication Order Number
NCP1560/D
NCP1560
Vin
UV/OV
CS
VAUX
High Voltage
Startup
Regulator
UV
Fault
Detection
5.0 V
Reference
Modulator
Delay
Logic
Output
Drivers
OUT1
OUT2
tD
CSKIP
RT
VREF
Oscillator
VEA
FF
SS
GND
DCMAX
Figure 1. Simplified Block Diagram
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2
NCP1560
1
Vin
ISTART
VAUX
Disable
16
One Shot
Pulse
(250 ns)
VAUX
CAUX
+
14
Disable_VREF
S
Q
Monotonic
Start
Latch
(Reset
Dominant)
R
Disable_VREF
Vin
1.52 V
+
−
+
−
2
UV/OV
3.61 V
VREF
12.3 A
12
−
tD
Disable
CSKIP
−
+
CS
One Shot
Pulse
(600 ns)
+
VREF
−
+
−
0.5 V
RT
RFF
5.3 k
4
FF
V
I+
125 k
IFF
6.7 k
+
V
−
+
Max DC
+ − Comparator
+
2V
−
2V
One Shot
Pulse
FF Ramp
(Adjustable)
40 k
+
−
−
CFF
Figure 2. NCP1560 Functional Block Diagram
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3
VREF
RMDP
32 k
8
VDC(inv)
10 pF
VEA
20 k
+
−
2V
Clock
Vin
OUT2
2V
+
−
10
Oscillator Ramp
10 pF
* Trimmed during
manufacturing to obtain
1.3 V with RT = 101 k
13
2 k
STOP
+
1.3 V*
−
DIS
PWM
Comparator
I1
2
I1
7
RT
VAUX
+ −
Disable_ss
OUT1
VAUX
CURRENT MIRROR
SS
CSS
Delay
Logic
Soft Start
− + Comparator
6 A
9
DIS 15
Q
Output
Latch
(Reset
Dominant)
R
−
+
+
2V
−
CCSKIP
+
−
+
0.57 V
−
S
Clock
6
5
RD
Disable_ss
STOP
+
−
+
VREF
11
DIS
VAUX(on)/AUX(off)
−
GND
5.0 V Reference
27 k
DCMAX
RP
NCP1560
PIN DESCRIPTION
Pin
Name
Application Information
1
Vin
This pin is connected to the bulk DC input voltage supply. A constant current source supplies current from
this pin to the capacitor connected on the VAUX pin. The charge current is typically 13.8 mA. Input voltage
range is 21.5 V to 150 V.
2
UV/OV
Input supply voltage is scaled down and sampled by means of a resistor divider. The supply voltage must
be scaled down between 1.52 V and 3.61 V within the specified input voltage range.
3
NC
Not Connected.
4
FF
An external resistor between Vin and this pin adjusts the amplitude of the FF Ramp in proportion to Vin. By
varying the feedforward ramp amplitude in proportion to the input voltage, changes in loop bandwidth are
eliminated.
5
CS
Over current sense input. If the CS voltage exceeds 0.48 V or 0.57 V, the converter enters the
Cycle−by−Cycle or Cycle Skip current limit mode, respectively.
6
CSKIP
7
RT
8
DCMAX
9
SS
An internal 6.2 A current source charges the external capacitor connected to this pin. The duty cycle is
limited during startup by comparing the voltage on this pin to the Oscillator Ramp.
10
VEA
The error signal from an external error amplifier is fed into this input and compared to the Feedforward
Ramp. A series diode and resistor offset the voltage on this pin before it is applied to the PWM
Comparator inverting input.
11
VREF
Precision 5.0 V reference output. Maximum output current is 6.0 mA.
12
tD
13
OUT2
Output of the PWM controller with leading and trailing edge overlap delay. OUT2 can be used to drive a
synchronous rectifier topology, an active clamp/reset switch, or both.
14
GND
Control circuit ground.
15
OUT1
Main output of the PWM controller.
16
VAUX
Positive input supply voltage. This pin is connected to an external capacitor for energy storage. An
internal current supplies current from Vin to this pin. Once the voltage on VAUX reaches 11 V, the current
source turns OFF. It turns ON again once VAUX falls to 7.0 V. During normal operation, power is supplied
to the IC via this pin, by means of an auxiliary winding.
The capacitor connected between this pin and ground sets the Cycle Skip period. A soft−start sequence
follows at the conclusion of the fault period.
A single external resistor between this pin and GND sets the oscillator fixed frequency.
An external resistor between this pin and GND sets the voltage on the Max DC Comparator inverting
input. The duty cycle is limited by comparing the voltage on the Max DC Comparator inverting input to the
Feedforward Ramp.
An external resistor between VREF and this pin sets the overlap delay between OUT1 and OUT2
transitions.
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4
NCP1560
MAXIMUM RATINGS
Symbol
Value
Unit
Input Line Voltage
−0.3 to 150
V
VAUX
Auxiliary Supply Voltage
−0.3 to 16
V
IAUX
Auxiliary Supply Input Current
35
mA
VOUT
OUT1 and OUT2 Voltage
−0.3 to (VAUX + 0.3 V)
V
IOUT
OUT1 and OUT2 Output Current
10
mA
VREF
5.0 V Reference Voltage
−0.3 to 6.0
V
IREF
5.0 V Reference Output Current
6.0
mA
VIO
All Other Inputs/Outputs Voltage
−0.3 to VREF
V
IIO
All Other Inputs/Outputs Current
10
mA
TJ
Operating Junction Temperature
−40 to 125
°C
Tstg
Storage Temperature Range
−55 to 150
°C
PD
Power Dissipation at TA = 25°C
0.77
W
Thermal Resistance, Junction−to−Ambient
130
°C/W
Vin
RJA
Rating
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Pin 1 is the HV startup of the device and is rated to the max rating of the part, or 150 V.
Machine Model Method 150 V.
Pins 2−16: Human Body Model 4000 V per MIL−STD−883, Method 3015.
Machine Model Method 200 V.
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NCP1560
ELECTRICAL CHARACTERISTICS (Vin = 48 V, VAUX = 12 V, VEA = 2 V, RT = 101 k, CCSKIP = 6800 pF,
RD = 60.4 k, RFF = 432 k, for typical values TJ = 25°C, for min/max values, TJ = −40°C to 125°C, unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
VAUX(on)
VAUX(off)
VH
10.5
6.6
−
11.0
7.0
4.0
11.5
7.4
−
−
19.3
21.5
Unit
STARTUP CONTROL AND VAUX REGULATOR
VAUX Regulation
Startup Threshold/VAUX Regulation Peak (VAUX increasing)
Minimum Operating VAUX Valley Voltage After Turn−On
Hysteresis
Minimum Startup Voltage (Pin 1)
ISTART = 1.0 mA, VAUX = VAUX(on) − 0.2 V
VSTART(min)
Startup Circuit Output Current
VAUX = 0 V
TJ = 25°C
TJ = −40°C to 125°C
VAUX = VAUX(on) − 0.2 V
TJ = 25°C
TJ = −40°C to 125°C
ISTART
Startup Circuit Off−State Leakage Current (Vin = 150 V)
TJ = 25°C
TJ = −40°C to 125°C
ISTART(off)
Startup Circuit Breakdown Voltage (Note 2)
ISTART(off) = 50A, TJ = 25°C
V(BR)DS
Auxiliary Supply Current After VAUX Turn−On
Outputs Disabled
VEA = 0 V
VUV/OV = 0.7 V
Outputs Enabled
V
V
mA
13
10
17.5
−
21
25
10
8
13.8
−
17
19
−
−
23
−
50
100
150
−
−
A
V
mA
IAUX1
IAUX2
IAUX3
−
−
−
2.7
1.3
4.6
5.0
2.5
6.5
VUV
1.40
1.52
1.64
V
VUV(H)
0.080
0.098
0.120
V
VOV
3.47
3.61
3.75
V
VOV(H)
−
0.145
−
V
Undervoltage Propagation Delay to Output
tUV
−
250
−
ns
Overvoltage Propagation Delay to Output
tOV
−
160
−
ns
Cycle−by−Cycle Threshold Voltage
ILIM1
0.44
0.48
0.52
V
Propagation Delay to Output (VEA = 2.0 V)
VCS = ILIM1 to 2.0 V, measured when VOUT reaches 0.5 VOH
tILIM
−
90
150
ns
Cycle Skip Threshold Voltage
ILIM2
0.54
0.57
0.62
V
ICSKIP
8.0
12.3
15
A
LINE UNDER/OVERVOLTAGE DETECTOR
Undervoltage Threshold (Vin Increasing)
Undervoltage Hysteresis
Overvoltage Threshold (Vin Increasing)
Overvoltage Hysteresis
CURRENT LIMIT
Cycle Skip Charge Current (VCSKIP = 0 V)
2. Guaranteed by design only.
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NCP1560
ELECTRICAL CHARACTERISTICS (Vin = 48 V, VAUX = 12 V, VEA = 2 V, RT = 101 k, CCSKIP = 6800 pF,
RD = 60.4 k, RFF = 432 k, for typical values TJ = 25°C, for min/max values, TJ = −40°C to 125°C, unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
285
280
300
−
315
320
456
444
480
−
504
516
57
75
62
80
66
85
Unit
OSCILLATOR
Frequency (RT = 101 k, Vin = 36 V)
TJ = 25°C
TJ = −40°C to 125°C
fOSC1
Frequency (RT = 59 k, Vin = 36 V, VEA = 1 V)
TJ = 25°C
TJ = −40°C to 125°C
fOSC2
kHz
kHz
MAXIMUM DUTY CYCLE COMPARATOR
Maximum Duty Cycle (Vin = 36 V, VEA = 3 V, TJ = 25°C)
RP = 0 , RMDP = open
RP = open, RMDP = open
DCMAX
%
Open Circuit Voltage
VDCMAX
0.40
0.47
0.60
V
Charge Current (VSS = 1.0 V)
ISS(C)
5.0
6.2
7.4
A
Discharge Current (VSS = 5.0 V, VUV/OV = 3.7 V)
ISS(D)
20
52.5
−
mA
RIN(VEA)
8.0
22
60
k
Lower Input Threshold
VEA(L)
0.3
0.7
0.9
V
Delay to Output (from VOH to 0.5 VOH)
tPWM
−
200
−
ns
VREF
4.9
5.0
5.1
V
Load Regulation (IREF = 0 to 6 mA)
VREF(Load)
−
10
50
mV
Line Regulation (VAUX = 7.5 V to 16 V)
VREF(Line)
−
50
100
mV
VOL
VOH
−
−
0.25
11.8
−
−
SOFT−START
PWM COMPARATOR
Input Resistance (V1 = 1.25 V, V2 = 1.50 V)
RIN(VEA) = (V2 − V1)/(I2 − I1)
5.0 V REFERENCE
Output Voltage (IREF = 0 mA)
CONTROL OUTPUTS
Output Voltage (IOUT = 0 mA)
Low State
High State
Overlap Delay (Vin = 36 V)
RD = 1 M
Leading
Trailing
RD = 60 k
Leading
Trailing
tD
V
ns
−
−
342
312
−
−
50
32
77
77
130
130
RSNK
RSRC
20
50
40
90
80
170
Rise Time (CL = 100 pF, 10% to 90% of VOH)
ton
−
30
−
ns
Fall Time (CL = 100 pF, 90% to 10% of VOH)
toff
−
12
−
ns
Drive Resistance (Vin = 15 V)
Sink (VEA = 0 V, VOUT = 2 V)
Source (VEA = 3 V, VOUT = 10 V)
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7
NCP1560
20
12
11
ISTART, STARTUP CIRCUIT OUTPUT
CURRENT (mA)
VAUX, AUXILIARY SUPPLY VOLTAGE (V)
TYPICAL CHARACTERISTICS
STARTUP
THRESHOLD
10
9
8
7
MINIMUM
OPERATING
THRESHOLD
6
5
−50
−25
0
25
50
75
100
125
150
18
17
VAUX = 0 V
16
15
14
13
VAUX = VAUX(on) − 0.2 V
12
11
10
−50
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 4. Startup Circuit Output Current
versus Junction Temperature
ISTART, STARTUP CIRCUIT OUTPUT
CURRENT (mA)
17.0
Vin = 48 V
16.5
16.0
15.5
15.0
14.5
14.0
13.5
40
0
2
4
6
8
12
TJ = 125°C
8
4
0
VAUX = VAUX(on) − 0.2 V
0
25
50
75
100
125
Figure 6. Startup Circuit Output Current
versus Line Voltage
25
TJ = 25°C
20
TJ = 125°C
15
10
5
0
TJ = 25°C
12
Figure 5. Startup Circuit Output Current
versus Auxiliary Supply Voltage
30
0
TJ = −40°C
16
Vin, LINE VOLTAGE (V)
TJ = −40°C
25
50
75
100
125
150
150
4.0
3.5
VAUX = 12 V
3.0
VEA = 0 V
2.5
2.0
1.5
VUV/OV = 0 V
1.0
0.5
0
−50
−25
0
25
50
75
100
125 150
Vin, LINE VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Startup Circuit Off−State Leakage
Current versus Line Voltage
Figure 8. Auxiliary Supply Current versus
Junction Temperature
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8
150
20
VAUX, AUXILIARY SUPPLY VOLTAGE (V)
VAUX = 12 V
35
10
IAUX, AUXILIARY SUPPLY CURRENT (mA)
ISTART, STARTUP CIRCUIT OUTPUT
CURRENT (mA)
Vin = 48 V
Figure 3. Auxiliary Supply Voltage Thresholds
versus Junction Temperature
17.5
ISTART(off), STARTUP CIRCUIT OFF−
STATE LEAKAGE CURRENT (A)
19
NCP1560
TYPICAL CHARACTERISTICS
VUV/OV, UV/OV VOLTAGE (V)
6
4.0
VAUX = 12 V
DC [ 50%
fOSC = 440 kHz
fOSC = 300 kHz
5
4
3
fOSC = 87 kHz
2
1
0
−50
−25
0
25
50
75
100
125
VUV/OV(H), UV/OV THRESHOLD
VOLTAGE HYSTERESIS (mV)
OV THRESHOLD
3.0
2.5
2.0
1.5
UV THRESHOLD
1.0
0.5
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. Operating Auxiliary Supply Current
versus Junction Temperature
Figure 10. Line Under/Overvoltage Thresholds
versus Junction Temperature
160
150
OV HYSTERESIS
140
130
120
110
UV HYSTERESIS
100
90
−50
−25
0
25
50
75
100
125
150
600
575
CYCLE SKIP
550
525
500
CYCLE−BY−CYCLE
475
450
425
400
−50
−25
0
25
50
75
100
125 150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. Line Under/Overvoltage Thresholds
Hysteresis versus Junction Temperature
Figure 12. Current Limit Thresholds versus
Junction Temperature
115
VAUX = 12 V
110
Measured from VOH to 0.5 VOH
fosc, OSCILLATOR FREQUENCY (kHz)
120
tILIM, CURRENT LIMIT
PROPAGATION DELAY (ns)
3.5
0
−50
150
ILIM, CURRENT LIMIT THRESHOLDS (mV)
IAUX3, OPERATING AUXILIARY
SUPPLY CURRENT (mA)
7
105
100
95
90
85
80
75
70
−50
−25
0
25
50
75
100
125
150
450
400
RT = 68 k
350
300
RT = 101 k
250
200
150
100
RT = 390 k
50
0
−50
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. Current Limit Propagation Delay
versus Junction Temperature
Figure 14. Oscillator Frequency versus
Junction Temperature
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9
150
NCP1560
TYPICAL CHARACTERISTICS
600
fosc, OSCILLATOR FREQUENCY (kHz)
fosc, OSCILLATOR FREQUENCY (kHz)
315
RT = 101 k
400
305
300
300
200
295
100
290
−25
0
25
50
75
100
125
100
150
200
250
300
350
RT, TIMING RESISTOR (k)
Figure 15. Oscillator Frequency versus
Junction Temperature
Figure 16. Oscillator Frequency versus
Timing Resistor
17
16
15
14
13
12
11
10
−25
0
25
50
75
100
125
VEA = 3.0 V
VDCMAX = 0 V
80
70
60
50
TJ = −40°C
40
30
20
TJ = 125°C
10
0
150
0
75
150
225
300
375
450
IFF, FEEDFORWARD CURRENT (A)
Figure 17. Feedforward Internal Resistance
versus Junction Temperature
Figure 18. Maximum Duty Cycle versus
Feedforward Current
Vin = 36 V
RFF = 432 k
90
RP = OPEN, RMDP = OPEN
80
70
RP = 0 , RMDP = OPEN
60
−25
0
25
50
75
100
125 150
ISS(C), SOFT−START CHARGE CURRENT (A)
TJ, JUNCTION TEMPERATURE (°C)
100
400
90
DCMAX, MAXIMUM DUTY CYCLE (%)
19
50
−50
50
TJ, JUNCTION TEMPERATURE (°C)
18
9
−50
0
150
525
70
7.0
6.5
65
CHARGE
6.0
60
5.5
55
DISCHARGE
5.0
50
4.5
45
4.0
40
3.5
35
3.0
−50
−25
0
25
50
75
100
30
125 150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 19. Maximum Duty Cycle versus
Junction Temperature
Figure 20. Soft−Start Charge/Discharge
Currents versus Junction Temperature
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ISS(D), SOFT−START DISCHARGE CURRENT (mA)
DCMAX, MAXIMUM DUTY CYCLE (%)
FEEDFORWARD INTERNAL RESISTANCE (k)
285
−50
TJ = 25°C
DC [ 50%
500
310
NCP1560
50
VEA(L), PWM COMPARATOR LOWER
INPUT THRESHOLD (V)
RIN(VEA), VEA INPUT RESISTANCE (k)
TYPICAL CHARACTERISTICS
40
30
20
10
0
−50
−25
25
0
50
75
100
125
150
0.85
0.75
0.65
0.55
0.45
0.35
−50
−25
Figure 21. VEA Input Resistance versus
Junction Temperature
75
100
125
150
350
tD, OUTPUTS OVERLAP DELAY (ns)
VREF, REFERENCE VOLTAGE (V)
50
Figure 22. PWM Comparator Lower Input
Threshold versus Junction Temperature
5.03
5.01
IREF = 0 mA
4.99
IREF = 6 mA
4.97
4.95
4.93
−50
−25
0
25
50
75
100
125
150
300
250
200
150
100
RD = 60 k, LEADING
50
0
−50
−25
LEADING
300
TRAILING
250
200
150
100
0
200
400
600
800
1000
1200
1400
RSNK/SRC OUTPUTS DRIVE RESISTANCE ()
TJ = 25°C
CD = 220 pF
350
25
50
75
100
125
150
Figure 24. Outputs Overlap Delay versus
Junction Temperature
450
400
0
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 23. Reference Voltage versus Junction
Temperature
tD, OUTPUTS OVERLAP DELAY (ns)
25
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
50
0
200
160
Vin = 36 V
VAUX = 12 V
RMDP = 100 k
120
RSRC (VEA = 0 V, VOUT = 10 V)
80
40
RSNK (VEA = 3 V, VOUT = 2 V)
0
−50
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
RD, DELAY RESISTOR (k)
Figure 25. Outputs Overlap Delay versus
Delay Resistor
Figure 26. Outputs Drive Resistance Voltage
versus Junction Temperature
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11
NCP1560
TYPICAL CHARACTERISTICS
35
Measured from 10% to 90% of VOH
VAUX = 12 V
70
TJ = 125°C
TJ = 25°C
60
toff, OUTPUTS FALL TIME (ns)
ton, OUTPUTS RISE TIME (ns)
80
50
40
30
TJ = −40°C
20
10
0
0
25
50
75
100
125
150
175
Measured from 90% to 10% of VOH
30 VAUX = 12 V
20
TJ = 25°C
15
10
TJ = −40°C
5
0
200
TJ = 125°C
25
0
25
75
50
100
125
150
175
CL, LOAD CAPACITANCE (pF)
CL, LOAD CAPACITANCE (pF)
Figure 27. Outputs Rise Time versus Load
Capacitance
Figure 28. Outputs Fall Time versus Load
Capacitance
200
DETAILED OPERATING DESCRIPTION
as Dynamic Self Supply (DSS). The VAUX pin can be biased
externally above 7 V once the outputs are enabled to prevent
the startup regulator from turning ON. It is recommended to
bias the VAUX pin using an auxiliary supply generated out of
an auxiliary winding from the power transformer. An
independent voltage supply can also be used. However, if
VAUX is biased before the outputs are enabled or while a
fault is present, the One Shot Pulse Generator (Figure 2) will
not be enabled and the outputs will remain OFF.
As the DSS sources current to the VAUX pin, a diode should
be placed between CAUX and the auxiliary supply as shown
in Figure 29. This will allow the NCP1560 to charge CAUX
while preventing the startup regulator from sourcing current
into the auxiliary supply.
The NCP1560 PWM controller contains all the features
and flexibility needed for implementation of
Voltage−Mode Control in high performance DC−DC
converters. This device cost effectively reduces system part
count with the inclusion of a high voltage startup regulator.
The NCP1560 provides two control outputs. Output 1
controls the main switch of a forward or flyback topology.
Output 2 has an adjustable overlap delay, which can be used
to control an active clamp/reset switch, a synchronous
rectifier switch, or both. Other distinctive features include:
two mode overcurrent protection, line under/overvoltage
lockout, fast line feedforward, soft−start and a maximum
duty cycle limit. The Functional Block Diagram is shown in
Figure 2.
The features included in the NCP1560 provide all the
advantages of Current−Mode Control, fast line
feedforward, and cycle−by−cycle current limit. It eliminates
the disadvantages of low power jitter, slope compensation
and noise susceptibility.
ISTART
Vin
ISTART
To auxiliary supply
VAUX
IAUX
CAUX
Isupply
Disable
High Voltage Startup Regulator
The NCP1560 contains an internal high voltage startup
regulator that eliminates the need for external startup
components. In addition, this regulator increases the
efficiency of the supply as it uses no power when in the
normal mode of operation, but instead uses power supplied
by an auxiliary winding.
The startup regulator consists of a constant current source
that supplies current from the input line voltage (Vin) to the
capacitor on the VAUX pin (CAUX). The startup current is
typically 13.8 mA. Once VAUX reaches 11 V, the startup
regulator turns OFF and the outputs are enabled. When VAUX
reaches 7.0 V, the outputs are disabled and the startup
regulator turns ON. This “7 − 11” mode of operation is known
Figure 29. Recommended VAUX Configuration
Power to the controller while operating in the self−bias or
DSS mode is provided by CAUX. Therefore, CAUX must be
sized such that a VAUX voltage greater than 7 V is
maintained while the outputs are switching and the
converter reaches regulation. Also, the VAUX discharge time
(from 11 V to 7 V) must be greater that the soft−start charge
period to assure the converter turns ON.
The startup circuit is rated at a maximum voltage of 150 V.
If the device operates in the DSS mode, power dissipation
should be controlled to avoid exceeding the maximum
power dissipation of the controller.
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12
NCP1560
Line Under/Overvoltage Shutdown
be sized to enable the controller once Vin is within the
required operating range. If the UV or OV threshold is
reached, the soft−start capacitor is discharged, and the
outputs are immediately disabled with no overlap delay as
shown in Figure 30. Also, if an UV condition is detected, the
5.0 V Reference Supply is disabled.
The NCP1560 incorporates a line under/overvoltage
shutdown (UV/OV) circuit. The undervoltage (UV)
threshold is 1.52 V and the overvoltage threshold (OV) is
3.61 V, for a ratio of 1:2.4.
The UV/OV circuit can be biased using an external
resistor divider from the input line. The resistor divider must
VAUX(on)
VAUX
VAUX(off)
0V
VOV
UV/OV Voltage
VUV
0V
UV or OV Fault
Propagation delay to
outputs (tUV or tOV)
OUT2
0V
OUT1
0V
Figure 30. UV/OV Fault Timing Diagram
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13
NCP1560
The UV/OV pin can also be used to implement a remote
enable/disable function. Biasing the UV/OV pin below its
UV threshold disables the converter.
Once the UV or OV condition is removed and VAUX
reaches 11 V, the controller initiates a soft−start cycle.
Figure 31 shows the relationship between the UV/OV
voltage, the outputs and the soft−start voltage.
SOFT−START
VAUX(on)
VAUX
VAUX(off)
0V
2V
0V
0V
UV/OV Voltage
Soft−Start Voltage
OUT2
0V
OUT1
0V
Figure 31. Soft−Start Timing Diagram (Using Auxiliary Winding)
Feedforward Ramp Generator
Figure 18 shows the relationship between IFF and DCMAX.
For example, if a system is designed to operate at 300 kHz,
with a 60% maximum duty cycle at 36 V, the DCMAX pin can
be grounded and IFF is calculated as follows:
The NCP1560 incorporates line feedforward (FF) to
compensate for changes in line voltage. A FF Ramp
proportional to Vin is generated and compared to VEA. If the
line voltage changes, the FF Ramp slope changes
accordingly. The duty cycle will be adjusted immediately
instead of waiting for the line voltage change to propagate
around the system and be reflected back on VEA.
A resistor between Vin and the FF pin (RFF) sets the
feedforward current (IFF). The FF Ramp is generated by
charging an internal 10 pF capacitor (CFF) with a constant
current proportional to IFF. The FF Ramp is finished
(capacitor is discharged) once the Oscillator Ramp reaches
2.0 V. Please refer to Figure 2 for a functional drawing of the
Feedforward Ramp generator.
IFF is usually a few hundred A, depending on the
operating frequency and the required duty cycle. If the
operating frequency and maximum duty cycle are known,
IFF is calculated using the equation below:
IFF +
1
T+1+
+ 3.33 s
300 kHz
f
ton(max) + DCMAX
IFF +
+
T + 0.6
3.33 s + 2.0 s
CFF VDC(inv) 125 k
6.7 k ton(max)
10 pF 0.888 V 125 k
+ 82.8 A
6.7 k 2.0 s
As the minimum line voltage is 36 V, the required
feedforward resistor is calculated using the equation below:
V
RFF + in * 12.0 k + 36 V * 12.0 k [ 434 k
IFF
82.8 A
From the above calculations it can be observed that IFF is
controlled predominantly by the value of RFF, as the
resistance seen into the FF pin is only 12 k. If a tight
maximum duty cycle control over temperature is required,
RFF should have a low thermal coefficient.
CFF VDC(inv) 125 k
6.7 k ton(max)
where VDC(inv) is the voltage on the inverting input of the
Max DC Comparator and ton(max) is the maximum ON time.
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14
NCP1560
Current Limit
The cycle skip period is set by an external capacitor
(CCSKIP). Once a cycle skip fault is detected, the cycle skip
capacitor is discharged followed by a charge cycle. The
charge current is 12.3 A. The cycle skip period ends when
the voltage on the cycle skip capacitor reaches 2.0 V. The
cycle skip capacitor is calculated using the equation below:
The NCP1560 has two over current protection modes,
cycle−by−cycle and cycle skip. It allows the NCP1560 to
handle momentary and hard shorts differently for the best
tradeoff in performance and safety. The outputs are disabled
typically 90 ns after a current limit fault is detected.
The cycle−by−cycle mode terminates the conduction
cycle (reducing the duty cycle) if the voltage on the CS pin
exceeds 0.48 V. The cycle skip mode is enabled if the
voltage on the CS pin reaches 0.57 V. Once a cycle skip fault
is detected, the outputs are disabled, the soft−start and cycle
skip capacitors are discharged, and the cycle skip period
(TCSKIP) commences.
VAUX(on)
VAUX
VAUX(off)
NORMAL
OPERATION
ILIM1 ILIM2
CCSKIP [
TCSKIP
2V
12.3 A
Using the above equation, a cycle skip period of 11.0 s
requires a cycle skip capacitor of 68 pF. The differences
between the cycle−by−cycle and cycle skip modes are
observed in Figure 32.
SOFT−START
RESET
NORMAL
OPERATION
0V
OUT2
0V
OUT1
0V
ILIM2
ILIM1
CS Voltage
0V
TCSKIP
0V
Cycle Skip
Voltage
Figure 32. Over Current Faults Timing Diagram
The voltage on the RT pin is laser trim adjusted during
manufacturing to 1.3 V for an RT of 101 k. A current set
by RT generates an Oscillator Ramp by charging an internal
10 pF capacitor as shown in Figure 2. The period ends
(capacitor is discharged) once the Oscillator Ramp reaches
2.0 V. If RT increases, the current and the Oscillator Ramp
slope decrease, thus reducing the frequency. If RT decreases,
the opposite effect is obtained. Figure 16 shows the
relationship between RT and the oscillator frequency.
Once the cycle skip period is complete and VAUX reaches
11 V, a soft−start sequence commences. The possible
minimum OFF time is set by CCSKIP. However, the actual
OFF time is generally greater than the cycle skip period
because it is the cycle skip period added to the time it takes
VAUX to reach 11 V.
Oscillator
The NCP1560 oscillator frequency is set by a single
external resistor connected between the RT pin and GND.
The oscillator is designed to operate up to 500 kHz.
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15
NCP1560
Maximum Duty Cycle
5.0 V Reference
A dedicated internal comparator limits the maximum ON
time of OUT1 by comparing the FF Ramp to VDC(inv). If the
FF Ramp voltage exceeds VDC(inv), the output of the Max
DC Comparator goes high. This will reset the Output Latch,
thus turning OFF the outputs and limiting the duty cycle.
Duty cycle is defined as:
The NCP1560 includes a precision 5.0 V reference output.
The reference output is biased directly from VAUX and it can
supply up to 6 mA. Load regulation is 50 mV and line
regulation is 100 mV within the specified operating range.
It is recommended to bypass the reference output with a
0.1 F ceramic capacitor. The reference output is disabled
when an UV fault is present.
t
DC + on + ton
T
f
PWM Comparator
Therefore, the maximum ON time can be set to yield the
desired DC if the operating frequency is known. The
maximum ON time is set by adjusting the FF Ramp to reach
VDC(inv) in a time equal to ton(max) as shown in Figure 33.
The maximum ON time should be set for the minimum line
voltage. As line voltage increases, the slope of the FF Ramp
increases. This reduces the duty cycle below DCMAX, which
is a desirable feature as the duty cycle is inversely
proportional to line voltage.
The output of an external error amplifier is compared to
the FF Ramp by means of the PWM Comparator. The
external error amplifier drives the VEA input. There is a
0.7 V offset between the VEA input and the PWM
Comparator inverting input. The offset is provided by a
series diode and resistor. If the voltage on the VEA input is
below 0.7 V, the outputs are disabled.
The PWM Comparator controls the duty cycle by turning
OFF the outputs once the FF Ramp voltage exceeds the
offset VEA voltage. The VEA range required to control the
DC from 0% to DCMAX is given by the equation below:
Oscillator Ramp
2V
0V
VEA(L) t VEA t
where, VEA(L) is the PWM comparator lower input
threshold.
T
FF Ramp
Soft−Start
VDC(inv)
Soft−start (SS) allows the converter to gradually reach
steady state operation, thus reducing startup stress and
surges on the system. The duty cycle is limited during a
soft−start sequence by comparing the Oscillator Ramp to the
SS voltage (VSS) by means of the Soft−Start Comparator.
A 6.2 A current source starts to charge the capacitor on
the SS pin once faults are removed and VAUX reaches 11 V.
The Soft−Start Comparator controls the duty cycle while the
SS voltage is below 2.0 V. Once VSS reaches 2.0 V, it exceeds
the Oscillator Ramp voltage and the Soft−Start Comparator
does not limit the duty cycle. Figure 34 shows the
relationship between the outputs duty cycle and the
soft−start voltage.
0V
ton(max)
Figure 33. Maximum ON Time Limit Waveforms
An internal resistor divider from a 2.0 V reference is used
to set VDC(inv). If the DCMAX pin is grounded, VDC(inv) is
0.88 V. If the pin is floating, VDC(inv) is 1.19 V. This is
equivalent to 60% or 80% of a 1.5 V FF Ramp. VDC(inv) can
be adjusted to other values by using an external resistor
network on the DCMAX pin. For example, if the minimum
line voltage is 36 V, RFF is 434 k, operating frequency is
300 kHz and a maximum duty cycle of 70% is required,
VDC(inv) is calculated as follows:
VDC(inv) +
VDC(inv) +
IFF DC
ǒ186.56
) VEA(L)Ǔ
pf f
IFF
Oscillator
Ramp
6.7 k
CFF
ton(max)
125 k
88.2 A 6.7 k 2.33 s
+1.10 V
10 pF 125 k
OUT2
This can be achieved by connecting a 45.3 k resistor
from the DCMAX pin to GND. The maximum duty cycle
limit can be disabled connecting a 100 k resistor between
the DCMAX and VREF pins.
OUT1
Figure 34. Soft−Start Timing Diagram
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16
VSS
NCP1560
If the control outputs need to drive a large capacitive load,
a driver should be used between the NCP1560 and the load.
ON Semiconductor’s MC33152 is a good selection for an
integrated driver. Figures 27 and 28 shows the relationship
between the output’s rise and fall times vs capacitive load.
If the soft−start period is too long, VAUX may discharge to
7.0 V before the converter output is completely in regulation
causing the outputs to be disabled. If the converter output is
not completely discharged when the outputs are reenabled,
the converter will eventually reach regulation exhibiting a
nonmonotonic startup behavior. But, if the converter output
is completely discharged when the outputs are reenabled, the
cycle may repeat and the converter will not start.
In the event of an UV, OV, or cycle skip fault, the soft−start
capacitor is discharged. Once the fault is removed, a
soft−start cycle commences. The soft−start steady state
voltage is approximately 4.1 V.
Time Delay
The overlap delay between the outputs is set connecting
a resistor (RD) between the tD and VREF pins. An overlap
delay of 80 ns is obtained when RD is 60 k. A higher delay
is obtained by increasing RD. As RD increases, the bias
current of the time delay circuit is reduced, increasing its
noise susceptibility. If a delay higher than 150 ns is required,
it is recommended to place a small capacitor between the tD
pin and ground.
The output duty cycle can be adjusted from 0% to 85%
selecting appropriate values of RFF and VDC(inv). It should
be noted that the overlap delay may cause OUT2 to reach
100% duty cycle. Therefore, if OUT2 is used, the maximum
duty cycle of OUT2 needs to be kept below 100%. The
maximum overlap delay, tD(max), depends on the maximum
duty cycle and frequency of operation. The maximum
overlap delay is calculated using the equation below.
Control Outputs
The NCP1560 has two in−phase control outputs, OUT1
and OUT2, with adjustable overlap delay (tD). OUT2
precedes OUT1 during a low to high transition and OUT1
precedes OUT2 at any high to low transition. Figure 35
shows the relationship between OUT1 and OUT2.
tD (Leading)
tD (Trailing)
OUT1
tD(max) v
OUT2
(1 * DC)
2ƒ
For example, if the converter operates at a frequency of
300 kHz with a maximum duty cycle of 80%, the maximum
allowed overlap delay is 333 ns. However, this is a
theoretical limit and variations over the complete operating
range should be considered when selecting the overlap
delay.
Figure 35. Control Outputs Timing Diagram
Generally, OUT1 controls the main switching element.
Output 2, once inverted, can control a synchronous rectifier.
The overlap delay prevents simultaneous conduction.
Output 2 can also be used to control an active clamp reset.
Once VAUX reaches 11 V, the internal startup circuit is
disabled and the One Shot Pulse Generator is enabled. If no
faults are present, the outputs turn ON. Otherwise, the
outputs remain OFF until the fault is removed and VAUX
reaches 11 V again.
The control outputs are biased from VAUX. The outputs
can supply up to 10 mA each and their high state voltage is
usually 0.2 V below VAUX. Therefore, the auxiliary supply
voltage should not exceed the maximum input voltage of the
driver stage.
Additional Information
A 100 W DC−DC converter for telecom systems is
designed and implemented using the NCP1560. The
converter delivers 100 W at 3.3 V and achieves a full load
efficiency of 85%. The system is built using a 4 layer FR4,
single sided board. The components location within the
board is shown in Figure 36 and the complete circuit
schematic is shown in Figure 37. The converter design is
discussed in Application Note AND8105/D. Please contact
your sales representative for board availability.
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17
NCP1560
2.70”
3.10”
Figure 36. Board Arrangement
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18
10
249 k
150 k
R19
10 k
6.81
5.1 k
1000 p
SS
RT
CSKIP
GND
R5
110 k
C8
0.1
C7
10
ON/OFF
Figure 37. Complete Circuit Schematic
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19
VAUX
E3
47.5 k
E2
D3
Open
R9
0
110 k
VREF
*Note: D6 is removed for active clamp/reset operation.
C26 is removed for reset winding operation.
9
8
DCMAX
tD
6
10
VEA
12
OUT2
VREF
13
15
5
CS
VAUX
11
0.01
OUT1
C6
UV/OV
0.1
R4
−
Vin
+
2200 p
C28
L1
10 H
E1
C5
0.1
16
C27
N/C
FF
1M
U1
R1
2
4.7
100
3
C1
R2
Vin
4.7
C9
R7
4
C2
R8
487 k
NCP1560
4.7
A
U4
SFH6156A−4
R18
0 (Short)
1
C3
R34
Open
0.1
C11
R3
4.7
B
EA (out)
R33
0
C14
1000 p
C4
XT3
7
R10
100
D8
MMBT914
R11
0.1
R15
0 (Short)
VAUX
D1
MMBD914
0.1
10 k C12
VREF
R12
10 k
5
D2
C10
D4
MMBD914
R16
R14
MMBD914
XT1
1:100
2T
C23
0.1
NTB30N20
6.2
X6
MJD44H11
4
2
3T 1 11 5T
D6*
MURS120T3
10
MMBD914
14
8,9
R27
D5
X1
1
1T
C22
0 (Short)
R13
XT2
6,7
MMBD914
1000 p
U2
0 (Short)
NTB75N03L09
X3
R28
OUT2 (Isolated)
D7
49.9
SEC_PWR
R25
OUT2 (Isolated)
X5
MMBT2907
10 k
R23
C13
0.047
7
X4
10 k
5
+ U6B
LM358
NTB75N03 L09
R24
0.1
SEC_PWR
6
R30
10 k
C31
R17
10k
−
D9
5
U3
TLV431
D10
1PMT5929BT1
47
U6A
LM358 1
2k
−
C15
R20
R29
5.1 k
3
EA (out)
47
3
+ 8
1.27 k
C16
4
A
47
2
C24 470 p
C21
1000 p
C17
R26
6.2
L2
2 H
C25 0.1
1000 p
X2
IRFR9220
R22
C26*
0.1
R21
4
47
R31
3
C18
C30
4
VAUX
330
1k
8
MC33152
N/C
N/C
7
IN_A
OUT_A
6
VCC
GND
5
IN_B
OUT_B
C19
100 p
2
330
R6
B
C20
C29
MMBD914
E4
−
E5
+
3.3 V
NCP1560
NCP1560
PACKAGE DIMENSIONS
SO−16
D SUFFIX
CASE 751B−05
ISSUE J
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
The product described herein (NCP1560) may be covered by one or more U.S. patents. There may be other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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For additional information, please contact your local
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NCP1560/D