WEDC EDI2AG272128V12D1 2 megabyte sync/sync burst, small outline dimm Datasheet

White Electronic Designs
EDI2AG272128V-D1
ADVANCED*
2 Megabyte Sync/Sync Burst, Small Outline DIMM
FEATURES
2x128Kx72 Synchronous, Synchronous Burst
Flow-Through Architecture
Linear Burst Mode
Clock Controlled Registered Bank Enables (E1#, E2#)
Clock Controlled Byte Write Mode Enable (BWE#)
Clock Controlled Byte Write Enables
(BW1# - BW8#)
Clock Controlled Registered Address
Clock Controlled Registered Global Write (GW#)
Aysnchronous Output Enable (G#)
Internally self-timed Write
Gold Lead Finish
3.3V ± 10% Operation
Access Speed(s): TKHQV=8.5, 9, 10, 12ns
Common Data I/O
High Capacitance (30pf) drive, at rated Access Speed
Single total array Clock
Multiple Vcc and Gnd
The EDI2AG272128VxxD1 is a Synchronous/Synchronous
Burst SRAM, 72 position DIMM (144 contacts) Module,
organized as 2x128Kx72. The Module con tains four
(4) Synchronous Burst Ram Devices, packaged in the
industry standard JEDEC 14mmx20mm TQFP placed on
a Multilayer FR4 Substrate. The module architecture is
defined as a Sync/Sync Burst, Flow-Through, with support
for linear burst. This module provides High Performance,
2-1-1-1 accesses when used in Burst Mode, and used as
a Synchronous Only Mode, provides a high performance
cost advantage over BiCMOS aysnchronous device
architectures.
Synchronous Only operations are performed via strapping
ADSC# Low, and ADSP#/ADV# High, which provides for
Ultra Fast Accesses in Read Mode while providing for
internally self-timed Early Writes.
Synchronous/Synchronous Burst operations are in relation
to an externally supplied clock, Registered Address,
Registered Global Write, Registered Enables as well as
an Asynchronous Output enable. This Module has been
defined with full flexibility, which allows individual control
of each of the eight bytes, as well as Quad Words in both
Read and Write Operations.
*This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
1
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EDI2AG272128V-D1
ADVANCED
PIN CONFIGURATION
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
FUNCTION
VSS
VSS
A0
RFU
A16
A1
A2
A15
A14
A3
A4
A13
A12
A5
A6
A11
A10
A7
A8
A9
VCC
VCC
G#
RFU
GW#
ADV#
ADSP#
ADSC#
E1#
CK
E2#
BWE#
BW1#
DQP0
VCC
VCC
PIN
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
FUNCTION
DQ0
DQ7
DQ1
DQ6
DQ2
DQ5
DQ3
DQ4
VSS
VSS
BW2#
DQP1
VCC
VCC
DQ8
DQ15
DQ9
DQ14
DQ10
DQ13
DQ11
DQ12
VSS
VSS
BW3#
DQP2
VCC
VCC
DQ16
DQ23
DQ17
DQ22
DQ18
DQ21
DQ19
DQ20
PIN
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
FUNCTION
VSS
VSS
BW4#
DQP3
VCC
VCC
DQ24
DQ31
DQ25
DQ30
DQ26
DQ29
DQ27
DQ28
VSS
VSS
BW5#
DQP4
VCC
VCC
DQ32
DQ39
DQ33
DQ38
DQ34
DQ37
DQ35
DQ36
VSS
VSS
BW6#
DQP5
VCC
VCC
DQ40
DQ47
PIN
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
FUNCTION
DQ41
DQ46
DQ42
DQ45
DQ43
DQ44
VSS
VSS
BW7#
DQP6
VCC
VCC
DQ48
DQ55
DQ49
DQ54
DQ50
DQ53
DQ51
DQ52
VSS
VSS
BW8#
DQP7
VCC
VCC
DQ56
DQ63
DQ57
DQ62
DQ58
DQ61
DQ59
DQ60
VSS
VSS
PIN NAMES
DQ0-DQ63
Input/Output Bus
DQP0-DQP7
Parity Bits
A0-A16
Address Bus
E1#, E2#
Synchronous Bank Enables
BWE#
Byte Write Mode Enable
BW1#-BW8#
Byte Write Enables
CK
Array Clock
GW#
Synchronous Global write
Enable
G#
Asynchronous Output
Enable
VCC
3.3V Power Supply
VSS
Gnd
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July 1999
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EDI2AG272128V-D1
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
A0-16
ADSC#
ADSP#
ADV#
BWE#
CK
G#
GW#
ADSC#
ADSP#
ADV#
BWE#
CK
G#
GW#
E#
BW#
E1#
BW1-4#
ADSC#
ADSP#
ADV#
BWE#
CK
G#
GW#
E#
BW#
E2#
ADSC#
ADSP#
ADV#
BWE#
CK
G#
GW#
E#
BW#
BW5-8#
ADSC#
ADSP#
ADV#
BWE#
CK
G#
GW#
E#
BW#
DQ
DQ0-31
DQP0-3
U1
DQ
DQ0-31
DQP0-3
U2
DQ
DQ32-63
DQP4-7
U3
DQ
DQ32-63
DQP4-7
U4
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July 1999
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EDI2AG272128V-D1
ADVANCED
PIN DESCRIPTIONS
DIMM
Pins
Symbol
Type
Description
3, 6, 7, 10, 11, 14
15, 18, 19, 20, 17
16, 13, 12, 9, 8, 5
A0-A16
Input
Synchronous
Addresses: These inputs are registered and must meet the setup and hold times
around the rising edge of CK. The burst counter generates internal addresses
associated with A0 and A1, during burst and wait cycle.
33, 47, 61, 75,
89, 103, 117, 131
BW1#, BW2#,
BW3#, BW4#,
BW5#, BW6#,
BW7#, BW8#
Input
Synchronous
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ cycle.
BW0# controls DQ0-7 and DQP0, BW1# controls DQ8-15 and DQP1. BW2#
controls DQ16-23 and DQP2. BW3# controls DQ24-31 and DQP3.
BW4# controls DQ32-39 and DQP4. BW5# controls DQ40-47 and DQP5.
BW6#controls DQ48-55 and DQP6. BW7# controls DQ56-64 and DQP7.
32
BWE#
Input
Synchronous
Write Enable: This active LOW input gates byte write operations and must meet the
setup and hold times around the rising edge of CK.
25
GW#
Input
Synchronous
Global Write: This active LOW input allows a full 72-bit WRITE to occur
independent of the BWE# and BWx# lines and must meet the setup and hold times
around the rising edge of CK.
30
CK
Input
Synchronous
Clock: This signal registers the addresses, data, chip enables, write control and
burst control inputs on its rising edge. All synchronous inputs must meet setup and
hold times around the clock’s rising edge.
29, 31
E1#, E2#
Input
Synchronous
Bank Enables: These active LOW inputs are used to enable each individual bank
and to gate ADSP#.
23
G#
Input
26
ADV#
Input
Synchronous
Address Status Processor: This active LOW input is used to control the internal
burst counter. A HIGH on this pin generates wait cycle (no address advance)
27
ADSP#
Input
Synchronous
Address Status Processor: This active LOW input, along with EL# and EH# being
LOW, causes a new external address to be registered and a READ cycle is initiated
using the new address.
28
ADSC#
Input
Synchronous
Address Status Controller: This active LOW input causes device to be de-selected
or selected along with new external address to be registered.
A READ or WRITE cycle is initiated depending upon write control inputs.
Various
DQ0-63
Input/Output
Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is
DQ16-23, fourth byte is DQ24-31, fifth byte is DQ32-39, sixth byte is
DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64.
34, 48, 62,
76, 90, 104,
118, 132
DQP0-7
Input/Output
Parity Inputs/Outputs: DQP0 is parity bit for DQ0-7. DQP1 is parity bit for DQ8-15.
DQP2 is parity bit for DQ16-23. DQP3 is parity bit for DQ24-31. DQP4# is parity
bit for DQ32-39. DQP5 is parity bit for DQ40-47. DQP6# is parity bit for DQ48-55.
DQP7 is parity bit for DQ56-64 and DQP7. In order to use the device configured as
a parity bit parity bit 128K x 64, the parity bits need to be tied to Vss through a 10K
ohm resistor.
Various
Vcc
Supply
Core power supply: +3.3V -5%/ + 10%
Various
Vss
Ground
Ground
Output Enable: This active LOW asynchronous input enables the data output
drivers.
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July 1999
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EDI2AG272128V-D1
ADVANCED
SYNCHRONOUS BURST - TRUTH TABLE
Operation
E1#
E2#
ADSP#
ADSC#
ADV#
GW#
G#
CK
DQ
Addr. Used
Deselected Cycle, Power Down; Bank 1
H
X
X
L
X
X
X
L-H
High-Z
None
Deselected Cycle, Power Down; Bank 2
X
H
X
L
X
X
X
L-H
High-Z
None
Read Cycle, Begin Burst; Bank 1
L
H
L
X
X
X
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L
H
L
X
X
X
H
L-H
High-Z
External
Read Cycle, Begin Burst; Bank 2
H
L
L
X
X
X
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H
L
L
X
X
X
H
L-H
High-Z
External
Write Cycle, Begin Burst; Bank 1
L
H
H
L
X
L
X
L-H
D
External
Write Cycle, Begin Burst; Bank 2
H
L
H
L
X
L
X
L-H
D
External
Read Cycle, Begin Burst; Bank 1
L
H
H
L
X
H
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L
H
H
L
X
H
H
L-H
High-Z
External
Read Cycle, Begin Burst; Bank 2
H
L
H
L
X
H
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H
L
H
L
X
H
H
L-H
High-Z
External
Read Cycle, Continue Burst; Bank 1
X
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
X
H
X
H
L
H
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 2
H
X
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H
X
X
H
L
H
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 1
H
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
H
H
X
H
L
H
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 2
H
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H
H
X
H
L
H
H
L-H
High-Z
Next
Write Cycle, Continue Burst; Bank 1
X
H
H
H
L
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 1
H
H
X
H
L
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H
X
H
H
L
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H
H
X
H
L
L
X
L-H
D
Next
Read Cycle, Suspend Burst; Bank 1
X
H
H
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
X
H
H
H
H
H
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 2
H
X
H
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H
X
H
H
H
H
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 1
H
H
X
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
H
H
X
H
H
H
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 2
H
H
X
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H
H
X
H
H
H
H
L-H
High-Z
Current
Write Cycle, Suspend Burst; Bank 1
X
H
H
H
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 1
H
H
X
H
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H
X
H
H
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H
H
X
H
H
L
X
L-H
D
Current
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July 1999
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EDI2AG272128V-D1
ADVANCED
SYNCHRONOUS ONLY - TRUTH TABLE
Operation
E1#
E2#
GW#
G#
ZZ
CK
Synchronous Write-Bank 1
L
H
L
H
L
High-Z
Synchronous Read-Bank 1
L
H
H
L
L
Synchronous Write-Bank 2
H
L
L
H
L
Synchronous Read-Bank 2
H
L
H
L
L
Operating Temperature (Industrial)
Short Circuit Output Current
High-Z
RECOMMENDED DC OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Relative to VSS
VIN
Storage Temperature
Operating Temperature (Commercial)
DQ
-0.5V to +4.6V
-0.5V to VCC +0.5V
-55°C to +125°C
0°C to +70°C
-40°C to +85°C
10 mA
*Stress greater than those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions greater
than those indicated in operational sections of this specifications is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Parameter
Sym
Min
Typ
Max
Units
Supply Voltage
Supply Voltage
Input High
Input Low
Input Leakage
Output Leakage
VCC
VSS
VIH
VIL
ILI
ILO
3.14
0.0
1.1
-0.3
-2
-2
3.3
0.0
3.0
0.0
1
1
3.6
0.0
VCC+0.3
0.3
2
2
V
V
V
V
µA
µA
DC ELECTRICAL CHARACTERISTICS - READ CYCLE
Max
Description
SYM
Typ
8.5
9
10
12
Units
Power Supply Current
Power Supply Current Device
Selected, No Operation
ICC1
1.6
2.2
2.1
2.1
2.0
A
ICC
750
1.5
1.5
1.0
1.0
A
CMOS Standby
ICC3
500
300
300
300
300
mA
Clock Running-Deselect
ICCK
600
1000
1000
750
750
mA
AC TEST LOAD
AC TEST CONDITIONS
Input Pulse Levels
Input and Output Timing Ref.
Output Test equivalencies
VSS to 3.0V
1.25V
DQ
Z0 = 50Ω
Z 0 = 50Ω
50Ω
Fig. 1
Output Load Equivalent
Vt = 1.5V
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July 1999
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EDI2AG272128V-D1
ADVANCED
BURST ADDRESS TABLE (MODE=GND)
BURST ADDRESS TABLE (MODE=NC/VCC)
First
Address
(external)
A-A00
A-A01
A-A10
A-A11
Second
Address
(internal)
A-A01
A-A00
A-A11
A-A10
Third
Address
(internal)
A-A10
A-A11
A-A00
A-A01
Fourth
Address
(internal)
A-A11
A-A10
A-A01
A-A00
First
Address
(external)
A-A00
A-A01
A-A10
A-A11
Second
Address
(internal)
A-A01
A-A10
A-A11
A-A00
Third
Address
(internal)
A-A10
A-A11
A-A00
A-A01
Fourth
Address
(internal)
A-A11
A-A00
A-A01
A-A10
READ CYCLE TIMING PARAMETERS
Description
Clock Cycle Time
Clock High Time
Clock Low Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output Low-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Address Setup
Bank Enable Setup
Address Hold
Bank Enable Hold
8.5ns
Min
Max
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Sym
tKHKH
tKHKL
tKLKH
tKHQV
tKHQX1
tKHQX
tGLQV
tGLQX
tGHQZ
tAVKH
tEVKH
tKHAX
tKHEX
9ns
Min
10
4
4
Max
Min
12
5
5
10ns
Max
9
3
2
10
3
2
4
0
4
0
4
2.5
2.5
1.0
1.0
4
2.5
2.5
1.0
1.0
12ns
Min
Max
15
5
5
12
3
2
5
0
5
2.5
2.5
1.0
1.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*TBD
SYNCHRONOUS ONLY READ CYCLE
tKHKH
tKHKL
tKLKH
CK
tAVKH
Ex#
ADDR
G#
Addr 1
Addr 1
tKHAX
tKHQV
tGLQV
tGLQX
GW#
tKHQX
DQ
Addr 2
Q(Addr 1)
Q(Addr 1)
tKHQZ
Q(Addr 2)
tKHQX1
Read Cycle
Back to Back Read
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July 1999
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EDI2AG272128V-D1
ADVANCED
SYNC-BURST READ CYCLE
tKHKH
tKHKL
tKLKH
CK
tSPVKH
tKHSPX
ADSP#
tSCVKH
tKHSCX
ADSC#
tAVKH
tKHAX
ADDR
BWx,
GW#
tEVKH
tKHEX
Ex#
tAVVKH
tKHAVX
ADV#
tGHQX
tKHQV
G#
tGLQV
tGLQX
tGHQZ
DQ
tKHQX
tKHQX
Burst Read Cycle
Read Cycle
WRITE CYCLE TIMING PARAMETERS
Sym
8.5ns
Min
Max
9ns
Max
Min
12
10ns
Max
12ns
Min Max
15
Units
ns
Description
Clock Cycle Time
tKHKH
Min
10
Clock High Time
tKHKL
4
Clock Low Time
tKLKH
4
5
5
ns
Address Setup
tAVKH
2.5
2.5
2.5
ns
Address Hold
tKHAX
1.0
1.0
1.0
ns
Bank Enable Setup
tEVKH
2.5
2.5
2.5
ns
Bank Enable Hold
tKHEX
1.0
1.0
1.0
ns
Global Write Enable Setup
tWVKH
2.5
2.5
2.5
ns
Global Write Enable Hold
tKHWX
1.0
1.0
1.0
ns
Data Setup
tDVKH
2.5
2.5
2.5
ns
Data Hold
tKHDX
1.0
1.0
1.0
ns
5
5
ns
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EDI2AG272128V-D1
ADVANCED
SYNC (NON-BURST) WRITE CYCLE
tKHKH
tKHKL
tAVKH
tKHAX
tKLKH
CK
Ex#
Addr 1
ADDR
Addr 1
Addr 2
tGWLKH
tKHGWH
GW#
OE#
tKHGH
DQ
tKHDX
tDVKH
tGHKH
Write Cycle
Back to Back Writes
SYNCBURST WRITE CYCLE
tKHKH
tKHKL
tKLKH
CK
ADSP#
ADSC#
tAVKH
tKHAX
ADDR
BWx#
GW#
tEVKH
tKHEX
Ex#
tAVVKH
tKHAVX
ADV#
G#
tDVKH
tKHQX
DQ
tKHQX
Early Write Cycle
Burst - Late Write - Cycle
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EDI2AG272128V-D1
ADVANCED
SYNC (NON-BURST) READ/WRITE CYCLE
tKHKH
tKHKL
tKLKH
CK
tAVKH
Ex#
ADDR
G#
Addr 1
Addr 2
tKHQV
tKHDX
GW#
tKHQX
DQ
Q (Addr 1)
D (Addr 2)
tDVKH
Read Cycle
tKHDX
Write Cycle
Back to Back Cycles
G# Controlled
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
10
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
EDI2AG272128V-D1
ADVANCED
PACKAGE DESCRIPTION
Package No. 409
144 Lead
Small Outline DIMM
0.175
MAX.
R9
R1
R3
R11
2.667 MAX.
0.157
U1
R17
0.788
R15
R7
R13
R5
1.000
MAX.
R18
U3
P1
0.181 TYP
0.913
1.112
1.291
1.490
ORDERING INFORMATION
Part Number
Organization
Voltage
Speed (ns)
Package
EDI2AG272128V85D1*
4x256Kx72
3.3
8.5
144 Small Outline DIMM
EDI2AG272128V9D1*
4x256Kx72
3.3
9
144 Small Outline DIMM
EDI2AG272128V10D1
4x256Kx72
3.3
10
144 Small Outline DIMM
EDI2AG272128V12D1
4x256Kx72
3.3
12
144 Small Outline DIMM
*Consult Factory for Availability
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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