PD - 95480
AUTOMOTIVE MOSFET
IRFP2907ZPbF
Features
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HEXFET® Power MOSFET
Advanced Process Technology
Ultra Low On-Resistance
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free
D
VDSS = 75V
RDS(on) = 4.5mΩ
G
Description
ID = 90A
S
Specifically designed for Automotive applications,
this HEXFET® Power MOSFET utilizes the latest
processing techniques to achieve extremely low
on-resistance per silicon area. Additional features
of this design are a 175°C junction operating
temperature, fast switching speed and improved
repetitive avalanche rating . These features combine to make this design an extremely efficient
and reliable device for use in Automotive applications and a wide variety of other applications.
TO-247AC
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
Parameter
Max.
Units
Continuous Drain Current, VGS @ 10V (Silicon Limited)
170
A
Continuous Drain Current, VGS @ 10V (See Fig. 9)
120
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Package Limited)
90
IDM
Pulsed Drain Current
680
PD @TC = 25°C
Maximum Power Dissipation
310
W
Linear Derating Factor
2.0
± 20
W/°C
V
520
mJ
c
VGS
EAS
Gate-to-Source Voltage
EAS (tested)
Single Pulse Avalanche Energy Tested Value
Single Pulse Avalanche Energy (Thermally Limited)
c
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
TJ
Operating Junction and
TSTG
Storage Temperature Range
i
d
h
Parameter
RθCS
Case-to-Sink, Flat, Greased Surface
RθJA
Junction-to-Ambient
j
300 (1.6mm from case )
10 lbf•in (1.1N•m)
Thermal Resistance
j
A
°C
-55 to + 175
Mounting torque, 6-32 or M3 screw
Junction-to-Case
See Fig.12a,12b,15,16
mJ
Soldering Temperature, for 10 seconds
RθJC
690
j
Typ.
Max.
Units
–––
0.49
°C/W
0.24
–––
–––
40
HEXFET® is a registered trademark of International Rectifier.
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1
7/16/04
IRFP2907ZPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
V(BR)DSS
∆ΒVDSS/∆TJ
RDS(on)
VGS(th)
Min. Typ. Max. Units
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
LD
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Drain Inductance
75
–––
–––
2.0
180
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
0.069
3.5
–––
–––
–––
–––
–––
–––
180
46
65
19
140
97
100
5.0
–––
–––
4.5
4.0
–––
20
250
200
-200
270
–––
–––
–––
–––
–––
–––
–––
LS
Internal Source Inductance
–––
13
–––
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
–––
–––
–––
–––
–––
–––
7500
970
510
3640
650
1020
–––
–––
–––
–––
–––
–––
gfs
IDSS
IGSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Drain-to-Source Leakage Current
f
f
f
6mm (0.25in.)
from package
pF
Diode Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
90
ISM
(Body Diode)
Pulsed Source Current
–––
–––
680
VSD
trr
Qrr
ton
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
–––
–––
–––
–––
41
59
1.3
61
89
c
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C,
L=0.13mH, RG = 25Ω, IAS = 90A, VGS =10V.
Part not recommended for use above this value.
ISD ≤ 90A, di/dt ≤ 340A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
2
Conditions
V VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 90A
V VDS = VGS, ID = 250µA
S VDS = 25V, ID = 90A
µA VDS = 75V, VGS = 0V
VDS = 75V, VGS = 0V, TJ = 125°C
nA VGS = 20V
VGS = -20V
ID = 90A
nC VDS = 60V
VGS = 10V
ns VDD = 38V
ID = 90A
RG = 2.5Ω
VGS = 10V
D
nH Between lead,
G
S
and center of die contact
VGS = 0V
VDS = 25V
ƒ = 1.0MHz, See Fig. 5
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 60V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 60V
Conditions
MOSFET symbol
A
V
ns
nC
D
showing the
integral reverse
G
p-n junction diode.
TJ = 25°C, IS = 90A, VGS = 0V
TJ = 25°C, IF = 90A, VDD = 38V
di/dt = 100A/µs
f
f
S
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Coss eff. is a fixed capacitance that gives the same
charging time as Coss while VDS is rising from 0 to 80% VDSS.
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
This value determined from sample failure population. 100%
tested to this value in production.
Rθ is measured at TJ of approximately 90°C.
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IRFP2907ZPbF
1000
10000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
1000
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
100
100
4.5V
10
4.5V
≤60µs PULSE WIDTH
≤60µs PULSE WIDTH
Tj = 175°C
Tj = 25°C
1
0.1
1
10
10
0.1
100
Fig 1. Typical Output Characteristics
10
100
Fig 2. Typical Output Characteristics
1000
200
Gfs, Forward Transconductance (S)
ID, Drain-to-Source Current (Α)
1
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
T J = 175°C
100
10
T J = 25°C
1
VDS = 25V
≤60µs PULSE WIDTH
0.1
T J = 25°C
150
T J = 175°C
100
50
V DS = 10V
380µs PULSE WIDTH
0
2
4
6
8
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10
0
25
50
75
100
125
150
ID,Drain-to-Source Current (A)
Fig 4. Typical Forward Transconductance
vs. Drain Current
3
IRFP2907ZPbF
100000
12.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
ID= 90A
10000
Ciss
Coss
Crss
1000
VDS= 60V
VDS= 38V
10.0
VGS, Gate-to-Source Voltage (V)
C, Capacitance(pF)
C oss = C ds + C gd
VDS= 15V
8.0
6.0
4.0
2.0
100
0.0
1
10
100
0
VDS, Drain-to-Source Voltage (V)
150
200
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
1000
10000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
100
QG Total Gate Charge (nC)
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
1000
T J = 175°C
100
TJ = 25°C
10
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
100µsec
10
1msec
1
1
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.1
0.0
0.5
1.0
1.5
2.0
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
50
2.5
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFP2907ZPbF
175
ID, Drain Current (A)
150
RDS(on) , Drain-to-Source On Resistance
(Normalized)
2.5
Limited By Package
125
100
75
50
25
0
ID = 90A
VGS = 10V
2.0
1.5
1.0
0.5
25
50
75
100
125
150
-60 -40 -20 0
175
T C , Case Temperature (°C)
20 40 60 80 100 120 140 160 180
T J , Junction Temperature (°C)
Fig 10. Normalized On-Resistance
vs. Temperature
Fig 9. Maximum Drain Current vs.
Case Temperature
1
Thermal Response ( Z thJC )
D = 0.50
0.1
0.20
0.10
0.05
0.02
0.01
0.01
0.001
τJ
SINGLE PULSE
( THERMAL RESPONSE )
R1
R1
τJ
τ1
τ1
R2
R2
τ2
R3
R3
τ3
τ2
Ci= τi/Ri
Ci i/Ri
τC
τ
τ3
Ri (°C/W)
0.1224
τi (sec)
0.000360
0.1238
0.001463
0.2433
0.021388
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFP2907ZPbF
DRIVER
L
VDS
D.U.T
RG
VGS
20V
+
V
- DD
IAS
tp
A
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
EAS , Single Pulse Avalanche Energy (mJ)
2500
15V
ID
16A
25A
BOTTOM 90A
TOP
2000
1500
1000
500
tp
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
I AS
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
10 V
QGS
QGD
4.0
Charge
Fig 13a. Basic Gate Charge Waveform
L
DUT
0
1K
Fig 13b. Gate Charge Test Circuit
6
VCC
VGS(th) Gate threshold Voltage (V)
VG
3.5
3.0
2.5
ID = 250µA
2.0
1.5
1.0
-75 -50 -25
0
25
50
75 100 125 150 175 200
T J , Temperature ( °C )
Fig 14. Threshold Voltage vs. Temperature
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IRFP2907ZPbF
Avalanche Current (A)
1000
Duty Cycle = Single Pulse
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆ Tj = 25°C due to
avalanche losses
100
0.01
0.05
0.10
10
1
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
EAR , Avalanche Energy (mJ)
600
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 90A
500
400
300
200
100
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
vs. Temperature
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175
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T jmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asT jmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav ) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
7
IRFP2907ZPbF
D.U.T
Driver Gate Drive
+
-
P.W.
+
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
V DD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• I SD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
P.W.
Period
*
RG
D=
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
Period
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
*
VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V DS
V GS
RG
RD
D.U.T.
+
-V DD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on)
tr
t d(off)
tf
Fig 18b. Switching Time Waveforms
8
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IRFP2907ZPbF
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
TO-247AC Part Marking Information
EXAMPLE: T HIS IS AN IRFPE30
WIT H ASSEMBLY
LOT CODE 5657
ASSEMBLED ON WW 35, 2000
IN THE AS SEMBLY LINE "H"
Note: "P" in assembly line
position indicates "Lead-Free"
INT ERNATIONAL
RECT IFIER
LOGO
PART NUMBER
IRFPE30
56
035H
57
ASSEMBLY
LOT CODE
DAT E CODE
YEAR 0 = 2000
WEEK 35
LINE H
TO-247AC package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 07/04
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9