AD ADF4113 Rf pll frequency synthesizer Datasheet

a
RF PLL Frequency Synthesizers
ADF4110/ADF4111/ADF4112/ADF4113
GENERAL DESCRIPTION
FEATURES
ADF4110: 550 MHz
ADF4111: 1.2 GHz
ADF4112: 3.0 GHz
ADF4113: 4.0 GHz
2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (VP) Allows Extended
Tuning Voltage in 3 V Systems
Programmable Dual Modulus Prescaler 8/9, 16/17,
32/33, 64/65
Programmable Charge Pump Currents
Programmable Antibacklash Pulsewidth
3-Wire Serial Interface
Analog and Digital Lock Detect
Hardware and Software Power-Down Mode
The ADF4110 family of frequency synthesizers can be used
to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. They
consist of a low-noise digital PFD (Phase Frequency Detector),
a precision charge pump, a programmable reference divider,
programmable A and B counters and a dual-modulus prescaler
(P/P+1). The A (6-bit) and B (13-bit) counters, in conjunction
with the dual modulus prescaler (P/P+1), implement an N
divider (N = BP + A). In addition, the 14-bit reference counter
(R Counter), allows selectable REFIN frequencies at the PFD
input. A complete PLL (Phase-Locked Loop) can be implemented if the synthesizer is used with an external loop filter and
VCO (Voltage Controlled Oscillator).
Control of all the on-chip registers is via a simple 3-wire interface.
The devices operate with a power supply ranging from 2.7 V to
5.5 V and can be powered down when not in use.
APPLICATIONS
Base Stations for Wireless Radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VP
RSET
CPGND
REFERENCE
14-BIT
R COUNTER
REFIN
PHASE
FREQUENCY
DETECTOR
14
CHARGE
PUMP
CP
R COUNTER
LATCH
CLK
24-BIT
INPUT REGISTER
DATA
FUNCTION
LATCH
22
LOCK
DETECT
LE
A, B COUNTER
LATCH
SDOUT
CURRENT
SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
19
FROM
FUNCTION
LATCH
CURRENT
SETTING 1
HIGH Z
13
AVDD
MUX
N = BP + A
RFINA
PRESCALER
P/P +1
RFINB
13-BIT
B COUNTER
SDOUT
LOAD
LOAD
6-BIT
A COUNTER
6
CE
AGND
MUXOUT
M3
M2
M1
ADF4110/ADF4111
ADF4112/ADF4113
DGND
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1
ADF4110/ADF4111/ADF4112/ADF4113–SPECIFICATIONS
(AV = DV = 3 V ⴞ 10%, 5 V ⴞ 10%; AV ≤ V ≤ 6.0 V; AGND = DGND = CPGND = 0 V; R = 4.7 k⍀; T = T to T unless otherwise noted)
DD
DD
Parameter
RF CHARACTERISTICS (3 V)
RF Input Frequency
ADF4110
ADF4110
ADF4111
ADF4112
ADF4112
ADF4113
RF Input Sensitivity
Maximum Allowable Prescaler
Output Frequency3
RF CHARACTERISTICS (5 V)
RF Input Frequency
ADF4110
ADF4111
ADF4112
ADF4113
ADF4113
RF Input Sensitivity
Maximum Allowable Prescaler
Output Frequency3
DD
P
B Version
SET
2
B Chips
Unit
MIN
MAX
Test Conditions/Comments
See Figure 25 for Input Circuit.
Use a square wave for lower frequencies.
45/550
25/550
0.045/1.2
0.2/3.0
0.1/3.0
0.2/3.7
–15/0
45/550
25/550
0.045/1.2
0.2/3.0
0.1/3.0
0.2/3.7
–15/0
MHz min/max
MHz min/max
GHz min/max
GHz min/max
GHz min/max
GHz min/max
dBm min/max
165
165
MHz max
25/550
0.025/1.4
0.1/3.0
0.2/3.7
0.2/4.0
–10/0
25/550
0.025/1.4
0.1/3.0
0.2/3.7
0.2/4.0
–10/0
MHz min/max
GHz min/max
GHz min/max
GHz min/max
GHz min/max
dBm min/max
200
200
MHz max
REFIN CHARACTERISTICS
REFIN Input Frequency
Reference Input Sensitivity4
0/100
–5/0
0/100
–5/0
MHz min/max
dBm min/max
REFIN Input Capacitance
REFIN Input Current
10
± 100
10
± 100
pF max
µA max
PHASE DETECTOR
Phase Detector Frequency5
55
55
MHz max
CHARGE PUMP
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP 3-State Leakage Current
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
5
625
2.5
2.7/10
1
2
1.5
2
5
625
2.5
2.7/10
1
2
1.5
2
mA typ
µA typ
% typ
kΩ typ
nA typ
% typ
% typ
% typ
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
0.8 × DVDD
0.2 × DVDD
±1
10
0.8 × DVDD
0.2 × DVDD
±1
10
V min
V max
µA max
pF max
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
DVDD – 0.4
0.4
DVDD – 0.4
0.4
V min
V max
2.7/5.5
AVDD
AVDD/6.0
2.7/5.5
AVDD
AVDD/6.0
V min/V max
5.5
5.5
7.5
11
0.5
1
4.5
4.5
6.5
8.5
0.5
1
mA max
mA max
mA max
mA max
mA max
µA typ
POWER SUPPLIES
AVDD
DVDD
VP
IDD6 (AIDD + DIDD )
ADF4110
ADF4111
ADF4112
ADF4113
IP
Low Power Sleep Mode
A
Input Level = –10 dBm
Input Level = –10 dBm
Input Level = –10 dBm
Use a square wave for lower frequencies.
–2–
V min/V max
Input Level = –5 dBm
AC-Coupled. When DC-Coupled:
0 to VDD max (CMOS-Compatible)
Programmable: See Table V
With RSET = 4.7 kΩ
With RSET = 4.7 kΩ
See Table V
0.5 V ≤ VCP ≤ VP – 0.5
0.5 V ≤ VCP ≤ VP – 0.5
VCP = VP/2
IOH = 500 µA
IOL = 500 µA
AVDD ≤ VP ≤ 6.0 V
See Figures 22 and 23
4.5 mA Typical
4.5 mA Typical
6.5 mA Typical
8.5 mA Typical
TA = 25°C
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
Parameter
NOISE CHARACTERISTICS
ADF4113 Phase Noise Floor 7
Phase Noise Performance8
ADF4110: 540 MHz Output9
ADF4111: 900 MHz Output10
ADF4112: 900 MHz Output10
ADF4113: 900 MHz Output10
ADF4111: 836 MHz Output11
ADF4112: 1750 MHz Output 12
ADF4112: 1750 MHz Output 13
ADF4112: 1960 MHz Output 14
ADF4113: 1960 MHz Output 14
ADF4113: 3100 MHz Output 15
Spurious Signals
ADF4110: 540 MHz Output9
ADF4111: 900 MHz Output10
ADF4112: 900 MHz Output10
ADF4113: 900 MHz Output10
ADF4111: 836 MHz Output11
ADF4112: 1750 MHz Output 12
ADF4112: 1750 MHz Output 13
ADF4112: 1960 MHz Output 14
ADF4113: 1960 MHz Output 14
ADF4113: 3100 MHz Output15
B Version
B Chips2
Unit
Test Conditions/Comments
–171
–164
–171
–164
dBc/Hz typ
dBc/Hz typ
–91
–87
–90
–91
–78
–86
–66
–84
–85
–86
–91
–87
–90
–91
–78
–86
–66
–84
–85
–86
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
@ 25 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ VCO Output
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 300 Hz Offset and 30 kHz PFD Frequency
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 200 Hz Offset and 10 kHz PFD Frequency
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 1 kHz Offset and 200 kHz PFD Frequency
@ 1 kHz Offset and 1 MHz PFD Frequency
–97/–106
–98/–110
–91/–100
–100/–110
–81/–84
–88/–90
–65/–73
–80/–84
–80/–84
–80/–82
–97/–106
–98/–110
–91/–100
–100/–110
–81/–84
–88/–90
–65/–73
–80/–84
–80/–84
–82/–82
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
@ 30 kHz/60 kHz and 30 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
@ 10 kHz/20 kHz and 10 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
@ 1 MHz/2 MHz and 1 MHz PFD Frequency
NOTES
1
Operating temperature range is as follows: B Version: –40°C to +85°C.
The B Chip specifications are given as typical values.
3
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency
which is less than this value.
4
AVDD = DVDD = 3 V; For AVDD = DVDD = 5 V, use CMOS-compatible levels.
5
Guaranteed by design.
6
TA = 25°C; AVDD = DVDD = 3 V; P = 16; SYNC = 0; DLY = 0; RFIN for ADF4110 = 540 MHz; RFIN for ADF4111, ADF4112, ADF4113 = 900 MHz.
7
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).
8
The phase noise is measured with the EVAL-ADF411XEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for
the synthesizer (fREFOUT = 10 MHz @ 0 dBm). SYNC = 0; DLY = 0 (See Table III).
9
fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; Loop B/W = 20 kHz.
10
fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz.
11
fREFIN = 10 MHz; fPFD = 30 kHz; Offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; Loop B/W = 3 kHz.
12
fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; Loop B/W = 20 kHz.
13
fREFIN = 10 MHz; fPFD = 10 kHz; Offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; Loop B/W = 1 kHz.
14
fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; Loop B/W = 20 kHz.
15
fREFIN = 10 MHz; fPFD = 1 MHz; Offset frequency = 1 kHz; f RF = 3100 MHz; N = 3100; Loop B/W = 20 kHz.
2
Specifications subject to change without notice.
(AVDD = DVDD = 3 V ⴞ 10%, 5 V ⴞ 10%; AVDD ≤ VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V;
SET = 4.7 k⍀; TA = TMIN to TMAX unless otherwise noted)
TIMING CHARACTERISTICS1 R
Parameter
Limit at TMIN to TMAX
(B Version)
Unit
Test Conditions/Comments
t1
t2
t3
t4
t5
t6
10
10
25
25
10
20
ns min
ns min
ns min
ns min
ns min
ns min
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulsewidth
NOTES
1
Guaranteed by design but not production tested.
Specifications subject to change without notice.
REV. 0
–3–
ADF4110/ADF4111/ADF4112/ADF4113
t3
t4
CLOCK
t1
DATA
DB20 (MSB)
t2
DB19
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t6
LE
t5
LE
Figure 1. Timing Diagram
CSP θJA Thermal Impedance
(Paddle Not Soldered) . . . . . . . . . . . . . . . . . . . . . 216°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ABSOLUTE MAXIMUM RATINGS 1, 2
(TA = 25°C unless otherwise noted)
AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
VP to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VP to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to VP + 0.3 V
REFIN, RFINA, RFINB to GND . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
TSSOP θJA Thermal Impedance . . . . . . . . . . . . . 150.4°C/W
CSP θJA Thermal Impedance (Paddle Soldered) . . . 122°C/W
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
This device is a high-performance RF integrated circuit with an ESD rating of
< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.
3
GND = AGND = DGND = 0 V.
TRANSISTOR COUNT
6425 (CMOS) and 303 (Bipolar).
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the
ADF4110/ADF4111/ADF4112/ADF4113 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option*
ADF4110BRU
ADF4110BCP
ADF4111BRU
ADF4111BCP
ADF4112BRU
ADF4112BCP
ADF4113BRU
ADF4113BCP
ADF4113BCHIPS
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Thin Shrink Small Outline Package (TSSOP)
Chip Scale Package (CSP)
Thin Shrink Small Outline Package (TSSOP)
Chip Scale Package (CSP)
Thin Shrink Small Outline Package (TSSOP)
Chip Scale Package (CSP)
Thin Shrink Small Outline Package (TSSOP)
Chip Scale Package (CSP)
DICE
RU-16
CP-20
RU-16
CP-20
RU-16
CP-20
RU-16
CP-20
DICE
*Contact the factory for chip availability.
–4–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
RSET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The
nominal voltage potential at the RSET pin is 0.56 V. The relationship between ICP and RSET is
ICP max =
2
CP
3
4
5
CPGND
AGND
RFINB
6
7
RFINA
AVDD
8
REFIN
9
10
DGND
CE
11
CLK
12
DATA
13
LE
14
MUXOUT
15
DVDD
16
VP
23.5
RSET
So, with RSET = 4.7 kΩ, ICPmax = 5 mA.
Charge Pump Output. When enabled this provides ±ICP to the external loop filter, which in turn drives the
external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF. See Figure 25.
Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.
Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 kΩ. See Figure 24. This input can be driven from a TTL or CMOS crystal oscillator or
it can be ac-coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into threestate mode. Taking the pin high will power up the device depending on the status of the power-down bit F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one
of the four latches, the latch being selected using the control bits.
This multiplexer output allows either the Lock Detect, the scaled RF or the scaled Reference Frequency
to be accessed externally.
Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V,
it can be set to 6 V and used to drive a VCO with a tuning range of up to 6 V.
PIN CONFIGURATIONS
CPGND
13 LE
TOP VIEW 12 DATA
(Not to Scale)
11 CLK
RFINA 6
RFINB 5
REV. 0
AVDD 7
10 CE
REFIN 8
9
AGND
2
AGND
3
RFINB
4
RFINA
5
–5–
18 VP
17 DVDD
16 DVDD
15 MUXOUT
ADF4110
ADF4111
ADF4112
ADF4113
14 LE
13 DATA
TOP VIEW
(Not to Scale)
12 CLK
11 CE
AVDD 6
DGND
1
DGND 10
14 MUXOUT
19 RSET
15 DVDD
DGND 9
AGND 4
ADF4110
ADF4111
ADF4112
ADF4113
AVDD 7
CPGND 3
20 CP
16 VP
RSET 1
CP 2
CHIP SCALE PACKAGE
REFIN 8
TSSOP
ADF4110/ADF4111/ADF4112/ADF4113–Typical Performance Characteristics
0
FREQ
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
MAGS11
0.89207
0.8886
0.89022
0.96323
0.90566
0.90307
0.89318
0.89806
0.89565
0.88538
0.89699
0.89927
0.87797
0.90765
0.88526
0.81267
0.90357
0.92954
0.92087
0.93788
ANGS11
–2.0571
–4.4427
–6.3212
–2.1393
–12.13
–13.52
–15.746
–18.056
–19.693
–22.246
–24.336
–25.948
–28.457
–29.735
–31.879
–32.681
–31.522
–34.222
–36.961
–39.343
FREQ
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
IMPEDANCE – OHMS
50
MAGS11
0.9512
0.93458
0.94782
0.96875
0.92216
0.93755
0.96178
0.94354
0.95189
0.97647
0.98619
0.95459
0.97945
0.98864
0.97399
0.97216
ANGS11
–40.134
–43.747
–44.393
–46.937
–49.6
–51.884
–51.21
–53.55
–56.786
–58.781
–60.545
–61.43
–61.241
–64.051
–66.19
–63.775
ICP = 5mA
LOOP BANDWIDTH = 20kHz
–30
RES. BANDWIDTH = 10Hz
–40
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
–50
AVERAGES = 19
–60
–92.5dBc/Hz
–70
–80
–90
–2kHz
10dB/DIVISION
–40
0
900MHz
+1kHz
+2kHz
RL = –40dBc/Hz
RMS NOISE = 0.52ⴗ
–50
VDD = 3V
VP = 3V
–60
PHASE NOISE – dBc/Hz
–5
–1kHz
Figure 5. ADF4113 Phase Noise (900 MHz, 200 kHz,
20 kHz) with DLY and SYNC Enabled
Figure 2. S-Parameter Data for the ADF4113 RF Input (Up
to 1.8 GHz)
–10
–15
TA = +85ⴗC
–20
VDD = 3V, VP = 5V
PFD FREQUENCY = 200kHz
–20
–100
RF INPUT POWER – dBm
REFERENCE
LEVEL = –4.2dBm
–10
OUTPUT POWER – dB
FREQ-UNIT PARAM-TYPE DATA-FORMAT KEYWORD
GHz
S
MA
R
TA = +25ⴗC
–25
0.52ⴗ rms
–70
–80
–90
–100
–110
–120
–30
–130
TA = –40ⴗC
–35
0
1
3
2
RF INPUT FREQUENCY – GHz
–140
100Hz
5
4
Figure 3. Input Sensitivity (ADF4113)
10dB/DIVISION
–40
REFERENCE
LEVEL = –4.2dBm
VDD = 3V, VP = 5V
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
–40
VIDEO BANDWIDTH = 10Hz
–50
SWEEP = 1.9 SECONDS
AVERAGES = 19
–60
–91.0dBc/Hz
–70
0.62ⴗ rms
–70
–80
–90
–100
–110
–80
–120
–90
–130
–140
100Hz
–100
–2kHz
–1kHz
900MHz
+1kHz
RMS NOISE = 0.62ⴗ
–60
PFD FREQUENCY = 200kHz
–30
RL = –40dBc/Hz
–50
ICP = 5mA
PHASE NOISE – dBc/Hz
OUTPUT POWER – dB
–20
1MHz
Figure 6. ADF4113 Integrated Phase Noise (900 MHz,
200 kHz, 20 kHz, Typical Lock Time: 400 µ s)
0
–10
FREQUENCY OFFSET FROM 900MHz CARRIER
+2kHz
Figure 4. ADF4113 Phase Noise (900 MHz, 200 kHz, 20 kHz)
FREQUENCY OFFSET FROM 900MHz CARRIER
1MHz
Figure 7. ADF4113 Integrated Phase Noise (900 MHz,
200 kHz, 35 kHz, Typical Lock Time: 200 µ s)
–6–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
10dB/DIVISION
–40
0
REFERENCE
LEVEL = –4.2dBm
VDD = 3V, VP = 5V
–50
–20
PFD FREQUENCY = 200kHz
–30
LOOP BANDWIDTH = 20kHz
–60
RES. BANDWIDTH = 10Hz
–40
VIDEO BANDWIDTH = 10Hz
–50
SWEEP = 2.5 SECONDS
AVERAGES = 30
–60
–70
–70
1.6ⴗ rms
–80
–90
–100
–110
–120
–90.2dBc
–80
–130
–90
–140
100Hz
–100
–400kHz
–200kHz
900MHz
+200kHz
+400kHz
Figure 8. ADF4113 Reference Spurs (900 MHz, 200 kHz,
20 kHz)
0
REFERENCE
LEVEL = –4.2dBm
–20
VDD = 3V, VP = 5V
ICP = 5mA
–10
PFD FREQUENCY = 200kHz
–20
POWER OUTPUT – dB
OUTPUT POWER – dB
–30
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
–40
SWEEP = 2.5 SECONDS
–50
AVERAGES = 30
–60
–70
REFERENCE
LEVEL = –5.7dBm
–30
RES. BANDWIDTH = 3Hz
–40
VIDEO BANDWIDTH = 3Hz
POSITIVE PEAK DETECT
MODE
–60
–79.6dBc
–70
–80
–90
–100
–400kHz
–200kHz
900MHz
+200kHz
–80kHz
+400kHz
Figure 9. ADF4113 Reference Spurs (900 MHz, 200 kHz,
35 kHz)
REFERENCE
LEVEL = –8.0dBm
–10
–20
–40kHz
0
VDD = 3V, VP = 5V
ICP = 5mA
–10
PFD FREQUENCY = 30kHz
–20
REFERENCE
LEVEL = –4.2dBm
OUTPUT POWER – dB
VIDEO BANDWIDTH = 10kHz
SWEEP = 477ms
–50
AVERAGES = 10
–60
–70
–80
+80kHz
VDD = 3V, VP = 5V
ICP = 5mA
LOOP BANDWIDTH = 100kHz
RES. BANDWIDTH = 10kHz
–40
+40kHz
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 3kHz
–30
1750MHz
Figure 12. ADF4113 Reference Spurs (1750 MHz, 30 kHz,
3 kHz)
0
OUTPUT POWER – dB
ICP = 5mA
SWEEP = 255 SECONDS
–90
–30
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
–40
SWEEP = 1.9 SECONDS
–50
AVERAGES = 45
–60
–86.6dBc/Hz
–70
–80
–75.2dBc/Hz
–90
–90
–100
–400Hz
–200Hz
1750MHz
+200Hz
–100
+400Hz
Figure 10. ADF4113 Phase Noise (1750 MHz, 30 kHz,
3 kHz)
REV. 0
VDD = 3V, VP = 5V
PFD FREQUENCY = 30kHz
–50
–89.3dBc
–80
1MHz
LOOP BANDWIDTH = 3kHz
LOOP BANDWIDTH = 35kHz
–100
FREQUENCY OFFSET FROM 1750MHz CARRIER
Figure 11. ADF4113 Integrated Phase Noise (1750 MHz,
30 kHz, 3 kHz)
0
–10
RMS NOISE = 1.6ⴗ
ICP = 5mA
PHASE NOISE – dBc/Hz
OUTPUT POWER – dB
–10
RL = –40dBc/Hz
–2kHz
–1kHz
3100MHz
+1kHz
+2kHz
Figure 13. ADF4113 Phase Noise (3100 MHz, 1 MHz,
100 kHz)
–7–
ADF4110/ADF4111/ADF4112/ADF4113
10dB/DIVISION
–40
RL = –40dBc/Hz
RMS NOISE = 1.7ⴗ
–60
–50
VDD = 3V
VP = 3V
1.7ⴗ rms
PHASE NOISE – dBc/Hz
PHASE NOISE – dBc/Hz
–60
–70
–80
–90
–100
–110
–70
–80
–90
–120
–130
–140
100Hz
FREQUENCY OFFSET FROM 3100MHz CARRIER
–100
–40
1MHz
Figure 14. ADF4113 Integrated Phase Noise (3100 MHz,
1 MHz, 100 kHz)
0
REFERENCE
LEVEL = –17.2dBm
–10
ICP = 5mA
FIRST REFERENCE SPUR – dBc
LOOP BANDWIDTH = 100kHz
OUTPUT POWER – dB
60
RES. BANDWIDTH = 1kHz
–40
VIDEO BANDWIDTH = 1kHz
SWEEP = 13 SECONDS
AVERAGES = 1
–60
–80.6dBc
–70
80
100
–60
VDD = 3V, VP = 5V
–30
–50
20
40
TEMPERATURE – ⴗC
Figure 17. ADF4113 Phase Noise vs. Temperature
(900 MHz, 200 kHz, 20 kHz)
PFD FREQUENCY = 1MHz
–20
0
–20
–80
VDD = 3V
VP = 5V
–70
–80
–90
–90
–100
–2MHz
–1MHz
3100MHz
+1MHz
–100
–40
+2MHz
Figure 15. ADF4113 Reference Spurs (3100 MHz, 1 MHz,
100 kHz)
20
40
TEMPERATURE – ⴗC
60
80
100
Figure 18. ADF4113 Reference Spurs vs. Temperature
(900 MHz, 200 kHz, 20 kHz)
–5
–120
VDD = 3V
VP = 5V
–15
FIRST REFERENCE SPUR – dBc
–130
PHASE NOISE – dBc/Hz
0
–20
–140
–150
–160
–170
VDD = 3V
VP = 5V
–25
–35
–45
–55
–65
–75
–85
–95
–180
1
10
100
1000
PHASE DETECTOR FREQUENCY – kHz
–105
10000
Figure 16. ADF4113 Phase Noise (Referred to CP Output)
vs. PFD Frequency
0
1
2
3
TUNING VOLTAGE – Volts
4
5
Figure 19. ADF4113 Reference Spurs (200 kHz) vs.
VTUNE (900 MHz, 200 kHz, 20 kHz)
–8–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
10
–60
9
8
ADF4113
–70
7
AIDD – mA
PHASE NOISE – dBc/Hz
VDD = 3V
VP = 5V
–80
6
5
ADF4112
4
3
–90
2
ADF4110
ADF4111
1
–100
–40
0
–20
0
20
40
TEMPERATURE – ⴗC
60
80
100
0
16/17
32/33
64/65
PRESCALER VALUE
Figure 20. ADF4113 Phase Noise vs. Temperature
(836 MHz, 30 kHz, 3 kHz)
Figure 22. AIDD vs. Prescaler Value
–60
3.0
VDD = 3V
VP = 5V
VDD = 3V
VP = 3V
2.5
–70
2.0
DIDD – mA
FIRST REFERENCE SPUR – dBc
8/9
–80
1.5
1.0
–90
–100
–40
0.5
–20
0
20
40
TEMPERATURE – ⴗC
60
80
0
100
Figure 21. ADF4113 Reference Spurs vs. Temperature
(836 MHz, 30 kHz, 3 kHz)
REV. 0
0
50
100
150
PRESCALER OUTPUT FREQUENCY – MHz
200
Figure 23. DIDD vs. Prescaler Output Frequency
(ADF4110, ADF4111, ADF4112, ADF4113)
–9–
ADF4110/ADF4111/ADF4112/ADF4113
CIRCUIT DESCRIPTION
Pulse Swallow Function
REFERENCE INPUT SECTION
The A and B counters, in conjunction with the dual modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:
The reference input stage is shown in Figure 24. SW1 and SW2
are normally-closed switches. SW3 is normally-open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
POWER-DOWN
CONTROL
NC
100k⍀
SW2
TO R COUNTER
REFIN NC
fVCO = [(P × B) + A] × fREFIN/R
fVCO
Output frequency of external voltage controlled oscillator (VCO).
P
Preset modulus of dual modulus prescaler
B
Preset Divide Ratio of binary 13-bit counter (3 to 8191).
A
Preset Divide Ratio of binary 6-bit swallow counter (0 to
63).
BUFFER
SW1
SW3
fREFIN Output frequency of the external reference frequency
oscillator.
NO
Figure 24. Reference Input Stage
R
Preset divide ratio of binary 14-bit programmable reference counter (1 to 16383).
RF INPUT STAGE
The RF input stage is shown in Figure 25. It is followed by a
2-stage limiting amplifier to generate the CML (Current Mode
Logic) clock levels needed for the prescaler.
BIAS
GENERATOR
500⍀
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
1.6V
AVDD
500⍀
N = BP + A
13-BIT B
COUNTER
RFINA
FROM RF
INPUT STAGE
RFINB
PRESCALER
P/P + 1
MODULUS
CONTROL
TO PFD
LOAD
LOAD
6-BIT A
COUNTER
AGND
Figure 25. RF Input Stage
Figure 26. A and B Counters
PRESCALER (P/P+1)
The dual-modulus prescaler (P/P+1), along with the A and B
counters, enables the large division ratio, N, to be realized
(N = BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the RF input stage and divides it
down to a manageable frequency for the CMOS A and B counters.
The prescaler is programmable. It can be set in software to 8/9,
16/17, 32/33, or 64/65. It is based on a synchronous 4/5 core.
A AND B COUNTERS
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL feedback counter. The counters are specified to work when the
prescaler output is 200 MHz or less. Thus, with an RF input
frequency of 2.5 GHz, a prescaler value of 16/17 is valid but a
value of 8/9 is not valid.
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE
PUMP
The PFD takes inputs from the R counter and N counter
(N = BP + A) and produces an output proportional to the phase
and frequency difference between them. Figure 27 is a simplified schematic. The PFD includes a programmable delay element
which controls the width of the antibacklash pulse. This pulse
ensures that there is no dead zone in the PFD transfer function
and minimizes phase noise and reference spurs. Two bits in the
Reference Counter Latch, ABP2 and ABP1 control the width
of the pulse. See Table III.
–10–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When
lock has been detected this output will be high with narrow lowgoing pulses.
VP
CHARGE
PUMP
HI
D1
Q1
UP
U1
DVDD
R DIVIDER
CLR1
PROGRAMMABLE
DELAY
ABP1
CLR2
HI
D2
Q2
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
CP
U3
ABP2
MUX
CONTROL
MUXOUT
DOWN
DGND
U2
Figure 28. MUXOUT Circuit
N DIVIDER
CPGND
INPUT SHIFT REGISTER
The ADF4110 family digital section includes a 24-bit input shift
register, a 14-bit R counter and a 19-bit N counter, comprising
a 6-bit A counter and a 13-bit B counter. Data is clocked into
the 24-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the two LSBs DB1, DB0 as
shown in the timing diagram of Figure 1. The truth table for
these bits is shown in Table VI. Table I shows a summary of
how the latches are programmed.
R DIVIDER
N DIVIDER
CP OUTPUT
Figure 27. PFD Simplified Schematic and Timing
(In Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4110 family allows the
user to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2 and M1 in the function
latch. Table V shows the full truth table. Figure 28 shows the
MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Table I. C2, C1 Truth Table
Control Bits
C2
C1
Data Latch
0
0
1
1
R Counter
N Counter (A and B)
Function Latch (Including Prescaler)
Initialization Latch
Digital lock detect is active high. When LDP in the R counter
latch is set to 0, digital lock detect is set high when the phase
error on three consecutive Phase Detector cycles is less than 15 ns.
With LDP set to 1, five consecutive cycles of less than 15 ns
are required to set the lock detect. It will stay set high until a
phase error of greater than 25 ns is detected on any subsequent
PD cycle.
REV. 0
–11–
0
1
0
1
ADF4110/ADF4111/ADF4112/ADF4113
Table II. ADF4110 Family Latch Summary
DB23
X
DLY
SYNC
DB22 DB21
DLY
SYNC
LOCK
DETECT
PRECISION
RESERVED
REFERENCE COUNTER LATCH
TEST
MODE BITS
DB20 DB19
LDP
ANTIBACKLASH
WIDTH
DB18 DB17
T2
T1
DB16 DB15
ABP2 ABP1
CONTROL
BITS
14-BIT REFERENCE COUNTER, R
R14
DB14 DB13
R13
R12
DB12 DB11
R11
R10
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
R9
R8
R7
R6
R5
R4
R3
R2
R1
DB1
DB0
C2 (0) C1 (0)
X = DON'T CARE
RESERVED
DB23 DB22
X
X
CP GAIN
N COUNTER LATCH
DB21 DB20
G1
B13
DB19
DB18 DB17 DB16 DB15
B12
B11
B10
B9
B8
DB14 DB13
B7
B6
CONTROL
BITS
6-BIT A COUNTER
13-BIT B COUNTER
DB12 DB11
B5
B4
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
B3
B2
B1
A6
A5
A4
A3
A2
A1
C2 (0) C1 (1)
CONTROL
BITS
DB1
DB0
X = DON'T CARE
DB20 DB19
DB18 DB17
CPI6
CPI4
CPI5
CPI3
DB16 DB15 DB14 DB13 DB12 DB11
CPI2
CPI1
TC4
TC3
TC2
TC1
COUNTER
RESET
PD2
POWERDOWN 1
P1
PD
POLARITY
DB22 DB21
TIMER COUNTER
CONTROL
CP
THREESTATE
P2
CURRENT
SETTING
1
FASTLOCK
ENABLE
DB23
CURRENT
SETTING
2
FASTLOCK
MODE
PRESCALER
VALUE
POWERDOWN 2
FUNCTION LATCH
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
F5
F4
F3
F2
M3
M2
M1
PD1
F1
C2 (1) C1 (0)
CONTROL
BITS
MUXOUT
CONTROL
DB1
DB0
DB19 DB18
DB17 DB16
DB15 DB14
CPI3
CPI1
CPI2
DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
F4
F3
F2
M3
M2
M1
PD1
F1
TIMER COUNTER
CONTROL
CPI5
CPI4
COUNTER
RESET
CPI6
POWERDOWN 1
PD2
PD
POLARITY
P1
CP
THREESTATE
DB21 DB20
P2
CURRENT
SETTING
1
FASTLOCK
ENABLE
DB23 DB22
CURRENT
SETTING
2
FASTLOCK
MODE
PRESCALER
VALUE
POWERDOWN 2
INITIALIZATION LATCH
TC4
DB13 DB12
TC3
TC2
TC1
–12–
F5
MUXOUT
CONTROL
DB1
DB0
C2 (1) C1 (1)
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
DLY
SYNC
DB23 DB22
X
DLY
LOCK
DETECT
PRECISION
RESERVED
Table III. Reference Counter Latch Map
DB21 DB20
LDP
SYNC
TEST
MODE BITS
ANTIBACKLASH
WIDTH
DB19 DB18
DB17 DB16
DB15 DB14
DB13 DB12
DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
ABP2 ABP1
R14
R12
R10
R8
R7
R6
R5
R4
R3
R2
R1
T2
T1
CONTROL
BITS
14-BIT REFERENCE COUNTER
R13
R11
R9
DB1
DB0
C2 (0) C1 (0)
X = DON'T
CARE
ABP2 ABP1
R14
R13
R12
••••••••••
R3
R2
R1
DIVIDE RATIO
0
0
0
••••••••••
0
0
1
1
0
0
0
••••••••••
0
1
0
2
0
0
0
••••••••••
0
1
1
3
0
0
0
••••••••••
1
0
0
4
•
•
•
••••••••••
•
•
•
•
•
•
•
••••••••••
•
•
•
•
•
•
•
••••••••••
•
•
•
•
1
1
1
••••••••••
1
0
0
16380
1
1
1
••••••••••
1
0
1
16381
1
1
1
••••••••••
1
1
0
16382
1
1
1
••••••••••
1
1
1
16383
ANTIBACKLASH PULSEWIDTH
0
0
3.0ns
0
1
1.5ns
1
0
6.0ns
1
1
3.0ns
TEST MODE BITS SHOULD
BE SET TO 00 FOR NORMAL
OPERATION
LDP
DLY
SYNC
OPERATION
0
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
OPERATION
0
0
NORMAL OPERATION
0
1
OUTPUT OF PRESCALER IS RESYNCHRONIZED
WITH NONDELAYED VERSION OF RF INPUT
1
0
NORMAL OPERATION
1
1
OUTPUT OF PRESCALER IS RESYNCHRONIZED
WITH DELAYED VERSION OF RF INPUT
REV. 0
–13–
ADF4110/ADF4111/ADF4112/ADF4113
RESERVED
DB23 DB22
X
X
CP GAIN
Table IV. AB Counter Latch Map
13-BIT B COUNTER
DB21 DB20
G1
DB19 DB18
B13
B12
B11
DB17 DB16
B10
DB15 DB14
B8
B9
DB13 DB12
B7
CONTROL
BITS
6-BIT A COUNTER
B6
B5
DB11 DB10
B4
B3
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
B2
B1
A6
A5
A4
A3
A2
A1
DB1
DB0
C2 (0) C1 (1)
X = DON'T CARE
A6
A5
••••••••••
A2
A1
A COUNTER
DIVIDE RATIO
0
0
••••••••••
0
0
0
0
0
••••••••••
0
1
1
0
0
••••••••••
1
0
2
0
0
••••••••••
1
1
3
•
•
••••••••••
•
•
•
•
•
••••••••••
•
•
•
•
•
••••••••••
•
•
•
1
1
••••••••••
0
0
60
1
1
••••••••••
0
1
61
1
1
••••••••••
1
0
62
1
1
••••••••••
1
1
63
B13
0
B12
0
B11
0
••••••••••
••••••••••
B3
0
B2
0
B1
0
0
0
0
••••••••••
0
0
1
NOT ALLOWED
0
0
0
••••••••••
0
1
0
NOT ALLOWED
0
0
0
••••••••••
0
1
1
3
0
0
0
••••••••••
1
0
0
4
•
•
•
••••••••••
•
•
•
•
•
•
•
••••••••••
•
•
•
•
•
•
•
••••••••••
•
•
•
•
1
1
1
••••••••••
1
0
0
8188
1
1
1
••••••••••
1
0
1
8189
1
1
1
••••••••••
1
1
0
8190
1
1
1
••••••••••
1
1
1
8191
F4 (FUNCTION LATCH)
FASTLOCK ENABLE*
CP GAIN
OPERATION
0
0
CHARGE PUMP CURRENT
SETTTING 1 IS PERMANENTLY USED
0
1
CHARGE PUMP CURRENT SETTING
2 IS PERMANENTLY USED
1
0
CHARGE PUMP CURRENT SETTING
1 IS USED
1
1
CHARGE PUMP CURRENT IS SWITCHED
TO SETTING 2. THE TIME SPENT IN
SETTING 2 IS DEPENDENT UPON WHICH
FASTLOCK MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION
*SEE TABLE 5
B COUNTER DIVIDE RATIO
NOT ALLOWED
N = BP + A, P IS PRESCALER VALUE SET IN THE
FUNCTION LATCH B MUST BE GREATER THAN OR
EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES
OF (NX FREF), AT THE OUTPUT, NMIN IS (P2-P).
THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BITS
–14–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
PRESCALER
VALUE
POWERDOWN 2
FASTLOCK
MODE
FASTLOCK
ENABLE
CP
THREESTATE
PD
POLARITY
POWERDOWN 1
COUNTER
RESET
Table V. Function Latch Map
CONTROL
BITS
DB23 DB22
DB21 DB20
DB19 DB18
DB17 DB16
DB15 DB14
DB13 DB12
DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
PD2
CPI5
CPI3
CPI1
TC3
TC1
F4
F3
F2
M3
M2
M1
PD1
F1
P2
P1
CURRENT
SETTTING
2
CPI6
CURRENT
SETTTING
1
CPI4
CPI2
TIMER COUNTER
CONTROL
TC4
TC2
F5
MUXOUT
CONTROL
F1
F2
F3
REV. 0
FASTLOCK MODE 1
1
1
FASTLOCK MODE2
3
1
7
0
0
1
0
11
0
0
1
1
15
0
1
0
0
19
0
1
0
1
23
0
1
1
0
27
0
1
1
1
31
1
0
0
0
35
M3
M2
M1
1
0
0
1
39
0
0
0
THREE-STATE OUTPUT
1
0
1
0
43
0
0
1
1
0
1
1
47
DIGITAL LOCK DETECT
(ACTIVE HIGH)
1
1
0
0
51
0
1
0
N DIVIDER OUTPUT
1
1
0
1
55
0
1
1
DVDD
1
1
1
0
59
1
0
0
R DIVIDER OUTPUT
1
1
1
1
63
1
0
1
ANALOG LOCK DETECT
(N-CHANNEL OPEN-DRAIN)
SEE PAGE 17
ICP (mA)
OUTPUT
CPI5
CPI4
CPI3
CPI2
CPI1
2.7k⍀
4.7k⍀
10k⍀
1
1
0
SERIAL DATA OUTPUT
0
0
0
1.09
0.63
0.29
1
1
1
DGND
0
0
1
2.18
1.25
0.59
0
1
0
3.26
1.88
0.88
0
1
1
4.35
2.50
1.76
1
0
0
5.44
3.13
1.47
1
0
1
6.53
3.75
1.76
1
1
0
7.62
4.38
2.06
1
1
1
8.70
5.00
2.35
MODE
ASYNCHRONOUS POWER-DOWN
1
1
SYNCHRONOUS POWER-DOWN
64/65
0
0
1
32/33
FASTLOCK DISABLED
1
0
NORMAL OPERATION
1
FASTLOCK MODE
X
0
1
1
F5
0
0
0
16/17
F4
0
0
0
THREE-STATE
0
X
1
NORMAL
1
0
1
1
CHARGE PUMP OUTPUT
0
TIMEOUT
(PFD CYCLES)
1
0
R, A, B COUNTERS
HELD IN RESET
TC1
ASYNCHRONOUS POWER-DOWN
8/9
POSITIVE
NORMAL
1
TC2
X
0
1
0
TC3
X
P1
NEGATIVE
COUNTER
OPERATION
TC4
0
0
0
C2 (1) C1 (0)
CPI6
CE PIN PD2 PD1
P2
PD POLARITY
DB0
PRESCALER VALUE
–15–
ADF4110/ADF4111/ADF4112/ADF4113
PRESCALER
VALUE
POWERDOWN 2
FASTLOCK
MODE
FASTLOCK
ENABLE
CP
THREESTATE
PD
POLARITY
POWERDOWN 1
COUNTER
RESET
Table VI. Initialization Latch Map
CONTROL
BITS
DB23 DB22
DB21 DB20
DB19 DB18
DB17 DB16
DB15 DB14
DB13 DB12
DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
PD2
CPI5
CPI3
CPI1
TC3
TC1
F4
F3
F2
M3
M2
M1
PD1
F1
P2
P1
CURRENT
SETTTING
2
CPI6
CURRENT
SETTTING
1
CPI4
CPI2
TIMER COUNTER
CONTROL
TC4
TC2
F5
MUXOUT
CONTROL
F1
F2
CHARGE PUMP
0
OUTPUT NORMAL
1
THREE-STATE
F4
F5
0
X
FASTLOCK DISABLED
1
0
FASTLOCK MODE 1
1
1
FASTLOCK MODE2
TIMEOUT
(PFD CYCLES)
0
0
0
0
3
0
0
0
1
7
0
0
1
0
11
0
0
1
1
15
0
1
0
0
19
0
1
0
1
23
0
1
1
0
27
0
1
1
1
31
1
0
0
0
35
1
0
0
1
39
1
0
1
0
43
1
0
1
1
47
1
1
0
0
51
1
1
0
1
55
1
1
1
1
0
1
DIGITAL LOCK DETECT
(ACTIVE HIGH)
0
1
0
N DIVIDER OUTPUT
0
1
1
DVDD
1
0
0
R DIVIDER OUTPUT
1
0
1
ANALOG LOCK DETECT
(N-CHANNEL OPEN-DRAIN)
2.7k⍀
4.7k⍀
10k⍀
1
1
0
SERIAL DATA OUTPUT
1.09
0.63
0.29
1
1
1
DGND
0
0
1
2.18
1.25
0.59
0
1
0
3.27
1.88
0.88
0
1
1
4.35
2.50
1.76
1
0
0
5.44
3.13
1.47
1
0
1
6.53
3.75
1.76
1
1
0
7.62
4.38
2.06
1
1
1
8.70
5.00
2.35
PD2 PD1
MODE
ASYNCHRONOUS POWERDOWN
NORMAL OPERATION
ASYNCHRONOUS POWERDOWN
SYNCHRONOUS POWER-DOWN
64/65
1
0
1
32/33
0
CPI1
1
1
0
OUTPUT
0
1
1
THREE-STATE OUTPUT
CPI2
1
16/17
63
M1
0
0
0
0
59
M2
0
CPI3
0
1
R, A, B
COUNTERS
HELD IN RESET
0
M3
ICP (mA)
X
1
NORMAL
1
CPI4
1
0
0
CPI5
1
8/9
COUNTER
OPERATION
CPI6
X
0
C2 (1) C1 (1)
FASTLOCK MODE
TC1
X
P1
POSITIVE
TC2
0
0
1
F3
SEE PAGE 17
P2
NEGATIVE
TC3
1
CE PIN
0
TC4
1
PD POLARITY
DB0
PRESCALER VALUE
–16–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
THE FUNCTION LATCH
Fastlock Mode 2
With C2, C1 set to 1, 0, the on-chip function latch will be programmed. Table V shows the input data format for programming
the Function Latch.
The charge pump current is switched to the contents of Current
Setting 2.
DB2 (F1) is the counter reset bit. When this is “1,” the R counter
and the A, B counters are reset. For normal operation this bit
should be “0.” Upon powering up, the F1 bit needs to be disabled,
the N counter resumes counting in “close” alignment with the R counter.
(The maximum error is one prescaler cycle.)
The device enters Fastlock by having a “1” written to the CP
Gain bit in the AB counter latch. The device exits Fastlock under
the control of the Timer Counter. After the timeout period determined by the value in TC4–TC1, the CP Gain bit in the AB
counter latch is automatically reset to “0” and the device reverts
to normal mode instead of Fastlock. See Table V for the timeout periods.
Power-Down
Timer Counter Control
DB3 (PD1) and DB21 (PD2) on the ADF4110 family, provide
programmable power-down modes. They are enabled by the
CE pin.
The user has the option of programming two charge pump currents. The intent is that the Current Setting 1 is used when the
RF output is stable and the system is in a static state. Current
Setting 2 is meant to be used when the system is dynamic
and in a state of change (i.e., when a new output frequency is
programmed).
Counter Reset
When the CE pin is low, the device is immediately disabled
regardless of the states of PD2, PD1.
In the programmed asynchronous power-down, the device powers down immediately after latching a “1” into bit PD1, with the
condition that PD2 has been loaded with a “0.”
In the programmed synchronous power-down, the device powerdown is gated by the charge pump to prevent unwanted frequency
jumps. Once the power-down is enabled by writing a “1” into
bit PD1 (on condition that a “1” has also been loaded to PD2),
the device will go into power-down on the occurrence of the next
charge pump event.
The normal sequence of events is as follows:
The user initially decides what the preferred charge pump currents are going to be. For example, they may choose 2.5 mA as
Current Setting 1 and 5 mA as the Current Setting 2.
At the same time, they must also decide how long they want the
secondary current to stay active before reverting to the primary
current. This is controlled by the Timer Counter Control Bits
DB14 to DB11 (TC4–TC1) in the Function Latch. The truth
table is given in Table V.
When a power-down is activated (either synchronous or asynchronous mode including CE-pin-activated power-down), the
following events occur:
When the user wishes to program a new output frequency, he
can simply program the AB counter latch with new values for A
and B. At the same time, he can set the CP Gain bit to a “1,”
which sets the charge pump with the value in CPI6–CPI4 for a
period of time determined by TC4–TC1. When this time is up,
the charge pump current reverts to the value set by CPI3– CPI1.
At the same time the CP Gain bit in the A, B Counter latch is
reset to 0 and is now ready for the next time the user wishes
to change the frequency again.
All active dc current paths are removed.
The R, N, and timeout counters are forced to their load state
conditions.
The charge pump is forced into three-state mode.
The digital clock detect circuitry is reset.
The RFIN input is debiased.
Note that there is an enable feature on the Timer Counter. It is
enabled when Fastlock Mode 2 is chosen by setting the Fastlock
Mode bit (DB10) in the Function Latch to “1.”
The reference input buffer circuitry is disabled.
The input register remains active and capable of loading and
latching data.
Charge Pump Currents
The on-chip multiplexer is controlled by M3, M2, M1 on the
ADF4110 family. Table V shows the truth table.
CPI3, CPI2, CPI1 program Current Setting 1 for the charge
pump. CPI6, CPI5, CPI4 program Current Setting 2 for the
charge pump. The truth table is given in Table V.
Fastlock Enable Bit
Prescaler Value
DB9 of the Function Latch is the Fastlock Enable Bit. Only
when this is “1” is Fastlock enabled.
P2 and P1 in the Function Latch set the prescaler values. The
prescaler value should be chosen so that the prescaler output
frequency is always less than or equal to 200 MHz. Thus, with
an RF frequency of 2 GHz, a prescaler value of 16/17 is valid
but a value of 8/9 is not.
MUXOUT Control
Fastlock Mode Bit
DB10 of the Function Latch is the Fastlock Enable bit. When
Fastlock is enabled, this bit determines which Fastlock Mode is
used. If the Fastlock Mode bit is “0” then Fastlock Mode 1
is selected and if the Fastlock Mode bit is “1,” then Fastlock
Mode 2 is selected.
PD Polarity
This bit sets the PD Polarity Bit. See Table V.
CP Three-State
This bit the CP output pin. With the bit set high, the CP output
is put into three-state. With the bit set low, the CP output is
enabled.
Fastlock Mode 1
The charge pump current is switched to the contents of Current
Setting 2.
The device enters Fastlock by having a “1” written to the CP
Gain bit in the AB counter latch. The device exits Fastlock by
having a “0” written to the CP Gain bit in the AB counter latch.
REV. 0
–17–
ADF4110/ADF4111/ADF4112/ADF4113
THE INITIALIZATION LATCH
When C2, C1 = 1, 1, the Initialization Latch is programmed.
This is essentially the same as the Function Latch (programmed
when C2, C1 = 1, 0).
However, when the Initialization Latch is programmed an additional internal reset pulse is applied to the R and AB counters.
This pulse ensures that the AB counter is at load point when the
AB counter data is latched and the device will begin counting in
close phase alignment.
If the Latch is programmed for synchronous power-down (CE
pin is High; PD1 bit is High; PD2 bit is Low), the internal pulse
also triggers this power-down. The prescaler reference and the
oscillator input buffer are unaffected by the internal reset pulse and
so close phase alignment is maintained when counting resumes.
When the first AB counter data is latched after initialization, the
internal reset pulse is again activated. However, successive AB
counter loads after this will not trigger the internal reset pulse.
DEVICE PROGRAMMING AFTER INITIAL POWER-UP
After initially powering up the device, there are three ways to
program the device.
CE can be used to power the device up and down in order to
check for channel activity. The input register does not need to
be reprogrammed each time the device is disabled and enabled
as long as it has been programmed at least once after VDD was
initially applied.
The Counter Reset Method
Apply VDD.
Do a Function Latch Load (“10” in 2 LSBs). As part of this, load
“1” to the F1 bit. This enables the counter reset.
Do an R Counter Load (“00” in 2 LSBs) Do an AB Counter Load
(“01” in 2 LSBs). Do a Function Latch Load (“10” in 2 LSBs).
As part of this, load “0” to the F1 bit. This disables the counter
reset.
This sequence provides the same close alignment as the initialization method. It offers direct control over the internal reset.
Note that counter reset holds the counters at load point and threestates the charge pump, but does not trigger synchronous powerdown. The counter reset method requires an extra function latch
load compared to the initialization latch method.
RESYNCHRONIZING THE PRESCALER OUTPUT
Table III (the Reference Counter Latch Map) shows two bits,
DB22 and DB21 that are labelled DLY and SYNC respectively.
These bits affect the operation of the prescaler.
Initialization Latch Method
Apply VDD. Program the Initialization Latch (“11” in 2 LSBs
of input word). Make sure that F1 bit is programmed to “0.”
Then do an R load (“00” in 2 LSBs). Then do an AB load (“01”
in 2 LSBs).
With SYNC = “1,” the prescaler output is resynchronized with
the RF input. This has the effect of reducing jitter due to the
prescaler and can lead to an overall improvement in synthesizer
phase noise performance. Typically, a 1 dB to 2 dB improvement is seen in the ADF4113. The lower bandwidth devices can
show an even greater improvement. For example, the ADF4110
phase noise is typically improved by 3 dB when SYNC is enabled.
When the Initialization Latch is loaded, the following occurs:
1. The function latch contents are loaded.
2. An internal pulse resets the R, A, B, and timeout counters
to load state conditions and also three-states the charge pump.
Note that the prescaler bandgap reference and the oscillator
input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes.
With DLY = “1,” the prescaler output is resynchronized with a
delayed version of the RF input.
3. Latching the first AB counter data after the initialization word
will activate the same internal reset pulse. Successive AB loads
will not trigger the internal reset pulse unless there is another
initialization.
The CE Pin Method
Apply VDD.
Bring CE low to put the device into power-down. This is an
asynchronous power-down in that it happens immediately.
Program the Function Latch (10). Program the R Counter Latch
(00). Program the AB Counter Latch (01).
Bring CE high to take the device out of power-down. The R
and AB counters will now resume counting in close alignment.
Note that after CE goes high, a duration of 1 µs may be required
for the prescaler bandgap voltage and oscillator input buffer bias
to reach steady state.
If the SYNC feature is used on the synthesizer, some care must
be taken. At some point, (at certain temperatures and output
frequencies), the delay through the prescaler will coincide with
the active edge on RF input and this will cause the SYNC feature to break down. So, it is important when using the SYNC
feature to be aware of this. Adding a delay to the RF signal, by
programming DLY = “1,” will extend the operating frequency
and temperature somewhat. Using the SYNC feature will also
increase the value of the AIDD for the device. With a 900 MHz
output, the ADF4113 AIDD increases by about 1.3 mA when
SYNC is enabled and a further 0.3 mA if DLY is enabled.
All the typical performance plots on the data sheet except for
Figure 5 apply for DLY and SYNC = “0,” i.e., no resynchronization or delay enabled.
–18–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
KD = 5 mA
KV = 12 MHz/V
Loop Bandwidth = 20 kHz
FREF = 200 kHz
N = 4500
Extra Reference Spur Attenuation = 10 dB
APPLICATIONS SECTION
Local Oscillator for GSM Base Station Transmitter
The following diagram shows the ADF4111/ADF4112/ADF4113
being used with a VCO to produce the LO for a GSM base station
transmitter.
The reference input signal is applied to the circuit at FREFIN
and, in this case, is terminated in 50 Ω. Typical GSM system
would have a 13 MHz TCXO driving the Reference Input
without any 50 Ω termination. In order to have a channel
spacing of 200 kHz (the GSM standard), the reference input
must be divided by 65, using the on-chip reference divider of
the ADF4111/ADF4112/ADF4113.
All of these specifications are needed and used to come up with
the loop filter components values shown in Figure 29.
The loop filter output drives the VCO, which, in turn, is fed
back to the RF input of the PLL synthesizer and also drives
the RF Output terminal. A T-circuit configuration provides
50 Ω matching between the VCO output, the RF output and
the RFIN terminal of the synthesizer.
The charge pump output of the ADF4111/ADF4112/ADF4113
(Pin 2) drives the loop filter. In calculating the loop filter component values, a number of items need to be considered. In this
example, the loop filter was designed so that the overall phase
margin for the system would be 45 degrees. Other PLL system
specifications are:
VDD
In a PLL system, it is important to know when the system is in
lock. In Figure 29, this is accomplished by using the MUXOUT
signal from the synthesizer. The MUXOUT pin can be programmed to monitor various internal signals in the synthesizer.
One of these is the LD or lock-detect signal.
VP
RFOUT
100pF
1000pF 1000pF
FREFIN
51⍀
8
7
15
16
AVDD DVDD VP
CP
REFIN
3.3k⍀
2
5.6k⍀
1nF
C
620pF
VCC
VCO190-902T
P
8.2nF
3
DGND
AGND
4
9
100pF
DECOUPLING CAPACITORS ON AVDD, DVDD, VP OF THE ADF411X
AND ON THE POSITIVE SUPPLY OF THE VCO190-902T HAVE
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 29. Local Oscillator for GSM Base Station
REV. 0
100pF 18⍀
CE
14
LOCK
CLK
DETECT
DATA MUXOUT
LE
100pF
6
RFINA
1
RSET
5
RFINB
51⍀
CPGND
SPI COMPATIBLE SERIAL BUS
ADF4111
ADF4112
ADF4113
4.7k⍀
18⍀
B
–19–
18⍀
ADF4110/ADF4111/ADF4112/ADF4113
RFOUT
100pF
8
FREFIN
CP
2
LOOP
FILTER
REFIN
18⍀
18⍀
OUTPUT
VCO
RSET
ADF4111
ADF4112
ADF4113
CE
CLK
DATA
LE
100pF
INPUT
18⍀
GND
14
MUXOUT
LOCK
DETECT
1
RSET
2.7k⍀
RFINA 6
RFINB
100pF
5
51⍀
100pF
AD5320
12-BIT
V-OUT DAC
POWER SUPPLY CONNECTIONS AND DECOUPLING
CAPACITORS ARE OMITTED FOR CLARITY.
SPI COMPATIBLE SERIAL BUS
Figure 30. Driving the RSET Pin with a D/A Converter
USING A D/A CONVERTER TO DRIVE R SET PIN
You can use a D/A converter to drive the RSET pin of the
ADF4110 family and thus increase the level of control over the
charge pump current ICP. This can be advantageous in wideband
applications where the sensitivity of the VCO varies over the
tuning range. To compensate for this, the ICP may be varied to
maintain good phase margin and ensure loop stability. See
Figure 30.
SHUTDOWN CIRCUIT
The attached circuit in Figure 31 shows how to shut down both
the ADF4110 family and the accompanying VCO. The ADG701
switch goes closed circuit when a Logic 1 is applied to the IN
input. The low-cost switch is available in both SOT-23 and
micro SO packages.
WIDEBAND PLL
Many of the wireless applications for synthesizers and VCOs in
PLLs are narrowband in nature. These applications include
the various wireless standards like GSM, DSC1800, CDMA or
WCDMA. In each of these cases, the total tuning range for the
local oscillator is less than 100 MHz. However, there are also
wide band applications where the local oscillator could have up
to an octave tuning range. For example, cable TV tuners have a
total range of about 400 MHz. Figure 32 shows an application where the ADF4113 is used to control and program the
Micronetics M3500-2235. The loop filter was designed for an
RF output of 2900 MHz, a loop bandwidth of 40 kHz, a PFD
frequency of 1 MHz, ICP of 10 mA (2.5 mA synthesizer ICP
multiplied by the gain factor of 4), VCO KD of 90 MHz/V (sensitivity of the M3500-2235 at an output of 2900 MHz) and a
phase margin of 45°C.
In narrow-band applications, there is generally a small variation
in output frequency (generally less than 10%) and also a small
variation in VCO sensitivity over the range (typically 10% to 15%).
However, in wide band applications both of these parameters
have a much greater variation. In Figure 32, for example, we have
–25% and +17% variation in the RF output from the nominal
2.9 GHz. The sensitivity of the VCO can vary from 120 MHz/V
at 2750 MHz to 75 MHz/V at 3400 MHz (+33%, –17%).
Variations in these parameters will change the loop bandwidth.
This in turn can affect stability and lock time. By changing the
programmable ICP, it is possible to get compensation for these
varying loop conditions and ensure that the loop is always operating close to optimal conditions.
–20–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
VP
POWER-DOWN CONTROL
VDD
D
7
15 16
AVDD DVDD VP CE
8
FREFIN
VDD
S
RFOUT
IN ADG701
CP
REFIN
RSET
GND
VCC
2
LOOP
FILTER
100pF
100pF 18⍀
VCO
1
18⍀
18⍀
GND
4.7k⍀
ADF4110
ADF4111
ADF4112
ADF4113
RFINA
AGND
3
100pF
5
51⍀
DGND
CPGND
RFINB
6
4
100pF
9
DECOUPLING CAPACITORS AND INTERFACE SIGNALS HAVE
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 31. Local Oscillator Shutdown Circuit
RFOUT
20V
VDD
VP
12V
3k⍀
1k⍀
1000pF 1000pF
FREFIN
51⍀
8
15
16
7
AVDD DVDD VP
2
CP
RSET
RFINA
3
4
DGND
RFINB
AGND
CPGND
SPI-COMPATIBLE SERIAL BUS
ADF4113
MUXOUT
9
14
6
2.8nF
19nF
4.7k⍀
680⍀
130pF
100pF 18⍀
GND
100pF
5
51⍀
100pF
DECOUPLING CAPACITORS ON AVDD, DVDD, VP OF THE ADF4113
AND ON VCC OF THE M3500-2250 HAVE BEEN OMITTED FROM
THE DIAGRAM TO AID CLARITY.
–21–
18⍀
OUT
LOCK
DETECT
Figure 32. Wideband Phase Locked Loop
REV. 0
V_TUNE
M3500-2235
REFIN
CE
CLK
DATA
LE
VCC
AD820
3.3k⍀
100pF
18⍀
ADF4110/ADF4111/ADF4112/ADF4113
The target application is a WCDMA base station transmitter.
Typical phase noise performance from this LO is –85 dBc/Hz at
a 1 kHz offset.
DIRECT CONVERSION MODULATOR
In some applications a direct conversion architecture can be used
in base station transmitters. Figure 33 shows the combination
available from ADI to implement this solution.
The LO port of the AD8346 is driven in single-ended fashion.
LOIN is ac-coupled to ground with the 100 pF capacitor and
LOIP is driven through the ac coupling capacitor from a 50 Ω
source. An LO drive level of between –6 dBm and –12 dBm is
required. The circuit of Figure 33 gives a typical level of –8 dBm.
The circuit diagram shows the AD9761 being used with the
AD8346. The use of dual integrated DACs such as the AD9761
with specified ± 0.02 dB and ± 0.004 dB gain and offset matching characteristics ensures minimum error contribution (over
temperature) from this portion of the signal chain.
The Local Oscillator (LO) is implemented using the ADF4113.
In this case, the OSC 3B1-13M0 provides the stable 13 MHz
reference frequency. The system is designed for a 200 kHz
channel spacing and an output center frequency of 1960 MHz.
REFIO
IOUTA
LOW-PASS
FILTER
IOUTB
MODULATED
DIGITAL
DATA
The RF output is designed to drive a 50 Ω load but must be
ac-coupled as shown in Figure 33. If the I and Q inputs are
driven in quadrature by 2 V p-p signals, the resulting output
power will be around –10 dBm.
IBBP
100pF
VOUT
IBBN
AD9761
TxDAC
AD8346
QOUTA
FS ADJ
LOW-PASS
FILTER
QOUTB
QBBP
QBBN
2k⍀
LOIN
4.7k⍀
LOIP
100pF
OSC 3B1-13M0
REFIN
SERIAL
DIGITAL
NTERFACE
100pF 18⍀
3.3k⍀
CP
910pF
ADF4113
VCO190-1960T
3.9k⍀
620pF
9.1nF
RFINB
100pF
100pF
18⍀
RSET
TCXO
RFOUT
18⍀
RFINA
100pF
51⍀
POWER SUPPLY CONNECTIONS AND DECOUPLING
CAPACITORS ARE OMITTED FROM DIAGRAM FOR CLARITY.
Figure 33. Direct Conversion Transmitter Solution
–22–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
INTERFACING
ADSP-2181 Interface
The ADF4110 family has a simple SPI-compatible serial interface for writing to the device. SCLK, SDATA and LE control
the data transfer. When LE (Latch Enable) goes high, the 24 bits
which have been clocked into the input register on each rising
edge of SCLK will get transferred to the appropriate latch. See
Figure 1 for the Timing Diagram and Table I for the Latch
Truth Table.
Figure 35 shows the interface between the ADF4110 family and
the ADSP-21xx Digital Signal Processor. The ADF4110 family
needs a 24-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP-21xx family is to use the
Autobuffered Transmit Mode of operation with Alternate
Framing. This provides a means for transmitting an entire
block of serial data before an interrupt is generated.
The maximum allowable serial clock rate is 20 MHz. This means
that the maximum update rate possible for the device is 833 kHz or
one update every 1.2 microseconds. This is certainly more than
adequate for systems that will have typical lock times in hundreds
of microseconds.
SCLK
ADSP-21xx
DT
TFS
ADuC812 Interface
Figure 34 shows the interface between the ADF4110 family and
the ADuC812 microconverter. Since the ADuC812 is based on
an 8051 core, this interface can be used with any 8051-based
microcontroller. The microconverter is set up for SPI Master
Mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4110 family
needs a 24-bit word. This is accomplished by writing three 8-bit
bytes from the microconverter to the device. When the third
byte has been written the LE input should be brought high to
complete the transfer.
I/O FLAGS
SCLK
SDATA
LE
I/O PORTS
CE
ADF4110
ADF4111
ADF4112
ADF4113
MUXOUT
(LOCK DETECT)
Figure 34. ADuC812 to ADF4110 Family Interface
REV. 0
CE
ADF4110
ADF4111
ADF4112
ADF4113
Set up the word length for 8 bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store
the three 8-bit bytes, enable the Autobuffered mode and then
write to the transmit register of the DSP. This last operation
initiates the autobuffer transfer.
When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maximum
rate at which the output frequency can be changed will be
166 kHz.
MOSI
LE
Figure 35. ADSP-21xx to ADF4110 Family Interface
I/O port lines on the ADuC812 are also used to control powerdown (CE input) and to detect lock (MUXOUT configured as
lock detect and polled by the port input).
ADuC812
SDATA
MUXOUT
(LOCK DETECT)
On first applying power to the ADF4110 family, it needs three
writes (one each to the R counter latch, the N counter latch and
the initialization latch) for the output to become active.
SCLOCK
SCLK
–23–
ADF4110/ADF4111/ADF4112/ADF4113
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.159 (4.05)
0.157 (4.00)
0.156 (3.95)
0.159 (4.05)
0.157 (4.00)
0.156 (3.95)
C3766–5–4/00 (rev. 0)
Chip Scale
(CP-20)
0.079 (2.0) REF
0.014 (0.35) ⴛ 45°
0.018 (0.45)
0.016 (0.40)
0.014 (0.35)
16
15
0.039 (1.00)
0.035 (0.90)
0.031 (0.80)
SEATING 0.0079 (0.20)
PLANE
REF
1
0.079
(2.0)
REF
DETAIL E
0.020 (0.5) REF
LEAD PITCH
TOP VIEW
20
11
10
5
6
BOTTOM VIEW
(ROTATED 180ⴗ)
0.0083 (0.211)
0.0079 (0.200)
0.0077 (0.195)
LEAD OPTION
DETAIL E
0.011 (0.275)
0.010 (0.250)
0.009 (0.225)
0.018 (0.45)
0.016 (0.40)
0.014 (0.35)
0.0059
(0.15)
REF
0.0059 (0.15)
REF
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
Thin Shrink Small Outline
(RU-16)
0.201 (5.10)
0.193 (4.90)
16
9
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
8
PIN 1
SEATING
PLANE
0.0256 (0.65)
BSC
0.0433 (1.10)
MAX
0.0118 (0.30)
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
–24–
8ⴗ
0ⴗ
0.028 (0.70)
0.020 (0.50)
PRINTED IN U.S.A.
0.006 (0.15)
0.002 (0.05)
REV. 0