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AS-Interface Slave IC
AS2702 (SAP4.1)
.H\)HDWXUHV
•
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•
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Interface Device to connect Actuators and Sensors to an AS-Interface Bus
Conforms to AS-Interface Spec. V2.11
DC Power Extraction from the AS-Interface Bus
Serial bidir. Data Communication with the Bus
Data Communication Watchdog
4-Bit bidir. Data Port plus Strobe to poll the Sensors and control the Actuators connected
4-Bit Parameter Port plus Strobe to provide Settings to the Sensors and Actuators
24V Power Supply for the Sensors and Actuators
Periphery Fault Input to signal Hardware Failure of the Sensors and Actuators
Integrated 16 x 8 Bit EEPROM to store (5 + 1)-Bit Slave Address and Settings
2 LED Outputs to optically flag Slave Unit Operation Status
Operating Temperature Ta:
- 25 °C … + 85 °C
Operating Supply Voltage / Bus DC Voltage:
typ. 30 V
Operating Current (Osc. on, Outputs idle):
≤ 6 mA
Supply for Sensors / Actuators:
typ. 24 V, ≤ 50 mA
Package:
SOIC 20 for full Functionality;
SOIC 16 for Applications not requiring the Parameter Port
*HQHUDO'HVFULSWLRQ
AS2702 (SAP4.1) is a new generation AS-interface slave device conforming to AS-interfacespecification V2.11, which supports AS-interface bus systems with up to 62 slave modules.
Each slave module is equipped with an AS2702 device, which interfaces the module to the
unshielded 2-wire AS-interface bus for serial bidirectional data communication and power extraction.
Data communication over the AS-interface bus takes place in master slave fashion, which
foresees that all slave devices AS2702 connected to the bus are sequentially and cyclicly addressed by a single, central master unit. Data on the AS-interface bus are Manchester encoded and can be found as sin2-pulses with a Vpp of between 3V and 8V on top of the bus’
dc voltage of nominally 30V.
AS2702 regulates the nominal dc bus voltage of 30V internally down to 5V to supply it’s internal circuitry including a 16 x 8 bits EEPROM, as well as down to a nominal supply level 24V
with a max. loading of 50 mA for the actuators and sensors connected to it at the field side.
Each slave device AS2702 may interface to up to 4 sensors or 3 actuators. An AS-interface
bus system based on AS2702 may hence link as many as 248 sensors or 186 actuators to a
single master unit.
Slave device AS2702 (SAP4.1) is system compatible with predecessor device AS2701A
(ISA3+): slave modules equipped with AS2702 (SAP4.1) will run in existing AS-interface bus
systems based on AS2701A (ISA3+).
The AS-interface concept is well established as a standardized digital bus system for industrial automation.
Rev. C, January 2001
Page 2 of 18
AS-Interface Slave IC
AS2702 (SAP4.1)
%ORFN'LDJUDP
CDC
LTGP
+
-
VLTGP-6V
UOUT
THERMODETECTOR
U5R
U5R
U5R
U5R
OSC1
OSCILLATOR
RECEIVE
TRANSMIT
JABBER
INHIBIT
OSC2
RESET
threshold
U5R
11
IMP_POS
IMP_NEG
LOGIC BLOCK
LTGN
+
-
U5R
PSTBn
P0...P3
4
DSTBn
4
D0...D3
LED1
PFAULT
16 x 8 BIT
SERIAL E2PROM
LED2
BANDGAP
SCL
SDA
PORN
TRIMMING
3 L Q $V V L J Q P H Q W D Q G ' H V F U L S W L R Q
62,& 62,&
Pin Nr.: Pin Nr.:
1
--
1DPH
7\SH
1RWH
'HVFULSWLRQ
P1
I/O, digital,
pull-up
I/O, digital,
pull-up
I/O, digital
I/O, digital
I/O, digital,
pull-up
I/O, digital,
pull-up
O, analog
I, analog
O, power
I, power
1, 2
Bidir. parameter port bit 1
1, 2
Bidir. parameter port bit 0
2
--
P0
3
4
5
1
2
3
D1
D0
DSTBn
6
4
LED1
7
8
9
10
5
6
7
8
OSC2
OSC1
U5R
LTGN
Rev. C, January 2001
1
Bidir. data port bit 1
Bidir. data port bit 0
Data port strobe output; reset-input
1
LED output 1 (IC test input)
Output to quarz crystal
Input from quartz crystal
Nom. 5V power supply output
Neg. supply pin, connected
Page 3 of 18
AS-Interface Slave IC
AS2702 (SAP4.1)
11
9
LTGP
12
13
14
10
11
12
15
13
LED2
16
14
PSTBn
17
18
19
15
16
--
D3
D2
P3
20
--
P2
I, power
CDC
I/O, analog
UOUT
O, power
PFAULT I, digital, pullup
I/O, digital,
pull-up
I/O, digital,
pull-up
I/O, digital
I/O, digital
I/O, digital,
pull-up
I/O, digital,
pull-up
1
1
1
to neg. AS-interface bus line;
ground reference.
Pos. supply pin, connected
to pos. AS-interface bus line
Pin for ext. buffer capacitor
Nom. 24V power supply output
Low-active input to flag failure
of the sensors / actuators circuitry connected
LED output 2 (IC test input)
1, 2
Parameter port strobe output
(IC test input)
Bidir. data port bit 3
Bidir. data port bit 2
Bidir. parameter port bit 3
1, 2
Bidir. parameter port bit 2
Notes:
1
The pull-up structure is a passive high-side current source with a nom. 10 µA current
2
The passive pull-up current source as per note 1 on these parameter port pins is off,
if the slave device is programmed with I/O-configuration code 7 and a master data
call is present
)XQFWLRQDOHOHFWULFDODQGWLPLQJFKDUDFWHULV
WLFV
All voltages are referenced to ground pin LTGN. Timing is valid for a quartz crystal frequency
of 5.333 MHz.
a) Absolute maximum ratings
6\PERO 3DUDPHWHU
VLTGP Voltage at the positive supply pin
VCDC Volage at pin for ext. buffer capacitor
0LQ
- 0.3
- 0.3
VU5R
IIN
- 0.3
- 50
Voltage at pins U5R, OSC1, OSC2
Input current at any pin, except for LTGP,
CDC
ESD1
Electrostatic discharge voltage
ESD2
Electrostatic discharge voltage
ΘSTG Storage temperature
ΘLEAD Solder temperature
PTOT
Max. power dissipation
RTHJA Thermal resistance SOIC 16
RTHJA Thermal resistance SOIC 20
Rev. C, January 2001
1500
200
- 55
61.2
58.5
0D[
40
VLTGP +
0.3V
7
50
125
260
1
74.8
71.5
8QLW
V
V
1RWH
1
V
mA
2
V
V
V
°C
W
°K / W
°K / W
3
4
5
6
7
7
Page 4 of 18
AS-Interface Slave IC
AS2702 (SAP4.1)
Notes:
1
2
3
4
5
50 V during t > 50 µs; repetition rate < 0.5 Hz
Latch-up immunity test. Pls. observe max. power dissipation allowed.
Human body model: R = 1.5 kOhm; C = 100 pF
Machine model; applies only for LTGP-LTGN
260 °C during 10 s (reflow and wave soldering); 360 °C during 3 s for manual soldering. Twofold reflow soldering is acceptable.
Free convection, see fig. 1
3
No forced cooling. PCB-surface: 21 cm2; still air volume around the device: 10 cm
6
7
Pv/ W
Pv/ W
1
1
0,5
0,5
50
100
t/ °C
50
62,&
100
t/ °C
62,&
Fig. 1: Max. acceptable power dissipation relative to ambient temperature
b) Recommended Operating Conditions
6\PERO
VLTGP
ILTG
OA
FC
3DUDPHWHU
Positive supply voltage / dc
portion
Supply current consumption
Ambient temperature
Quartz frequency
Sensitivity against moisture
Notes:
1
2
3
4
5
PLQ
17.5
QRP
- 25
25
5.3333
33
PD[
34
8QLW
V
1RWH
1
6
85
mA
°C
MHz
2
3
4
5
False-poling protection diode to be inserted between pos. AS-interface bus line and
LTGP-pin. LTGP-pin to be protected furthermore with a voltage clamp between
LTGP and LTGN.
Oscillator on; data transmission stage off; no loads connected
Power dissipation restrictions as per fig. 1 to be observed
ASI Quarz
Level 5 acc. to JEDEC-standard JESD22-A112, Table 1
Rev. C, January 2001
Page 5 of 18
AS-Interface Slave IC
AS2702 (SAP4.1)
F 6XSSO\SLQ/7*3
Positive supply pin connected to positive AS-interface bus line and clamped relative to neg.
supply pin / ground LTGN as described under Recommended Operating Conditions.
VLTGP and ILTG specified under Recommended Operating Conditions as well.
6\PERO 3DUDPHWHU
VSIG
VPP of sin2-data-pulses
on top of dc supply voltage
Z
Input impedance
between 50 kHz and 300 kHz
PLQ
3
PD[
8
8QLW
V
1RWH
40
pF
CCDC = 100 nF
1
1
1
18
50
Note:
1
kOhm
mH
Input equivalent circuit is parallel arrangement of C, R and L
G %XIIHUSLQ&'&
An external buffer capacitor with a recommended value of 100 nF should be connected to this
pin to ensure a sufficiently high input impedance Z at power supply pin LTGP.
Voltage at this pin can be as high as VLTGP.
H 1RP9SRZHUVXSSO\RXWSXW8287
The supply output voltage at UOUT is directly derived from VLTGP and regulated to a level
with an offset of about - 6V relative to VLTGP.
UOUT provides bias to the sensors and actuators circuitry connected to the slave device as
well as to the LEDs connected to outputs LED1 and LED2.
UOUT is equipped with a thermal overload protection, which foresees that VUOUT is switched
off as soon as the slave device’s substrate temperature TJ passes a threshold value in the
range of (155 -+ 20)°C.
After TJ has come down and has passed a temperature threshold about (15 -+ 5)°C lower
than (155 -+ 20)°C and after a consecutive minimum delay of 1 s has elapsed, VUOUT is
switched on again.
6\PERO
VUOUT
3DUDPHWHU
Power supply output voltage
IUOUT
VCOMOFF
Load current
UOUT voltage level
below which data transmission
is inhibited
Buffer capacitor
CUOUT
Notes:
1
PLQ
VLTGP 6.3V
9.5
10
PD[
VLTGP 5.3V
50
10.5
8QLW
V
1RWH
mA
V
1
µF
2
In case IUOUT > 40 mA and presence of sin2-data pulses on LTGP
Rev. C, January 2001
Page 6 of 18
AS-Interface Slave IC
AS2702 (SAP4.1)
2
with VSIG > 3V, VUOUT may drop as much as 1V below it’s level
in unloaded condition
Electrolythic and rf filter capacitor in parallel
I 1RP9SRZHUVXSSO\RXWSXW85
The voltage at U5R is derived from the voltage present at UOUT, as long as UOUT is not
switched off due to overload. In the latter case U5R is derived from an alternative voltage out
of the UOUT voltage regulator, which is more or less similar to VUOUT in non switched off
condition of UOUT. As a result VU5R is not affected by overload condition at UOUT and will
remain.
6\PERO
VU5R
IU5R
CU5R
3DUDPHWHU
Power supply output voltage
Load current
Buffer capacitor
PLQ
4.85
PD[
5.15
1
100
8QLW
V
mA
nF
J 2VFLOODWRUSLQV26&DQG26&
The only component to be connected to these pins is a quartz crystal with a resonance frequency of 5.333333 MHz (AS-Interface quartz crystal).
6\PERO
CX2
3DUDPHWHU
Stray capacitance
PLQ
PD[
10
8QLW
pF
K 'DWDSRUWSLQV'«'DQGGDWDVWUREHSLQ'67%Q
Basically data port D3, …, D0 is designed for bidirectional data transfer out of and into the
slave device. Each data port pin is equipped with both a low-side open-drain output stage as
well as an input stage to this purpose.
Depending on the so called IO-configuration code, written into and stored in the slave device,
each data port pin is individually set to behave as
• output, or
• output / input, or
• input.
The timing of the data transfer is presented in fig. 2.
Strobe signal DSTBn flags and governs the data transfer as follows:
ha) data port pin is set ‘output’:
output data become valid upon the HL-edge of the strobe and will remain so until the next
HL-edge, hence during the entire strobe cycle;
hb) data port pin is set ‘output / input’:
output data become valid upon the HL-edge of the strobe and will remain so until it’s LHedge; input data to be valid within a specific time window relative to the HL-edge, after
completion of the strobe’s L-phase;
hc) data port pin is set ‘input’:
Rev. C, January 2001
Page 7 of 18
AS-Interface Slave IC
AS2702 (SAP4.1)
input data to be valid within a specific time window relative to the HL-edge of the strobe,
after completion of the strobe’s L-phase.
If necessary, output data as per ha) and hb) can be easily latched with the LH-edge of strobe
DSTBn as they will remain valid for about 0.4 µs beyond as a minimum.
Care must be taken however, that signal delay added by external circuitry is lower for the
strobe than for the data.
Dx
Data out
Data in
tDSTBn + 0.4 µs
Dx
tSTB
Data out
Data in
tDSTBn + tOUTOFF
DSTBn
tDSTBn
tINPmin
tINPmax
Fig. 2: Timing of data transfer at data port D3, …, D0 relative to strobe DSTBn
The following table specifies the timing parameters relating to fig. 2:
6\PERO
tSTB
tDSTBn
tOUTOFF
tINP
Notes:
1
2
3
3DUDPHWHU
Delay DSTBn HL-edge to Dx
output data valid
DSTBn strobe width
Delay DSTBn LH-edge to Dx
output off
Input data valid time window
PLQ
PD[
1.5
8QLW
µs
1RWH
6
0.2
6.8
1
µs
µs
1
2
10.5
12.5
µs
3
Pulse width depends substantially on value of external pull-up resistor
Applies only to data port pins set to 'output / input' operation
Timing reference is DSTBn HL-edge.
Applies only to data port pins set to either 'output / input' or 'input' operation
Rev. C, January 2001
Page 8 of 18
AS-Interface Slave IC
AS2702 (SAP4.1)
The dc-parameters of the data port pins D3, …, D0 are specified as follows:
6\PERO
IOUTLO
3DUDPHWHU
Sink current @ output L
PLQ
10
PD[
8QLW
mA
IOUTHI
VSCHLT
VIN
Leakage current @ output off
Input threshold voltage
Acceptable input voltage @
output off
-1
2.5
- 0.3
1
3.5
40
µA
V
V
Notes:
1
2
1RWH
VOUT =
1V
1
2
Output stage is low-side open-drain; ext. pull-up resistor required as no pull-up
structure on chip
No hysteresis implemented
To govern the data transfer at data port D3, …,D0 strobe pin DSTBn is equipped with a lowside open-drain output switch plus a passive high-side current source with a nom. 10 µA pullup current capability.
However a second function is assigned to the DSTBn pin which requires it to be input as well:
if a low-pulse is imposed on DSTBn by external means with a pulse width of at least 50 to 100
ms, the slave device will be put in RESET condition, as described in section “Reset”.
The dc-and timing parameters of strobe pin DSTBn are specified as follows:
6\PERO
IOUTLO
IOUTHI
IINLO
VSCHLT
VIN
tNORESET
tRESET
CPINEXT
Notes:
1
2
3DUDPHWHU
Sink current @ output L
Leakge current @ output off
Input current @ VIN = 1V
Input threshold voltage
Acceptable input voltage @
output off
DSTBn L-phase width, not
triggering RESET
DSTBn L-phase width, triggering RESET
Stray capacitance
PLQ
10
- 10
-5
1.5
- 0.3
PD[
10
- 20
3.5
40
8QLW
mA
µA
µA
V
V
50
ms
100
1RWH
VOUT = 1V
VOUT = 5V
1
2
ms
20
pF
DSTBn is equipped with an on-chip pull-up current source, which ensures
a sufficiently fast LH-edge upon output switch-off in open-pin condition,
to prevent erroneous RESET triggering.
If DSTBn has an external load connected to it,
an additional external pull-up resistor may be needed
to prevent erroneous RESET triggering upon output switch-off
No hysteresis implemented
Rev. C, January 2001
Page 9 of 18
AS-Interface Slave IC
AS2702 (SAP4.1)
L 3DUDPHWHUSRUWSLQV3«3DQGSDUDPHWHUVWUREHSLQ367%Q
(Note that parameter port pins P3, …, P0 are only available on AS2702 package option SOIC
20, not on the SOIC 16 option.)
The transfer of data at P3, …, P0 and the supporting strobe action at pin PSTBn takes place
similarly as at D3, …, D0 resp. DSTBn.
Each parameter port pin P3, …, P0 is equipped with both a low-side open-drain output switch
plus a passive, but switchable high-side current source with a nom. 10 µA pull-up current capability, and with an input stage.
Though equipped for bidirectional data transfer as D3, …, D0, the parameter port is less flexible than the data port.
Basically the parameter port is set to behave portwise as
• output, or
• input
depending on the IO-configuration code, written into and stored in the slave device.
The timing of the data transfer is presented in fig. 3.
Strobe signal PSTBn flags and governs the data transfer as follows:
ia) parameter port is set ‘output’:
output data become valid upon the HL-edge of the strobe and will remain so until the
next HL-edge, hence during the entire strobe cycle;
ib) parameter port is set ‘input’:
input data to be valid within a specific time window relative to the HL-edge of the
strobe, after completion of the strobe’s L-phase.
Output data as per ia) could be easily latched with the LH-edge of strobe PSTBn, if at all necessary.
Px
tSTB
Parameter out
Px
Parameter out
Data in
PSTBn
tPSTBn
tINPmin
tINPmax
Fig. 3: Timing of data transfer at parameter port P3, …, P0 relative to strobe PSTBn
Rev. C, January 2001
Page 10 of 18
AS-Interface Slave IC
AS2702 (SAP4.1)
The following table specifies the timing parameters relating to fig. 3:
6\PERO
tSTB
tPSTBn
tINP
Notes:
1
2
3DUDPHWHU
Delay PSTBn HL-edge to Px
output data valid
PSTBn strobe width
Input data valid time window
PLQ
PD[
1.5
8QLW
µs
1RWH
6
10.5
6.8
12.5
µs
µs
1
2
Pulse width depends substantially on value of external pull-up resistor
Timing reference is PSTBn HL-edge.
Applies only to parameter port set to 'input' operation
The dc-parameters of the parameter port pins P3, …, P0 are specified as follows:
6\PERO
IOUTLO
IOUTHI
IOUTHI7
IINLO
VSCHLT
VIN
Notes:
1
2
3DUDPHWHU
Sink current @ output L
Leakage current @ output off
Leakage current @ output off;
pull-up current source off
Input current @ VIN = 1V
Input threshold voltage
Acceptable input voltage @
output off
PLQ
10
- 10
-1
PD[
10
1
8QLW
mA
µA
µA
-5
2.5
- 0.3
- 20
3.5
40
µA
V
V
1RWH
VOUT = 1V
VOUT = 5V
VOUT = 5V;
IO-conf. = 7
1
2
The passive high-side current-source provides an about constant input current @
0V <= VIN <= 4V
No hysteresis implemented
Though equipped for bidirectional data transfer as D3, …, D0, the parameter port is nevertheless less flexible than the data port.
Note the following differences:
ik) The parameter port is set portwise, the data port bitwise by the IO-configuration code;
il) The parameter port can only be set to either ‘output’ or ‘input’. A bidirectional behaviour
within a strobe cycle is not possible;
im) The parameter port is set to ‘output’ as a rule; the only exception occurs in case of IOconfiguration 7 and a master data request, which set it to ‘input’.
To govern the data transfer at the parameter port P3, …, P0 strobe pin PSTBn is equipped
with a low-side open-drain output switch plus a passive high-side current source with a nom.
10 µA pull-up current capability. Typically the PSTBn-strobe width is about 6 µs, see fig. 3.
( However to simplify and shorten the component test time of the slave device, the PSTBn pin
is also used as an input. Input low pulses of more than 50 µs each will step and cycle the device through 3 different testmodes beyond the regular operation as described in this datasheet.)
Rev. C, January 2001
Page 11 of 18
AS-Interface Slave IC
AS2702 (SAP4.1)
The dc- and timing parameters of strobe pin PSTBn are specified as follows:
6\PERO
IOUTLO
IOUTHI
IINLO
VSCHLT
VIN
tNOTM
tTM
CPINEXT
3DUDPHWHU
Sink current @ output L
Leakage current @ output off
Input current @ VIN = 1V
Input threshold voltage
Acceptable input voltage @ output off
PSTBn L-phase width, not triggering testmode
PSTBn L-phase width, triggering
testmode
Stray capacitance
PLQ
10
- 10
-5
1.5
- 0.3
PD[
10
- 20
3.5
40
8QLW
mA
µA
µA
V
V
35
µs
50
1RWH
VOUT = 1V
VOUT = 5V
1
2
µs
20
pF
Notes:
1
PSTBn is equipped with an on-chip pull-up current source, which ensures
a sufficiently fast LH-edge upon output switch-off in open-pin condition, to prevent
erroneous testmode triggering.
If PSTBn has an external load connected to it, an additional external pull-up resistor
may be needed to prevent erroneous testmode triggering upon output switch-off
2
No hysteresis implemented
2 S H U D W L R Q V WD W X V S L Q V / ( ' D Q G / ( ' Pins LED1 and LED2 are both equipped with a low-side open-drain output switch plus a passive high-side current source with a nom. 10 µA pull-up current capability. They will each have
an LED load connected to UOUT, which will flag the operation status of the slave device, according to the following table:
2XWSXW/('
2XWSXW/(' )ODJJLQJ3ULRULW\
JUHHQ/('
FRQQHFWHG
off
on
off
UHG/('FRQ
QHFWHG
off
off
on
KLJKHVW«
ORZHVW
blinks
on
3
blinks
blinks
(alternating with
LED1)
blinks
2
off
4
1
6ODYH'HYLFH
2SHUDWLRQ6WDWXV
Supply voltage off
Regular operation
No Data
Communication
No regular slave
address coded
Hardware failure in
sensor / acuator
circuitry
External RESET or
Overload at UOUT
pin
5HDVRQ
No supply voltage
Regular, non-zero
slave address coded;
data comm. watchdog
triggered
Slave address = default zero
Input PFAULT = L
DSTBn = L to RESET,
or UOUT switched-off
due to overload
(LED1 and LED2 both also feature an input stage, to simplify component test and shorten test
time of the slave device.)
The dc- and timing parameters of pins LED1 and LED2 are specified as follows:
Rev. C, January 2001
Page 12 of 18
AS-Interface Slave IC
AS2702 (SAP4.1)
6\PERO
ILED
IOUTHI
VIN
fBLINK
3DUDPHWHU
Sink current @ output L
Leackage current @ output off
Acceptable input voltage @ output off
Blinking frequency
PLQ
10
- 10
- 0.3
PD[
10
40
8QLW
mA
µA
V
2
3
Hz
1RWH
VOUT = 1V
VOUT = 5V
' D WD & R P P X Q L F D W L R Q :D W F K G R J
AS2702 is equipped with a watchdog timer to supervise data communication by monitoring
the strobe signals at pins DSTBn and PSTBn.
If a parameter or data strobe is not followed by a consecutive strobe within a time period of
50 … 100 ms, the watchdog is triggered and initiates a ‘soft’ reset, see section ‘Reset’
5(6(7
There are 2 categories of reset-events, leading to 2 slightly different reset-conditions of the
slave device:
1) a ‘hard’ reset taking place at power-up and power-down of supply-voltages U5R and
UOUT.
At power-up the slave device leaves reset-condition as soon as U5R has passed 3.75V
and UOUT has passed VCOMOFF = nom. 10V.
At power-down the slave device is forced into reset-condition as soon as U5R drops below
3.75V.
(Tolerance of the threshold voltages referred to is -/+ 5%.)
2) a ‘soft’ reset, resulting from one of the following events:
2.1) Data strobe pin DSTBn is kept L for more than 100 ms;
2.2) Master command ‘RESET SLAVE’ is received;
2.3) Master command ‘RESET BROADCAST’ is received;
2.4) The communication watchdog is triggered.
A ‘hard’ reset event conditions the slave device as follows:
• Internal states (counters, flags, …) are reset
• The slave device’s receiver is desynchronized from the AS-interface bus
• The low-side open-drain output stages at ports D3, …, D0 and ports P3, …, P0 are
switched off
• Any test-mode will be cancelled.
A ‘soft’ reset has the following consequences:
• A regular, nominal 6µs L-phase strobe is generated on both the DSTBn and PSTBn pin
• The low-side open-drain output stages at ports D3, …, D0 and ports P3, …, P0 are
switched off
• Internal states (counters, flags, …) are reset, however the following states and operations
are not affected:
•
the timer function which controls blinking of LED1 and LED2
•
the data communication watchdog
•
any testmode
•
any EEPROM write operation.
Remark:
Rev. C, January 2001
Page 13 of 18
AS-Interface Slave IC
AS2702 (SAP4.1)
If UOUT drops below VCOMOFF = nom. 10V data communication with the AS-interface bus is
aborted by the receiver or transmitter of the slave device. As long as U5R does not drop below 3.75V in this situation, no ‘hard’ reset takes place; however the data communication
watchdog will be triggered (unless disabled) and a ‘soft’ reset will result.
((3520
AS2702 has a 16 x 8 Bits serial interface EEPROM on board to store the slave unit’s address
and set-up data in a non-volatile fashion.
The EEPROM stores the following data:
((3520
$GGUHVV
0, 1
2
3
4
5
6
Note
1
'DWD
Slave Address
Settings (EID1)
Settings (IO-Conf.)
Settings (ID)
Settings (EID2)
Settings (ControlCode)
5HOHYDQW1U
RIELWV
5+1
4
5
5
5
5
3URJUDPPHGE\
1RWH
Master (Initialization)
Master (Initialization)
Slave unit manufacturer
Slave unit manufacturer
Slave unit manufacturer
Slave unit manufacturer
1
6 Bits (A4, …, A0 + Sel-bit) in extended address mode: 62 slaves addressable;
5 Bits (A4, …, A0) in non-extended address mode: 31 slaves addressable
Obviously the capacity of the EEPROM is only partially used.
Reading and writing of the EEPROM is performed bytewise and trough temporary, volatile
registers.
Writing of data from the volatile register into the EEPROM takes about 10 ms per byte,
whereas reading takes less than 1 ms per byte.
Upon RESET the EEPROM info is read into temporary registers, including the slave’s address
which has been written redundantly into EEPROM locations 0 and 1 before.
The temporary registers receiving the address are compared for similarity; in case of nonsimilarity – which e.g. may have been caused by a supply voltage dip during address writing –
the slave will flag non-regular operation status / slave address zero.
Rev. C, January 2001
Page 14 of 18
AS-Interface Slave IC
AS2702 (SAP4.1)
$6 , Q W H U I D F H % X V & R P P X Q L F D W L R Q
All slaves connected to an AS-interface bus are sequentially and cyclicly called by the master
in a string of individual transactions between the master and each slave unit.
A transaction consists of a 14 bits master request, typically containing the slave’s address as
well as data or parameter info, and an immediate acknowledging slave response of 7 bits.
The 14 bits master request - apart from Start Bit ST = 0 and End Bit EB = 1 – has the following contents:
•
•
•
•
1 Control Bit CB: CB = 0 stands for data transfer (typ. data or parameters)
CB = 1 identifies command-type requests
5 Address Bits: A4, …, A0
5 Information Bits:
I4, …, I0 (typ. data or parameters)
1 Parity Bit PB.
AS2702 allows for up to 62 slaves on the same AS-interface bus; this requires a slave address extended to 6 bits, hence an extra bit beyond A4, …, A0.
th
Information bit I3 is used as the 6 address bit in this so-called extended address mode. It is
called Sel-bit, as it is perceived as to select between A-slave (Sel = 0) and B-slave (Sel = 1) at
address location A4, …, A0.
In non-extended address mode AS2702 is addressed with A4, …, A0 only - for a max. total of
31 slaves per AS-interface bus system, and is system compatible with existing slave device
AS2701A.
The 7 bits slave response – apart from Start Bit ST = 0 and End Bit EB = 1 – has the following
contents:
•
•
4 Information Bits:
1 Parity Bit PB.
I4, …, I0 (typ. data or parameters)
Detailed descriptions of all types of master requests and corresponding slave responses can
be found in AS-Interface Specification V2.11, obtainable from the AS-International Association
(D) or its local representative, see section “Application Support”.
Rev. C, January 2001
Page 15 of 18
AS-Interface Slave IC
AS2702 (SAP4.1)
$S S O L F D W L R Q ( [ D P S O H
C2
P0
P1
D1
D0
LED1
DSTBn
V2
OSC2
U5R
OSC1
LTGN
G1
D2
P3
P2
D3
PSTBn
LED2
UOUT
CDC
LTGP
PFAULT
$6
ASI Line
ASI-P
V1
Sensor / Actuator Circuit
Sensor/actuator circuit supplied by the ASI Slave IC (UOUT) for supply current needs
≤ 50 mA.
C1
C3
C4
C1 = 100 nF / 35 V
C2 = 100 nF / 6 V
C3 = 10...470 µF / 30 V
C4 = 22...100 nF / 30 V
V1 = 1N4002 or equivalent
V2 = TGL 41-39A or equivalent
G1 = AS-Interface Crystal 5.333 MHz
$6 , Q W H U I D F H 4 X D U W ] 0 + ]
AS2702 works fine with the following crystal types:
Citizen CM 309
Philips SQ 4849
AS-Interface quartz crystals are available from:
Endrich GmbH
Contact: Axel Gensler
Hauptstr. 56
D-72202 Nagold
Tel.: +49-7452-6007-31
Fax: +49-7452-6007-70
Email: [email protected]
Rev. C, January 2001
Geyer electronic
Contact: Jürgen Blank
Camerloherstr. 71
D-80689 München
Tel.: +49-89-546868-13
Fax: +49-89-546868-90
Page 16 of 18
AS-Interface Slave IC
AS2702 (SAP4.1)
Kinseki Europe GmbH
Contact: Dirk Holstein
Schirmer Str. 76
D-40211 Düsseldorf
Tel.: +49-211-36815-33
Fax: +49-211-36815-10
Email: [email protected]
Rutronik Elektronische Bauelemente GmbH
Contact: Jürgen Tischhauser
Industriestrasse 2
D-75228 Ispringen / Pforzheim
Tel.: +49-7231-801-543
Fax: +49-7231-801-633
Email: [email protected]
$S S O L F D W L R Q 6 X S S R U W
For general information and documentation on the AS-Interface concept you may contact one
of the following AS-Interface Associations:
AS-International Association
Contact: Rolf Becker
Zum Taubengarten 52
D-63571 Gelnhausen
Tel.: +49-6051-473212
Fax: +49-6051-473282
Email: [email protected]
AS-Interface Switzerland
Contact: Rainer Schnaidt
Bittertenstraße 15
CH-4702 Oensingen
Tel.: +41-62-388-2567
Fax: +41-62-388-2525
Email: [email protected]
AS-Interface France
Contact: Gilles Mazet
5 rue Nadar
F-92566 Rueil Malmaison cedex
Tel.: +33-1-41-298294
Fax: +33-1-41-298482
Email: [email protected]
AS-Interface Italy
Contact: Maurizio Ghizzoni
Via G.B. Barinetti, 1
I-20145 Milano
Tel.: +39-02-66761
Fax: +39-02-6676-3491
Email: [email protected]
AS-Interface The Nederlands
Contact: Andre Braakman
Boerhaavelaan 40
NL-2700 AD Zoetermeer
Tel.: +31-79-353-1269
Fax: +31-79-353-1365
Email: [email protected]
AS-Interface Great Britain
Contact: Geoff Hodgkinson
1 West Street
GB-PO 14 4DH Titchfield, Hampshire
Tel.: +44-1329-511882
Fax: +44-1329-512063
Email: [email protected]
AS-Interface USA
Contact: Michael Bryant
16101 N. 82nd Street, Suite 3B
USA-85260 Scottsdale, Arizona
Tel.: +1-480-368-9091
Fax: +1-480-483-7202
Email: [email protected]
AS-Interface Belgium
Contact: Maurice de Smedt
Avenue Paul Hymanslaan 47
B-1200 Bruxelles-Brussel
Tel.: +32-2-771-3912
Fax: +32-2-771-1264
Email: [email protected]
Rev. C, January 2001
AS-Interface Sweden
Contact: Lars Mattsson
Karl Nordströms väg 31
SE-43253 Varberg
Tel.: +46-3406-29270
Fax: +46-3406-77190
Email: [email protected]
Page 17 of 18
AS-Interface Slave IC
AS2702 (SAP4.1)
%LEOLRJUDSK\
ASI: The Actuator-Sensor-Interface for Automation
Edts.: Werner Kriesel, Otto W. Madelung
Carl Hanser Verlag, Munich and Vienna, 1995
ISBN: 3-446-18265-9
2UGHULQJ,QIRUPDWLRQ
AS2702-20T
AS2702-16T
AS2702-20
AS2702-16
Package: SOIC 20; delivery: tape & reel
Package: SOIC 16 W; delivery: tape & reel; no parameter port available
Package: SOIC 20; delivery: tubes
Package: SOIC 16 W; delivery: tubes; no parameter port available
Copyright 2000, Austria Mikro Systeme International AG, Schloß Premstätten, 8141 Unterpremstätten, Austria.
Tel. +43-(0)3136-500-0, Fax +43-(0)3136-52501, E-Mail [email protected]
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by
any means, without the prior permission in writing by the copyright holder. To the best of its knowledge, Austria Mikro Systeme
International asserts that the information contained in this publication is accurate and correct.
Rev. C, January 2001
Page 18 of 18