TI1 LMP90098MHE/NOPB Lmp90100/lmp90099/lmp90098/lmp90097 sensor afe system: multi-channel, low power 24-bit sensor afe with true continuous background calibration Datasheet

LMP90100
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SNAS510P – JANUARY 2011 – REVISED MARCH 2013
LMP90100/LMP90099/LMP90098/LMP90097 Sensor AFE System: Multi-Channel, Low
Power 24-Bit Sensor AFE with True Continuous Background Calibration
Check for Samples: LMP90100
FEATURES
APPLICATIONS
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24-Bit Low Power Sigma Delta ADC
True Continuous Background Calibration at all
gains
In-Place System Calibration using Expected
Value programming
Low-Noise programmable gain (1x - 128x)
Continuous background open/short and out of
range sensor diagnostics
8 output data rates (ODR) with single-cycle
settling
2 matched excitation current sources from 100
µA to 1000 µA (LMP90100/LMP90098)
4-DIFF / 7-SE inputs (LMP90100/LMP90099)
2-DIFF / 4-SE inputs (LMP90098/LMP90097)
7 General Purpose Input/Output pins
Chopper-stabilized buffer for low offset
SPI 4/3-wire with CRC data link error detection
50 Hz to 60 Hz line rejection at ODR ≤13.42
SPS
Independent gain and ODR selection per
channel
Supported by Webench Sensor AFE Designer
Automatic Channel Sequencer
KEY SPECIFICATIONS
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ENOB/NFR Up to 21.5/19 bits
Offset Error (typ) 8.4 nV
Gain Error (typ) 7 ppm
Total Noise < 10 µV-rms
Integral Non-Linearity (INL max) ±15 ppm of
FSR
Output Data Rates (ODR) 1.6775 - 214.65 SPS
Analog Voltage, VA +2.85 to +5.5 V
Operating Temp Range -40°C to 125 °C
Package 28 Pin HTSSOP exposed pad
Temperature and Pressure Transmitters
Strain Gauge Interface
Industrial Process Control
DESCRIPTION
The LMP90100/LMP90099/LMP90098/LMP90097 are
highly integrated, multi-channel, low power 24-bit
Sensor AFEs. The devices features a precision, 24bit Sigma Delta Analog-to-Digital Converter (ADC)
with a low-noise programmable gain amplifier and a
fully differential high impedance analog input
multiplexer. A true continuous background calibration
feature allows calibration at all gains and output data
rates without interrupting the signal path. The
background calibration feature essentially eliminates
gain and offset errors across temperature and time,
providing measurement accuracy without sacrificing
speed and power consumption.
Another
feature
of
the
LMP90100/LMP90099/LMP90098/LMP90097
is
continuous background sensor diagnostics, allowing
the detection of open and short circuit conditions and
out-of-range
signals,
without
requiring
user
intervention, resulting in enhanced system reliability.
Two sets of independent external reference voltage
pins allow multiple ratiometric measurements. In
addition, two matched programmable current sources
are available in the LMP90100/LMP90098 to excite
external sensors such as resistive temperature
detectors and bridge sensors. Furthermore, seven
GPIO pins are provided for interfacing to external
LEDs and switches to simplify control across an
isolation barrier.
Collectively,
these
features
make
the
LMP90100/LMP90099/LMP90098/LMP90097
complete analog front-ends for low power, precision
sensor applications such as temperature, pressure,
strain gauge, and industrial process control. The
LMP90100/LMP90099/LMP90098/LMP90097
are
ensured over the extended temperature range of 40°C to +125°C and are available in a 28-pin
HTSSOP package with an exposed pad.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TRI-STATE is a registered trademark of National Semiconductor Corporation.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
LMP90100
SNAS510P – JANUARY 2011 – REVISED MARCH 2013
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Typical Application
2 -Wire RTD
3-Wire RTD
IB1
2
3
4
SCLK
IB2
VIN0
...
VIN2
...
VIN4
...
VIN6/VREFP2
VIN7/
VREFN2
2
VIO
CSB
1
+
VREFP1 VREFN1
VA
4-Wire RTD
Thermocouple
VA
GND
SDO/DRDYB
LMP90100
LM90xxx 24-bit Sensor AFE Family of Products
MicroController
SDI
D0
...
D6/DRDYB
CLK/XIN XOUT
LEDs/
Switches
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Product
Channel Configuration
Current Sources
LMP90100
4 Differential/7 Single-Ended
Yes
LMP90099
4 Differential/7 Single-Ended
No
LMP90098
2 Differential/4 Single-Ended
Yes
LMP90097
2 Differential/4 Single-Ended
No
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Block Diagram
Chip Configurable
LMP90xxx
Channel Configurable
Fixed
EXC.
CURRENT
EXC.
CURRENT
IB1
LMP90100/LMP9
0098 only
VIO
VA
VA
IB2
POR
Open/Short
Sensor Diag.
VIN0
VIN1
VIN3
LMP90100/LMP9
0099 only
VIN4
VIN5
BACKGROUND
CALIBRATION
INPUT MUX
VIN2
FGA
16x
PGA
1x, 2x,
4x, 8x
SERIAL I/F
CONTROL
&
CALIBRATION
DATA PATH
SCLK
SDI
SDO/DRDYB
CSB
BUFF
24 bit SD
Module
VIN6/VREFP2
DIGITAL
FILTER
VIN7/VREFN2
CLK
MUX
VREF
Ext. Clk
Detect
Internal
CLK
MUX
GND
VREFP1
GPIO
VREFN1
XOUT
CLK/ D6/
XIN DRDYB
D0
Figure 1. Block Diagram
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• True Continuous Background Calibration
The LMP90100/LMP90099/LMP90098/LMP90097 feature a 24 bit ΣΔ core with continuous background
calibration to compensate for gain and offset errors in the ADC, virtually eliminating any drift with time and
temperature. The calibration is performed in the background without user or ADC input interruption, making it
unique in the industry and eliminating down time associated with field calibration required with other solutions.
Having this continuous calibration improves performance over the entire life span of the end product.
• Continuous Background Sensor Diagnostics
Sensor diagnostics are also performed in the background, without interfering with signal path performance,
allowing the detection of sensor shorts, opens, and out-of-range signals, which vastly improves system reliability.
In addition, the fully flexible input multiplexer described below allows any input pin to be connected to any ADC
input channel providing additional sensor path diagnostic capability.
• Flexible Input MUX Channels
The flexible input MUX allows interfacing to a wide range of sensors such as thermocouples, RTDs, thermistors,
and bridge sensors. The LMP90100/LMP90099’s multiplexer supports 4 differential channels while the
LMP90098/LMP90097 supports 2. Each effective input voltage that is digitized is VIN = VINx – VINy, where x
and y are any input. In addition, the input multiplexer of the LMP90100/LMP90099 also supports 7 single-ended
channels (LMP90098/LMP90097 supports 4), where the common ground is any one of the inputs.
• Programmable Gain Amplifiers (FGA & PGA)
The LMP90100/LMP90099/LMP90098/LMP90097 contain an internal 16x fixed gain amplifier (FGA) and a 1x,
2x, 4x, or 8x programmable gain amplifier (PGA). This allows accurate gain settings of 1x, 2x, 4x, 8x, 16x, 32x,
64x, or 128x through configuration of internal registers. Having an internal amplifier eliminates the need for
external amplifiers that are costly, space consuming, and difficult to calibrate.
• Excitation Current Sources (IB1 & IB2) - LMP90100/LMP90098
Two matched internal excitation currents, IB1 and IB2, can be used for sourcing currents to a variety of sensors.
The current range is from 100 µA to 1000 µA in steps of 100 µA.
4
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Connection Diagram
LMP90100/
LMP90099 only
VA
1
28
VIO
VIN0
2
27
D6/DRDYB
VIN1
3
26
D5
VIN2
4
25
D4
VIN3
5
24
D3
VIN4
6
23
D2
22
D1
VIN5
7
VREFP1
8
VREFN1
LMP90xxx
28-pin HTSSOP
21
D0
9
20
SDO/DRDYB
SDI
VIN6/VREFP2
10
19
VIN7/VREFN2
11
18
SCLK
IB2
12
17
CSB
IB1
13
16
GND
XOUT
14
15
XIN/CLK
LMP90100/
LMP90098 only
Figure 2. See Package Number PWP0028A
See Pin Descriptions for specific information regarding options LMP90099, LMP90098, and LMP90097.
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Pin Functions
PIN DESCRIPTIONS
Pin #
Pin Name
Type
1
VA
Analog Supply
2-4
VIN0 - VIN2
Analog Input
Analog input pins
5-7
(LMP90100,
LMP90099)
VIN3 - VIN5
Analog Input
Analog input pins
5-7
(LMP90098,
LMP90097)
VIN3 - VIN5
No Connect
No connect: must be left unconnected
8
VREFP1
Analog Input
Positive reference input
9
VREFN1
Analog Input
Negative reference input
10
VIN6 / VREFP2
Analog Input
Analog input pin or VREFP2 input
11
VIN7 / VREFN2
Analog Input
Analog input pin or VREFN2 input
12 - 13
(LMP90100,
LMP90098)
IB2 & IB1
Analog output
Excitation current sources for external RTDs
12 - 13
(LMP90099,
LMP90097)
IB2 & IB1
No Connect
14
XOUT
Analog output
External crystal oscillator connection
15
XIN / CLK
Analog input
External crystal oscillator connection or external clock input
16
GND
Ground
17
CSB
Digital Input
Chip select bar
18
SCLK
Digital Input
Serial clock
19
SDI
Digital Input
Serial data input
20
SDO / DRDYB
Digital Output
21 - 26
D0 - D5
Digital IO
General purpose input/output (GPIO) pins
27
D6 / DRDYB
Digital IO
General purpose input/output pin or data ready bar
28
VIO
Digital Supply
Thermal Pad
6
Function
Analog power supply pin
No connect: must be left unconnected
Power supply ground
Serial data output and data ready bar
Digtal input/output supply pin
You can leave this thermal pad floating.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2)
Analog Supply Voltage, VA
-0.3V to 6.0V
Digital I/O Supply Voltage, VIO
-0.3V to 6.0V
Reference Voltage, VREF
-0.3V to VA+0.3V
Voltage on Any Analog Input Pin to GND
(3)
-0.3V to VA+0.3V
Voltage on Any Digital Input PIN to GND
(3)
-0.3V to VIO+0.3V
Voltage on SDO
(3)
Input Current at Any Pin
-0.3V to VIO + 0.3V
(3)
5mA
Output Current Source or Sink by SDO
3mA
Total Package Input and Output Current
20mA
ESD Susceptibility
Human Body Model (HBM)
2500V
Machine Models (MM)
200V
Charged Device Model (CDM)
1250V
Junction Temperature (TJMAX)
+150°C
Storage Temperature Range
–65°C to +150°C
For soldering specifications: see product folder at www.ti.com and http://www.ti.com/lit/SNOA549.
(1)
(2)
(3)
All voltages are measured with respect to GND, unless otherwise specified
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
When the input voltage (VIN) exceeds the power supply (VIN < GND or VIN > VA), the current at that pin must be limited to 5mA and
VIN has to be within the Absolute Maximum Rating for that pin. The 20 mA package input current rating limits the number of pins that
can safely exceed the power supplies with current flow to four pins.
Operating Ratings
Analog Supply Voltage, VA
+2.85V to 5.5V
Digital I/O Supply Voltage, VIO
+2.7V to 5.5V
Full Scale Input Range, VIN
±VREF / PGA
Reference Voltage, VREF
+0.5V to VA
TMIN = –40°C
Temperature Range for Electrical Characteristics
TMAX = +125°C
–40°C ≤ TA ≤ +125°C
Operating Temperature Range
Junction to Ambient Thermal Resistance (θJA)
(1)
(1)
41°C/W
The maximum power dissipation is a function of TJ(MAX) AND θJA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA) / θJA.
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Electrical Characteristics
Unless otherwise noted, the key for the condition is (VA = VIO = VREF) / ODR (SPS) / buffer / calibration / gain . Boldface
limits apply for TMIN ≤ TA ≤ TMAX; the typical values apply for TA = +25°C.
Symbol
n
Parameter
Conditions
Min
Typ
Resolution
ENOB /
NFR
ODR
INL
Effective Number
of Bits and Noise
Free Resolution
3V / all / ON / OFF / all. Shorted input.
Table 1
Bits
5V / all / ON / OFF / all. Shorted input.
Table 3
Bits
Gain
FGA × PGA
Integral NonLinearity
3V / 214.65 / ON / ON / 1
1.6675
Table 1
1
Table 1
128
-15
±7
+15
3V & 5V / 214.65 / ON / ON / 16
Table 2
µV
5V / all / ON / OFF / all. Shorted input.
Table 4
µV
Below Noise
Floor (rms)
µV
3V / 214.65 / ON / ON / 128
5V / 214.65 / ON / ON / 128
1.22
9.52
µV
0.00838
0.70
µV
1.79
8.25
µV
0.0112
0.63
µV
3V & 5V / 214.65 / ON or OFF / OFF /
1-8
100
nV/°C
3
nV/°C
3V & 5V / 214.65 / ON / OFF / 16
25
nV/°C
3V & 5V / 214.65 / ON / ON / 16
0.4
nV/°C
3V & 5V / 214.65 / ON / OFF / 128
6
nV/°C
3V & 5V / 214.65 / ON / ON / 128
0.125
nV/°C
5V / 214.65 / ON / OFF / 1, TA = 150°C
2360
nV / 1000
hours
5V / 214.65 / ON / ON / 1, TA = 150°C
100
nV / 1000
hours
3V & 5V / 214.65 / ON / ON / 1-8
Offset Drift over
Time (1)
3V & 5V / 214.65 / ON / ON / 1
GE
Gain Error
Gain Drift over
Temp (1)
Gain Drift over
Time (1)
ppm
3V / all / ON / ON / all. Shorted input.
5V / 214.65 / ON / ON / 1
Offset Drift Over
Temp (1)
SPS
ppm
3V / 214.65 / ON / ON / 1
Offset Error
214.6
± 15
3V & 5V / all / ON or OFF / ON / all
OE
Units
Bits
Output Data Rates
Total Noise
Max
24
-80
7
3V & 5V / 13.42 / ON / ON / 16
80
ppm
50
ppm
3V & 5V / 13.42 / ON / ON / 64
50
ppm
3V & 5V / 13.42 / ON / ON / 128
100
ppm
3V & 5V / 214.65 / ON / ON / all
0.5
ppm/°C
5V / 214.65 / ON / OFF / 1, TA = 150°C
5.9
ppm / 1000
hours
5V / 214.65 / ON / ON / 1, TA = 150°C
1.6
ppm / 1000
hours
CONVERTER'S CHARACTERISTIC
CMRR
Input Common
Mode Rejection
Ratio
Reference
Common Mode
Rejection
PSRR
(1)
8
Power Supply
Rejection Ratio
DC, 3V / 214.65 / ON / ON / 1
70
117
dB
DC, 5V / 214.65 / OFF / OFF / 1
90
120
dB
50/60 Hz, 5V / 214.65 / OFF / OFF / 1
117
dB
VREF = 2.5V
101
dB
115
dB
112
dB
DC, 3V / 214.65 / ON / ON / 1
75
DC, 5V / 214.65 / ON / ON / 1
This parameter is specified by design and/or characterization and is not tested in production.
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Electrical Characteristics (continued)
Unless otherwise noted, the key for the condition is (VA = VIO = VREF) / ODR (SPS) / buffer / calibration / gain . Boldface
limits apply for TMIN ≤ TA ≤ TMAX; the typical values apply for TA = +25°C.
Symbol
NMRR
Parameter
Normal Mode
Rejection Ratio
(2)
Cross-talk
Conditions
Min
47 Hz to 63 Hz, 5V / 13.42 / OFF / OFF
/1
Typ
Max
Units
78
3V / 214.65 / OFF / OFF / 1
95
136
dB
5V / 214.65 / OFF / OFF / 1
95
143
dB
dB
POWER SUPPLY CHARACTERISTICS
VA
Analog Supply
Voltage
2.85
3.0
5.5
V
VIO
Digital Supply
Voltage
2.7
3.3
5.5
V
3V / 13.42 / OFF / OFF / 1, ext. CLK
400
500
µA
5V / 13.42 / OFF / OFF / 1, ext. CLK
464
555
µA
3V / 13.42 / ON / OFF / 64, ext. CLK
600
700
µA
IVA
Analog Supply
Current
5V / 13.42 / ON / OFF / 64, ext. CLK
690
800
µA
3V / 214.65 / ON / OFF / 64, int. CLK
1547
1700
µA
5V / 214.65 / ON / OFF / 64, int. CLK
1760
2000
µA
3V / 214.65 / OFF / OFF / 1, int. CLK
826
1000
µA
5V / 214.65 / OFF / OFF / 1, int. CLK
941
1100
µA
Standby, 3V , int. CLK
3
10
µA
Standby, 3V , ext. CLK
257
Standby, 5V, int. CLK
5
Standby, 3V, ext. CLK
300
Power-down, 3V, int/ext CLK
2.6
5
µA
Power-down, 5V, int/ext CLK
4.6
9
µA
VREFN + 0.5
VA
V
GND
VREFP - 0.5
V
0.5
VA
V
µA
15
µA
µA
REFERENCE INPUT
VREFP
Positive Reference
VREFN
Negative
Reference
VREF
Differential
Reference
VREF = VREFP - VREFN
ZREF
Reference
Impedance
3V / 13.42 / OFF / OFF / 1
10
MOhm
IREF
Reference Input
3V / 13.42 / ON or OFF / ON or OFF /
all
±2
µA
CREFP
Capacitance of the
Positive Reference
(2)
6
pF
CREFN
Capacitance of the
Negative
Reference
(2)
6
pF
1
nA
ILREF
Reference
Leakage Current
, gain = 1
, gain = 1
Power-down
ANALOG INPUT
VINP
VINN
Positive Input
Negative Input
Gain = 1-8, buffer ON
GND + 0.1
VA - 0.1
V
Gain = 16 - 128, buffer ON
GND + 0.4
VA - 1.5
V
Gain = 1-8, buffer OFF
GND
VA
V
Gain = 1-8, buffer ON
GND + 0.1
VA - 0.1
V
Gain = 16 - 128, buffer ON
GND + 0.4
VA - 1.5
V
VA
V
Gain = 1-8, buffer OFF
VIN
(2)
Differential Input
GND
VIN = VINP - VINN
±VREF / PGA
This parameter is specified by design and/or characterization and is not tested in production.
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Electrical Characteristics (continued)
Unless otherwise noted, the key for the condition is (VA = VIO = VREF) / ODR (SPS) / buffer / calibration / gain . Boldface
limits apply for TMIN ≤ TA ≤ TMAX; the typical values apply for TA = +25°C.
Symbol
Parameter
Differential Input
Impedance
ZIN
Conditions
Min
ODR = 13.42 SPS
Typ
Max
Units
15.4
MOhm
CINP
Capacitance of the 5V / 214.65 / OFF / OFF / 1
Positive Input
4
pF
CINN
Capacitance of the 5V / 214.65 / OFF / OFF / 1
Negative Input
4
pF
3V & 5V / 13.42 / ON / OFF / 1-8
500
pA
3V & 5V / 13.42 / ON / OFF / 16 - 128
100
pA
Input Leakage
Current
IIN
DIGITAL INPUT CHARACTERISTICS at VA = VIO = VREF = 3.0V
VIH
Logical "1" Input
Voltage
VIL
Logical "0" Input
Voltage
IIL
Digital Input
Leakage Current
VHYST
0.7 x VIO
V
-10
Digital Input
Hysteresis
0.3 x VIO
V
+10
µA
0.1 x VIO
V
DIGITAL OUTPUT CHARACTERISTICS at VA = VIO = VREF = 3.0V
VOH
Logical "1" Output
Voltage
Source 300 µA
VOL
Logical "0" Output
Voltage
Sink 300 µA
IOZH,
IOZL
TRISTATE®Leakage
Current
COUT
TRI-STATE
Capacitance
2.6
V
-10
(3)
0.4
V
10
µA
5
pF
0, 100, 200,
300, 400, 500,
600, 700, 800,
900, 1000
µA
EXCITATION CURRENT SOURCES CHARACTERISTICS (LMP90100/LMP90098 only)
IB1, IB2
Excitation Current
Source Output
IB1/IB2 Tolerance
VA = VREF = 3V
-7
2.5
7
%
VA = VREF = 5V
-3.5
0.2
3.5
%
IB1/IB2 Output
VA = 3.0V & 5.0V, IB1/IB2 = 100 µA to
Compliance Range 1000 µA
IB1/IB2 Regulation
IBTC
(3)
10
IB1/IB2 Drift
VA - 0.8
V
0.07
%/V
VA = 3.0V
95
ppm/°C
VA = 5.0V
60
ppm/°C
VA = 5.0V, IB1/IB2 = 100 µA to 1000
µA
This parameter is specified by design and/or characterization and is not tested in production.
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Electrical Characteristics (continued)
Unless otherwise noted, the key for the condition is (VA = VIO = VREF) / ODR (SPS) / buffer / calibration / gain . Boldface
limits apply for TMIN ≤ TA ≤ TMAX; the typical values apply for TA = +25°C.
Symbol
IBMT
IBMTC
Parameter
Conditions
IB1/IB2 Matching
IB1/IB2 Matching
Drfit
Typ
Max
Units
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 100 µA
Min
0.34
1.53
%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 200 µA
0.22
1
%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 300 µA
0.2
0.85
%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 400 µA
0.15
0.8
%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 500 µA
0.14
0.7
%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 600 µA
0.13
0.7
%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 700 µA
0.075
0.65
%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 800 µA
0.085
0.6
%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 900 µA
0.11
0.55
%
3V & 5V / 214.65 / OFF / OFF / 1,
IB1/IB2 = 1000 µA
0.11
0.45
%
VA = 3.0V & 5.0V, IB1/IB2 = 100 µA to
1000 µA
2
ppm/°C
893
kHz
INTERNAL/EXTERNAL CLK
CLKIN
Internal Clock
Frequency
CLKEXT
External Clock
Frequency
External Crystal
Frequency
(3)
1.8
3.5717
Input Low Voltage
0
Input High Voltage
1
Frequency
1.8
MHz
V
V
3.5717
Start-up time
SCLK
7.2
7.2
MHz
10
MHz
7
ms
Serial Clock
Table 1. ENOB (Noise Free Resolution) vs. Sampling Rate and Gain at VA = VIO = VREF = 3V
ODR (SPS)
Gain
1
2
4
8
16
32
64
128
1.6775
20.5 (18)
20.5 (18)
19.5 (17)
19 (16.5)
20.5 (18)
19.5 (17)
19 (16.5)
18 (15.5)
3.355
20 (17.5)
20 (17.5)
19 (16.5)
18.5 (16)
20 (17.5)
19 (16.5)
18.5 (16)
17 (14.5)
6.71
19.5 (17)
19.5 (17)
18.5 (16)
18 (15.5)
19.5 (17)
18.5 (16)
17.5 (15)
17 (14.5)
13.42
19 (16.5)
18.5 (16)
18 (15.5)
17.5 (15)
19 (16.5)
18 (15.5)
17.5 (15)
16.5 (14)
26.83125
20.5 (18)
20 (17.5)
19.5 (17)
19 (16.5)
20 (17.5)
19 (16.5)
18 (15.5)
17.5 (15)
53.6625
20 (17.5)
19.5 (17)
19 (16.5)
18.5 (16)
19.5 (17)
18.5 (16)
17.5 (15)
17 (14.5)
107.325
19.5 (17)
19 (16.5)
18.5 (16)
18 (15.5)
19 (16.5)
18 (15.5)
17 (14.5)
16.5 (14)
214.65
19 (16.5)
18.5 (16)
18 (15.5)
17.5 (15)
18.5 (16)
17.5 (15)
17 (14.5)
16 (13.5)
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Table 2. ENOB (Noise Free Resolution) vs. Sampling Rate and Gain at VA = VIO = VREF = 3V
Gain
ODR (SPS)
1
2
4
8
16
32
64
128
1.6775
20.5 (18)
20.5 (18)
19.5 (17)
19 (16.5)
20.5 (18)
19.5 (17)
19 (16.5)
18 (15.5)
3.355
20 (17.5)
20 (17.5)
19 (16.5)
18.5 (16)
20 (17.5)
19 (16.5)
18.5 (16)
17 (14.5)
6.71
19.5 (17)
19.5 (17)
18.5 (16)
18 (15.5)
19.5 (17)
18.5 (16)
17.5 (15)
17 (14.5)
13.42
19 (16.5)
18.5 (16)
18 (15.5)
17.5 (15)
19 (16.5)
18 (15.5)
17.5 (15)
16.5 (14)
26.83125
20.5 (18)
20 (17.5)
19.5 (17)
19 (16.5)
20 (17.5)
19 (16.5)
18 (15.5)
17.5 (15)
53.6625
20 (17.5)
19.5 (17)
19 (16.5)
18.5 (16)
19.5 (17)
18.5 (16)
17.5 (15)
17 (14.5)
107.325
19.5 (17)
19 (16.5)
18.5 (16)
18 (15.5)
19 (16.5)
18 (15.5)
17 (14.5)
16.5 (14)
214.65
19 (16.5)
18.5 (16)
18 (15.5)
17.5 (15)
18.5 (16)
17.5 (15)
17 (14.5)
16 (13.5)
Table 3. RMS Noise (µV) vs. Sampling Rate and Gain at VA = VIO = VREF = 3V
Gain of the ADC
ODR (SPS)
1
2
4
8
16
32
64
128
1.6775
3.08
1.90
1.53
1.27
0.23
0.21
0.15
0.14
3.355
4.56
2.70
2.21
1.67
0.34
0.27
0.24
0.26
6.71
6.15
4.10
3.16
2.39
0.51
0.40
0.37
0.35
13.42
8.60
5.85
4.29
3.64
0.67
0.54
0.51
0.49
26.83125
3.35
2.24
1.65
1.33
0.33
0.27
0.26
0.25
53.6625
4.81
3.11
2.37
1.90
0.44
0.39
0.37
0.36
107.325
6.74
4.51
3.38
2.66
0.63
0.54
0.52
0.49
214.65
9.52
6.37
4.72
3.79
0.90
0.79
0.72
0.70
Table 4. ENOB (Noise Free Resolution) vs. Sampling Rate and Gain at VA = VIO = VREF = 5V
Gain of the ADC
SPS
1
2
4
8
16
32
64
128
1.6775
21.5 (19)
21.5 (19)
20.5 (18)
20 (17.5)
21 (18.5)
20.5 (18)
19.5 (17)
18.5 (16)
3.355
21 (18.5)
21 (18.5)
20 (17.5)
19.5 (17)
20.5 (18)
20 (17.5)
19 (16.5)
18 (15.5)
6.71
20.5 (18)
20 (17.5)
19.5 (17)
19 (16.5)
20 (17.5)
19.5 (17)
19 (16.5)
17.5 (15)
13.42
20 (17.5)
19.5 (17)
19 (16.5)
18.5 (16)
20 (17.5)
19 (16.5)
18 (15.5)
17.5 (15)
26.83125
21.5 (19)
21 (18.5)
20.5 (18)
20 (17.5)
21 (18.5)
20 (17.5)
19.5 (17)
18 (15.5)
53.6625
21 (18.5)
20.5 (18)
20 (17.5)
19.5 (17)
20.5 (18)
19.5 (17)
18.5 (16)
17.5 (15)
107.325
20.5 (18)
20 (17.5)
19.5 (17)
19 (16.5)
20 (17.5)
19 (16.5)
18 (15.5)
17 (14.5)
214.65
20 (17.5)
19.5 (17)
19 (16.5)
18.5 (16)
19.5 (17)
18.5 (16)
17.5 (15)
16.5 (14)
Table 5. RMS Noise (µV) vs. Sampling Rate and Gain at VA = VIO = VREF = 5V
Gain of the ADC
SPS
1
2
4
8
16
32
64
128
1.6775
2.68
1.65
1.24
1.00
0.22
0.19
0.17
0.16
3.355
3.86
2.36
1.78
1.47
0.34
0.27
0.22
0.22
6.71
5.23
3.49
2.47
2.09
0.44
0.34
0.30
0.32
13.42
7.94
5.01
3.74
2.94
0.61
0.50
0.45
0.43
26.83125
2.90
1.86
1.34
1.08
0.29
0.24
0.23
0.23
53.6625
4.11
2.60
1.90
1.50
0.39
0.35
0.32
0.31
107.325
5.74
3.72
2.72
2.11
0.56
0.48
0.46
0.44
214.65
8.25
5.31
3.82
2.97
0.79
0.68
0.64
0.63
12
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Timing Diagrams
Unless otherwise noted, specified limits apply for VA = VIO = 3.0V. Boldface limits apply for TMIN ≤ TA ≤ TMAX; the
typical values apply for TA = +25°C.
CSB
tCH
SCLK
1
2
3
1/fSCLK
tCL
4
5
6
7
8
9
10
11
12
13
14
15
16
n
17
INST2
SDI
MSB
LSB
DRDYB is driving the pin
SDO is driving the pin
Data Byte (s)
SDO/
DRDYB
MSB
LSB
Figure 3. Timing Diagram
Symbol
Parameter
Conditions
Min
Typical
fSCLK
Max
10
Units
MHz
tCH
SCLK High time
0.4 / fSCLK
ns
tCL
SCLK Low time
0.4 / fSCLK
ns
CSB
CSB
0.3VIO
tCSHmin
tCSSUmin
0.7VIO
SCLK
SCLK
Symbol
Parameter
Conditions
Min
0.7VIO
Typical
Max
Units
tCSSU
CSB Setup time prior to an SCLK
rising edge
5
ns
tCSH
CSB Hold time after the last rising
edge of SCLK
6
ns
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0.9VIO
0.9VIO
0.7VIO
SCLK
SCLK
0.1VIO
0.1VIO
t CLKR
t DISU
t CLKF
0.7VIO
DB
0.3VIO 0.3VIO
0.7VIO
SDI
Symbol
Parameter
t DIH
Conditions
Min
Typical
Max
Units
tCLKR
SCLK Rise time
1.15
ns
tCLKF
SCLK Fall time
1.15
ns
tDISU
SDI Setup time prior to an SCLK
rising edge
5
ns
tDIH
SDI Hold time after an SCLK rising
edge
6
ns
0.7VIO
SCLK
0.3VIO
CSB
t DOH
t DOD1
t DOA
0.9VIO
0.7VIO
0.7VIO
0.3VIO
0.3VIO
Symbol
Parameter
0.1VIO
Conditions
tDOA
SDO Access time after an SCLK
falling edge
tDOH
SDO Hold time after an SCLK
falling edge
tDOD1
SDO Disable time after the rising
edge of CSB
DB0
SDO
DB
DB
SDO
Min
Typical
Max
Units
35
ns
5
ns
5
0.7VIO
ns
SCLK
SCLK
tDOD2 (optional,
0.3 VIO
SW_OFF_TRG = 1)
t DOD2
0.9 VIO
0.9VIO
SDO
DB0
SDO
DB0
0.1 VIO
0.1VIO
Symbol
Parameter
tDOD2
SDO Disable time after either edge
of SCLK
14
Conditions
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Min
Typical
Max
Units
27
ns
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SCLK
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8
0.9VIO
0.9VIO
9
0.3VIO
SDO
tDOE
0.1VIO
0.7VIO
SDO
0.1VIO
t DOR
t DOF
DB7
0.3VIO
Symbol
Parameter
Conditions
Min
Typical
Max
Units
35
ns
tDOE
SDO Enable time from the falling
edge of the 8th SCLK
tDOR
SDO Rise time
(1)
7
tDOF
SDO Fall time
(1)
7
ns
ODR ≤ 13.42 SPS
64
µs
13.42 < ODR ≤ 214.65 SPS
4
µs
tDRDYB
Data Ready Bar pulse at every
1/ODR second, see Figure 53
ns
Specific Definitions
COMMON MODE REJECTION RATIO is a measure of how well in-phase signals common to both input pins are
rejected. To calculate CMRR, the change in output offset is measured while the common mode input voltage is
changed.
CMRR = 20 LOG(ΔCommon Input / ΔOutput Offset)
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) – says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits. LMP90100’s ENOB is a DC ENOB spec, not the dynamic ENOB that
is measured using FFT and SINAD. Its equation is as follows:
§ 2 x VREF/Gain·
ENOB = log2 ¨¨
¸¸
© RMS Noise ¹
(1)
GAIN ERROR is the deviation from the ideal slope of the transfer function.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line
through the input to output transfer function. The deviation of any given code from this straight line is measured
from the center of that code value. The end point fit method is used. INL for this product is specified over a
limited range, per the Electrical Tables.
NEGATIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output
code transitions to negative full scale and (-VREF + 1LSB).
NEGATIVE GAIN ERROR is the difference between the negative full-scale error and the offset error divided by
(VREF / Gain).
NOISE FREE RESOLUTION is a method of specifying the number of bits for a converter with noise.
§ 2 x VREF/Gain ·
NFR = log2 ¨¨
¸¸
© Peak-to-Peak Noise¹
(2)
ODR Output Data Rate.
OFFSET ERROR is the difference between the differential input voltage at which the output code transitions from
code 0000h to 0001h and 1 LSB.
POSITIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output
code transitions to positive full scale and (VREF – 1LSB).
POSITIVE GAIN ERROR is the difference between the positive full-scale error and the offset error divided by
(VREF / Gain).
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well a change in the analog supply voltage
is rejected. PSRR is calculated from the ratio of the change in offset error for a given change in supply voltage,
expressed in dB.
(1)
This parameter is specified by design and/or characterization and is not tested in production.
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PSRR = 20 LOG (ΔVA / ΔOutput Offset)
Typical Performance Characteristics
Unless otherwise noted, specified limits apply for VA = VIO = VREF = 3.0V. The maximum and minimum values apply for TA
= TMIN to TMAX; the typical values apply for TA = +25°C.
Noise Measurement with Calibration at Gain = 1
250
50
230
30
VOUT ( V)
VOUT ( V)
Noise Measurement without Calibration at Gain = 1
210
190
170
10
-10
-30
VA = 3V
VA = 3V
150
-50
0
200
400
600
TIME (ms)
800
1000
0
200
800
1000
Figure 4.
Figure 5.
Histogram without Calibration at Gain = 1
Histogram with Calibration at Gain = 1
1600
VA = 3V
1400
1400
1200
1200
1000
1000
COUNT
COUNT
1600
800
600
400
400
200
200
170
190
210
230
VA = 3V
800
600
0
150
0
-50
250
-30
VOUT (PV)
-10
10
30
50
VOUT (PV)
Figure 7.
Noise Measurement without Calibration at Gain = 8
Noise Measurement with Calibration at Gain = 8
40
20
35
15
30
10
VOUT ( V)
VOUT ( V)
Figure 6.
25
20
15
10
5
0
-5
-10
5
-15
VA = 3V
0
0
200
VA = 3V
-20
400
600
TIME (ms)
800
1000
Figure 8.
16
400
600
TIME (ms)
0
200
400
600
TIME (ms)
800
1000
Figure 9.
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Typical Performance Characteristics (continued)
Unless otherwise noted, specified limits apply for VA = VIO = VREF = 3.0V. The maximum and minimum values apply for TA
= TMIN to TMAX; the typical values apply for TA = +25°C.
Histogram without Calibration at Gain = 8
2000
Histogram with Calibration at Gain = 8
2000
VA = 3V
1500
COUNT
COUNT
1500
VA = 3V
1000
500
1000
500
0
-25
-15
-5
5
15
25
0
-25
35
-15
-5
5
15
25
35
VOUT (#V)
Figure 11.
Noise Measurement without Calibration at Gain = 128
Noise Measurement without Calibration at Gain = 128
4
4
3
3
2
2
VOUT ( V)
VOUT ( V)
VOUT (PV)
Figure 10.
1
0
-1
-2
1
0
-1
-2
-3
-3
VA = 3V
-4
0
200
VA = 3V
-4
400
600
TIME (ms)
800
1000
0
200
400
600
TIME (ms)
800
1000
Figure 12.
Figure 13.
Histogram without Calibration at Gain = 128
Histogram with Calibration at Gain = 128
3000
VA = 3V
2500
2500
2000
2000
COUNT
COUNT
3000
1500
1500
1000
1000
500
500
0
-5
-3
-1
1
3
5
VA = 3V
0
-5
-3
-1
1
VOUT (PV)
VOUT (PV)
Figure 14.
Figure 15.
3
5
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Typical Performance Characteristics (continued)
Unless otherwise noted, specified limits apply for VA = VIO = VREF = 3.0V. The maximum and minimum values apply for TA
= TMIN to TMAX; the typical values apply for TA = +25°C.
ENOB
vs.
Gain without Calibration at ODR = 13.42 SPS
ENOB
vs.
Gain with Calibration at ODR = 13.42 SPS
21
21
VA = 3V
VA = 5V
20
20
19
19
ENOB (bits)
ENOB (bits)
VA = 3V
VA = 5V
18
17
18
17
16
16
15
1
2
4
8
16
32
15
64 128
1
2
4
8
16
32
Figure 16.
Figure 17.
Noise
vs.
Gain without Calibration at ODR = 13.42 SPS
Noise
vs.
Gain with Calibration at ODR = 13.42 SPS
12
12
VA = 3V
VA = 5V
VA = 3V
VA = 5V
10
RMS NOISE (#V)
RMS NOISE (#V)
10
8
6
4
2
0
8
6
4
2
1
2
4
8
16
32
0
64 128
1
2
4
GAIN
8
16
32
64 128
GAIN
Figure 18.
Figure 19.
ENOB
vs.
Gain without Calibration at ODR = 214.65 SPS
ENOB
vs.
Gain with Calibration at ODR = 214.65 SPS
21
21
VA = 3V
VA = 5V
20
20
19
19
ENOB (bits)
ENOB (bits)
VA = 3V
VA = 5V
18
17
16
15
18
17
16
1
2
4
8
16
32
64 128
GAIN
15
1
2
4
8
16
32
64 128
GAIN
Figure 20.
18
64 128
GAIN
GAIN
Figure 21.
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Typical Performance Characteristics (continued)
Unless otherwise noted, specified limits apply for VA = VIO = VREF = 3.0V. The maximum and minimum values apply for TA
= TMIN to TMAX; the typical values apply for TA = +25°C.
Noise
vs.
Gain without Calibration at ODR = 214.65 SPS
Noise
vs.
Gain with Calibration at ODR = 214.65 SPS
12
12
VA = 3V
VA = 5V
VA = 3V
VA = 5V
10
RMS NOISE (#V)
RMS NOISE (#V)
10
8
6
4
2
8
6
4
2
0
0
1
2
4
8
16
32
64 128
1
2
4
GAIN
8
16
32
64 128
GAIN
Figure 22.
Figure 23.
Offset Error
vs.
Temperature without Calibration at Gain = 1
Offset Error
vs.
Temperature with Calibration at Gain = 1
2.0
VA = 3V
250
OFFSET VOLTAGE ( V)
OFFSET VOLTAGE ( V)
300
200
VA = 5V
150
VA = 3V
100
50
0
1.5
1.0
0.5
VA = 5V
0.0
-40 -20
0 20 40 60 80 100 120
TEMPERATURE (°C)
-40 -20
0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 24.
Figure 25.
Offset Error
vs.
Temperature without Calibration at Gain = 8
Offset Error
vs.
Temperature with Calibration at Gain = 8
0.4
20
OFFSET VOLTAGE (uV)
OFFSET VOLTAGE ( V)
25
VA = 5V
15
10
VA = 3V
5
0
0.2
VA = 3V
0.0
-0.2
VA = 5V
-0.4
-40 -20
0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 26.
-40 -20
0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 27.
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Typical Performance Characteristics (continued)
Unless otherwise noted, specified limits apply for VA = VIO = VREF = 3.0V. The maximum and minimum values apply for TA
= TMIN to TMAX; the typical values apply for TA = +25°C.
Gain Error
vs.
Temperature without Calibration at Gain = 1
Gain Error
vs.
Temperature with Calibration at Gain = 1
40
160
VA = 5V
GAIN ERROR (ppm)
GAIN ERROR (ppm)
150
140
130
VA = 3V
120
20
VA = 5V
0
-20
VA = 3V
110
-40
-40 -20
0 20 40 60 80 100 120
TEMPERATURE (°C)
-40 -20
Figure 28.
Figure 29.
Gain Error
vs.
Temperature without Calibration at Gain = 8
Gain Error
vs.
Temperature with Calibration at Gain = 8
-100
-20
-120
VA = 3V
-130
-140
VA = 5V
-60
-80
VA = 5V
-100
-150
-160
-120
-40 -20
0 20 40 60 80 100 120
TEMPERATURE (°C)
-40 -20
0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 30.
Figure 31.
Digital Filter Frequency Response
Digital Filter Frequency Response
0
0
-20
-20
-40
-40
GAIN (dB)
GAIN (dB)
VA = 3V
-40
GAIN ERROR (ppm)
GAIN ERROR (ppm)
-110
-60
-80
-60
-80
1.7 SPS
3.4 SPS
6.7 SPS
13.4 SPS
-100
-100
-120
26.83 SPS
53.66 SPS
107.33 SPS
214.65 SPS
-120
1
10
FREQUENCY (Hz)
100
Figure 32.
20
0 20 40 60 80 100 120
TEMPERATURE (°C)
10
100
FREQUENCY (Hz)
1k
Figure 33.
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Typical Performance Characteristics (continued)
Unless otherwise noted, specified limits apply for VA = VIO = VREF = 3.0V. The maximum and minimum values apply for TA
= TMIN to TMAX; the typical values apply for TA = +25°C.
INL at Gain = 1
INL (ppm of FSR)
10
5
0
-5
VA = 5V, 13.4 SPS
-10
-5 -4 -3 -2 -1 0 1
VIN (V)
2
3
4
5
Figure 34.
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FUNCTIONAL DESCRIPTION
Throughout this datasheet, the LMP90100/LMP90099/LMP90098/LMP90097 will be referred to as the
LMP90xxx.
The LMP90xxx is a low-power 24-Bit ΣΔ ADC with 4 fully differential / 7 single-ended analog channels for the
LMP90100/LMP90099 and 2 full differential / 4 single-ended for the LMP90098/LMP90097. Its serial data output
is two’s complement format. The output data rate (ODR) ranges from 1.6775 SPS to 214.65 SPS.
The serial communication for LMP90xxx is SPI, a synchronous serial interface that operates using 4 pins: chip
select bar (CSB), serial clock (SCLK), serial data in (SDI), and serial data out / data ready bar (SDO/DRYDYB).
True continuous built-in offset and gain background calibration is also available to improve measurement
accuracy. Unlike other ADCs, the LMP90xxx’s background calibration can run without heavily impacting the input
signal. This unique technique allows for positive as well as negative gain calibration and is available at all gain
settings.
The registers can be found in Registers, and a detailed description of the LMP90xxx are provided in the following
sections.
SIGNAL PATH
Reference Input (VREF)
The differential reference voltage VREF (VREFP – VREFN) sets the range for VIN.
The muxed VREF allows the user to choose between VREF1 or VREF2 for each channel. This selection can be
made by programming the VREF_SEL bit in the CHx_INPUTCN registers (CHx_INPUTCN: VREF_SEL). The
default mode is VREF1. If VREF2 is used, then VIN6 and VIN7 cannot be used as inputs because they share the
same pin.
Refer to VREF for VREF applications information.
Flexible Input MUX (VIN)
LMP90xxx provides a flexible input MUX as shown in Figure 35. The input that is digitized is VIN = VINP – VINN;
where VINP and VINN can be any availablie input.
The digitized input is also known as a channel, where CH = VIN = VINP – VINN. Thus, there are a maximum of 4
differential channels: CH0, CH1, CH2, and CH3 for the LMP90100/LMP90099. The LMP90098/LMP90097 has a
maximum of 2 differential channels: CH0 and CH1 because it does not have access to the VIN3, VIN4, and VIN5
pins.
LMP90xxx can also be configured single-endedly, where the common ground is any one of the inputs. There are
a maximum of 7 single-ended channels: CH0, CH1, CH2, CH3, CH4, CH5, and CH6 for the
LMP90100/LMP90099 and 4: CH0, CH1, CH2, CH3 for the LMP90098/LMP90097.
The input MUX can be programmed in the CHx_INPUTCN registers. For example on the LMP90100, to program
CH0 = VIN = VIN4 – VIN1, go to the CH0_INPUTCN register and set:
1. VINP = 0x4
2. VINN = 0x1
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VREFP1
VIN0
VIN1
VIN2
VIN3*
VINP
+
+
-
ADC
BUFF
FGA
VINN
+
-
-
VIN4*
VIN5*
VIN6/VREFP2
VIN7/VREFN2
VREFN1
* VIN3, VIN4, VIN5 are only available for LMP90100 and LMP90099
Figure 35. Simplified VIN Circuitry
Selectable Gains (FGA & PGA)
LMP90xxx provides two types of gain amplifiers: a fixed gain amplifier (FGA) and a programmable gain amplifier
(PGA). FGA has a fixed gain of 16x or it can be bypassed, while the PGA has programmable gain settings of 1x,
2x, 4x, or 8x.
Total gain is defined as FGA x PGA. Thus, LMP90xxx provides gain settings of 1x, 2x, 4x, 8x, 16x, 32x, 64x, or
128x with true continuous background calibration.
The gain is channel specific, which means that one channel can have one gain, while another channel can have
the same or a different gain.
The gain can be selected by programming the CHx_CONFIG: GAIN_SEL bits.
Buffer (BUFF)
There is an internal unity gain buffer that can be included or excluded from the signal path. Including the buffer
provides a high input impedance but increases the power consumption.
When gain ≥ 16, the buffer is automatically included in the signal path. When gain < 16, including or excluding
the buffer from the signal path can be done by programming the CHX_CONFIG: BUF_EN bit.
Internal/External CLK Selection
LMP90xxx allows two clock options: internal CLK or external CLK (crystal (XTAL) or clock source).
There is an “External Clock Detection” mode, which detects the external XTAL if it is connected to XOUT and
XIN. When operating in this mode, the LMP90xxx shuts off the internal clock to reduce power consumption.
Below is a flow chart to help set the appropriate clock registers.
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Clock
Options
Internal CLK
External CLK Source
External
XTAL
LMP90100 will use the
internal clock
No
Is there a XTAL
connected to XIN and
XOUT?
Connect a XTAL
to XIN and XOUT
Connect an external
CLK source to the
XIN/CLK pin
LMP90100 will
automatically detect
and use the XTAL if
CLK_EXT_DET = 0
(default)
LMP90100 will
automatically use the
external CLK source
Yes
Set CLK_EXT_DET = 1 to
E\SDVV WKH ³([WHUQDO-Clock
'HWHFWLRQ´ PRGH
Set CLK_SEL = 0 to select
the internal clock
Figure 36. CLK Register Settings
The recommended value for the external CLK is discussed in the next sections.
Programmable ODRs
If using the internal CLK or external CLK of 3.5717 MHz, then the output date rates (ODR) can be selected
(using the ODR_SEL bit) as:
1. 13.42/8 = 1.6775 SPS
2. 13.42/4 = 3.355 SPS
3. 13.42/2 = 6.71SPS
4. 13.42 SPS
5. 214.65/8 = 26.83125 SPS
6. 214.65/4 = 53.6625 SPS
7. 214.65/2 = 107.325 SPS
8. 214.65 SPS (default)
If the internal CLK is not being used and the external CLK is not 3.5717 MHz, then the ODR will be different. If
this is the case, use the equation below to calculate the new ODR values.
ODR_Base1 = (CLKEXT) / (266,240)
ODR_Base2 = (CLKEXT) / (16,640)
ODR1 = (ODR_Base1) / n, where n = 1,2,4,8
ODR2 = (ODR_Base2) / n, where n = 1,2,4,8
(3)
(4)
(5)
(6)
For example, a 3.6864 MHz XTAL or external clock has the following ODR values:
ODR_Base1 = (3.6864 MHz) / (266,240) = 13.85 SPS
ODR_Base2 = (3.6864 MHz) / (16,640) = 221.54 SPS
ODR1 = (13.85 SPS) / n = 13.85, 6.92, 3.46, 1.73 SPS
ODR2 = (221.54 SPS) / n = 221.54, 110.77, 55.38, 27.69 SPS
(7)
(8)
(9)
(10)
The ODR is channel specific, which means that one channel can have one ODR, while another channel can
have the same or a different ODR.
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Note that these ODRs are meant for a single channel conversion; the ODR needs to be divided by n for n
channels scanning. For example, if the ADC were running at 214.65 SPS and four channels are being scanned,
then the ODR per channel would be 214.65/4 = 53.6625 SPS.
Digital Filter
The LMP90xxx has a fourth order rotated sinc filter that is used to configure various ODRs and to reject power
supply frequencies of 50Hz and 60Hz. The 50/60 Hz rejection is only effective when the device is operating at
ODR ≤ 13.42 SPS. If the internal CLK or the external CLK of 3.5717 MHz is used, then the LMP90xxx will have
the frequency response shown in Figure 37 to Figure 41.
0
1.6775 SPS
3.355 SPS
-20
GAIN (dB)
-40
-60
-80
-100
-120
0
12
24
36
48
60
72
84
96
108
120
FREQUENCY (Hz)
Figure 37. Digital Filter Response, 1.6775 SPS and 3.355 SPS
0
6.71 SPS
13.42 SPS
-20
GAIN (dB)
-40
-60
-80
-100
-120
0
12
24
36
48
60
72
84
96
108
120
FREQUENCY (Hz)
Figure 38. Digital Filter Response, 6.71 SPS and 13.42 SPS
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13.42 SPS
-70
GAIN (dB)
-80
-90
-100
-110
-120
45
47
49
51
53
55
57
59
61
63
65
1800
2000
FREQUENCY (Hz)
Figure 39. Digital Filter Response at 13.42 SPS
0
26.83125 SPS
53.6625 SPS
GAIN (dB)
-40
-80
-120
0
200
400
600
800
1000
1200
1400
1600
FREQUENCY (Hz)
Figure 40. Digital Filter Response, 26.83125 SPS and 53.6625 SPS
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0
107.325 SPS
214.65 SPS
GAIN (dB)
-40
-80
-120
0
200
400
600
800
1000
1200
1400
1600
1800
2000
FREQUENCY (Hz)
Figure 41. Digital Filter Response 107.325 SPS and 214.65 SPS
If the internal CLK is not being used and the external CLK is not 3.5717 MHz, then the filter response would be
the same as the response shown above, but the frequency will change according to the equation:
fNEW = [(CLKEXT) / 256 ] x (fOLD / 13.952k)
(11)
Using the equation above, an example of the filter response for a 3.5717 MHz XTAL versus a 3.6864 MHz XTAL
can be seen in Figure 42.
0
Crystal = 3.5717 MHz
Crystal = 3.6864 MHz
-20
GAIN (dB)
-40
-60
-80
-100
-120
-140
40
45
50
55
60
FREQUENCY (Hz)
65
70
Figure 42. Digital Filter Response for a 3.5717MHz versus 3.6864 MHz XTAL
GPIO (D0–D6)
Pins D0-D6 are general purpose input/output (GPIO) pins that can be used to control external LEDs or switches.
Only a high or low value can be sourced to or read from each pin.
Figure 43 shows a flowchart how these GPIOs can be programmed.
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inputs
outputs
Pins
D0 ± D6 =
Set
GPIO_DIRCNx = 0
Set
GPIO_DIRCNx = 1
Read the
GPIO_DAT: Dx bit to
determine if Dx is
high or low, where
0 ” [ ” 6.
Write to GPIO_DAT: Dx bit
to drive Dx high or low,
where 0 ” [ ” 6.
Figure 43. GPIO Register Settings
CALIBRATION
As seen in Figure 44, there are two types of calibration: background calibration and system calibration. These
calibrations are further described in the next sections.
Calibration
Background
calibration
Correction
System
calibration
Estimation
Offset
Gain
Figure 44. Types of Calibration
Background Calibration
Background calibration is the process of continuously determining and applying the offset and gain calibration
coefficients to the output codes to minimize the LMP90xxx’s offset and gain errors. Background calibration is a
feature built into the LMP90xxx and is automatically done by the hardware without interrupting the input signal.
Four differential channels, CH0-CH3, each with its own gain and ODRs, can be calibrated to improve the
accuracy.
Types of Background Calibration:
Figure 44 also shows that there are two types of background calibration:
1. Type 1: Correction - the process of continuously determining and applying the offset and gain calibration
coefficients to the output codes to minimize the LMP90xxx’s offset and gain errors.
– This method keeps track of changes in the LMP90xxx's gain and offset errors due to changes in the
operating condition such as voltage, temperature, or time.
2. Type 2: Estimation - the process of determining and continuously applying the last known offset and gain
calibration coefficients to the output codes to minimize the LMP90xxx’s offset and gain errors.
– The last known offset or gain calibration coefficients can come from two sources. The first source is the
default coefficient which is pre-determined and burnt in the device’s non-volatile memory. The second
source is from a previous calibration run of Type 1: Correction.
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The benefits of using type 2 calibration is a higher throughput, lower power consumption, and slightly better
noise. The exact savings would depend on the number of channels being scanned, and the ODR and gain of
each channel.
Using Background Calibration:
There are four modes of background calibration, which can be programmed using the BGCALCN bits. They are
as follows:
1. BgcalMode0: Background Calibration OFF
2. BgcalMode1: Offset Correction / Gain Estimation
3. BgcalMode2: Offset Correction / Gain Correction
– Follow Figure 45 to set other appropriate registers when using this mode.
4. BgcalMode3: Offset Estimation / Gain Estimation
Is the channel
JDLQ • 16x?
No
Set
BGCALCN = 10b to
operate the device in
BgcalMode2
Yes
Set CH_SCAN_SEL = 10b to
operate the device in
ScanMode2. Set FIRST_CH &
LAST_CH accordingly.
Correct FGA
error?
No
Set
FGA_BGCAL = 1 to
correct for FGA error
using the last known
coefficients.
Yes
Set FGA_BGCAL = 0 (default)
Figure 45. BgcalMode2 Register Settings
If operating in BgcalMode2, four channels (with the same ODR) are being converted, and FGA_BGCAL = 0
(default), then the ODR is reduced by:
1. 0.19% of 1.6775 SPS
2. 0.39% of 3.355 SPS
3. 0.78% of 6.71 SPS
4. 1.54% of 13.42 SPS
5. 3.03% of 26.83125 SPS
6. 5.88% of 53.6625 SPS
7. 11.11% of 107.325 SPS
8. 20% of 214.65 SPS
System Calibration
The LMP90xxx provides some unique features to support easy system offset and system gain calibrations.
The System Calibration Offset Registers (CHx_SCAL_OFFSET) hold the System Calibration Offset Coefficients
in 24-bit, two's complement binary format. The System Calibration Gain Registers (CHx_SCAL_GAIN) hold the
System Calibration Gain Coefficient in 24-bit, 1.23, unsigned, fixed-point binary format. For each channel, the
System Calibration Offset coefficient is subtracted from the conversion result prior to the division by the System
Calibration Gain Coefficient.
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A data-flow diagram of these coefficients can be seen in Figure 46.
Uncalibrated
VIN
±
OFFSET
[CHx_SCAL_
OFFSET]
y
Calibrated
ADC_DOUT
GAIN
[CHx_SCAL_
GAIN]
Figure 46. System Calibration Data-Flow Diagram
There are four distinct sets of System Calibration Offset and System Calibration Gain Registers for use with
CH0-CH3. CH4-CH6 reuse the registers of CH0-CH2, respectively.
The LMP90xxx provides two system calibration modes that automatically fill the Offset and Gain coefficients for
each channel. These modes are the System Calibration Offset Coefficient Determination mode and the System
Calibration Gain Coefficient Determination mode. The System Calibration Offset Coefficient Determination mode
must be entered prior to the System Calibration Gain Coefficient Determination mode, for each channel.
The system zero-scale condition is a system input condition (sensor loading) for which zero (0x00_0000) systemcalibrated output code is desired. It may not, however, cause a zero input voltage at the input of the ADC.
The system reference-scale condition is usually the system full-scale condition in which the system's input (or
sensor's loading) would be full-scale and the desired system-calibrated output code would be 0x80_0000
(unsigned 24-bit binary). However, system full-scale condition need not cause full-scale input voltage at the input
of the ADC.
The system reference-scale condition is not restricted to just the system full-scale condition. In fact, it can be any
arbitrary fraction of full-scale (up to 1.25 times) and the desired system-calibrated output code can be any
appropriate value (up to 0xA00000). The CHx_SCAL_GAIN register must be written with the desired systemcalibrated output code (default:0x800000) before entering the System Calibration Gain Coefficient Determination
mode. This helps in in-place system calibration.
Below are the detailed procedures for using the System Calibration Offset Coefficient Determination and System
Calibration Gain Coefficient Determination modes.
System Calibration Offset Coefficient Determination mode
1. Apply system zero-scale condition to the channel (CH0/CH1/CH2/CH3).
2. Enter the System Calibration Offset Coefficient Determination mode by programming 0x1 in the SCALCN
register.
3. LMP90xxx starts a fresh conversion at the selected output data rate for the selected channel. At the end of
the conversion, the CHx_SCAL_OFFSET register is filled-in with the System Calibration Offset coefficient.
4. The System Calibration Offset Coefficient Determination mode is automatically exited.
5. The computed calibration coefficient is accurate only to the effective resolution of the device and will
probably contain some noise. The noise factor can be minimized by computing over many times, averaging
(externally) and putting the resultant value back into the register. Alternatively, select the output data rate to
be 26.83 sps or 1.67 sps.
System Calibration Gain Coefficient Determination mode
1. Repeat the System Calibration Offset Coefficient Determination mode to calibrate for the channel's system
offset.
2. Apply the system reference-scale condition to the channel CH0/CH1/CH2/CH3.
3. In the CHx_SCAL_GAIN Register, program the expected (desired) system-calibrated output code for this
condition in 24-bit unsigned format.
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4. Enter the System Calibration Gain Coefficient Determination mode by programming 0x3 in the SCALCN
register.
5. LMP90xxx starts a fresh conversion at the selected output data rate for the channel. At the end of the
conversion, the CHx_SCAL_GAIN is filled-in (or overwritten) with the System Calibration Gain coefficient.
6. The System Calibration Gain Coefficient Determination mode is automatically exited.
7. The computed calibration coefficient is accurate only to the effective resolution of the device and will
probably contain some noise. The noise factor can be minimized by computing over many times, averaging
(externally) and putting the resultant value back into the register. Alternatively, select the output data rate to
be 26.83 sps or 1.67 sps.
Post-calibration Scaling
LMP90xxx allows scaling (multiplication and shifting) for the System Calibrated result. This eases downstream
processing, if any. Multiplication is done using the System Calibration Scaling Coefficient in the
CHx_SCAL_SCALING register and shifting is done using the System Calibration Bits Selector in the
CHx_SCAL_BITS_SELECTOR register.
The System Calibration Bits Selector value should ideally be the logarithm (to the base 2) of the System
Calibration Scaling Coefficient value.
There are four distinct sets of System Calibration Scaling and System Calibration Bits Selector Registers for use
with Channels 0-3. Channels 4-6 reuse the registers of Channels 0-2, respectively.
A data-flow diagram of these coefficients can be seen in Figure 47
1/ODR
D6 = drdyb
1/ODR
ADC
Data
1
ADC
Data
2
Valid
ADC_DOUT
(ADC Data 2)
Valid
ADC_DOUT
(ADC Data 1)
MSB
SDO
LSB
LSB
MSB
Figure 47. Post-calibration Scaling Data-Flow Diagram
CHANNELS SCAN MODE
There are four scan modes. These scan modes are selected using the CH_SCAN: CH_SCAN_SEL bit. The first
scanned channel is FIRST_CH, and the last scanned channel is LAST_CH; they are both located in the
CH_SCAN register.
The CH_SCAN register is double buffered. That is, user inputs are stored in a slave buffer until the start of the
next conversion during which time they are transferred to the master buffer. Once the slave buffer is written,
subsequent updates are disregarded until a transfer to the master buffer happens. Hence, it may be appropriate
to check the CH_SCAN_NRDY bit before programming the CH_SCAN register.
ScanMode0: Single-Channel Continuous Conversion
LMP90xxx continuously converts the selected FIRST_CH.
Do not operate in this scan mode if gain ≥ 16 and the LMP90xxx is running in background calibration modes
BgcalMode1 or BgcalMode2. If this is the case, then it is more suitable to operate the device in ScanMode2
instead.
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ScanMode1: Multiple-Channels Single Scan
LMP90xxx converts one or more channels starting from FIRST_CH to LAST_CH, and then enters the stand-by
state.
ScanMode2: Multiple-Channels Continuous Scan
LMP90xxx continuously converts one or more channels starting from FIRST_CH to LAST_CH, and then it
repeats this process.
ScanMode3: Multiple-Channels Continuous Scan with Burnout Currents
This mode is the same as ScanMode2 except that the burnout current is provided in a serially scanned fashion
(injected in a channel after it has undergone a conversion). Thus it avoids burnout current injection from
interfering with the conversion result for the channel.
The sensor diagnostic burnout currents are available for all four scan modes. The burnout current is further gated
by the BURNOUT_EN bit for each channel. ScanMode3 is the only mode that scans multiple channels while
injecting burnout currents without interfering with the signal. This is described in details in Burnout Currents.
SENSOR INTERFACE
LMP90100/LMP90098 contain two types of current sources: excitation currents (IB1 & IB2) and burnout currents.
They are described in the next sections.
IB1 & IB2 - Excitation Currents
IB1 and IB2 can be used for providing currents to external sensors, such as RTDs or bridge sensors. 100µA to
1000µA, in steps of 100µA, can be sourced by programming the ADC_AUXCN: RTD_CUR_SEL bits.
Refer to 3–Wire RTD to see how IB1 and IB2 can be used to source a 3-wire RTD.
Burnout Currents
As shown in Figure 48, the LMP90xxx contains two internal 10 µA burnout current sources, one sourcing current
from VA to VINP, and the other sinking current from VINN to ground. These currents are used for sensor
diagnostics and can be enabled for each channel using the CHx_INPUTCN: BURNOUT_EN bit.
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Burnout
Current = 10 PA
VIN0
VIN1
VIN2
VIN3*
VINP
VINN
VIN4*
VIN5*
VIN6/VREFP2
VIN7/VREFN2
Burnout
Current = 10 PA
* VIN3, VIN4, VIN5 are only available for LMP90100 and LMP90099
Figure 48. Burnout Currents
Burnout Current Injection:
Burnout currents are injected differently depending on the channel scan mode selected.
When BURNOUT_EN = 1 and the device is operating in ScanMode0, 1, or 2, the burnout currents are injected
into all the channels for which the BURNOUT_EN bit is selected. This will cause problems and hence in this
mode, more than one channel should not have its BURNOUT_EN bit selected. Also, the burnout current will
interfere with the signal and introduce a fixed error depending on the particular external sensor.
When BURNOUT_EN = 1 and the device is operating in ScanMode3, burnout currents are injected into the last
sampled channel on a cyclical basis (Figure 49). In this mode, burnout currents injection is truly done in the
background without affecting the accuracy of the on-going conversion. Operating in this mode is recommended.
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Burnout Currents
BURNOUT_EN
CH0 is being sampled
CH0
CH1
CH2
CH3
BURNOUT_EN
CH1 is being sampled
CH0
CH1
CH2
CH3
BURNOUT_EN
CH2 is being sampled
CH0
CH1
CH2
CH3
BURNOUT_EN
CH3 is being sampled
CH0
CH1
CH2
CH3
Figure 49. Burnout Currents Injection for ScanMode3
Sensor Diagnostic Flags
Burnout currents can be used to verify that an external sensor is still operational before attempting to make
measurements on that channel. A non-operational sensor means that there is a possibility the connection
between the sensor and the LMP90xxx is open circuited, short circuited, shorted to VA or GND, overloaded, or
the reference may be absent. The sensor diagnostic flags diagram can be seen in Figure 50.
RAILS_FLAG
Generator
RAILS_FLAG
Overflow detection
OFLO_FLAGS
VINP
FGA
VINN
BUFF
Modulator
Filter
RAILS_FLAG
Generator
ADC_DOUT
RAILS_FLAG
SENDIAG_THLDH
and SENDIAG_THLDL
SHORT_THLD_
FLAG
Figure 50. Sensor Diagnostic Flags Diagram
The sensor diagnostic flags are located in the SENDIAG_FLAGS register and are described in further details
below.
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SHORT_THLD_FLAG:
The short circuit threshold flag is used to report a short-circuit condition. It is set when the output voltage (VOUT)
is within the absolute Vthreshold. Vthreshold can be programmed using the 8-bit SENDIAG_THLDH register
concatenated with the 8-bit SENDIAG_THLDL register.
For example, assume VREF = 5V, gain = 1, SENDIAG_THLDH = 0xFA, and SENDIAG_THLDL = 0x45. In this
case, Dthreshold = 0xFA45 = 64069d, and Vthreshold can be calculated as:
Vthreshold = [(Dthreshold)(2)(VREF)] / [(Gain)(224)]
Vthreshold = [(64069)(2)(5V)] / [(1)(224)]
Vthreshold = 38.2 mV
(12)
(13)
(14)
When (-38.2mV) ≤ VOUT ≤ (38.2mV), then SHORT_THLD_FLAG = 1; otherwise, SHORT_THLD_FLAG = 0.
RAILS_FLAG:
The rails flag is used to detect if one of the sampled channels is within 50mV of the rails potential (VA or VSS).
This can be further investigated to detect an open-circuit or short-circuit condition. If the sampled channel is near
a rail, then RAILS_FLAG = 1; otherwise, RAILS_FLAG = 0.
POR_AFT_LST_RD:
If POR_AFT_LST_READ = 1, then there was a power-on reset since the last time the SENDIAG_FLAGS register
was read. This flag's status is cleared when this bit is read, unless this bit is set again on account of another
power-on-reset event in the intervening period.
OFLO_FLAGS:
OFLO_FLAGS is used to indicate whether the modulator is over-ranged or under-ranged. The following
conditions are possible:
1. OFLO_FLAGS = 0x0: Normal Operation
2. OFLO_FLAGS = 0x1: The differential input is more than (±VREF/Gain) but is not more than
±(1.3*VREF/Gain) to cause a modulator over-range.
3. OFLO_FLAGS = 0x2: The modulator was over-ranged towards +VREF/Gain.
4. OFLO_FLAGS = 0x3: The modulator was over-ranged towards −VREF/Gain.
The condition of OFLO_FLAGS = 10b or 11b can be used in conjunction with the RAILS_FLAG to determine the
fault condition.
SAMPLED_CH:
These three bits show the channel number for which the ADC_DOUT and SENDIAG_FLAGS are available. This
does not necessarily indicate the current channel under conversion because the conversion frame and
computation of results from the channels are pipelined. That is, while the conversion is going on for a particular
channel, the results for the previous conversion (of the same or a different channel) are available.
SERIAL DIGITAL INTERFACE
A synchronous 4-wire serial peripheral interface (SPI) provides access to the internal registers of LMP90xxx via
CSB, SCLK, SDI, SDO/DRDYB.
Register Address (ADDR)
All registers are memory-mapped. A register address (ADDR) is composed of an upper register address (URA)
and lower register address (LRA) as shown in Table 6. For example, ADDR 0x3A has URA=0x3 and LRA=0xA.
Table 6. ADDR Map
Bit
[6:4]
[3:0]
Name
URA
LRA
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Register Read/Write Protocol
Figure 51 shows the protocol how to write to or read from a register.
Transaction 1 sets up the upper register address (URA) where the user wants to start the register-write or
register-read.
Transaction 2 sets the lower register address (LRA) and includes the Data Byte(s), which contains the incoming
data from the master or outgoing data from the LMP90xxx.
Examples of register-reads or register-writes can be found in REGISTER READ/WRITE EXAMPLES.
Transaction 1 ± URA Setup ± necessary only when the previous URA is different than the desired URA.
Upper Address Byte (UAB)
Instruction Byte 1 (INST1)
[7:0]
[7:3]
[2:0]
RA/WAB
0x0
Upper Register
Address (URA)
R/WB = Read/Write Address
0x10: Write Address
0x90: Read Address
Transaction 2 ± Data Access
Instruction Byte 2 (INST2)
Data Byte (s)
7
[6:5]
4
[3:0]
[N:0]
R/WB
SZ
0
Lower Register
Address (LRA)
Data Byte (s)
R/WB = Read/Write Data
0: Write Data
1: Read Data
SZ = Size
0x0: 1 byte
0x1: 2 bytes
0x2: 3 bytes
0x3: Streaming ± 3+ bytes until CSB is de-asserted
Figure 51. Register Read/Write Protocol
Streaming
When writing/reading 3+ bytes, the user must operate the device in Normal Streaming mode or Controlled
Streaming mode. In the Normal Streaming mode, which is the default mode, data runs continuously starting from
ADDR until CSB deasserts. This mode is especially useful when programming all the configuration registers in a
single transaction. See Normal Streaming Example for an example of the Normal Streaming mode.
In the Controlled Streaming mode, data runs continuously starting from ADDR until the data has run through all
(STRM_RANGE + 1) registers. For example, if the starting ADDR is 0x1C, STRM_RANGE = 5, then data will be
written to or read from the following ADDRs: 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21. Once the data reaches ADDR
0x21, LMP90xxx will wrap back to ADDR 0x1C and repeat this process until CSB deasserts. See Controlled
Streaming Example for an example of the Controlled Streaming mode.
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If streaming reaches ADDR 0x7F, then it will wrap back to ADDR 0x00. Furthermore, reading back the Upper
Register Address after streaming will report the Upper Register Address at the start of streaming, not the Upper
Register Address at the end of streaming.
To stream, write 0x3 to INST2’s SZ bits as seen in Figure 51. To select the stream type, program the
SPI_STREAMCN: STRM_TYPE bit. The STRM_RANGE can also be programmed in the same register.
CSB - Chip Select Bar
An SPI transaction begins when the master asserts (active low) CSB and ends when the master deasserts
(active high) CSB. Each transaction might be separated by a subsequent one with a CSB deassertion, but this is
optional. Once CSB is asserted, it must not pulse (deassert and assert again) during a (desired) transaction.
CSB can be grounded in systems where LMP90xxx is the only SPI slave. This frees the software from handling
the CSB. Care has to be taken to avoid any false edge on SCLK, and while operating in this mode, the streaming
transaction should not be used because exiting from this mode can only be done through a CSB deassertion.
SPI Reset
SPI Reset resets the SPI-Protocol State Machine by monitoring the SDI for at least 73 consecutive 1's at each
SCLK rising edge. After an SPI Reset, SDI is monitored for a possible Write Instruction at each SCLK rising
edge.
SPI Reset will reset the Upper Address Register (URA) to 0, but the register contents are not reset.
By default, SPI reset is disabled, but it can be enabled by writing 0x01 to SPI Reset Register (ADDR 0x02).
DRDYB - Data Ready Bar
DRDYB is a signal generated by the LMP90xxx that indicates a fresh conversion data is available in the
ADC_DOUT registers.
DRDYB is automatically asserted every (1/ODR) second and deasserts when ADC_DOUT is completely read out
(LSB of ADC_DOUTL) (Figure 52).
1/ODR
DRDYB:
SDO:
...
...
LSB
LSB
Figure 52. DRDYB Behavior for a Complete ADC_DOUT Reading
If ADC_DOUT is not completely read out (Figure 53) or is not read out at all, but a new ADC_DOUT is available,
then DRDYB will automatically pulse for tDRDYB second. The value for tDRDYB can be found in Timing Diagrams.
1/ODR
DRDYB:
tDRDYB
SDO:
Figure 53. DRDYB Behavior for an ADC_DOUT not Read
If ADC_DOUT is being read, while the new ADC_DOUT becomes available, then the ADC_DOUT that is being
read is still valid (Figure 54). DRDYB will be deasserted at the LSB of the data being read, but a consecutive
read on the ADC_DOUT register will fetch the newly converted data available.
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1/ODR
D6 = drdyb
1/ODR
ADC
Data
1
ADC
Data
2
Valid
ADC_DOUT
(ADC Data 2)
Valid
ADC_DOUT
(ADC Data 1)
LSB
MSB
SDO
MSB
LSB
Figure 54. DRDYB Behavior for an Incomplete ADC_DOUT Reading
DRDYB can also be accessed via registers using the DT_AVAIL_B bit. This bit indicates when fresh conversion
data is available in the ADC_DOUT registers. If new conversion data is available, then DT_AVAIL_B = 0;
otherwise, DT_AVAIL_B = 1.
As opposed to the drdyb signal, a complete reading for DT_AVAIL_B occurs when the MSB of ADC_DOUTH is
read out. This bit cannot be reset even if REG_AND_CNV_RST = 0xC3.
DrdybCase1: Combining SDO/DRDYB with SDO_DRDYB_DRIVER = 0x00
LMP90100
uC
SCLK
SCLK
CSB
CSB
SDI
MOSI
SDO/
DRDYB
MISO
INT
Figure 55. DrdybCase1 Connection Diagram
As shown in Figure 55, the drdyb signal and SDO can be multiplexed on the same pin as their functions are
mostly complementary. In fact, this is the default mode for the SDO/DRDYB pin.
Figure 56 shows a timing protocol for DrdybCase1. In this case, start by asserting CSB first to monitor a drdyb
assertion. When the drdyb signal asserts, begin writing the Instruction Bytes (INST1, UAB, INST2) to read from
or write to registers. Note that INST1 and UAB are omitted from the figure below because this transaction is only
required if a new UAB needs to be implemented.
While the CSB is asserted, DRDYB is driving the SDO/DRDYB pin unless the device is reading data, in which
case, SDO will be driving the pin. If CSB is deasserted, then the SDO/DRDYB pin is High-Z.
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CSB
tCH
SCLK
1
2
3
1/fSCLK
tCL
4
5
6
7
8
9
10
11
12
13
14
15
16
n
17
INST2
SDI
MSB
LSB
DRDYB is driving the pin
SDO is driving the pin
Data Byte (s)
SDO/
DRDYB
MSB
LSB
Figure 56. Timing Protocol for DrdybCase1
DrdybCase2: Combining SDO/DRDYB with SDO_DRDYB_DRIVER = 0x03
SDO/DRDYB can be made independent of CSB by setting SDO_DRDYB_DRIVER = 0x03 in the SPI Handshake
Control register. In this case, DRDYB will drive the pin unless the device is reading data, independent of the
state of CSB. SDO will drive the pin when CSB is asserted and the device is reading data.
With this scheme, one can use SDO/DRDYB as a true interrupt source, independent of the state of CSB. But this
scheme can only be used when the LMP900xx is the only device connected to the master's SPI bus because the
SDO/DRDYB pin will be DRDYB even when CSB is deasserted.
The timing protocol for this case can be seen in Figure 57. When drdyb asserts, assert CSB to start the SPI
transaction and begin writing the Instruction Bytes (INST1, UAB, INST2) to read from or write to registers.
CSB
tCH
SCLK
1
1/fSCLK
tCL
4
5
6
7
8
9
10
11
12
13
14
15
16
n
17
INST2
SDI
MSB
LSB
DRDYB is driving the pin
SDO is driving the pin
Data Byte (s)
SDO/
DRDYB
MSB
LSB
Figure 57. Timing Protocol for DrdybCase2
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DrdybCase3: Routing DRDYB to D6
LMP90100
uC
SCLK
SCLK
CSB
CSB
SDI
MOSI
SDO
MISO
Interrupt
D6 = DRDYB
Figure 58. DrdybCase3 Connection Diagram
The drdyb signal can be routed to pin D6 by setting SPI_DRDYB_D6 high and SDO_DRDYB_DRIVER to 0x4.
This is the behavior for DrdybCase3 as shown in Figure 58.
The timing protocol for this case can be seen in Figure 59. Since DRDYB is separated from SDO, it can be
monitored using the interrupt or polling method. If polled, the drdyb signal needs to be polled faster than tDRDYB to
detect a drdyb assertion. When drdyb asserts, assert CSB to start the SPI transaction and begin writing the
Instruction Bytes (INST1, UAB, INST2) to read from or write to registers.
CSB
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
n
INST2
SDI
MSB
LSB
Drdyb = D6
Data Byte (s)
SDO
High-Z
MSB
LSB
Figure 59. Timing Protocol for DrdybCase3
Data Only Read Transaction
In a data only read transaction, one can directly access the data byte(s) as soon as the CSB is asserted without
having to send any instruction byte. This is useful as it brings down the latency as well as the overhead
associated with the instruction byte (as well as the Upper Address Byte, if any).
In order to use the data only transaction, the device must be placed in the data first mode. The following table
lists transaction formats for placing the device in and out of the data first mode and reading the mode status.
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Table 7. Data First Mode Transactions
Bit[7]
Bits[6:5]
Bit[4]
Bits[3:0]
Data Bytes
Enable Data First
Mode Instruction
1
11
1
1010
None
Disable Data First
Mode Instruction
1
11
1
1011
None
Read Mode Status
Transaction
1
00
1
1111
One
Note that while being in the data first mode, once the data bytes in the data only read transaction are sent out,
the device is ready to start on any normal (non-data-only) transaction including the Disable Data First Mode
Instruction. The current status of the data first mode (enabled/disabled status) can be read back using the Read
Mode Status Transaction. This transaction consists of the Read Mode Status Instruction followed by a single
data byte (driven by the device). The data first mode status is available on bit [1] of this data byte.
The data only read transaction allows reading up to eight consecutive registers, starting from any start address.
Usually, the start address will be the address of the most significant byte of conversion data, but it could just as
well be any other address. The start address and number of bytes to be read during the data only read
transaction can be programmed using the DATA_ONLY_1 AND DATA_ONLY_2 registers respectively.
The upper register address is unaffected by a data only read transaction. That is, it retains its setting even after
encountering a data only transaction. The data only transaction uses its own address (including the upper
address) from the DATA_ONLY_1 register. When in the data first mode, the SCLK must stop high before
entering the Data Only Read Transaction; this transaction should be completed before the next scheduled
DRDYB deassertion.
Cyclic Redundancy Check (CRC)
CRC can be used to ensure integrity of data read from LMP90xxx. To enable CRC, set EN_CRC high. Once
CRC is enabled, the CRC value is calculated and stored in SPI_CRC_DAT so that the master device can
periodically read for data comparison. Conveniently, the SPI_CRC_DAT register address is located next to the
ADC_DOUT register address so that the CRC value can be easily read as part of the data set. The CRC is
automatically reset when CSB or DRDYB is deasserted.
The CRC polynomial is x8 + x5 + x4 + 1. The reset value of the SPI_CRC_DAT register is zero, and the final
value is ones-complemented before it is sent out. Note that CRC computation only includes the bits sent out on
SDO and does not include the bits of the SPI_CRC_DAT itself; thus it is okay to read SPI_CRC_DAT repeatedly.
The drdyb signal normally deasserts (active high) every 1/ODR second or when the LSB of ADC_DOUTL is read.
However, this behavior can be changed so that drdyb deassertion can occur after SPI_CRC_DAT is read, but not
later than normal DRDYB deassertion which occurs at every 1/ODR seconds. This is done by setting bit
DRDYB_AFT_CRC high.
The timing protocol for CRC can be found in Figure 60.
1/ODR
1/ODR
Sampling CH0
Sampling CH1
Reading
SPI_CRC_DAT
Reading
ADC_DOUT of CH0
SDO
MSB
LSB
MSB
LSB
Reading
SPI_CRC_DAT
Reading
ADC_DOUT of CH1
MSB
LSB
MSB
LSB
Figure 60. Timing Protocol for Reading SPI_CRC_DAT
If SPI_CRC_DAT read extends beyond the normal DRDYB deassertion at every 1/ODR seconds, then
CRC_RST has to be set in the SPI Data Ready Bar Control Register. This is done to avoid a CRC reset at the
DRDYB deassertion.Timing protocol for reading CRC with CRC_RST set is shown in Figure 61.
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1/ODR
CH0
1/ODR
CH1
SDO
LSB
MSB
MSB
LSB
Reading
SPI_CRC_DAT
Reading
ADC_DOUT of CH1
Reading
SPI_CRC_DAT
Reading
ADC_DOUT of CH0
LSB
MSB
MSB
LSB
Figure 61. Timing Protocol for Reading SPI_CRC_DAT beyond normal DRDYB deassertion at every
1/ODR seconds
Follow the steps below to enable CRC:
1. Set SPI_CRC_CN = 1 (register 0x13, bit 4) to enable CRC.
2. Set DRDYB_AFT_CRC = 1 (register 0x13, bit 2) to dessert the DRDYB after CRC.
3. Compute the CRC externally, which should include CH_STS, ADC_DOUTH, ADC_DOUTM , and
ADC_DOUTL.
4. Collect the data and verify the reported CRC matches with the computed CRC (step above).
POWER MANAGEMENT
The device can be placed in Active, Power-Down, or Stand-By state.
In Power-Down, the ADC is not converting data, contents of the registers are unaffected, and there is a drastic
power reduction. In Stand-By, the ADC is not converting data, but the power is only slightly reduced so that the
device can quickly transition into the active state if desired.
These states can be selected using the PWRCN register. When written, PWRCN brings the device into the
Active, Power-Down, or Stand-By state. When read, PWRCN indicates the state of the device.
The read value would confirm the write value after a small latency (approximately 15 µs with the internal CLK). It
may be appropriate to wait for this latency to confirm the state change. Requests not adhering to this latency
requirement may be rejected.
It is not possible to make a direct transition from the power-down state to the stand-by state. This state diagram
is shown below.
PWRCN
= 11b
PWRCN
= 00b
Stand-by
PWRCN
= 01b
Active
PWRCN
= 00b
Power-down
Figure 62. Active, Power-Down, Stand-by State Diagram
RESET and RESTART
Writing 0xC3 to the REG_AND_CNV_RST field will reset the conversion and most of the programmable registers
to their default values. The only registers that will not be reset are the System Calibration Registers
(CHx_SCAL_OFFSET, CHx_SCAL_GAIN) and the DT_AVAIL_B bit.
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If it is desirable to reset the System Calibration Coefficient Registers, then set RESET_SYSCAL = 1 before
writing 0xC3 to REG_AND_CNV_RST. If the device is operating in the “System Calibration Offset/Gain
Coefficient Determination” mode (SCALCN register), then write REG_AND_CNV_RST = 0xC3 twice to get out of
this mode.
After a register reset, any on-going conversions will be aborted and restarted. If the device is in the power-down
state, then a register reset will bring it out of the power-down state.
To restart a conversion, write 1 to the RESTART bit. This bit can be used to synchronize the conversion to an
external event.
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APPLICATIONS INFORMATION
QUICK START
This section shows step-by-step instructions to configure the LMP90xxx to perform a simple DC reading from
CH0.
1. Apply VA = VIO = VREFP1 = 5V, and ground VREFN1
2. Apply VINP = ¾VREF and VINN = ¼VREF for CH0. Thus, set CH0 = VIN = VINP - VINN = ½VREF
(CH0_INPUTCN register)
3. Set gain = 1 (CH0_CONFIG: GAIN_SEL = 0x0)
4. Exclude the buffer from the signal path (CH0_CONFIG: BUF_EN = 1)
5. Set the background to BgcalMode2 (BGCALCN = 0x2)
6. Select VREF1 (CH0_INPUTCN: VREF_SEL = 0)
7. To use the internal CLK, set CLK_EXT_DET = 1 and CLK_SEL = 0.
8. Follow the register read/write protocol (Figure 51) to capture ADC_DOUT from CH0.
CONNECTING THE SUPPLIES
VA and VIO
Any ADC architecture is sensitive to spikes on the analog voltage, VA, digital input/output voltage, VIO, and
ground pins. These spikes may originate from switching power supplies, digital logic, high power devices, and
other sources. To diminish these spikes, the LMP90xxx’s VA and VIO pins should be clean and well bypassed. A
0.1 µF ceramic bypass capacitor and a 1 µF tantalum capacitor should be used to bypass the LMP90xxx
supplies, with the 0.1 µF capacitor placed as close to the LMP90xxx as possible.
Since the LMP90xxx has both external VA and VIO pins, the user has two options on how to connect these pins.
The first option is to tie VA and VIO together and power them with the same power supply. This is the most cost
effective way of powering the LMP90xxx but is also the least ideal because noise from VIO can couple into VA
and negatively affect performance. The second option involves powering VA and VIO with separate power
supplies. These supply voltages can have the same amplitude or they can be different.
VREF
Operation with VREF below VA is also possible with slightly diminished performance. As VREF is reduced, the
range of acceptable analog input voltages is also reduced. Reducing the value of VREF also reduces the size of
the LSB. When the LSB size goes below the noise floor of the LMP90xxx, the noise will span an increasing
number of codes and performance will degrade. For optimal performance, VREF should be the same as VA and
sourced with a clean source that is bypassed with a ceramic capacitor value of 0.1 µF and a tantalum capacitor
of 10 µF.
LMP90xxx also allows ratiometric connection for noise immunity reasons. A ratiometric connection is when the
ADC’s VREFP and VREFN are used to excite the input device’s (i.e. a bridge sensor) voltage references. This
type of connection severely attenuates any VREF ripple seen the ADC output, and is thus strongly
recommended.
ADC_DOUT CALCULATION
The output code of the LMP90xxx can be calculated as:
§ (VINP - VINN) x GAIN ·
23
ADC_DOUT = ± ¨
¸ x (2 )
VREFP
VREFN
¹
©
Equation 1 — Output Code
(15)
ADC_DOUT is in 24−bit two's complement binary format. The largest positive value is 0x7F_FFFF while the
largest negative value is 0x80_0000. In case of an over range the value is automatically clamped to one of these
two values.
Figure 63 shows the theoretical output code, ADC_DOUT, vs. analog input voltage, VIN, using the equation
above.
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ADC_DOUT
8,388,607d
-1 LSB
|
|
(-VREF + 1LSB)
1d
|
|
+1LSB
- 16, 777, 215d
VIN
(VREF - 1LSB)
|
|
- 8,388,608d
Figure 63. ADC_DOUT vs. VIN of a 24-Bit Resolution (VREF = 5.5V, Gain = 1).
REGISTER READ/WRITE EXAMPLES
Writing to Register Examples
Using the register read/write protocol shown in Figure 51, the following example shows how to write three data
bytes starting at register address (ADDR) 0x1F. After the last byte has been written to ADDR 0x21, deassert
CSB to end the register-write.
Transaction 1 ± URA Setup ± necessary only when the previous URA is different than the desired URA.
Instruction Byte 1 (INST1)
Upper Address Byte (UAB)
[7:0]
[7:3]
[2:0]
0x10
0x0
0x1
R/WB = Read/Write Address
0x10: Write Address
0x90: Read Address
Transaction 2 ± Data Access
Data Bytes
Instruction Byte 2 (INST2)
7
[6:5]
4
[3:0]
[23:0]
st
The 1 Data Byte will be written to ADDR 0x1F, the 2
0
0x2
R/WB = Read/Write Data
0: Write Data
1: Read Data
0
0xF
nd
Data Byte will
rd
be written to ADDR 0x20, and the 3 Data Byte will be written to ADR
0x21. After this process, deassert CSB.
SZ = Size
0x0: 1 byte
0x1: 2 bytes
0x2: 3 bytes
0x3: Streaming ± 3+ bytes until CSB is de-asserted
Figure 64. Register-Write Example 1
The next example shows how to write one data byte to ADDR 0x12. Since the URA for this example is the same
as the last example, transaction 1 can be omitted.
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Transaction 2 ± Data Access
Instruction Byte 2 (INST2)
Data Byte (s)
7
[6:5]
4
[3:0]
[7:0]
0
0x00
0
0x2
One Data Byte will be written to ADDR 0x12. After this process, deassert CSB.
R/WB = Read/Write Data
0: Write Data
1: Read Data
SZ = Size
0x0: 1 byte
0x1: 2 bytes
0x2: 3 bytes
0x3: Streaming ± 3+ bytes until CSB is de-asserted
Figure 65. Register-Write Example 2
Reading from Register Example
The following example shows how to read two bytes. The first byte will be read from starting ADDR 0x24, and
the second byte will be read from ADDR 0x25.
Transaction 1 ± URA Setup ± necessary only when the previous URA is different than the desired URA.
Instruction Byte 1 (INST1)
Upper Address Byte (UAB)
[7:0]
[7:3]
[2:0]
0x10
0x0
0x2
R/WB = Read/Write Address
0x10: Write Address
0x90: Read Address
Transaction 2 ± Data Access
Instruction Byte 2 (INST2)
7
[6:5]
4
[3:0]
1
0x1
0
0x4
R/WB = Read/Write Data
0: Write Data
1: Read Data
Data Bytes
[15:0]
2 Data Bytes will be read from ADDR 0x24 and ADDR 0x25.
After this process, deassert CSB.
SZ = Size
0x0: 1 byte
0x1: 2 bytes
0x2: 3 bytes
0x3: Streaming ± 3+ bytes until CSB is de-asserted
Figure 66. Register-Read Example
46
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STREAMING EXAMPLES
Normal Streaming Example
This example shows how to write six data bytes starting at ADDR 0x28 using the Normal Streaming mode.
Because the default STRM_TYPE is the Normal Streaming mode, setting up the SPI_STREAMCN register can
be omitted.
Transaction 1 ± URA Setup ± necessary only when the previous URA is different than the desired URA.
Upper Address Byte (UAB)
Instruction Byte 1 (INST1)
[7:0]
[7:3]
[2:0]
0x10
0x0
0x2
R/WB = Read/Write Address
0x10: Write Address
0x90: Read Address
Transaction 2 ± Data Access
Instruction Byte 2 (INST2)
7
[6:5]
4
Data Bytes
[3:0]
[47:0]
st
nd
The 1 Data Byte will be written to ADDR 0x28, the 2
0
0x3
R/WB = Read/Write Data
0: Write Data
1: Read Data
0
0x8
Data Byte will be
th
written to ADDR 0x29, etc. The last and 6 Data Byte will be written to
ADDR 0x2D. After this process, deassert CSB.
SZ = Size
0x0: 1 byte
0x1: 2 bytes
0x2: 3 bytes
0x3: Streaming ± 3+ bytes until CSB is de-asserted
Figure 67. Normal Streaming Example
Controlled Streaming Example
This example shows how to read the 24-bit conversion data (ADC_DOUT) four times using the Controlled
Streaming mode. The ADC_DOUT registers consist of ADC_DOUTH at ADDR 0x1A, ADC_DOUTM at ADDR
0x1B, and ADC_DOUTL at ADDR 0x1C.
The first step (Figure 68) sets up the SPI_STREAMCN register. This step enters the Controlled Streaming mode
by setting STRM_TYPE high in ADDR 0x03. Since three registers (ADDR 0x1A - 0x1C) need to be read, the
STRM_RANGE is 2.
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Transaction 1 ± URA Setup ± necessary only when the previous URA is different than the desired URA.
Instruction Byte 1 (INST1)
Upper Address Byte (UAB)
[7:0]
[7:3]
[2:0]
0x10
0x0
0x0
R/WB = Read/Write Address
0x10: Write Address
0x90: Read Address
Transaction 2 ± Data Access
Instruction Byte 2 (INST2)
Data Byte (s)
7
[6:5]
4
[3:0]
[7:0]
0
0x0
0
0x3
1000_0010b
R/WB = Read/Write Data
0: Write Data
1: Read Data
SZ = Size
0x0: 1 byte
0x1: 2 bytes
0x2: 3 bytes
0x3: Streaming ± 3+ bytes until CSB is de-asserted
Figure 68. Setting up SPI_STREAMCN
The next step shows how to perform the Controlled Streaming mode so that the master device will read
ADC_DOUT from ADDR 0x1A, 0x1B, 0x1C, then wrap back to ADDR 0x1A, and repeat this process for four
times. After this process, deassert CSB to end the Controlled Streaming mode.
48
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Transaction 1 ± URA Setup ± necessary only when the previous URA is different than the desired URA.
Instruction Byte 1 (INST1)
Upper Address Byte (UAB)
[7:0]
[7:3]
[2:0]
0x10
0x0
0x1
R/WB = Read/Write Address
0x10: Write Address
0x90: Read Address
Transaction 2 ± Data Access
Instruction Byte 2 (INST2)
Data Byte (s)
7
[6:5]
4
[3:0]
[95:0]
1
0x3
0
0xA
Read ADC_DOUTH, ADC_DOUTM, and ADC_DOUTL four times. After this
process, deassert CSB.
R/WB = Read/Write Data
0: Write Data
1: Read Data
SZ = Size
0x0: 1 byte
0x1: 2 bytes
0x2: 3 bytes
0x3: Streaming ± 3+ bytes until CSB is de-asserted
Figure 69. Controlled Streaming Example
EXAMPLE APPLICATIONS
3–Wire RTD
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+
1 PF
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3V
3V
VA
VIO
+
0.1 PF
0.1 PF
1 PF
SCLK
IB1
CSB
IB1 =
1 mA
SDO
SDI
drdyb = D6
VIN0
LMP90100
RLINE1
RTD
PT-100
RCOMP
= 0:
D5
VIN1
RLINE2
Microcontroller
IB2 =
1 mA
IB2
12 pF
VIN6/VREFP2
RLINE3
3.57
MHz
XOUT
RREF
VIN7/VREFN2
XIN/CLK
12 pF
Figure 70. Topology #1: 3-wire RTD Using 2 Current Sources
Figure 70 shows the first topology for a 3-wire resistive temperature detector (RTD) application. Topology #1
uses two excitation current sources, IB1 and IB2, to create a differential voltage across VIN0 and VIN1. As a
result of using both IB1 and IB2, only one channel (VIN0-VIN1) needs to be measured. As shown in Equation 2,
the equation for this channel is IB1 x (RTD – RCOMP) assuming that RLINE1 = RLINE2.
VIN0 = IB1 (RLINE1 + RTD) + (IB1 + IB2) (RLINE3 + RREF)
VIN1 = IB2 (RLINE2 + RCOMP) + (IB1 + IB2) (RLINE3 + RREF)
If RLINE1 = RLINE2, then:
VIN = (VIN0 - VIN1) = IB1 (RTD - RCOMP)
Equation 2 — VIN Equation for Topology #1
(16)
The PT-100 changes linearly from 100 Ohm at 0°C to 146.07 Ohm at 120°C. If desired, choose a suitable
compensating resistor (RCOMP) so that VIN can be virtually 0V at any desirable temperature. For example, if
RCOMP = 100 Ohm, then at 0°C, VIN = 0V and thus a higher gain can be used.
The advantage of this circuit is its ratiometric configuration, where VREF = (IB1 + IB2) x (RREF). Equation 3
shows that a ratiometric configuration eliminates IB1 and IB2 from the output equation, thus increasing the
overall performance.
ADC_DOUT =
VIN (Gain) ( n)
2
2 VREF
ADC_DOUT =
[IB1( RTD - RCOMP) Gain] n
(2 )
2( IB1 + IB 2 ) RREF
ADC_DOUT =
>(RTD - RCOMP) Gain@
2 (2 ) RREF
( 2 n)
Equation 3 — ADC_DOUT Showing IB1 & IB2 Elimination
50
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3V
3V
+
+
0.1 PF
2.2 PF
0.1 PF
VA
1 PF
VIO
SCLK
IB1
IB1 =
1 mA
CSB
SDO/DRDYB
RLINE1
SDI
VIN0
Microcontroller
RTD
PT-100
LMP90100
D2
VIN1
RLINE2
VIN6/VREFP2
RLINE3
RREF
OSC
XIN/CLK
VIN7/VREFN2
51:
Figure 71. Topology #2: 3-wire RTD Using 1 Current Source
Figure 71 shows the second topology for a 3-wire RTD application. Topology #2 shows the same connection as
topology #1, but without IB2. Although this topology eliminates a current source, it requires two channel
measurements as shown in Equation 4.
VIN0 = IB1 (RLINE1 + RTD + RLINE3 + RREF)
VIN1 = IB1 (RLINE3 + RREF)
VIN6 = IB1 (RREF)
CH0 = VIN0 - VIN1 = IB1 (RLINE1 + RTD)
CH1 = VIN1 - VIN6 = IB1 (RLINE3)
Assume RLINE1 = RLINE3, thus:
CH0 - CH1 = IB1 (RTD)
Equation 4 — VIN Equation for Topology #2
(18)
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Thermocouple and IC Analog Temperature
5V
2.7V
VA
VIO
+
+
0.1 PF
1 PF
Thermocouple
10 nF
VREFP1
SCLK
+
TC [ VIN4 ± VIN3]
-
2.2 PF
CSB
SDO
2k
SDI
VIN3
2k
1 PF
Tcold
VIN4
Thot
0.1 PF
D6 = DRDYB
10 nF
LMP90100
Microcontroller
5V
LM94022
IC Temp
Sensor
+
1 PF
Tcold
VIN5
+
LM [ VIN5]
-
0.1 PF
XOUT
VIN7
5V
VREFP1
LM4140-4.1
+
1 PF
0.1 PF
0.1 PF
XIN/CLK
VREFN1
GND
Figure 72. Thermocouple with CJC
The LMP90xxx is also ideal for thermocouple temperature applications. Thermocouples have several advantages
that make them popular in many industrial and medical applications. Compare to RTDs, thermistors, and IC
sensors, thermocouples are the most rugged, least expensive, and can operate over the largest temperature
range.
A thermocouple is a sensor whose junction generates a differential voltage, VIN, that is relative to the
temperature difference (Thot – Tcold). Thot is also known as the measuring junction or “hot” junction, which is
placed at the measured environment. Tcold is also known as the reference or “cold” junction, which is placed at
the measuring system environment.
Because a thermocouple can only measure a temperature difference, it does not have the ability to measure
absolute temperature. To determine the absolute temperature of the measured environment (Thot), a technique
known as cold junction compensation (CJC) must be used.
In a CJC technique, the “cold” junction temperature, Tcold, is sensed by using an IC temperature sensor, such
as the LM94022. The temperature sensor should be placed within close proximity of the reference junction and
should have an isothermal connection to the board to minimize any potential temperature gradients.
Once Tcold is obtained, use a standard thermocouple look-up-table to find its equivalent voltage. Next, measure
the differential thermocouple voltage and add the equivalent cold junction voltage. Lastly, convert the resulting
voltage to temperature using a standard thermocouple look-up-table.
For example, assume Tcold = 20°C. The equivalent voltage from a type K thermocouple look-up-table is 0.798
mV. Next, add the measured differential thermocouple voltage to the Tcold equivalent voltage. For example, if
the thermocouple voltage is 4.096 mV, the total would be 0.798 mV + 4.096 mV = 4.894 mV. Referring to the
type K thermocouple table gives a temperature of 119.37°C for 4.894 mV.
52
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REGISTERS
1. If written to, RESERVED bits must be written to only 0 unless otherwise indicated.
2. Read back value of RESERVED bits and registers is unspecified and should be discarded.
3. Recommended values must be programmed and forbidden values must not be programmed where they are
indicated in order to avoid unexpected results.
4. If written to, registers indicated as Reserved must have the indicated default value as shown below. Any
other value can cause unexpected results.
REGISTER MAP
Register Name
ADDR
(URA & LRA)
Type
Default
RESETCN
Reset Control
0x00
WO
-
SPI_HANDSHAKECN
SPI Handshake Control
0x01
R/W
0x00
SPI_RESET
SPI Reset Control
0x02
R/W
0x00
SPI_STREAMCN
SPI Stream Control
0x03
R/W
0x00
Reserved
-
0x04 - 0x07
-
0x00
PWRCN
Power Mode Control and Status
0x08
RO & WO
0x00
DATA_ONLY_1
Data Only Read Control 1
0x09
R/W
0x1A
DATA_ONLY_2
Data Only Read Control 2
0x0A
R/W
0x02
ADC_RESTART
ADC Restart Conversion
0x0B
WO
-
Reserved
-
0x0C - 0x0D
-
0x00
GPIO_DIRCN
GPIO Direction Control
0x0E
R/W
0x00
GPIO_DAT
GPIO Data
0x0F
RO & WO
-
BGCALCN
Background Calibration Control
0x10
R/W
0x00
SPI_DRDYBCN
SPI Data Ready Bar Control
0x11
R/W
0x03
ADC_AUXCN
ADC Auxiliary Control
0x12
R/W
0x00
SPI_CRC_CN
CRC Control
0x13
R/W
0x02
SENDIAG_THLD
Sensor Diagnostic Threshold 1,0
0x14 - 0x15
R/W
0x0000
Reserved
-
0x16
-
0x00
SCALCN
System Calibration Control
0x17
R/W
0x00
ADC_DONE
ADC Data Available
0x18
RO
-
SENDIAG_FLAGS
Sensor Diagnostic Flags
0x19
RO
-
ADC_DOUT
Conversion Data 2,1,0
0x1A - 0x1C
RO
-
SPI_CRC_DAT
CRC Data
0x1D
RO & WO
-
CHANNEL CONFIGURATION REGISTERS (CH4 to CH6 for LMP90100/LMP9099 only)
CH_STS
Channel Status
0x1E
RO
0x00
CH_SCAN
Channel Scan Mode
0x1F
R/W
0x30
CH0_INPUTCN
CH0 Input Control
0x20
R/W
0x01
CH0_CONFIG
CH0 Configuration
0x21
R/W
0x70
CH1_INPUTCN
CH1 Input Control
0X22
R/W
0x13
CH1_CONFIG
CH1 Configuration
0x23
R/W
0x70
CH2_INPUTCN
CH2 Input Control
0x24
R/W
0x25
CH2_CONFIG
CH2 Configuration
0x25
R/W
0x70
CH3_INPUTCN
CH3 Input Control
0x26
R/W
0x37
CH3_CONFIG
CH3 Configuration
0x27
R/W
0x70
CH4_INPUTCN
CH4 Input Control
0x28
R/W
0x01
CH4_CONFIG
CH4 Configuration
0x29
R/W
0x70
CH5_INPUTCN
CH5 Input Control
0x2A
R/W
0x13
CH5_CONFIG
CH5 Configuration
0x2B
R/W
0x70
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Register Name
CH6_INPUTCN
CH6 Input Control
CH6_CONFIG
CH6 Configuration
Reserved
-
ADDR
(URA & LRA)
Type
Default
0x2C
R/W
0x25
0x2D
R/W
0x70
0x2E - 0x2F
-
0x00
SYSTEM CALIBRATION REGISTERS
CH0_SCAL_OFFSET
CH0 System Calibration Offset Coefficients
0x30 - 0x32
R/W
0x00_0000
CH0_SCAL_GAIN
CH0 System Calibration Gain Coefficients
0x33 - 0x35
R/W
0x80_0000
CH0_SCAL_SCALING
CH0 System Calibration Scaling Coefficients
0x36
R/W
0x01
CH0_SCAL_BITS_SELECT
CH0 System Calibration Bits Selector
OR
0x37
R/W
0x00
CH1_SCAL_OFFSET
CH1 System Calibration Offset Coefficients
0x38 - 0x3A
R/W
0x00_0000
CH1_SCAL_GAIN
CH1 System Calibration Gain Coefficient
0x3B - 0x3D
R/W
0x80_0000
CH1_SCAL_SCALING
CH1 System Calibration Scaling Coefficients
0x3E
R/W
0x01
0x3F
R/W
0x00
CH1_SCAL_BITS_SELECT
CH1 System Calibration Bits Selector
OR
CH2_SCAL_OFFSET
CH2 System Calibration Offset Coefficients
0x40 - 0x42
R/W
0x00_0000
CH2_SCAL_GAIN
CH2 System Calibration Gain Coefficient
0x43 - 0x45
R/W
0x80_0000
CH2_SCAL_SCALING
CH2 System Calibration Scaling Coefficients
0x46
R/W
0x01
CH2_SCAL_BITS_SELECT
CH2 System Calibration Bits Selector
OR
0x47
R/W
0x00
CH3_SCAL_OFFSET
CH3 System Calibration Offset Coefficients
0x48 - 0x4A
R/W
0x00_0000
CH3_SCAL_GAIN
CH3 System Calibration Gain Coefficient
0x4B - 0x4D
R/W
0x80_0000
CH3_SCAL_SCALING
CH3 System Calibration Scaling Coefficients
0x4E
R/W
0x01
0x4F
R/W
0x00
0x50 - 0x7F
-
0x00
CH3_SCAL_BITS_SELECT
CH3 System Calibration Bits Selector
OR
Reserved
-
POWER AND RESET REGISTERS
Table 8. RESETCN: Reset Control (Address 0x00)
Bit
Bit Symbol
Bit Description
Register and Conversion Reset0xC3: Register and conversion reset
Others: Neglected
[7:0] REG_AND_CNV_ RST
Table 9. SPI_RESET: SPI Reset Control (Address 0x02)
Bit
[0]
54
Bit Symbol
Bit Description
SPI_ RST
SPI Reset Enable
0x0 (default): SPI Reset Disabled
0x1: SPI Reset Enabled
Note:Once Written, The contents of this register are sticky. That is, the content of this register
cannot be changed with subsequent write.However, a Register reset clears the register as well as
the sticky status.
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Table 10. PWRCN: Power Mode Control and Status (Address 0x08)
Bit
Bit Symbol
Bit Description
[7:2] Reserved
Power Control
Write Only – power down mode control
0x0: Active Mode
0x1: Power-down Mode
0x3: Stand-by Mode
[1:0] PWRCN
Read Only – the present mode is:
0x0 (default): Active Mode
0x1: Power-down Mode
0x3: Stand-by Mode
ADC REGISTERS
Table 11. ADC_RESTART: ADC Restart Conversion (Address 0x0B)
Bit
Bit Symbol
Bit Description
[7:1] Reserved
0
Restart conversion
1: Restart conversion.
RESTART
Table 12. ADC_AUXCN: ADC Auxiliary Control (Address 0x12)
Bit
Bit Symbol
Bit Description
7
Reserved
-
6
RESET_SYSCAL
The System Calibration registers (CHx_SCAL_OFFSET and CHx_SCAL_GAIN) are:
0 (default): preserved even when "REG_AND_CNV_ RST" = 0xC3.
1: reset by setting "REG_AND_CNV_ RST" = 0xC3.
5
CLK_EXT_DET
External clock detection
0 (default): "External Clock Detection" is operational
1: "External-Clock Detection" is bypassed
4
CLK_SEL
Clock select – only valid if CLK_EXT_DET = 1
0 (default): Selects internal clock
1: Selects external clock
RTD_CUR_SEL
[3:0] (LMP90100 and LMP90098
only)
Selects RTD Current as follows:
0x0 (default): 0 µA
0x1: 100 µA
0x2: 200 µA
0x3: 300 µA
0x4: 400 µA
0x5: 500 µA
0x6: 600 µA
0x7: 700 µA
0x8: 800 µA
0x9: 900 µA
0xA: 1000 µA
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Table 13. ADC_DONE: ADC Data Available (Address 0x18)
Bit
Bit Symbol
Bit Description
Data Available – indicates if new conversion data is available
0x00 − 0xFE: Available
0xFF: Not available
[7:0] DT_AVAIL_B
Table 14. ADC_DOUT: 24-bit Conversion Data (two’s complement) (Address 0x1A - 0x1C)
Address
Name
Register Description
0x1A
ADC_DOUTH
ADC Conversion Data [23:16]
0x1B
ADC_DOUTM
ADC Conversion Data [15:8]
0x1C
ADC_DOUTL
ADC Conversion Data [7:0]
Note: Repeat reads of these registers are allowed as long as such reads are spaced apart by at least 72 µs.
CHANNEL CONFIGURATION REGISTERS
Table 15. CH_STS: Channel Status (Address 0x1E)
Bit
Bit Symbol
Bit Description
[7:2] Reserved
-
1
CH_SCAN_NRDY
Channel Scan Not Ready – indicates if it is okay to program CH_SCAN
0: Update not pending, CH_SCAN register is okay to program
1: Update pending, CH_SCAN register is not ready to be programmed
0
INV_OR_RPT_RD_STS
Invalid or Repeated Read Status
0: ADC_DOUT just read was valid and hitherto unread
1: ADC_DOUT just read was either invalid (not ready) or there was a repeated read.
Table 16. CH_SCAN: Channel Scan Mode (Address 0x1F)
Bit
Bit Symbol
[7:6] CH_SCAN_SEL
Bit Description
Channel Scan Select
0x0 (default): ScanMode0: Single-Channel Continuous Conversion
0x1: ScanMode1: One or more channels Single Scan
0x2: ScanMode2: One or more channels Continuous Scan
0x3: ScanMode3: One or more channels Continuous Scan with Burnout Currents
Last channel for conversion
0x0: CH0
0x1: CH1
0x2: CH2
LAST_CH
0x3: CH3
[5:3] (CH4 to CH6 for LMP90100 and
0x4: CH4
LMP90099 only)
0x5: CH5
0x6 (default): CH6
Note: LAST_CH cannot be smaller than FIRST_CH. For example, if LAST_CH = CH5, then
FIRST_CH cannot be CH6. If 0x7 is written it is ignored.
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Table 16. CH_SCAN: Channel Scan Mode (Address 0x1F) (continued)
Bit
Bit Symbol
Bit Description
Starting channel for conversion
0x0 (default): CH0
0x1: CH1
0x2: CH2
FIRST_CH
0x3: CH3
[2:0] (CH4 to CH6 for LMP90100 and
0x4: CH4
LMP90099 only)
0x5: CH5
0x6: CH6
Note: FIRST_CH cannot be greater than LAST_CH. For example, if FIRST_CH = CH1, then
LAST_CH cannot be CH0. If 0x7 is written it is ignored.
Note: While writing to the CH_SCAN register, if 0x7 is written to FIRST_CH or LAST_CH the write to the entire
CH_SCAN register is ignored.
Table 17. CHx_INPUTCN: Channel Input Control (CH4 to CH6 for LMP90100/LMP9099 only) (1)
Bit
Bit Symbol
Bit Description
7
BURNOUT_EN
Enable sensor diagnostic
0 (default): Disable Sensor Diagnostics current injection for this Channel
1: Enable Sensor Diagnostics current injection for this Channel
6
VREF_SEL
Select the reference
0 (Default): Select VREFP1 and VREFN1
1: Select VREFP2 and VREFN2
VINP
Positive input select
0x0: VIN0
0x1: VIN1
0x2: VIN2
0x3: VIN3 (LMP90100/LMP90099 only)
0x4: VIN4 (LMP90100/LMP90099 only)
0x5: VIN5 (LMP90100/LMP90099 only)
0x6: VIN6
0x7: VIN7
Note: to see the default values for each channel, refer to the table below.
VINN
Negative input select
0x0: VIN0
0x1: VIN1
0x2: VIN2
0x3: VIN3 (LMP90100/LMP90099 only)
0x4: VIN4 (LMP90100/LMP90099 only)
0x5: VIN5 (LMP90100/LMP90099 only)
0x6: VIN6
0x7: VIN7
Note: to see the default values for each channel, refer to the table below.
[5:3]
[2:0]
(1)
Register Address (hex):
(a) CH0: 0x20
(b) CH1: 0X22
(c) CH2: 0x24
(d) CH3: 0x26
(e) CH4: 0x28
(f) CH5: 0x2A
(g) CH6: 0x2C
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Table 18. Default VINx for CH0-CH6
VINP
VINN
CH0
VIN0
VIN1
CH1
VIN2
VIN3 (LMP90100/LMP90099 only)
CH2
VIN4 (LMP90100/LMP90099 only)
VIN5 (LMP90100/LMP90099 only)
CH3
VIN6
VIN7
CH4 (LMP90100/LMP90099 only)
VIN0
VIN1
CH5 (LMP90100/LMP90099 only)
VIN2
VIN3
CH6 (LMP90100/LMP90099 only)
VIN4
VIN5
Table 19. CHx_CONFIG: Channel Configuration (CH4 to CH6 LMP90100/LMP90099 only) (1)
Bit
7
Bit Symbol
Bit Description
Reserved
-
[6:4] ODR_SEL
ODR Select
0x0: 13.42 / 8 = 1.6775 SPS
0x1: 13.42 / 4 = 3.355 SPS
0x2: 13.42 / 2 = 6.71 SPS
0x3: 13.42 SPS
0x4: 214.65 / 8 = 26.83125 SPS
0x5: 214.65 / 4 = 53.6625 SPS
0x6: 214.65 / 2 = 107.325 SPS
0x7(default): 214.65 SPS
[3:1] GAIN_SEL
Gain Select
0x0 (default): 1 (FGA OFF)
0x1: 2 (FGA OFF)
0x2: 4 (FGA OFF)
0x3: 8 (FGA OFF)
0x4: 16 (FGA ON)
0x5: 32 (FGA ON)
0x6: 64 (FGA ON)
0x7: 128 (FGA ON)
0
(1)
Enable/Disable the buffer
0 (default): Include the buffer in the signal path
1: Exclude the buffer from the signal path
Note: When gain ≥ 16, the buffer is automatically included in the signal path irrespective of this bit.
BUF_EN
Register Address (hex):
(a) CH0: 0x21
(b) CH1: 0x23
(c) CH2: 0x25
(d) CH3: 0x27
(e) CH4: 0x29
(f) CH5: 0x2B
(g) CH6: 0x2D
CALIBRATION REGISTERS
Table 20. BGCALCN: Background Calibration Control (Address 0x10)
Bit
Bit Symbol
Bit Description
[7:2] Reserved
-
[1:0] BGCALN
Background calibration control – selects scheme for continuous background calibration.
0x0 (default): BgcalMode0: Background Calibration OFF
0x1: BgcalMode1: Offset Correction / Gain Estimation
0x2: BgcalMode2: Offset Correction / Gain Correction
0x3: BgcalMode3: Offset Estimation / Gain Estimation
58
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Table 21. SCALCN: System Calibration Control (Address 0x17)
Bit
Bit Symbol
Bit Description
[7:2] Reserved
System Calibration Control
When written, set SCALCN to:
0x0 (default): Normal Mode
0x1: “System Calibration Offset Coefficient Determination” mode
0x2: “System Calibration Gain Coefficient Determination” mode
0x3: Reserved
[1:0] SCALCN
When read, this bit indicates the system calibration mode is in:
0x0: Normal Mode
0x1: "System Calibration Offset Coefficient Determination" mode
0x2: "System Calibration Gain Coefficient Determination" mode
0x3: Reserved
Note: when read, this bit will indicate the current System Calibration status. Since this coefficient
determination mode will only take 1 conversion cycle, reading this register will only return 0x00,
unless this register is read within 1 conversion window.
Table 22. CHx_SCAL_OFFSET: CH0-CH3 System Calibration Offset Registers (Two's-Complement)
ADDR
Name
Description
0x48
CHx_SCAL_OFFSETH
System Calibration Offset Coefficient Data [23:16]
0x49
CHx_SCAL_OFFSETM
System Calibration Offset Coefficient Data [15:8]
0x4A
CHx_SCAL_OFFSETL
System Calibration Offset Coefficient Data[7:0]
CH0
CH1
CH2
CH3
0x30
0x38
0x40
0x31
0x39
0x41
0x32
0x3A
0x42
Table 23. CHx_SCAL_GAIN: CH0-CH3 System Calibration Gain Registers (Fixed Point 1.23 Format)
ADDR
Name
Description
0x4B
CHx_SCAL_GAINH
System Calibration Gain Coefficient Data [23:16]
0x44
0x4C
CHx_SCAL_GAINM
System Calibration Gain Coefficient Data [15:8]
0x45
0x4D
CHx_SCAL_GAINL
System Calibration Gain Coefficient Data[7:0]
CH0
CH1
CH2
CH3
0x33
0x3B
0x43
0x34
0x3C
0x35
0x3D
Table 24. CHx_SCAL_SCALING: CH0-CH3 System Calibration Scaling Coefficient Registers
ADDR
CH0
CH1
CH2
CH3
0x36
0x3E
0x46
0x4E
Name
Description
CHx_SCAL_SCALING
System Calibration Scaling Coefficient Data [5:0]
Table 25. CHx_SCAL_BITS_SELECTOR: CH0-CH3 System Calibration Bits Selector Registers
ADDR
CH0
CH1
CH2
CH3
0x37
0x3F
0x47
0x4F
Name
Description
CHx_SCAL_BITS_SELECTOR
System Calibration Bits Selection Data [2:0]
SENSOR DIAGNOSTIC REGISTERS
Table 26. SENDIAG_THLD: Sensor Diagnostic Threshold (Address 0x14 - 0x15)
Address
Name
Register Description
0x14
SENDIAG_THLDH
Sensor Diagnostic threshold [15:8]
0x15
SENDIAG_THLDL
Sensor Diagnostic threshold [7:0]
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Table 27. SENDIAG_FLAGS: Sensor Diagnostic Flags (Address 0x19)
Bit
Bit Symbol
Bit Description
7
SHORT_THLD_ FLAG
Short Circuit Threshold Flag = 1 when the absolute value of VOUT is within the absolute threshold
voltage set by SENDIAG_THLDH and SENDIAG_THLDL.
6
RAILS_FLAG
Rails Flag = 1 when at least one of the inputs is near rail (VA or GND).
5
POR_AFT_LST_RD
Power-on-reset after last read = 1 when there was a power-on-reset event since the last time the
SENDIAG_FLAGS register was read.
[4:3] OFLO_FLAGS
Overflow flags
0x0: Normal operation
0x1: The modulator was not overranged, but ADC_DOUT got clamped to 0x7f_ffff (positive
fullscale) or 0x80_0000 (negative full scale)
0x2: The modulator was over-ranged (VIN > 1.3*VREF/GAIN)
0x3: The modulator was over-ranged (VIN < -1.3*VREF/GAIN)
[2:0] SAMPLED_CH
Channel Number – the sampled channel for ADC_DOUT and SENDIAG_FLAGS.
SPI REGISTERS
Table 28. SPI_HANDSHAKECN: SPI Handshake Control (Address 0x01)
Bit
Bit Symbol
Bit Description
[7:4] Reserved
SDO/DRDYB Driver – sets who is driving the SDO/DRYB pin
[3:1] SDO_DRDYB_ DRIVER
Whenever CSB is
Asserted and the Device
is Reading ADC_DOUT
Whenever CSB is
Asserted and the Device
is Not Reading
ADC_DOUT
CSB is Deasserted
0x0 (default)
SDO is driving
DRDYB is driving
High-Z
0x3
SDO is driving
DRDYB is driving
DRDYB is driving
0x4
SDO is driving
High-Z
High-Z
Others
Forbidden
Switch-off trigger - refers to the switching of the output drive from the slave to the master.
0 (default): SDO will be high-Z after the last (16th, 24th, 32nd, etc) rising edge of SCLK. This
option allows time for the slave to transfer control back to the master at the end of the frame.
0
SW_OFF_TRG
1: SDO’s high-Z is postponed to the subsequent falling edge following the last (16th, 24th, 32nd,
etc) rising edge of SCLK. This option provides additional hold time for the last bit, DB0, in nonstreaming read transfers.
Table 29. SPI_STREAMCN: SPI Streaming Control (Address 0x03)
Bit
7
Bit Symbol
Bit Description
STRM_TYPE
Stream type
0 (default): Normal Streaming mode
1: Controlled Streaming mode
Stream range – selects Range for Controlled Streaming mode
Default: 0x00
[6:0] STRM_ RANGE
Table 30. DATA_ONLY_1: Data Only Read Control 1 (Address 0x09)
Bit Symbol
Bit Description
7
Bit
Reserved
-
[6:0]
DATA_ONLY_ADR
Start address for the Data Only Read Transaction
Default: 0x1A
Please refer to the description of DT_ONLY_SZ in DATA_ONLY_2 register.
60
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Table 31. DATA_ONLY_2: Data Only Read Control 2 (Address 0x0A)
Bit
[7:3]
Bit Symbol
Bit Description
Reserved
-
DATA_ONLY_SZ
Number of bytes to be read out in Data Only mode. A value of 0x0 means read one byte and 0x7
means read 8 bytes.
Default: 0x2
[2:0]
Table 32. SPI_DRDYBCN: SPI Data Ready Bar Control (Address 0x11)
Bit
Bit Symbol
Bit Description
7
SPI_DRDYB_D6
Enable DRDYB on D6
0 (default): D6 is a GPIO
1: D6 = drdyb signal
6
Reserved
-
5
CRC_RST
CRC Reset
0 (default): Enable CRC reset on DRDYB deassertion
1: Disbale CRC reset on DRDYB deassertion
4
Reserved
-
FGA_BGCAL
Gain background calibration
0 (default): Correct FGA gain error. This is useful only if the device is operating in BgcalMode2
and ScanMode2 or ScanMode3.
1: Correct FGA gain error using the last known coefficients.
3
[2:0] Reserved
Default - 0x3 (do not change this value)
Table 33. SPI_CRC_CN: CRC Control (Address 0x13)
Bit
Bit Symbol
[7:5] Reserved
Bit Description
-
4
EN_CRC
Enable CRC
0 (default): Disable CRC
1: Enable CRC
3
Reserved
Default - 0x0 (do not change this value)
2
DRDYB_AFT_CRC
DRDYB After CRC
0 (default): DRDYB is deasserted (active high) after ADC_DOUTL is read.
1: DRDYB is deasserted after SPI_CRC_DAT (which follows ADC_DOUTL), is read.
[1:0] Reserved
-
Table 34. SPI_CRC_DAT: CRC Data (Address 0x1D)
Bit
Bit Symbol
Bit Description
CRC Data
[7:0] CRC_DAT
When written, this register reset CRC:
Any Value: Reset CRC
When read, this register indicates the CRC data.
GPIO REGISTERS
Table 35. GPIO_DIRCN: GPIO Direction (Address 0x0E)
Bit
7
Bit Symbol
Bit Description
Reserved
-
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Table 35. GPIO_DIRCN: GPIO Direction (Address 0x0E) (continued)
Bit
x
Bit Symbol
Bit Description
GPIO direction control – these bits are used to control the direction of each General Purpose
Input/Outputs (GPIO) pins D0 - D6.
0 (default): Dx is an Input
1: Dx is an Output
where 0 ≤ x ≤ 6.
GPIO_DIRCNx
For example, writing a 1 to bit 6 means D6 is an Output.
Note: If D6 is used for DRDYB, then it cannot be used for GPIO.
Table 36. GPIO_DAT: GPIO Data (Address 0x0F)
Bit
7
Bit Symbol
Bit Description
Reserved
Write Only - when GPIO_DIRCNx = 0
0: Dx is LO
1: Dx is HI
x
Dx
Read Only - when GPIO_DIRCNx = 1
0: Dx driven LO
1: Dx driven HI
where 0 ≤ x ≤ 6.
For example, writing a 0 to bit 4 means D4 is LO.
It is okay to Read the GPIOs that are configured as outputs and write to GPIOs that are configured
as inputs. Reading the GPIOs that are outputs would return the current value on those GPIOs, and
writing to the GPIOs that are inputs are neglected
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REVISION HISTORY
Changes from Revision O (March 2013) to Revision P
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 62
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LMP90097MH/NOPB
ACTIVE
HTSSOP
PWP
28
48
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
LMP90097
MH
LMP90097MHE/NOPB
ACTIVE
HTSSOP
PWP
28
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
LMP90097
MH
LMP90097MHX/NOPB
ACTIVE
HTSSOP
PWP
28
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
LMP90097
MH
LMP90098MH/NOPB
ACTIVE
HTSSOP
PWP
28
48
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
LMP90098
MH
LMP90098MHE/NOPB
ACTIVE
HTSSOP
PWP
28
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
LMP90098
MH
LMP90098MHX/NOPB
ACTIVE
HTSSOP
PWP
28
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
LMP90098
MH
LMP90099MH/NOPB
ACTIVE
HTSSOP
PWP
28
48
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
LMP90099
MH
LMP90099MHE/NOPB
ACTIVE
HTSSOP
PWP
28
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
LMP90099
MH
LMP90099MHX/NOPB
ACTIVE
HTSSOP
PWP
28
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
LMP90099
MH
LMP90100MH/NOPB
ACTIVE
HTSSOP
PWP
28
48
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
LMP90100
MH
LMP90100MHE/NOPB
ACTIVE
HTSSOP
PWP
28
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
LMP90100
MH
LMP90100MHX/NOPB
ACTIVE
HTSSOP
PWP
28
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
LMP90100
MH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
LMP90097MHE/NOPB
HTSSOP
PWP
28
250
178.0
16.4
LMP90097MHX/NOPB
HTSSOP
PWP
28
2500
330.0
LMP90098MHE/NOPB
HTSSOP
PWP
28
250
178.0
LMP90098MHX/NOPB
HTSSOP
PWP
28
2500
LMP90099MHE/NOPB
HTSSOP
PWP
28
LMP90099MHX/NOPB
HTSSOP
PWP
LMP90100MHE/NOPB
HTSSOP
PWP
LMP90100MHX/NOPB
HTSSOP
PWP
6.8
10.2
1.6
8.0
16.0
Q1
16.4
6.8
10.2
1.6
8.0
16.0
Q1
16.4
6.8
10.2
1.6
8.0
16.0
Q1
330.0
16.4
6.8
10.2
1.6
8.0
16.0
Q1
250
178.0
16.4
6.8
10.2
1.6
8.0
16.0
Q1
28
2500
330.0
16.4
6.8
10.2
1.6
8.0
16.0
Q1
28
250
178.0
16.4
6.8
10.2
1.6
8.0
16.0
Q1
28
2500
330.0
16.4
6.8
10.2
1.6
8.0
16.0
Q1
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMP90097MHE/NOPB
HTSSOP
PWP
LMP90097MHX/NOPB
HTSSOP
PWP
28
250
213.0
191.0
55.0
28
2500
367.0
367.0
38.0
LMP90098MHE/NOPB
HTSSOP
PWP
LMP90098MHX/NOPB
HTSSOP
PWP
28
250
213.0
191.0
55.0
28
2500
367.0
367.0
LMP90099MHE/NOPB
HTSSOP
38.0
PWP
28
250
213.0
191.0
55.0
LMP90099MHX/NOPB
LMP90100MHE/NOPB
HTSSOP
PWP
28
2500
367.0
367.0
38.0
HTSSOP
PWP
28
250
213.0
191.0
LMP90100MHX/NOPB
55.0
HTSSOP
PWP
28
2500
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
PWP0028A
MXA28A (Rev D)
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