AD ADM1270 High voltage input protection device Datasheet

FEATURES
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
Controls supply voltages from 4 V to 60 V
Gate drive for low voltage drop reverse supply protection
Gate drive for P-channel FETs
Inrush current limiting control
Adjustable current limit
Foldback current limiting
Automatic retry or latch-off on current fault
Programmable current-limit timer for safe operating area (SOA)
Power-good and fault outputs
Analog undervoltage (UV) and overvoltage (OV) protection
16-lead, 3 mm × 3 mm LFCSP
16-lead QSOP
APPLICATIONS
VCC/SENSE+ SENSE–
RPFG
ADM1270
VCAP
LDO
UV
+
–
IOUT
1V
–
GATE DRIVE/
LOGIC
1V
+
REF
SELECT
FLB
+
CURRENTLIMIT
CONTROL
GENERAL DESCRIPTION
The ADM1270 is a current-limiting controller that provides
inrush current limiting and overcurrent protection for modular
or battery-powered systems. When circuit boards are inserted
into a live backplane, discharged supply bypass capacitors draw
large transient currents from the backplane power bus as they
charge. These transient currents can cause permanent damage
to connector pins, as well as dips on the backplane supply that
can reset other boards in the system.
GATE
–
OV
ISET
Industrial modules
Battery-powered/portable instrumentation
+
CURRENT
LIMIT
FB_PG
–
TIMER
ON
TIMER
TIMEOUT
VCB
ENABLE FAULT PWRGD
GND
TIMER_OFF
TIMER
12259-001
Data Sheet
High Voltage Input Protection Device
ADM1270
Figure 1.
The ADM1270 is designed to control the inrush current, when
powering on the system, via an external P-channel field effect
transistor (FET).
To protect the system from a reverse polarity input supply, there
is a provision made to control an additional external P-channel
FET. This feature prevents reverse current flow in case of a reverse
polarity connection, which can damage the load or the ADM1270.
The ADM1270 is available in a 3 mm × 3 mm, 16-lead LFCSP and
a 16-lead QSOP.
Rev. A
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ADM1270
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Current Sense Inputs ................................................................. 16
Applications ....................................................................................... 1
Current-Limit Reference ........................................................... 16
General Description ......................................................................... 1
Setting the Current Limit (ISET) ............................................. 16
Simplified Functional Block Diagram ........................................... 1
Foldback ...................................................................................... 17
Revision History ............................................................................... 2
TIMER ......................................................................................... 17
Specifications..................................................................................... 3
TIMER_OFF ............................................................................... 18
Absolute Maximum Ratings ............................................................ 5
Hot Swap Retry Duty Cycle ...................................................... 18
Thermal Characteristics .............................................................. 5
Gate and RPFG Clamps ............................................................. 19
ESD Caution .................................................................................. 5
Fast Response to Severe Overcurrent ...................................... 19
Pin Configurations and Function Descriptions ........................... 6
Undervoltage and Overvoltage ................................................. 19
Typical Performance Characteristics ............................................. 9
Enable Input ................................................................................ 19
Typical Application Circuit ........................................................... 14
Power Good ................................................................................ 20
Theory of Operation ...................................................................... 15
Outline Dimensions ....................................................................... 21
Powering the ADM1270 ............................................................ 16
Ordering Guide .......................................................................... 21
REVISION HISTORY
4/16—Rev. 0 to Rev. A
Change to Setting the Current Limit (ISET) Section ................. 17
12/14—Revision 0: Initial Version
Rev. A | Page 2 of 21
Data Sheet
ADM1270
SPECIFICATIONS
VCC/VSENSE+ = 4 V to 60 V, VSENSE = (VSENSE+ − VSENSE−) = 0 V, TA = −40°C to +125°C, unless otherwise noted.
Table 1.
Parameter
POWER SUPPLY
Operating Voltage Range
Quiescent Current
UV PIN
Input Current
Symbol
Min
VCC
ICC
4
IUV
Max
Unit
Test Conditions/Comments
360
60
500
V
μA
GATE on
0.2
1
1.015
65
7
8
μA
μA
V
mV
μs
μs
UV ≤ 5.5 V, TA = −40°C to +85°C
UV ≤ 5.5 V, TA = −40°C to +125°C
UV falling
μA
μA
V
mV
μs
μs
OV ≤ 5.5 V, TA = −40°C to +85°C
OV ≤ 5.5 V, TA = −40°C to +125°C
OV rising
1.5
0.2
1
1.015
35
2.0
2.5
0.005
0.005
1.0
60
UV Threshold
UV Threshold Hysteresis
UV Glitch Filter
UV Propagation Delay
OV PIN
Input Current
UVTH
UVHYST
UVGF
UVPD
OV Threshold
OV Threshold Hysteresis
OV Glitch Filter
OV Propagation Delay
SENSE−
Input Current
VCAP PIN
Internally Regulated Voltage
Undervoltage Lockout
Rising
Falling
Hysteresis
ISET PIN
Input Current
OVTH
OVHYST
OVGF
OVPD
0.985
25
0.5
ISENSE−
20
40
70
μA
SENSE− = 60 V
VVCAP
UVLO
UVLORISE
UVLOFALL
UVLOHYST
3.546
3.6
3.636
V
0 μA ≤ IVCAP ≤ 1 mA, CVCAP = 1 μF
3.4
V
V
mV
VCC rising
VCC falling
Reference Select Threshold
Internal Reference
VISETRSTH
VCLREF
0.2
1
2.65
μA
μA
V
V
Gain of Current Sense Amplifier
AVCSAMP
40
V/V
VISET ≤ VVCAP, TA = −40°C to +85°C
VISET ≤ VVCAP, TA = −40°C to +125°C
If VISET > VISETRSTH, an internal reference (VCLREF) is used
Accuracies included in total sense voltage
accuracies
Accuracies included in total sense voltage
accuracies
VRPFG
0
V
VCC ≤ 10 V
RPFG PIN
Reverse Protection FET Gate Drive
Voltage
Reverse Protection FET Gate Drive
Voltage Offset
RPFG Pull-Down (On) Current
GATE PIN
GATE Drive Voltage
GATE Pull-Down (On) Current
GATE Pull-Up (Off ) Current
Regulation
Fault
0.985
55
4
Typ
6
IOV
0.005
0.005
1.0
30
3.0
230
IISET
2.55
0.005
0.005
2.6
2
50 mV overdrive
UV low to GATE pull-down circuit active
50 mV overdrive
OV high to GATE pull-up circuit active
ΔVRPFG
10
12
14
V
ΔVRPFG = VCC − VRPFG, 60 V ≥ VCC ≥ 14 V, IRPFG ≤ 5 μA
IRPFGND
7
9
12
μA
VRPFG = VCC
ΔVGATE
IGATEDN
IGATEUP
IGATEUP_REG
IGATEUP_FLT
10
20
12
25
14
30
V
μA
ΔVGATE = VCC − VGATE, 60 V ≥ VCC ≥ 14 V, IGATE ≤ 5 μA
VGATE = VCC
−50
−7
−65
−13
−80
−20
μA
mA
ΔVGATE ≥ 2 V, (VSENSE+ − VSENSE−) = 70 mV
ΔVGATE = 2 V
Rev. A | Page 3 of 21
ADM1270
Parameter
CURRENT SENSE VOLTAGE
Sense Voltage Current Limit
(VSENSE+ − VSENSE−)
Foldback Inactive
Data Sheet
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VSENSECL
47
50
53
mV
VISET > 2.65 V, VFLB > 1.1 V, ΔVGATE = 3 V, IGATE = 0 µA
VCBOS
47
22.5
10.0
7
22
0.5
62.5
50
25.0
12.5
10
25
1
53
27.5
15.0
13
28
1.5
mV
mV
mV
mV
mV
mV
mV
VISET = 2.5 V, VFLB > 1.35 V, ΔVGATE = 3 V, IGATE = 0 µA
VISET = 2 V, VFLB > 1.1 V, ΔVGATE = 3 V, IGATE = 0 µA
VISET = 1 V, VFLB > 0.57 V, ΔVGATE = 3 V, IGATE = 0 µA
VISET = 0.5 V, VFLB > 0.3 V, ΔVGATE = 3 V, IGATE = 0 µA
VFLB = 0 V, ΔVGATE = 3 V, IGATE = 0 µA
VISET > 2 V, VFLB = 0.5 V, ΔVGATE = 3 V, IGATE = 0 µA
Circuit breaker trip voltage, VCB = VSENSECL − VCBOS
110
30
1.6
3.5
mV
mV
µs
µs
VISET > 2.65 V
VISET = 0.5 V
−22
2.04
0.12
1.15
105
µA
V
V
µA
µA
Overcurrent fault, 0.2 V ≤ VTIMER ≤ 2 V
Foldback Active
Circuit Breaker Offset
SEVERE OVERCURRENT
Voltage Threshold
Glitch Filter Duration
Response Time
TIMER PIN
TIMER Pull-Up Current
TIMER High Threshold
TIMER Low Threshold
TIMER Pull-Down Current
TIMER_OFF PIN
Power-On Reset Pull-Up Current
Retry Pull-Up Current
TIMER_OFF High Threshold
FOLDBACK (FLB PIN)
Input Current
PWRGD FEEDBACK INPUT (FB_PG PIN)
Input Current
PWRGD Rising Threshold
PWRGD Threshold Hysteresis
Power-Good Glitch Filter
FAULT PIN
Output Low Voltage
Leakage Current
ENABLE PIN
Input High Voltage
Input Low Voltage
Leakage Current
PWRGD PIN
Output Low Voltage
Output Low Voltage
Leakage Current
VSENSEOC
90
20
0.4
100
25
2.0
ITIMERUP
VTIMERH
VTIMERL
ITIMERPD
−18
1.96
0.075
0.85
75
−20
2.0
0.10
IPOR
ITMROFF
VTMROFFH
−18
−0.85
1.96
−20
−1
2.0
−22
−1.15
2.04
µA
µA
V
Initial power-on reset, VTIMER_OFF = 1 V
After fault when GATE is off, VTIMER_OFF = 1 V
IFLB
0.005
0.005
0.2
1
µA
µA
VFLB ≤ 5.5 V, TA = −40°C to +85°C
VFLB ≤ 5.5 V, TA = −40°C to +125°C
IFBPG
0.005
0.005
1.0
30
0.2
1
1.015
35
1.5
µA
µA
V
mV
µs
VFB_PG ≤ 5.5 V, TA = −40°C to +85°C
VFB_PG ≤ 5.5 V, TA = −40°C to +125°C
FB_PG rising
0.005
0.1
0.4
1
V
V
µA
IFAULT = 100 µA
IFAULT = 1 mA
VFAULT = 5.5 V, FAULT output high-Z
0.005
0.4
1
V
V
µA
VEN = 5.5 V
0.005
0.1
0.4
0.4
1
V
V
V
µA
IPWRGD = 100 µA
IPWRGD = 1 mA
VCC = 1.7 V, ISINK = 100 µA,
VPWRGD = 60 V, PWRGD output high-Z
VPGTH
PGHYST
PGGF
0.985
25
0.5
VOL_FAULT
IFAULT
VIH
VIL
IEN
1.2
VOL_PWRGD
VOL_PWRGD
IPWRGD
Rev. A | Page 4 of 21
Timer pin voltage = 0.2 V
Timer pin voltage = 0.05 V
50 mV overdrive
Data Sheet
ADM1270
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VCC/SENSE+
VCAP
UV
OV
ISET
FLB
FB_PG
TIMER_OFF
TIMER
FAULT
ENABLE
PWRGD
GATE
GATE to VCC/SENSE+
SENSE−
RPFG
RPFG to VCC/SENSE+
VSENSE (VSENSE+ − VSENSE−)
Continuous Current into Any Pin
Storage Temperature Range
Operating Temperature Range
Lead Temperature, Soldering (10 sec)
Junction Temperature
Rating
−0.3 V to +66 V
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to VCAP + 0.3 V
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to VCAP + 0.3 V
−0.3 V to VCAP + 0.3 V
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +66 V
−0.3 V to VCC + 0.3 V
−22 V to +0.3 V
−0.3 V to VCC + 0.3 V
−0.3 V to VCC + 0.3 V
−22 V to +0.3 V
±0.3 V
±10 mA
−65°C to +150°C
−40°C to +125°C
300°C
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL CHARACTERISTICS
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
16-Lead, 3 mm × 3 mm LFCSP
16-Lead QSOP
ESD CAUTION
Rev. A | Page 5 of 21
θJA
49.5
106.03
θJC
35.2
28.31
ΨJB
29.6
43.22
Unit
°C/W
°C/W
ADM1270
Data Sheet
13 GATE
14 SENSE–
16 RPFG
15 VCC/SENSE+
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VCAP 1
12 PWRGD
11 FLB
ADM1270
TOP VIEW
UV 3
10 FB_PG
9
GND 7
TIMER_OFF
TIMER 8
FAULT 6
ENABLE 5
OV 4
NOTES
1. THE EXPOSED PAD IS LOCATED ON THE UNDERSIDE
OF THE LFCSP PACKAGE. SOLDER THE EXPOSED PAD
TO THE PRINTED CIRCUIT BOARD (PCB) TO IMPROVE
THERMAL DISSIPATION. THE EXPOSED PAD CAN BE
CONNECTED TO GROUND.
12259-002
ISET 2
Figure 2. 16-Lead LFCSP Pin Configuration
Table 4. 16-Lead LFCSP Pin Function Descriptions
Pin No.
1
Mnemonic
VCAP
2
ISET
3
UV
4
OV
5
ENABLE
6
FAULT
7
8
GND
TIMER
9
TIMER_OFF
10
FB_PG
11
FLB
12
PWRGD
13
GATE
14
SENSE−
Description
Internal Regulated Supply. Place a capacitor with a 1 µF or greater value on this pin to maintain good accuracy.
This pin can be used as a reference to program the ISET pin voltage.
Current Limit. This pin allows the current-limit threshold to be programmed. The default limit is set when this pin
is connected directly to VCAP. To achieve a user defined sense voltage, the current limit can be adjusted using a
resistor divider from VCAP. An external reference can also be used.
Undervoltage Input Pin. An external resistor divider is connected from the supply to this pin to allow an internal
comparator to detect whether the supply is under the UV limit.
Overvoltage Input Pin. An external resistor divider is connected from the supply to this pin to allow an internal
comparator to detect whether the supply is above the OV limit.
Enable Pin. This pin is a digital logic input. This input must be high to allow the ADM1270 controller to begin a
power-up sequence. If this pin is held low, the ADM1270 is prevented from powering up. There is no internal pullup on this pin.
Fault Output. This pin indicates that the device has shut down due to an overcurrent fault condition. The device
can be configured for automatic retry after shutdown by connecting this pin directly to the ENABLE pin.
Ground Pin.
Timer Pin. An external capacitor, CTIMER, sets an SOA overcurrent fault delay. The GATE pin is pulled off when the
voltage on the TIMER pin exceeds the upper threshold.
Timer Off Pin. An external capacitor, CTIMER_OFF, sets an initial timing cycle delay and the SOA off time delay. After an
SOA overcurrent fault has occurred, the GATE pin is pulled off until the voltage on the TIMER_OFF pin exceeds the
threshold.
PWRGD Feedback Input Pin. An external resistor divider is connected from the output voltage to this pin to allow
an internal comparator to detect when the output voltage is above the PWRGD threshold.
Foldback Pin. A foldback resistor divider is placed from the source of the FET to this pin. Foldback reduces the
current limit when the source voltage drops. The foldback feature ensures that the power through the FET is not
increased beyond the SOA limits.
Power-Good Signal. This signal indicates that the supply is within tolerance. This signal is based on the voltage
present on the FB_PG pin.
Gate Output Pin. This pin is the gate drive of an external P-channel FET. This pin is driven by the FET drive
controller, which provides a pull-down current to charge the FET gate pin. The FET drive controller regulates to a
maximum load current by regulating the GATE pin. GATE is held off when the supply is below the undervoltage
lockout (UVLO).
Negative Current Sense Input Pin. A sense resistor between the VCC/SENSE+ pin and the SENSE− pin sets the
analog current limit. The hot swap operation of the ADM1270 controls the external FET gate to maintain the sense
voltage (VSENSE+ − VSENSE−). This pin also connects to the FET drain pin.
Rev. A | Page 6 of 21
Data Sheet
Pin No.
15
Mnemonic
VCC/SENSE+
16
RPFG
N/A1
EP
1
ADM1270
Description
Positive Supply Input Pin (VCC). A UVLO circuit resets the device when a low supply voltage is detected. GATE is
held off when the supply is below UVLO. No sequencing is required.
Positive Current Sense Input Pin (SENSE+). This pin connects to the main supply input. A sense resistor between
the VCC/SENSE+ pin and the SENSE− pin sets the analog current limit. The hot swap operation of the ADM1270
controls the external FET gate to maintain the sense voltage (VSENSE+ − VSENSE−).
Reverse Protection FET Gate Driver Output. Connect this pin to the gate of the external reverse polarity protection
P-channel FET for low voltage drop operation.
Exposed Pad. The exposed pad is located on the underside of the LFCSP package. Solder the exposed pad to the
printed circuit board (PCB) to improve thermal dissipation. The exposed pad can be connected to ground.
N/A = not applicable.
Rev. A | Page 7 of 21
Data Sheet
VCC/SENSE+ 1
16
SENSE–
RPFG 2
15
GATE
VCAP 3
14
PWRGD
ISET 4
ADM1270
13
FLB
UV 5
TOP VIEW
(Not to Scale)
12
FB_PG
OV 6
11
TIMER_OFF
ENABLE 7
10
TIMER
FAULT 8
9
GND
12259-003
ADM1270
Figure 3. 16-Lead QSOP Pin Configuration
Table 5. 16-Lead QSOP Pin Function Descriptions
Pin No.
1
Mnemonic
VCC/SENSE+
2
RPFG
3
VCAP
4
ISET
5
UV
6
OV
7
ENABLE
8
FAULT
9
10
GND
TIMER
11
TIMER_OFF
12
FB_PG
13
FLB
14
PWRGD
15
GATE
16
SENSE−
Description
Positive Supply Input Pin (VCC). A UVLO circuit resets the device when a low supply voltage is detected. GATE is
held off when the supply is below UVLO. No sequencing is required.
Positive Current Sense Input Pin (SENSE+). This pin connects to the main supply input. A sense resistor between
the VCC/SENSE+ pin and the SENSE− pin sets the analog current limit. The hot swap operation of the ADM1270
controls the external FET gate to maintain the sense voltage (VSENSE+ − VSENSE−).
Reverse Protection FET Gate Driver Output. Connect this pin to the gate of the external reverse polarity protection
P-channel FET for low voltage drop operation.
Internal Regulated Supply. Place a capacitor with a 1 μF or greater value on this pin to maintain good accuracy.
This pin can be used as a reference to program the ISET pin voltage.
Current Limit. This pin allows the current-limit threshold to be programmed. The default limit is set when this pin
is connected directly to VCAP. To achieve a user defined sense voltage, the current limit can be adjusted using a
resistor divider from VCAP. An external reference can also be used.
Undervoltage Input Pin. An external resistor divider is connected from the supply to this pin to allow an internal
comparator to detect whether the supply is under the UV limit.
Overvoltage Input Pin. An external resistor divider is connected from the supply to this pin to allow an internal
comparator to detect whether the supply is above the OV limit.
Enable Pin. This pin is a digital logic input. This input must be high to allow the ADM1270 controller to begin a
power-up sequence. If this pin is held low, the ADM1270 is prevented from powering up. There is no internal pullup on this pin.
Fault Output. This pin indicates that the device has shut down due to an overcurrent fault condition. The device
can be configured for automatic retry after shutdown by connecting this pin directly to the ENABLE pin.
Ground Pin.
Timer Pin. An external capacitor, CTIMER, sets an SOA overcurrent fault delay. The GATE pin is pulled off when the
voltage on the TIMER pin exceeds the upper threshold.
Timer Off Pin. An external capacitor, CTIMER_OFF, sets an initial timing cycle delay and the SOA off time delay. After an
SOA overcurrent fault has occurred, the GATE pin is pulled off until the voltage on the TIMER_OFF pin exceeds the
threshold.
PWRGD Feedback Input Pin. An external resistor divider is connected from the output voltage to this pin to allow
an internal comparator to detect when the output voltage is above the PWRGD threshold.
Foldback Pin. A foldback resistor divider is placed from the source of the FET to this pin. Foldback reduces the
current limit when the source voltage drops. The foldback feature ensures that the power through the FET is not
increased beyond the SOA limits.
Power-Good Signal. This signal indicates that the supply is within tolerance. This signal is based on the voltage
present on the FB_PG pin.
Gate Output Pin. This pin is the gate drive of an external P-channel FET. This pin is driven by the FET drive
controller, which provides a pull-down current to charge the FET gate pin. The FET drive controller regulates to a
maximum load current by regulating the GATE pin. GATE is held off when the supply is below UVLO.
Negative Current Sense Input Pin. A sense resistor between the VCC/SENSE+ pin and the SENSE− pin sets the
analog current limit. The hot swap operation of the ADM1270 controls the external FET gate to maintain the sense
voltage (VSENSE+ − VSENSE−). This pin also connects to the FET drain pin.
Rev. A | Page 8 of 21
Data Sheet
ADM1270
TYPICAL PERFORMANCE CHARACTERISTICS
3.65
500
LOAD = 100µA
LOAD = 500µA
LOAD = 1mA
LOAD = 100µA
LOAD = 500µA
LOAD = 1mA
450
400
3.63
3.61
ICC (µA)
VVCAP (V)
350
300
250
200
3.59
150
100
3.57
50
25°C
–5°C
85°C
125°C
0
TJ (°C)
–40°C
25°C
–5°C
85°C
12259-007
–40°C
12259-004
3.55
125°C
TJ (°C)
Figure 4. VVCAP vs. Junction Temperature (TJ), Different Loads
Figure 7. Supply Current (ICC) vs. Junction Temperature (TJ), Different Loads
400
3.610
398
396
3.605
ICC (µA)
VVCAP (V)
394
3.600
392
390
388
386
3.595
384
0
0.2
0.4
0.6
0.8
1.0
ILOAD (mA)
380
12259-005
3.590
0
0.2
0.6
0.4
0.8
1.0
ILOAD (mA)
Figure 5. VVCAP vs. Load Current (ILOAD)
12259-008
382
Figure 8. Supply Current (ICC) vs. Load Current (ILOAD)
420
3.610
LOAD = 100µA
LOAD = 500µA
LOAD = 1mA
LOAD = 100µA
LOAD = 500µA
LOAD = 1mA
400
3.605
ICC (µA)
3.600
360
340
3.595
3.590
0
10
20
30
40
VIN (V)
50
Figure 6. VVCAP vs. Input Voltage (VIN), Different Loads
300
0
10
30
20
VCC (V)
40
50
12259-009
320
12259-006
VVCAP (V)
380
Figure 9. Supply Current (ICC) vs. Supply Voltage (VCC), Different Loads
Rev. A | Page 9 of 21
ADM1270
16
14
12
10
8
6
4
–10
10
30
70
50
90
110
130
9.2
9.0
8.8
8.6
8.4
–40
–20
20
0
40
60
80
100
120
140
TEMPERATURE (°C)
Figure 10. VVCAP Overcurrent (OC) Threshold vs. Temperature,
Different Input Voltages
Figure 13. RPFG Pull-Down Current (IRPFGND) vs. Temperature,
Different Input Voltages
0.070
13.0
4V
25V
50V
CURRENT SENSE VOLTAGE (V)
VIN = 14V
VIN = 25V
VIN = 50V
12.6
12.4
VGATE (V)
9.4
8.0
–60
12259-010
–30
TEMPERATURE (°C)
12.8
9.6
8.2
2
0
–50
VIN = 14V
VIN = 25V
VIN = 50V
9.8
12259-013
VVCAP OC THRESHOLD (mA)
18
10.0
VIN = 4.5V
VIN = 6V
VIN = 10V
RPFG PULL-DOWN CURRENT (µA)
20
Data Sheet
12.2
12.0
11.8
11.6
11.4
0.065
0.060
0.055
0.050
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
0.045
2.50
RPFG VOLTAGE (V)
12.6
12.4
12.2
12.0
11.8
11.6
11.4
11.0
–60
–40
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
140
12259-012
11.2
Figure 12. RPFG Voltage (VRPFG) vs. Temperature, Different Input Voltages
2.56
2.58
2.60
2.62
2.64
2.66
2.68
2.70
Figure 14. Current Sense Voltage vs. ISET Voltage (VISET),
Different Input Voltages
REFERENCE SELECT THRESHOLD VOLTAGE (V)
12.8
VIN = 14V
VIN = 25V
VIN = 50V
2.54
VISET (V)
Figure 11. GATE Voltage (VGATE) vs. Temperature, Different Input Voltages
13.0
2.52
2.65
2.60
2.55
2.50
–60
–40
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
140
12259-015
–40
12259-011
11.0
–60
12259-014
11.2
Figure 15. Reference Select Threshold Voltage (VISETRSTH) vs. Temperature,
VIN = 4 V
Rev. A | Page 10 of 21
Data Sheet
ADM1270
–18.0
–40°C
–5°C
+25°C
+85°C
+125°C
0.065
–40°C
–5°C
+25°C
+85°C
+125°C
–18.5
POR TIMER OFF CURRENT (µA)
REFERENCE SELECT THRESHOLD VOLTAGE (V)
0.070
0.060
0.055
0.050
–19.0
–19.5
–20.0
–20.5
–21.0
2.52
2.54
2.60
2.58
2.56
2.64
2.62
2.66
2.68
2.70
VISET (V)
–22.0
12259-016
0.045
2.50
–19.5
–20.0
–20.5
–21.0
–21.5
25
30
35
45
40
55
50
–19.0
–19.5
–20.0
–20.5
–21.0
–5
15
35
55
75
95
115
135
TEMPERATURE (°C)
–22.0
–45
12259-017
–25
–0.7
15
35
55
75
95
115
135
Figure 20. POR Timer Off Current (IPOR) vs. Temperature,
Different Input Voltages
7
4V
6V
10V
20V
50V
–0.6
–5
TEMPERATURE (°C)
Figure 17. Timer Current vs. Temperature, Different Input Voltages
–0.5
–25
12259-020
–21.5
–22.0
–45
OV INPUT RISE
OV INPUT FALL
6
5
–0.8
VGATE (V)
–0.9
–1.0
–1.1
–1.2
4
3
2
–1.3
1
–1.4
–1.5
–45
–25
–5
15
35
55
75
95
115
TEMPERATURE (°C)
135
12259-018
TIMER OFF CURRENT (µA)
20
Figure 18. Timer Off Current (ITMROFF) vs. Temperature,
Different Input Voltages
0
0.90
0.95
1.00
1.05
OV INPUT VOLTAGE (V)
Figure 21. VGATE vs. OV Input Voltage
Rev. A | Page 11 of 21
1.10
12259-021
TIMER CURRENT (µA)
–19.0
15
4V
6V
10V
20V
50V
–18.5
POR TIMER OFF CURRENT (µA)
–18.5
10
Figure 19. POR Timer Off Current (IPOR) vs. Input Voltage (VIN),
Different Temperatures
–18.0
4V
6V
10V
20V
50V
5
INPUT VOLTAGE (V)
Figure 16. Reference Select Threshold Voltage (VISETRSTH) vs. ISET Voltage (VISET),
Different Temperatures
–18.0
0
12259-019
–21.5
ADM1270
Data Sheet
0.970
0.04
0.03
1.00
0.02
0.01
UV RISE
UV FALL
HYSTERESIS
0.95
–60
–40
–20
HYSTERESIS (V)
1.05
0
20
40
60
80
100
0
140
120
TEMPERATURE (°C)
4V POWER-GOOD FALL
25V POWER-GOOD FALL
50V POWER-GOOD FALL
0.965
0.960
0.955
0.950
–60
12259-022
UV THRESHOLD VOLTAGE (V)
0.05
POWER-GOOD FALLING THRESHOLD (V)
0.06
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
Figure 22. UV Threshold Voltage vs. Temperature
12259-025
1.10
Figure 25. Power-Good Falling Threshold vs. Temperature,
Different Input Voltages
1.05
0.03
0.108
0.02
0.01
0.95
SEVERE OC THRESHOLD (V)
1.00
HYSTERESIS (V)
OV THRESHOLD VOLTAGE (V)
4V OV
25V OC
50V OC
0.106
0.104
0.102
–40
–20
0
40
20
100
80
60
120
0
140
TEMPERATURE (°C)
0.100
–60
12259-023
0.90
–60
0
20
40
60
80
100
120
140
Figure 26. Severe Overcurrent (OC) Threshold vs. Temperature,
Different Input Voltages
0.07
4V POWER-GOOD RISE
25V POWER-GOOD RISE
50V POWER-GOOD RISE
–40°C
–5°C
–25°C
–85°C
–125°C
0.06
0.995
VSENSE (V)
0.05
0.990
0.04
0.03
0.02
0.985
0.980
–60
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
140
Figure 24. Power-Good Rising Threshold vs. Temperature,
Different Input Voltages
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
FLB (V)
Figure 27. Sense Voltage (VSENSE ) vs. FLB, Different Temperatures
Rev. A | Page 12 of 21
12259-027
0.01
12259-024
POWER-GOOD RISING THRESHOLD (V)
–20
TEMPERATURE (°C)
Figure 23. OV Threshold vs. Temperature
1.000
–40
12259-026
OV RISE
OV FALL
HYSTERESIS
Data Sheet
0.07
ADM1270
2.02
0.06
OC TIMER THRESHOLD (V)
–40°C
–5°C
+25°C
+85°C
+125°C
VSENSE (V)
0.05
0.04
0.03
0.02
4V
50V
2.01
2.00
1.99
0
0.5
1.0
1.5
2.0
2.5
3.5
3.0
VISET (V)
Figure 28. Sense Voltage (VSENSE) vs. ISET Voltage (VISET),
Different Temperatures
50
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
2.01
OC TIMER_OFF THRESHOLD (V)
OC INPUT CURRENT (µA)
40
–40
Figure 31. OC TIMER Threshold vs. Temperature, Different Input Voltages
10mV
20mV
30mV
40mV
50mV
60mV
45
1.98
–60
12259-028
0
12259-031
0.01
35
30
25
20
15
10
4V
50V
2.00
1.99
1.98
–40
–20
0
40
20
60
80
100
120
140
TEMPERATURE (°C)
Figure 29. OC Input Current vs. Temperature, Different Sense Voltages (VSENSE)
50
45
35
30
25
20
15
–40°C
–5°C
+25°C
+85°C
+125°C
10
5
0
0
0.5
1.0
1.5
2.0
VSENSE (V)
2.5
3.0
3.5
12259-030
OC INPUT CURRENT (µA)
40
Figure 30. OC Input Current vs. Sense Voltage (VSENSE), Different Temperatures
Rev. A | Page 13 of 21
1.97
–60
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 32. OC TIMER_OFF Threshold vs. Temperature,
Different Input Voltages
140
12259-032
0
–60
12259-029
5
ADM1270
Data Sheet
TYPICAL APPLICATION CIRCUIT
RSENSE
VIN
VOUT
VCC/SENSE+
Q2
SENSE–
Q1
RPFG
LOAD
VCAP
LDO
+
R1
–
IOUT
UV
+
1V
R2
OV
–
GATE DRIVE/
LOGIC
GATE
–
1V
+
R4
R8
FLB
REF
SELECT
+
R7
FB_PG
CURRENTLIMIT
CONTROL
R3
CURRENT
LIMIT
–
TIMER
ON
R5
TIMER_OFF
R9
TIMER
TIMEOUT
ENABLE
FAULT
TIMER
VCB
PWRGD
GND
Figure 33. Typical Application Circuit
Rev. A | Page 14 of 21
CTIMER
CTIMER_OFF
12259-033
ISET
Data Sheet
ADM1270
THEORY OF OPERATION
connected to the TIMER pin and the TIMER_OFF pin. This
current-limit time helps to maintain the FET in its SOA.
When circuit boards are inserted into a live backplane, discharged
supply bypass capacitors draw large transient currents from the
backplane power bus as they charge. These transient currents
can cause permanent damage to connector pins, as well as voltage
dips on the backplane supply that can reset other boards in the
system.
In addition to the timer function, there is a foldback pin (FLB)
that is used to provide additional FET protection. The current
limit is linearly reduced by the voltage on the FLB pin, so that
for large drain to source voltage (VDS) voltage drops, the actual
current limit used by the device is lower, again helping to ensure
the FET is kept within its SOA.
The ADM1270 is designed to control the inrush current when
powering on the system, allowing a board to be inserted safely
into a live backplane by protecting it from excess currents.
A minimum voltage clamp ensures that even if the FLB voltage
is 0 V, the current is never reduced to zero, which otherwise
prevents the device from powering up.
The ADM1270 is a current-limiting controller that provides
inrush current limiting and overcurrent protection for modular
or battery-powered systems. The voltage developed across a
sense resistor in the power path is measured with a current
sense amplifier via the VCC/SENSE+ and SENSE− pins. A
default limit of 50 mV is set, but this limit can be adjusted, if
required, using a resistor divider network from the VCAP pin
to the ISET pin.
The ADM1270 features OV and UV protection, programmed
using external resistor dividers on the UV and OV pins.
A PWRGD signal can be used to indicate when the output
supply is greater than a voltage programmed using an external
resistor divider on the FB_PG pin.
To protect the system from a reverse polarity input supply, there
is a provision made to control an additional external P-channel
FET with the RPFG pin. This feature allows for a low on-resistance,
low voltage drop FET to be used in place of a diode to perform
the same function, thus saving power losses and improving overall
efficiency. The reverse voltage protection FET prevents negative
input voltages that can damage the load or the ADM1270.
The ADM1270 limits the current through the sense resistor by
controlling the gate voltage of an external P-channel FET in the
power path, via the GATE pin. The sense voltage and, therefore,
the load current is maintained below the preset maximum. The
ADM1270 protects the external FET by limiting the time that
the FET remains on while the current is at its maximum value.
This current-limit time is set by the choice of capacitors
VCC/SENSE+ SENSE–
RPFG
ADM1270
VCAP
LDO
UV
+
+
–
IOUT
1V
GATE DRIVE/
LOGIC
GATE
–
1V
+
REF
SELECT
FLB
+
CURRENTLIMIT
CONTROL
CURRENT
LIMIT
FB_PG
–
TIMER
ON
TIMER
TIMEOUT
VCB
ENABLE FAULT PWRGD
TIMER_OFF
TIMER
GND
Figure 34. Simplified Functional Block Diagram
Rev. A | Page 15 of 21
12259-034
OV
ISET
–
ADM1270
Data Sheet
POWERING THE ADM1270
CURRENT SENSE INPUTS
The load current is monitored by measuring the voltage drop
across an external current sense resistor, RSENSE (see Figure 35).
An internal current sense amplifier provides a gain of 40 to the
voltage drop detected across RSENSE. The result is compared to an
internal reference and is used by the hot swap control logic to
detect an overcurrent condition.
RSENSE
VCC/SENSE+
VCAP
LDO
SENSE–
–
Q1
+
GATE
–
REFERENCE
VCAP
LDO
SENSE–
+
Q1
–
40×
2V
GATE
REF
SELECT
ISET
+
CURRENTLIMIT
CONTROL
FLB
CURRENT
LIMIT
–
GND
Figure 36. Current-Limit Reference Selection
The FLB voltage varies during different modes of operation
and, therefore, is clamped to a minimum level of 200 mV. This
behavior prevents zero current flow due to the current limit
being set too low. Figure 37 provides an example of how the
FLB and ISET voltages interact during startup as the ADM1270
turns on the FET and charges the load capacitance. Depending
on how the foldback feature is configured, the transition point
varies to ensure that the FET operates within the correct limits.
40×
+
VCC/SENSE+
12259-036
A supply voltage from 4 V to 60 V is required to power the
ADM1270 via the VCC/SENSE+ pin. The VCC/SENSE+ pin
provides the majority of the bias current for the device; the
remainder of the current needed to control the gate drive and to
best regulate the gate to source voltage (VGS) is supplied by the
SENSE− pin.
4V TO 60V
RSENSE
4V TO 60V
VISET
FLB
CURRENT
LIMIT
12259-035
2V
GND
ISET
CURRENT-LIMIT
REFERENCE
Figure 35. Hot Swap Current Sense Amplifier
CURRENT-LIMIT REFERENCE
An internal current-limit reference selector block continuously
compares the ISET and FLB voltages to determine which
voltage is the lowest at any given time; the lowest voltage is used
as the current-limit reference. This behavior ensures that the
programmed current limit, ISET, is used in normal operation,
and that the foldback feature reduces the current limit when
required during startup and/or fault conditions.
0.2V
TIME
12259-037
The current-limit reference voltage determines the load current
at which the ADM1270 limits the current during an overcurrent
event. This reference voltage is compared to the amplified current
sense voltage to determine when the current-limit threshold is
reached.
Figure 37. Interaction of Foldback (FLB) and ISET Current Limits
SETTING THE CURRENT LIMIT (ISET)
The maximum current limit is partially determined by selecting
a sense resistor to match the current sense voltage limit on the
controller for the desired load current. However, as currents
become larger, the sense resistor value decreases for a given
current sense voltage. Choosing an appropriate current sense
resistor can be difficult due to the limited selection of low value
resistors. The ADM1270 provides an adjustable current sense
voltage limit to handle this issue. The device allows the user to
program the required current sense voltage limit from 12.5 mV
to 62.5 mV.
Rev. A | Page 16 of 21
Data Sheet
ADM1270
FOLDBACK
The default value is 50 mV and is achieved by connecting the
ISET pin directly to the VCAP pin. This circuit configuration
configures the device to use an internal 2 V reference, which
results in 50 mV at the sense inputs (see Figure 38).
RSENSE
4V TO 60V
VCC/SENSE+
VCAP
Foldback is a method to actively reduce the current limit as the
voltage drop across the FET increases. This technique keeps the
power dissipation in the FET at a minimum during power-up,
overcurrent, or short-circuit events. It also reduces the need to
oversize the FET to accommodate worst-case conditions,
resulting in board size and cost savings.
LDO
SENSE–
Q1
Assuming that the supply voltage remains constant and within
tolerance, the ADM1270 detects the voltage drop across the FET
by sensing output voltage through a resistor divider. The device,
therefore, relies on the principle that the drain of the FET is at
the maximum expected supply voltage, and that the magnitude
of the output voltage is relative to that of the VDS of the FET.
Using a resistor divider from the output voltage to the FLB pin,
the relationship from VOUT, and thus VDS, to VFLB can be derived.
–
+
40×
2V
ISET
GATE
REF
SELECT
+
CURRENTLIMIT
CONTROL
12259-038
FLB
CURRENT
LIMIT
–
GND
Figure 38. Fixed 50 mV Current Sense Limit
To program the sense voltage from 12.5 mV to 62.5 mV, an
external resistor divider sets the reference voltage on the ISET
pin (see Figure 39).
RSENSE
4V TO 60V
VCC/SENSE+
VCAP
LDO
SENSE–
+
Q1
To ensure that the SOA characteristics of a particular FET are
not violated, the minimum current for this clamp varies from
design to design. However, the current-limit reference fixes this
clamp at 200 mV, which equals 10 mV across the sense resistor.
Therefore, the main ISET voltage can be adjusted to adjust the
clamp to the required percentage current reduction. For example,
if VISET equals 1.6 V, set the clamp at 25% of the maximum current.
–
40×
2V
GATE
REF
SELECT
+
FLB
CURRENTLIMIT
CONTROL
–
CURRENT
LIMIT
TIMER
12259-039
ISET
Design the resistor divider to result in a voltage equal to VISET/2
when VOUT falls below the desired level. This voltage must be
well below the working tolerance of the supply rail. As VOUT
continues to drop, the current-limit reference follows VFLB
because it is now the lowest voltage input to the current-limit
reference selector block, resulting in a reduction of the current
limit and, therefore, the regulated load current. To prevent the
current from decreasing to zero, a clamp activates when VFLB
reaches 200 mV. The current limit cannot drop below this level.
GND
Figure 39. Adjustable 12.5 mV to 62.5 mV Current Sense Limit
The VCAP pin has a 3.6 V internally generated voltage that can
set a voltage at the ISET pin. Assuming that VISET equals the
voltage on the ISET pin, select the resistor divider values to set
the ISET voltage as follows:
VISET = VSENSE × 40
The TIMER pin handles the timing function with an external
capacitor, CTIMER. The two TIMER pin comparator thresholds
are VTIMERL (0.1 V) and VTIMERH (2.0 V). There are two timing
current sources as well: a 20 µA pull-up current and a 1 µA
pull-down current.
These current and voltage levels, in combination with the user
chosen value of CTIMER, determine the fault current-limit time
and the on-time of the hot swap retry duty cycle. The TIMER
pin capacitor value is determined using the following equation:
where VSENSE is the current sense voltage limit.
CTIMER = (tON × 20 µA)/VTIMERH
The VCAP rail also can be used as the pull-up supply for setting
other pins. To guarantee that VCAP meets its accuracy
specifications, do not apply a load to the VCAP pin greater
than 100 µA.
where:
tON is the time that the FET is allowed to spend in regulation at
the current limit.
VTIMERH is the TIMER high threshold.
The choice of FET is based on matching this time with the SOA
characteristics of the FET. Foldback can also be used to simplify
the selection.
Rev. A | Page 17 of 21
ADM1270
Data Sheet
When the voltage across the sense resistor reaches the circuit
breaker trip voltage, VCB, the 20 µA TIMER pull-up current is
activated. The ADM1270 begins to regulate the load current at
the current limit, initiating a rising voltage ramp on the TIMER
pin. If the sense voltage falls below this circuit breaker trip voltage
before the TIMER pin reaches VTIMERH, the 20 µA pull-up current is
disabled, and the 1 µA pull-down current is enabled. If the voltage
on the TIMER pin falls below VTIMERL, the TIMER pin is
discharged to GND using a strong pull-down current on the
TIMER pin.
defined window of operation when the initial timing cycle
terminates, the device is ready to start a hot swap operation.
However, if the overcurrent condition is continuous and the sense
voltage remains above the circuit breaker trip voltage, the 20 µA
pull-up current remains active, and the FET remains in
regulation. This condition allows the TIMER pin to reach VTIMERH
and to initiate the GATE shutdown, and the FAULT pin is pulled
low immediately.
This fault current-limit off time is determined by the following
equation:
The circuit breaker trip voltage is not the same as the hot swap
sense voltage current limit. There is a small circuit breaker offset,
VCBOS, which causes the timer to start shortly before the current
reaches the defined current limit.
In latch-off mode, the TIMER pin is discharged to GND when
it reaches the VTIMERH threshold. The TIMER_OFF pin begins to
charge up. While the TIMER_OFF pin is ramping up, the hot swap
controller remains off and cannot be turned back on, and the
FAULT pin remains low. When the voltage on the TIMER_OFF
pin rises above the VTMROFFH threshold, the hot swap controller
can be reenabled by toggling the ENABLE pin from high to low
and then high again.
TIMER_OFF
The TIMER_OFF pin handles two timing functions with an
external capacitor, CTIMER_OFF. There is one TIMER_OFF pin
comparator threshold at VTMROFFH (2.0 V). There are two timing
current sources, a 20 µA pull-up current and a 1 µA pull-up
current.
These current and voltage levels, in combination with the user
chosen value of CTIMER_OFF, determine the initial power-on reset
time and also set the fault current-limit off time.
When VCC is connected to the input supply, the internal supply
(VCAP) of the ADM1270 must charge up. VCAP starts up and
settles in a very short time. When the UVLO threshold voltage is
exceeded at VCAP, the device emerges from reset. During this first
brief reset period, the GATE and TIMER pins are both held low.
The ADM1270 then proceeds through an initial timing cycle.
The TIMER_OFF pin is pulled high with 20 µA. When the
TIMER_OFF pin reaches the VTMROFFH threshold (2.0 V), the
initial timing cycle is complete. This initial power-on reset
duration is determined by the following equation:
tINITIAL = VTMROFFH × (CTIMER_OFF/20 µA)
For example, a 100 nF capacitor results in a delay of approximately
10 ms. If the UV and OV inputs indicate that VCC is within the
At the completion of this initial power-on reset cycle, the
TIMER_OFF pin is ready to perform a second function. When
the voltage at the TIMER pin exceeds the fault current-limit
time threshold voltage of VTIMERH (2.0 V), the 1 µA pull-up
current is activated on TIMER_OFF, and CTIMER_OFF begins to
charge initiating a voltage ramp on the TIMER_OFF pin. When
the TIMER_OFF pin reaches VTMROFFH, the TIMER_OFF fault
current-limit off time is complete.
tTIMER_OFF = VTMROFFH × (CTIMER_OFF/1 µA)
For example, a 100 nF capacitor results in an off time of
approximately 200 ms from the time that TIMER exceeds
VTIMERH to the time that TIMER_OFF reaches VTMROFFH.
HOT SWAP RETRY DUTY CYCLE
The ADM1270 turns off the FET after an overcurrent fault and
then uses the capacitor on the TIMER_OFF pin to generate a
delay before automatically retrying the hot swap operation. To
configure the ADM1270 for automatic retry mode, tie the FAULT
pin to the ENABLE pin. Note that a pull-up resistor to VCAP is
required on the FAULT pin.
When an overcurrent fault occurs, the capacitor on the TIMER
pin charges with a 20 µA pull-up current. When the TIMER pin
reaches VTIMERH (2.0 V), the GATE pin is pulled high, turning
off the FET. When the FAULT pin is tied to the ENABLE pin
for automatic retry mode, the TIMER_OFF pin begins to
charge with a 1 µA current source. When the TIMER_OFF pin
reaches VTMROFFH (2.0 V), the ADM1270 automatically restarts
the hot swap operation.
The automatic retry duty cycle is set by the ratio of 1 µA/20 µA
and the ratio of CTIMER/CTIMER_OFF. The retry duty cycle is set by
the following equation:
Duty_Cycle = (CTIMER × 1 µA)/(CTIMER_OFF × 20 µA)
The value of the CTIMER and CTIMER_OFF capacitors
determine the on and off time of this cycle, which are calculated
as follows:
tON = VTIMERH × (CTIMER/20 µA)
tOFF = VTMROFFH × (CTIMER_OFF/1 µA)
A 100 nF capacitor on the TIMER pin gives an on time of
10 ms. A 100 nF capacitor on the TIMER_OFF pin gives an off
time of 200 ms. The device retries continuously in this manner
and can be disabled manually by holding the ENABLE pin low,
or by disconnecting the FAULT pin. To prevent thermal stress
in the FET, a capacitor on the TIMER_OFF pin can be used to
extend the retry time to any desired level.
Rev. A | Page 18 of 21
Data Sheet
ADM1270
RSENSE
4V TO 60V
The circuits driving the GATE and RPFG pins are clamped to less
than 14 V below the VCC/SENSE+ pin. These clamps ensure that
the maximum VGS rating of the external FETs is not exceeded.
The reverse protection FET gate pin (RPFG) drives the gate of
an external PMOSFET. This PMOSFET, Q2, provides reverse
polarity protection to the ADM1270 and the system being
powered. If the VCC and GND pins have been reverse
connected (that is, where power is actually applied to GND),
VCC is negative with respect to the system ground. In this
condition, Q2 prevents current from flowing in the reverse
direction because the gate of Q2 is held at GND, and Q2 is off.
VOUT is not pulled below GND, and the system is protected
against a reverse polarity connection.
In the typical case where power is applied to VCC, the gate is
still pulled down and allows the FET Q2 to turn on and conduct
current in the forward direction. Operating Q2 in this way
provides a low on-resistance, low voltage drop compared to a
diode for reverse polarity protection, giving the system higher
efficiency and more headroom for operation. Figure 33 shows
the connection of Q2 and RPFG for proper operation.
FAST RESPONSE TO SEVERE OVERCURRENT
The ADM1270 includes a separate, high bandwidth, current
sense amplifier to detect a severe overcurrent that is indicative of
a short circuit. The fast response time allows the ADM1270 to
handle events of this type that could otherwise cause catastrophic
damage if not detected and dealt with very quickly. The fast
response circuit ensures that the ADM1270 can detect an
overcurrent event of approximately 200% of the normal current
limit and control the current within approximately 2 µs.
VCC/SENSE+
SENSE–
+
VCAP
–
40×
LDO
UV
+
1V
–
GATE DRIVE/
LOGIC
OV
–
1V
GATE
+
GND
Figure 40. Undervoltage and Overvoltage Supply Monitoring
ENABLE INPUT
The ADM1270 provides a dedicated ENABLE digital input pin.
The ENABLE pin allows the ADM1270 to remain off by using a
hardware signal, even when the voltage on the UV pin is greater
than 1.0 V, and the voltage on the OV pin is less than 1.0 V.
Although the UV pin can be used to provide a digital enable
signal, using the ENABLE pin for this purpose keeps the ability
of the UV pin free to monitor undervoltage conditions.
In addition to the conditions for the UV and OV pins, the
ADM1270 ENABLE input pin must be high for the device to
begin a power-up sequence.
A similar function can be achieved using the UV pin directly.
Alternatively, if the UV divider function is still required, the
configuration shown in Figure 41 can be used.
VIN
SYSTEM CONTROL
ADM1270
UNDERVOLTAGE AND OVERVOLTAGE
The ADM1270 monitors the supply voltage for UV and OV
conditions. The UV and OV pins are connected to the inputs
of the voltage comparators and compared to an internal 1 V
voltage reference.
R1
EN
D1
UV
R2
12259-041
Figure 40 illustrates the voltage monitoring input connections.
An external resistor network divides the supply voltage for
monitoring. An undervoltage event is detected when the voltage
connected to the UV pin falls below 1 V, and the FET is turned
off using the 10 mA pull-up current. Similarly, when an overvoltage
event occurs and the voltage on the OV pin exceeds 1 V, the
FET is turned off using the 10 mA pull-up current.
Q1
12259-040
GATE AND RPFG CLAMPS
Figure 41. Using the UV Pin as an Enable
Diode D1 prevents the external driver pull-up resistor from
affecting the UV threshold. Select Diode D1 using the following
criteria:
(VF × D1) + (VOL × EN) << 1.0 V (IF = VIN/R1)
Ensure that the EN sink current does not exceed the specified
VOL value. If the open-drain device has no pull-up, the diode is
not required.
Rev. A | Page 19 of 21
ADM1270
Data Sheet
POWER GOOD
When the voltage at the FB_PG pin exceeds the 1 V threshold
(indicating that the output voltage has risen), the open-drain
pull-down current is disabled, allowing PWRGD to be pulled
high. The PWRGD pin is an open-drain output that pulls low
when the voltage at the FB_PG pin is lower than the 1 V
threshold minus the hysteresis (power bad). Hysteresis on the
FB_PG pin is fixed at 30 mV. PWRGD is guaranteed to be in a
valid state for VCC ≥ 1.7 V.
The power-good (PWRGD) output can be used to indicate
whether the output voltage exceeds a user defined threshold
and can, therefore, be considered good. The PWRGD output
is set by a resistor divider connected to the FB_PG pin (see
Figure 42).
RSENSE
4V TO 60V
VCC/SENSE+
SENSE–
+
VCAP
LDO
UV
Calculate the power-good threshold using the following
equation:
Q1
VPWRGD = 1 V × (1 + RPG1/RPG2)
–
40×
where:
RPG1 is the resistance from VOUT to FB_PG.
RPG2 is the resistance from FB_PG to GND.
+
–
GATE DRIVE/
LOGIC
–
1V
+
GATE
FB_PG
GND
12259-042
1V
OV
Figure 42. Generation of PWRGD Signal
Rev. A | Page 20 of 21
Data Sheet
ADM1270
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
13
0.50
BSC
PIN 1
INDICATOR
16
1
12
EXPOSED
PAD
1.65
1.50 SQ
1.45
9
TOP VIEW
0.80
0.75
0.70
4
5
8
0.50
0.40
0.30
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
0.20 MIN
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
01-26-2012-A
PIN 1
INDICATOR
0.30
0.25
0.20
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
Figure 43. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very, Very Thin Quad
(CP-16-27)
Dimensions shown in millimeters
0.197 (5.00)
0.193 (4.90)
0.189 (4.80)
16
9
1
8
0.010 (0.25)
0.006 (0.15)
0.069 (1.75)
0.053 (1.35)
0.065 (1.65)
0.049 (1.25)
0.010 (0.25)
0.004 (0.10)
COPLANARITY
0.004 (0.10)
0.244 (6.20)
0.236 (5.99)
0.228 (5.79)
0.025 (0.64)
BSC
SEATING
PLANE
0.012 (0.30)
0.008 (0.20)
8°
0°
0.020 (0.51)
0.010 (0.25)
0.050 (1.27)
0.016 (0.41)
COMPLIANT TO JEDEC STANDARDS MO-137-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.041 (1.04)
REF
09-12-2014-A
0.158 (4.01)
0.154 (3.91)
0.150 (3.81)
Figure 44. 16-Lead Body, Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches (and millimeters)
ORDERING GUIDE
Model 1
ADM1270ACPZ-R2
ADM1270ACPZ-R7
ADM1270ARQZ
ADM1270ARQZ-R7
ADM1270CP-EVALZ
ADM1270RQ-EVALZ
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Body, Shrink Small Outline Package [QSOP]
16-Lead Body, Shrink Small Outline Package [QSOP]
Evaluation Board for 16-Lead LFCSP_WQ
Evaluation Board for 16-Lead QSOP
Z = RoHS Compliant Part.
©2014–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12259-0-4/16(A)
Rev. A | Page 21 of 21
Package Option
CP-16-27
CP-16-27
RQ-16
RQ-16
Brand Code
LNQ
LNQ