ON NCP5314FTR2 Two/three/four−phase buck cpu controller Datasheet

NCP5314
Two/Three/Four−Phase
Buck CPU Controller
The NCP5314 provides full−featured and flexible control for the
latest high−performance CPUs. The IC can be programmed as a two−,
three− or four−phase buck controller, and the per−phase switching
frequency can be as high as 1.2 MHz. Combined with external gate
drivers and power components, the controller implements a compact,
highly integrated multi−phase buck converter.
Enhanced V2™ control inherently compensates for variations in
both line and load, and achieves current sharing between phases. This
control scheme provides the industry’s fastest transient response,
reducing the need for large banks of output capacitors and higher
switching frequency.
The controller meets VR(M)10.x specifications with all the required
functions and protection features.
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MARKING DIAGRAMS
32
1
NCP5314
AWLYYWW
32 PIN QFN
MN SUFFIX
CASE 485J
(Bottom View)
Features
NCP5314
AWLYYWWG
•
•
•
•
Programmable 2/3/4 Phase Operation
♦ Lossless Current Sensing
♦ Enhanced V2 Control Method Provides Fast Transient Response
♦ Programmable Up to 1.2 MHz Switching Frequency Per Phase
♦ 0 to 100% Adjustment of Duty Cycle
♦ Programmable Adaptive Voltage Positioning Reduces Output
Capacitor Requirements
♦ Programmable Soft−Start
Current Sharing
♦ Differential Current Sense Pins for Each Phase
♦ Current Sharing Within 10% Between Phases
Protection Features
♦ Programmable Pulse−by−Pulse Current Limit for Each Phase
♦ “111110” and “111111” DAC Code Fault
♦ Latching Off Overvoltage Protection
♦ Programmable Latching Overcurrent Protection
♦ Undervoltage Lockout
♦ External Enable Control
♦ Three−State MOSFET Driver Control through Driver−On Signal
System Power Management
♦ 6−Bit DAC with 0.5% Tolerance Compatible with VR(M)10.x
Specification
♦ Programmable Lower Power Good Threshold
♦ Power Good Output
Pb−Free Package is Available
LQFP−32
FTB SUFFIX
CASE 873A
A
WL
YY
WW
G
32
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
VID1
VID0
VID5
ENABLE
CS2N
CS2P
CS1N
CS1P
♦
32 31 30 29 28 27 26 25
24
1
23
2
22
3
21
4
20
5
19
6
18
7
17
8
9 10 11 12 13 14 15 16
VID2
VID3
VID4
PWRLS
VFFB
SS
PWRGD
DRVON
ILIM
ROSC
VCC
GATE1
GATE2
GATE3
GATE4
GND
SGND
VDRP
VFB
COMP
CS4N
CS4P
CS3N
CS3P
• Switching Regulator Controller
ORDERING INFORMATION
Device
Package
Shipping†
NCP5314MNR2
32 Pin QFN
2500 Tape & Reel
NCP5314FTR2
LQFP−32
2000 Tape & Reel
NCP5314FTR2G
2000 Tape & Reel
LQFP−32
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2007
January, 2007 − Rev. 10
1
Publication Order Number:
NCP5314/D
PWRGD
R1
1.5 k Typ
3.3 V
CSS
R2
VID2
VID3
VID4
PWRLS
VFFB
SS
PWRGD
DRVON
SGND Near
Socket
VFFB
Connection
8
7
6
5
4
3
2
32
9
1
31
10
VID2
VID3
VID4
30
NCP5314
11
Rdrp
VID5
VID0
VID1
29
Rfb
12
ENABLE
28
13
CAMP
1.5 k Typ
27
14
3.3 V
25
26
CCS4
CCS3
17
18
19
20
21
22
23
ILIM 24
CCS2
ROSC
VCC
GATE1
GATE2
GATE3
GATE4
GND
VID1
VID0
VID5
ENABLE
CS2N
CS2P
CS1N
CS1P
SGND
VDRP
VFB
COMP
CS4N
CS4P
CS3N
CS3P
2
15
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16
RCS2
CCS1
RCS1
RCS4
RCS3
ROSC1
12 V
ROSC2
ATX 12 V
BST
TG
DRN
PGND BG
NCP5355
6
VS
4
CO
5
EN
8
BST
TG
DRN
PGND BG
NCP5355
6
VS
4
CO
5
EN
8
BST
TG
DRN
PGND BG
NCP5355
6
VS
4
CO
5
EN
8
BST
TG
DRN
PGND BG
NCP5355
6
VS
4
CO
5
EN
8
LIN
3
2
1
7
3
2
1
7
3
2
1
7
3
2
1
7
CIN
+
L04
L03
L02
L01
+
COUT
GND
VCORE
NCP5314
Figure 1. Application Diagram, 12 V to 0.8 V − 1.6 V, Four−Phase Converter
NCP5314
MAXIMUM RATINGS
Rating
Value
Unit
150
°C
Lead Temperature Soldering, Reflow (Note 1)
230 peak
°C
Storage Temperature Range
−65 to 150
°C
Operating Junction Temperature
ESD Susceptibility: Human Body Model
2.0
kV
JEDEC Moisture Sensitivity Level (MSL): LQFP
QFN
1
2
−
−
Package Thermal Resistance: RθJA
52
34
°C/W
LQFP
QFN, Pad Soldered to PCB
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. 60 second maximum above 183°C.
MAXIMUM RATINGS
Pin Number
Pin Symbol
VMAX
VMIN
ISOURCE
ISINK
1−3, 30−32
VID0−VID5
18 V
−0.3 V
1.0 mA
1.0 mA
4
PWRGDS
7.0 V
−0.3 V
1.0 mA
1.0 mA
5
VFFB
7.0 V
−0.3 V
1.0 mA
1.0 mA
6
SS
7.0 V
−0.3 V
1.0 mA
1.0 mA
7
PWRGD
18 V
−0.3 V
1.0 mA
20 mA
8
DRVON
7.0 V
−0.3 V
1.0 mA
1.0 mA
9
SGND
1.0 V
−1.0 V
1.0 mA
−
10
VDRP
7.0 V
−0.3 V
1.0 mA
1.0 mA
11
VFB
7.0 V
−0.3 V
1.0 mA
1.0 mA
12
COMP
7.0 V
−0.3 V
1.0 mA
1.0 mA
13
CS4N
18 V
−0.3 V
1.0 mA
1.0 mA
14
CS4P
18 V
−0.3 V
1.0 mA
1.0 mA
15
CS3N
18 V
−0.3 V
1.0 mA
1.0 mA
16
CS3P
18 V
−0.3 V
1.0 mA
1.0 mA
17
GND
−
−
0.4 A, 1.0 ms, 100 mA DC
−
18−21
GATE4−GATE1
18 V
−0.3 V
0.1 A, 1.0 ms, 25 mA DC
0.1 A, 1.0 ms, 25 mA DC
22
VCC
18 V
−0.3 V
−
0.4 A, 1.0 ms, 100 mA DC
23
ROSC
7.0 V
−0.3 V
1.0 mA
1.0 mA
24
ILIM
7.0 V
−0.3 V
1.0 mA
1.0 mA
25
CS1P
18 V
−0.3 V
1.0 mA
1.0 mA
26
CS1N
18 V
−0.3 V
1.0 mA
1.0 mA
27
CS2P
18 V
−0.3 V
1.0 mA
1.0 mA
28
CS2N
18 V
−0.3 V
1.0 mA
1.0 mA
29
ENABLE
18 V
−0.3 V
1.0 mA
1.0 mA
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3
NCP5314
ELECTRICAL CHARACTERISTICS (0°C < TA < 70°C; VCC = 12 V; CGATEx = 100 pF, CCOMP = 0.01 μF,
CSS = 0.1 μF, CVCC = 0.1 μF, RROSC = 32.4 kΩ, V(ILIM) = 1.0 V, DAC Code 010100; unless otherwise noted)
VOLTAGE IDENTIFICATION (VID)
Min
VID Code*
(V)
Voltage Identification DAC (0 = Connected to GND,
1 = Open or Pull−Up to Internal 3.3 V or External 5 V)
Accuracy VID Code (All codes)
Connect VFB to COND,
Measure Comp
Typ
Max
Unit
VOUT No
Load† (V)
−0.5
−
+0.5%
%
VID4
VID3
VID2
VID1
VID0
VID5
0
1
0
1
0
0
0.8375
0.8134
0.8175
0.8216
V
0
1
0
0
1
1
0.8500
0.8259
0.8300
0.8342
V
0
1
0
0
1
0
0.8625
0.8383
0.8425
0.8467
V
0
1
0
0
0
1
0.8750
0.8507
0.8550
0.8593
V
0
1
0
0
0
0
0.8875
0.8632
0.8675
0.8718
V
0
0
1
1
1
1
0.9000
0.8756
0.8800
0.8844
V
0
0
1
1
1
0
0.9125
0.8880
0.8925
0.8970
V
0
0
1
1
0
1
0.9250
0.9005
0.9050
0.9095
V
0
0
1
1
0
0
0.9375
0.9129
0.9175
0.9221
V
0
0
1
0
1
1
0.9500
0.9254
0.9300
0.9347
V
0
0
1
0
1
0
0.9625
0.9378
0.9425
0.9472
V
0
0
1
0
0
1
0.9750
0.9502
0.9550
0.9598
V
0
0
1
0
0
0
0.9875
0.9627
0.9675
0.9723
V
0
0
0
1
1
1
1.0000
0.9751
0.9800
0.9849
V
0
0
0
1
1
0
1.0125
0.9875
0.9925
0.9975
V
0
0
0
1
0
1
1.0250
1.0000
1.0050
1.0100
V
0
0
0
1
0
0
1.0375
1.0124
1.0175
1.0226
V
0
0
0
0
1
1
1.0500
1.0249
1.0300
1.0352
V
0
0
0
0
1
0
1.0625
1.0373
1.0425
1.0477
V
0
0
0
0
0
1
1.0750
1.0497
1.0550
1.0603
V
0
0
0
0
0
0
1.0875
1.0622
1.0675
1.0728
V
1
1
1
1
1
1
OFF
V
1
1
1
1
1
0
OFF
V
1
1
1
1
0
1
1.1000
1.0746
1.0800
1.0854
V
1
1
1
1
0
0
1.1125
1.0870
1.0925
1.0980
V
1
1
1
0
1
1
1.1250
1.0995
1.1050
1.1105
V
1
1
1
0
1
0
1.1375
1.1119
1.1175
1.1231
V
1
1
1
0
0
1
1.1500
1.1244
1.1300
1.1357
V
1
1
1
0
0
0
1.1625
1.1368
1.1425
1.1482
V
1
1
0
1
1
1
1.1750
1.1492
1.1550
1.1608
V
1
1
0
1
1
0
1.1875
1.1617
1.1675
1.1733
V
1
1
0
1
0
1
1.2000
1.1741
1.1800
1.1859
V
1
1
0
1
0
0
1.2125
1.1865
1.1925
1.1985
V
1
1
0
0
1
1
1.2250
1.1990
1.2050
1.2110
V
*VID Code is for reference only.
†VOUT No Load is the input to the error amplifier.
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NCP5314
ELECTRICAL CHARACTERISTICS (0°C < TA < 70°C; VCC = 12 V; CGATEx = 100 pF, CCOMP = 0.01 μF,
CSS = 0.1 μF, CVCC = 0.1 μF, RROSC = 32.4 kΩ, V(ILIM) = 1.0 V, DAC Code 010100; unless otherwise noted)
VOLTAGE IDENTIFICATION (VID) (CONTINUED)
Min
VID Code*
(V)
Voltage Identification DAC (0 = Connected to GND,
1 = Open or Pull−Up to Internal 3.3 V or External 5 V)
Accuracy VID Code (All codes)
Connect VFB to COND,
Measure Comp
Typ
Max
Unit
VOUT No
Load† (V)
−0.5
−
+0.5%
%
VID4
VID3
VID2
VID1
VID0
VID5
1
1
0
0
1
0
1.2375
1.2114
1.2175
1.2236
V
1
1
0
0
0
1
1.2500
1.2239
1.2300
1.2362
V
1
1
0
0
0
0
1.2625
1.2363
1.2425
1.2487
V
1
0
1
1
1
1
1.2750
1.2487
1.2550
1.2613
V
1
0
1
1
1
0
1.2875
1.2612
1.2675
1.2738
V
1
0
1
1
0
1
1.3000
1.2736
1.2800
1.2864
V
1
0
1
1
0
0
1.3125
1.2860
1.2925
1.2990
V
1
0
1
0
1
1
1.3250
1.2985
1.3050
1.3115
V
1
0
1
0
1
0
1.3375
1.3109
1.3175
1.3241
V
1
0
1
0
0
1
1.3500
1.3234
1.3300
1.3367
V
1
0
1
0
0
0
1.3625
1.3358
1.3425
1.3492
V
1
0
0
1
1
1
1.3750
1.3482
1.3550
1.3618
V
1
0
0
1
1
0
1.3875
1.3607
1.3675
1.3743
V
1
0
0
1
0
1
1.4000
1.3731
1.3800
1.3869
V
1
0
0
1
0
0
1.4125
1.3855
1.3925
1.3995
V
1
0
0
0
1
1
1.4250
1.3980
1.4050
1.4120
V
1
0
0
0
1
0
1.4375
1.4104
1.4175
1.4246
V
1
0
0
0
0
1
1.4500
1.4229
1.4300
1.4372
V
1
0
0
0
0
0
1.4625
1.4353
1.4425
1.4497
V
0
1
1
1
1
1
1.4750
1.4477
1.4550
1.4623
V
0
1
1
1
1
0
1.4875
1.4602
1.4675
1.4748
V
0
1
1
1
0
1
1.5000
1.4726
1.4800
1.4874
V
0
1
1
1
0
0
1.5125
1.4850
1.4925
1.5000
V
0
1
1
0
1
1
1.5250
1.4975
1.5050
1.5125
V
0
1
1
0
1
0
1.5375
1.5099
1.5175
1.5251
V
0
1
1
0
0
1
1.5500
1.5224
1.5300
1.5377
V
0
1
1
0
0
0
1.5625
1.5348
1.5425
1.5502
V
0
1
0
1
1
1
1.5750
1.5472
1.5550
1.5628
V
0
1
0
1
1
0
1.5875
1.5597
1.5675
1.5753
V
0
1
0
1
0
1
1.6000
1.5721
1.5800
1.5879
V
*VID Code is for reference only.
†VOUT No Load is the input to the error amplifier.
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NCP5314
ELECTRICAL CHARACTERISTICS (0°C < TA < 70°C; VCC = 12 V; CGATEx = 100 pF, CCOMP = 0.01 μF,
CSS = 0.1 μF, CVCC = 0.1 μF, RROSC = 32.4 kΩ, V(ILIM) = 1.0 V, DAC Code 010100; unless otherwise noted)
Test Conditions
Characteristic
Min
Typ
Max
Unit
400
600
800
mV
−
0.1
1.0
μA
VID Inputs
Input Threshold
VID5, VID4, VID3, VID2, VID1, VID0
VID Pin Current
VID5, VID4, VID3, VID2, VID1, VID0 = 0 V
SGND Bias Current
SGND < 300 mV, All DAC Codes
SGND Voltage Compliance Range
−
10
20
40
μA
−200
−
300
mV
85
100
115
mV
0.475
0.500
0.525
V/V
Power Good
Upper Threshold, Offset from No Load Set Point
Lower Threshold Constant
PWRGDS/No Load Set Point
Output Low Voltage
VFFB = 1.0 V, IPWRGD = 4.0 mA
−
0.15
0.40
V
Delay
VFFB low to PWRGD low
50
232
600
μs
170
200
250
mV
0.7
0.8
V
Overvoltage Protection
−
OVP Threshold above VID
Enable Input
Start Threshold
Gates switching, SS high
0.6
Stop Threshold
Gates not switching, SS low
0.4
0.5
0.6
V
−
200
−
mV
Hysteresis
Input Pull−Up Voltage
−
1.0 MΩ to GND
Input Pull−Up Resistance
2.7
2.9
3.3
V
−
7.0
10
20
kΩ
−
−
0.1
1.0
μA
Voltage Feedback Error Amplifier
VFB Bias Current
40
70
100
μA
−
40
70
100
μA
Transconductance
(Note 2)
1.1
1.3
1.5
mmho
Open Loop DC Gain
(Note 2)
72
80
−
dB
CCOMP = 30 pF (Note 2)
−
4.0
−
MHz
(Note 2)
−
60
−
dB
2.4
2.7
−
V
COMP Source Current
COMP = 0.5 V to 2.0 V
COMP Sink Current
Unity Gain Bandwidth
PSRR @ 1.0 kHz
COMP Max Voltage
VFB = 0 V
COMP Min Voltage
VFB = 1.6 V
−
50
150
mV
Minimum Pulse Width
Measured from CSxP to GATEx,
VFB = CSxN = 0.5, COMP = 0.5 V,
60 mV step between CSxP and CSxN;
Measure at GATEx = 1.0 V
−
40
100
ns
Transient Response Time
Measured from CSxN to GATEx,
COMP = 2.1 V, CSxP = CSxN = 0.5 V,
CSxN stepped from 1.2 V to 2.0 V
−
40
60
ns
Channel Startup Offset
CSxP = CSxN = VFB = 0, Measure
Vcomp when GATEx switch high
0.35
0.62
0.75
V
Artificial Ramp Amplitude
50% duty cycle
−
100
−
mV
2.3
−
−
V
−
−
0.2
V
PWM Comparators
MOSFET Driver Enable (DRVON)
Output High
DRVON floating
Output Low
−
Pull−Down Resistance
DRVON = 1.5 V, ENABLE = 0 V,
R = 1.5 V/I(DRVON)
35
70
140
kΩ
Source Current
DRVON = 1.5 V
0.5
3.0
6.5
mA
2. Guaranteed by design, not tested in production.
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NCP5314
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; VCC = 12 V; CGATEx = 100 pF, CCOMP = 0.01 μF,
CSS = 0.1 μF, CVCC = 0.1 μF, RROSC = 32.4 kΩ, V(ILIM) = 1.0 V, DAC Code 010100; unless otherwise noted)
Characteristic
Test Conditions
Min
Typ
Max
Unit
V
GATES
High Voltage
Measure GATEx, IGATEx = 1.0 mA
−
2.70
−
Low Voltage
Measure GATEx, IGATEx = 1.0 mA
−
0.5
0.7
V
Rise Time GATE
0.8 V < GATEx < 2.0 V, VCC = 10 V
−
5.0
10
ns
Fall Time GATE
2.0 V > GATEx > 0.8 V, VCC = 10 V
−
5.0
10
ns
−15%
−15%
880
660
+15%
+15%
kHz
0.95
1.02
1.05
V
Oscillator
Switching Frequency
ROSC = 32.4 k, 3 Phase (Note 2)
ROSC = 32.4 k, 4 Phase (Note 2)
ROSC Voltage
−
Phase Delay, 3 Phases
VCC = CS4P = CS4N
−
120
−
deg
Phase Delay, 4 Phases
−
−
90
−
deg
VCC − (CS4P = CS4N)
500
−
−
mV
VDRP Output Voltage to DACOUT Offset
CSxP = CSxN, VFB = COMP,
Measure VDRP − COMP
−15
−
15
mV
Current Sense Amplifier to VDRP Gain
CSxP − CSxN = 80 mV, VFB = COMP,
Measure VDRP − COMP
2.25
2.54
2.75
V/V
Phase Disable Threshold
Adaptive Voltage Positioning
VDRP Source Current
−
1.0
7.0
14
mA
VDRP Sink Current
−
0.2
0.4
0.6
mA
Charge Current
−
30
44
50
μA
Discharge Current
−
90
120
150
μA
COMP Pull−Down Current
−
0.2
0.9
2.1
mA
μA
Soft−Start
Current Sensing and Overcurrent Protection
CSxP Input Bias Current
CSxN = CSxP = 0 V
−
0.1
1.0
CSxN Input Bias Current
CSxN = CSxP = 0 V
−
0.1
1.0
μA
Current Sense Amp to PWM Gain
CSxN = 0 V, CSxP = 80 mV, Measure
V(COMP) when GATEx switches high
−
3.1
−
V/V
(Note 2)
−
7.0
−
MHz
2.85
3.30
3.65
V/V
Current Sense Amp to PWM Bandwidth
Current Sense Amp to ILIM Gain
IO/(CSxP − CSxN), ILIM = 0.6 V,
GATEx not switching
Current Sense Amp to ILIM Bandwidth
(Note 2)
−
1.0
−
MHz
Current Limit Filter Slew Rate
(Note 2)
2.0
5.0
13
mV/ms
−
0.1
1.0
μA
V(CSxP) − V(CSxN)
80
90
110
mV
(Note 2)
0
−
2.0
V
ILIM Input Bias Current
ILIM = 0 V
Pulse−by−Pulse Current Limit Threshold
Voltage
Current Sense Common Mode Input
Range
General Electrical Specifications
VCC Operating Current
COMP = 0.3 V (no switching)
−
27
35
mA
UVLO Start Threshold
SS charging, GATEx switching
8.5
9.0
9.5
V
UVLO Stop Threshold
GATEx not switching, SS & COMP
discharging
7.5
8.0
8.5
V
UVLO Hysteresis
Start − Stop
0.8
1.0
1.2
V
2. Guaranteed by design, not tested in production.
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7
NCP5314
PIN DESCRIPTION
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Pin No.
Pin Symbol
Pin Name
Description
1−3,
30−32
VID0−VID5
DAC VID Inputs
4
PWRLS
Power Good Sense
5
VFFB
Fast Voltage Feedback
6
SS
Soft Start
7
PWRGD
Power Good Output
Open collector output goes high when the converter output is in regulation.
8
DRVON
Drive Enable
Logic high enables MOSFET drivers, and logic low turns all MOSFETs off
through MOSFET drivers. Pulled to ground through internal 70 k resistor.
9
SGND
Remote Sense Ground
Ground connection for DAC and error amplifier. Provides remote sensing of
load ground.
10
VDRP
Output of Current Sense
Amplifiers for Adaptive
Voltage Positioning
The offset above DAC voltage is proportional to the sum of inductor current.
A resistor from this pin to VFB programs the amount of Adaptive Voltage
Positioning. Leave this pin open for no Adaptive Voltage Positioning.
11
VFB
Voltage Feedback
Error amplifier inverting input.
12
COMP
Error Amp Output
Provides loop compensation and is clamped by SS during soft start and
fault conditions. It is also the inverting input of PWM comparators.
13
CS4N
Current Sense Reference
14
CS4P
Current Sense Input
15
CS3N
Current Sense Reference
16
CS3P
Current Sense Input
17
GND
Ground
18−21
GATE4−GATE1
Channel Outputs
PWM outputs to drive MOSFET driver ICs.
22
VCC
IC Power Supply
Power Supply Input for IC.
23
ROSC
Oscillator Frequency Adjust
24
ILIM
Total Current Limit
25
CS1P
Current Sense Input
26
CS1N
Current Sense Reference
27
CS2P
Current Sense Input
28
CS2N
Current Sense Reference
29
ENABLE
Enable
VID−compatible logic input used to program the converter output voltage.
All high on VID0−VID4 generates fault.
Voltage sensing pin for Power Good lower threshold.
Input of PWM comparator for fast voltage feedback, and also the inputs of
Power Good sense and overvoltage protection comparators
A capacitor between this pin and ground programs the soft start time.
Inverting input to current sense amplifier #4.
Non−inverting input to current sense amplifier #4.
Inverting input to current sense amplifier #3, and Phase 3 disable pin.
Non−inverting input to current sense amplifier #3, and Phase 3 disable pin.
IC power supply return. Connected to IC substrate.
Resistor to ground programs the oscillator frequency, as shown in Oscillator
Frequency graph Figure 7.
Resistor divider between ROSC and ground programs the average current
limit.
Non−inverting input to current sense amplifier #1.
Inverting input to current sense amplifier #1.
Non−inverting input to current sense amplifier #2.
Inverting input to current sense amplifier #2.
A voltage less than the threshold puts the IC in Fault Mode, discharging SS.
Connect to system VIDPWRGD signal to control powerup sequencing.
Hysteresis is provided to prevent chatter.
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8
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9
+
−
CS4P
CS4N
−
CS3P
CS3N
CO1
CO3
CO2F
× 10 CO2F
CO2
CO4
−
CO4F
× 10 CO4F
+
CO4
× 3.1
−
+
DAC Output
VID = 11111x
CO1F
× 10 CO1F
DAC
9.0 V
8.0 V
−+
−
+
UVLO Comparator
CO3F
× 10 CO3F
+
CO3
+ × 3.1
+
−
−
CS2N
+
−
CO1
× 3.1
CS2P
+
−
3.3 V
Reference
CO2
+ × 3.1
CS1N
CS1P
PWRLS
VID5
VID0
VID1
VID2
VID3
VID4
SGND
VCC
ENABLE
0.5
ILIM
+
+
−
−
+
R
S
R
S
Q
−+
+
−
Phase 4
Disable Comparator
+
−
1.0 V
+
−
Charge
Current
+
−
ROSC
Current Source
Generator
VCC
+
−
Delay
Discharge
Current
Error
Amplifier
VCC − 0.5 V
CS4P
−+
0.6 V
Q
Fault Latch
PWRGD
Comparator
PWRGD
Comparator
−
+
OVP
Comparator
VDRP VFFB VFB
− +
AVP
Buffer
x0.82
x1.06
Module OC
Comparator
+−
20 mV
−+
100 mV
−+
200 mV
0.7 V
0.5 V
−+
−
+
Enable
Comparator
SET
Dominant
SET
Dominant
10 k
Oscillator
+
+
+
−
−
+
+
−
−
+
+
−
−
+
Pulse−by−Pulse
Current Limit
+ 900 mV
−
CO4
CO4F
+
PWM Comparator
RAMP4
CO3
CO3F
+
−
Pulse Current
Comparator
−
+
PWM Comparator
RAMP3
CO2
CO2F
+
PWM Comparator
PWM Comparator
RAMP2
CO1F
CO1
RAMP1
COMP
Ramp4
Phase4
Ramp3
Phase3
Ramp2
Phase2
Ramp1
Phase1
SS
Phase4
Phase3
Phase2
Phase1
Q
Q
Q
R
S
Q
GND
PWM Latch
R
S
PWM Latch
R
S
PWM Latch
R
S
PWM Latch
RESET
Dominant
RESET
Dominant
RESET
Dominant
3.3 V
− +
Figure 2. Block Diagram
RESET
Dominant
PWRGD
VCC
VCC
VCC
VCC
GATE4
GATE3
GATE2
GATE1
DRVON
NCP5314
NCP5314
235
0.5
0.4
0.3
PWRGD DELAY (ms)
0.2
VID = 111101
0.1
VID = 010100
0
−0.1
VID = 010101
−0.2
VID = 101101
−0.3
−0.4
−0.5
20
40
60
80
100
120
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 3. DAC Variation versus Temperature
Figure 4. Power Good Delay versus
Temperature
230
120
700
AVERAGE CHANNEL OFFSET (mV)
OVP THRESHOLD (mV)
225
220
0
220
210
200
190
230
650
600
550
500
450
400
0
20
40
60
80
100
120
20
40
60
80
100
TEMPERATURE (°C)
Figure 5. OVP Threshold above VID versus
Temperature
Figure 6. Channel Startup Offset versus
Temperature
4−PHASE FREQUENCY (kHz)
3 Phase Mode
4 Phase Mode
680
895
675
890
670
885
4 PHASE
880
665
660
3 PHASE
100 k
865
0
1000 k
20
40
60
80
100
ROSC (OHMS)
TEMPERATURE (°C)
Figure 7. Oscillator Frequency versus Total
ROSC Value
Figure 8. Switching Frequency versus
Temperature (ROSC = 32.4 kW)
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10
875
870
655
650
100
10 k
120
TEMPERATURE (°C)
1000
SWITCHING FREQUENCY (kHz)
0
120
3−PHASE FREQUENCY (kHz)
DAC VARIATION FROM NOMINAL (%)
TYPICAL PERFORMANCE CHARACTERISTICS
NCP5314
TYPICAL PERFORMANCE CHARACTERISTICS
2.60
1.025
ROSC VOLTAGE (V)
CS TO VDRP GAIN (V/V)
1.020
1.015
1.010
1.005
1.000
20
40
60
80
100
2.45
120
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. VROSC versus Temperature
Figure 10. Current Sense to VDRP Gain versus
Temperature
3.6
CURRENT SENSE AMP GAIN (V/V)
45
SS CHARGE CURRENT (mA)
2.50
2.40
0
44
43
42
41
40
39
38
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
0
20
40
60
80
100
120
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Soft−Start Charge Current versus
Temperature
Figure 12. Current Sense Amplifier to PWM
Gain versus Temperature
3.35
110
IPLIM THRESHOLD VOLTAGE (mV)
CURRENT SENSE TO ILIM GAIN (V/V)
2.55
3.30
3.25
3.20
3.15
3.10
3.05
3.00
105
100
95
90
85
80
0
20
40
60
80
100
120
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. CS Amp to ILIM Gain versus
Temperature
Figure 14. Pulse−by−Pulse Current Limit
Threshold versus Temperature
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11
120
NCP5314
TYPICAL PERFORMANCE CHARACTERISTICS
30
ICC CURRENT (mA)
29
28
27
26
25
24
23
22
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 15. VCC Operating Current versus
Temperature
VCC
Enable
VREF Fault
UVLO Fault
Fault Reset
Fault Latch
Fault
DRVON
SS
COMP
VOUT
IOUT
Figure 16. Operating Waveforms
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12
Power−Off
Overvoltage
Startup
Enabled
Power−On
UVLO
Power−Off to
Reset OC Fault
Startup
Enabled
Power−On
Power−Off to
Reset OC Fault
Overcurrent
Latchoff
Pulse−by−Pulse
Current Limit
Normal
Operation
Startup
Enabled
Power−On
PWRGD
NCP5314
THEORY OF OPERATION
Overview
Fixed Frequency Multi−Phase Control
The NCP5314 DC/DC controller from ON Semiconductor
was developed using the Enhanced V2 topology. Enhanced
V2 combines the original V2 topology with peak
current−mode control for fast transient response and current
sensing capability. The addition of an internal PWM ramp
and implementation of fast−feedback directly from Vcore
has improved transient response and simplified design. This
controller can be adjusted to operate as a two−, three− or
four−phase controller. Differential current sensing provides
improved current sharing and easier layout. The NCP5314
includes Power Good (PWRGD), providing a highly
integrated solution to simplify design, minimize circuit
board area, and reduce overall system cost.
Two advantages of a multi−phase converter over a
single−phase converter are current sharing and increased
effective output frequency. Current sharing allows the designer
to use less inductance in each phase than would be required in
a single−phase converter. The smaller inductor will produce
larger ripple currents but the total per−phase power dissipation
is reduced because the RMS current is lower. Transient
response is improved because the control loop will measure
and adjust the current faster with a smaller output inductor.
Increased effective output frequency is desirable because
the off−time and the ripple voltage of the multi−phase
converter will be less than that of a single−phase converter.
In a multi−phase converter, multiple converters are
connected in parallel and are switched on at different times.
This reduces output current from the individual converters
and increases the ripple frequency. Because several
converters are connected in parallel, output current can ramp
up or down faster than a single converter (with the same
value output inductor) and heat is spread among multiple
components.
The NCP5314 controller uses four−phase, fixed−frequency,
Enhanced V2 architecture to measure and control currents in
individual phases. In four phase mode, each phase is
delayed 90° from the previous phase (120° in three−phase
mode). Normally, GATEx transitions to a high voltage at
the beginning of each oscillator cycle. Inductor current
ramps up until the combination of the amplified current
sense signal, the internal ramp and the output voltage ripple
trip the PWM comparator and bring GATEx low. Once
GATEx goes low, it will remain low until the beginning of
the next oscillator cycle. While GATEx is high, the
Enhanced V2 loop will respond to line and load variations.
On the other hand, once GATEx is low, the loop cannot
respond until the beginning of the next PWM cycle.
Therefore, constant frequency Enhanced V2 will typically
respond to disturbances within the off−time of the
converter.
x = 1, 2, 3 or 4
SWNODE
Lx
RLx
CSxP
+
CSA
−
RSx
COx
Internal Ramp
CSxN
+
VFB
+
−
VOUT
(VCORE)
VFFB
“Fast−Feedback”
Channel
Connection
Startup
Offset
−
DAC
COMP Out
E.A.
+
To F/F
Reset
+
−
PWM
COMP
+
Figure 17. Enhanced V2 Control Employing Resistive Current Sensing and Internal Ramp
The Enhanced V2 architecture measures and adjusts the
output current in each phase. An additional differential input
(CSxN and CSxP) for inductor current information has been
added to the V2 loop for each phase as shown in Figure 17.
The triangular inductor current is measured differentially
across RS, amplified by CSA and summed with the channel
startup offset, the internal ramp and the output voltage at the
non−inverting input of the PWM comparator. The purpose
of the internal ramp is to compensate for propagation delays
in the NCP5314. This provides greater design flexibility by
allowing smaller external ramps, lower minimum pulse
widths, higher frequency operation and PWM duty cycles
above 50% without external slope compensation. As the
sum of the inductor current and the internal ramp increase,
the voltage on the positive pin of the PWM comparator rises
and terminates the PWM cycle. If the inductor starts a cycle
with higher current, the PWM cycle will terminate earlier
providing negative feedback. The NCP5314 provides a
differential current sense input (CSxN and CSxP) for each
phase. Current sharing is accomplished by referencing all
phases to the same COMP pin, so that a phase with a larger
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13
NCP5314
current signal will turn off earlier than a phase with a smaller
current signal.
Enhanced V2 responds to disturbances in VCORE by
employing both “slow” and “fast” voltage regulation. The
internal error amplifier performs the slow regulation.
Depending on the gain and frequency compensation set by
the amplifier’s external components, the error amplifier will
typically begin to ramp its output to react to changes in the
output voltage in one or two PWM cycles. Fast voltage
feedback is implemented by a direct connection from Vcore
to the non−inverting pin of the PWM comparator via the
summation with the inductor current, internal ramp and
offset. A rapid increase in output current will produce a
negative offset at Vcore and at the output of the summer.
This will cause the PWM duty cycle to increase almost
instantly. Fast feedback will typically adjust the PWM duty
cycle in one PWM cycle.
As shown in Figure 17, an internal ramp (nominally 100 mV
at a 50% duty cycle) is added to the inductor current ramp
at the positive terminal of the PWM comparator. This
additional ramp compensates for propagation time delays
from the current sense amplifier (CSA), the PWM
comparator and the MOSFET gate drivers. As a result, the
minimum ON time of the controller is reduced and lower
duty−cycles may be achieved at higher frequencies. Also,
the additional ramp reduces the reliance on the inductor
current ramp and allows greater flexibility when choosing
the output inductor and the RCSxCCSx time constant of the
feedback components from VCORE to the CSx pin.
Including both current and voltage information in the
feedback signal allows the open loop output impedance of
the power stage to be controlled. When the average output
current is zero, the COMP pin will be:
SWNODE
VFB (VOUT)
Internal Ramp
CSA Out w/
Exaggerated
Delays
COMP−Offset
CSA Out + Ramp + CSREF
T1
T2
Figure 18. Open Loop Operation
If the COMP pin is held steady and the inductor current
changes, there must also be a change in the output voltage
or, in a closed loop configuration when the output current
changes, the COMP pin must move to keep the same output
voltage. The required change in the output voltage or COMP
pin depends on the scaling of the current feedback signal and
is calculated as:
DV + RS @ GCSA @ DIOUT
The single−phase power stage output impedance is:
Single Stage Impedance + DVOUTńDIOUT + RS @ GCSA
The total output impedance will be the single stage
impedance divided by the number of phases in operation.
The output impedance of the power stage determines how
the converter will respond during the first few microseconds
of a transient before the feedback loop has repositioned the
COMP pin.
The peak output current can be calculated from:
VCOMP + VOUT @ 0 A ) Channel_Startup_Offset
) Int_Ramp ) GCSA @ Ext_Rampń2
Int_Ramp is the “partial” internal ramp value at the
corresponding duty cycle, Ext_Ramp is the peak−to−peak
external steady−state ramp at 0 A, GCSA is the current sense
amplifier gain (nominally 3.0 V/V) and the channel startup
offset is typically 0.60 V. The magnitude of the Ext_Ramp
can be calculated from:
IOUT,PEAK + (VCOMP * VOUT * Offset)ń(RS @ GCSA)
Figure 18 shows the step response of the COMP pin at a
fixed level. Before T1, the converter is in normal steady−state
operation. The inductor current provides a portion of the
PWM ramp through the current sense amplifier. The PWM
cycle ends when the sum of the current ramp, the “partial”
internal ramp voltage signal and offset exceed the level of the
COMP pin. At T1, the output current increases and the output
voltage sags. The next PWM cycle begins and the cycle
continues longer than previously while the current signal
increases enough to make up for the lower voltage at the VFB
pin and the cycle ends at T2. After T2, the output voltage
remains lower than at light load and the average current signal
level (CSx output) is raised so that the sum of the current and
voltage signal is the same as with the original load. In a closed
Ext_Ramp + D @ (VIN * VOUT)ń(RCSx @ CCSx @ fSW)
For example, if VOUT at 0 A is set to 1.480 V with AVP
and the input voltage is 12.0 V, the duty cycle (D) will be
1.48/12.0 or 12.3%. Int_Ramp will be 100 mV/50% ⋅ 12.3%
= 25 mV. Realistic values for RCSx, CCSx and fSW are 10 kΩ,
0.015 μF and 650 kHz. Using these and the previously
mentioned formula, Ext_Ramp will be 15.0 mV.
VCOMP + 1.48 V ) 0.62 V ) 25 mV
) 2.65 VńV @ 15.0 mVń2
+ 2.145 Vdc
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NCP5314
To compensate the current sense signal, the values of RCSx
and CCSx are chosen so that L/RL = RCSx ⋅ CCSx. If this
criteria is met, the current sense signal should be the same
shape as the inductor current and the voltage signal at CSx
will represent the instantaneous value of inductor current.
Also, the circuit can be analyzed as if a sense resistor of value
RL was used.
loop system, the COMP pin would move higher to restore the
output voltage to the original level.
Inductive Current Sensing
For lossless sensing, current can be measured across the
inductor as shown in Figure 19. In the diagram, L is the
output inductance and RL is the inherent inductor resistance.
RCSx
SWNODE
x = 1, 2, 3 or 4
CSxP
Lx
+
CSA
−
CCSx
COx
CSxN
Internal Ramp
RLx
VOUT
(VCORE)
+
−
VFFB
“Fast−Feedback”
Connection
+
VFB
−
E.A.
+
DAC
Out
Channel
Startup
Offset
To F/F
Reset
+
−
PWM
COMP
COMP
+
Figure 19. Enhanced V2 Control Employing Lossless Inductive Current Sensing and Internal Ramp
phases will be the CSA input mismatch divided by the
current sense resistance. If all current sense components are
of equal resistance, a 3.0 mV mismatch with a 2.0 mΩ sense
resistance will produce a 1.5 A difference in current between
phases.
When choosing or designing inductors for use with
inductive sensing, tolerances and temperature effects should
be considered. Cores with a low permeability material or a
large gap will usually have minimal inductance change with
temperature and load. Copper magnet wire has a
temperature coefficient of 0.39% per °C. The increase in
winding resistance at higher temperatures should be
considered when setting the OCSET threshold. If a more
accurate current sense is required than inductive sensing can
provide, current can be sensed through a resistor as shown
in Figure 17.
External Ramp Size and Current Sensing
The internal ramp allows flexibility in setting the current
sense time constant. Typically, the current sense RCSx ⋅ CCSx
time constant should be equal to or slightly slower than the
inductor’s time constant. If RC is chosen to be smaller
(faster) than L/RL, the AC or transient portion of the current
sensing signal will be scaled larger than the DC portion. This
will provide a larger steady−state ramp, but circuit
performance will be affected and must be evaluated
carefully. The current signal will overshoot during transients
and settle at the rate determined by RCSx ⋅ CCSx. It will
eventually settle to the correct DC level, but the error will
decay with the time constant of RCSx ⋅ CCSx. If this error is
excessive, it will affect transient response, adaptive
positioning and current limit. During a positive current
transient, the COMP pin will be required to undershoot in
response to the current signal in order to maintain the output
voltage. Similarly, the VDRP signal will overshoot which
will produce too much transient droop in the output voltage.
The single−phase pulse−by−pulse overcurrent protection
will trip earlier than it would if compensated correctly and
hiccup−mode current limit will have a lower threshold for
fast rising step loads than for slowly rising output currents.
Current Sharing Accuracy
Printed Circuit Board (PCB) traces that carry inductor
current can be used as part of the current sense resistance
depending on where the current sense signal is picked off.
For accurate current sharing, the current sense inputs should
sense the current at relatively the same points for each phase.
In some cases, especially with inductive sensing, resistance
of the PCB can be useful for increasing the current sense
resistance. The total current sense resistance used for
calculations must include any PCB trace resistance that
carries inductor current between the CSxP input and the
CSxN input.
Current Sense Amplifier (CSA) input mismatch and the
value of the current sense component will determine the
accuracy of the current sharing between phases. The worst
case CSA input mismatch is ±10 mV and will typically be
within 4.0 mV. The difference in peak currents between
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NCP5314
output voltage is not repositioned quickly enough after
current is stepped up and the upper limit is exceeded.
The controller can be configured to adjust the output
voltage based on the output current of the converter. (Refer to
the application diagram in Figure 1). The no−load positioning
is now set internally to VID − 20 mV, reducing the potential
error due to resistor and bias current mismatches.
In order to realize the AVP function, a resistor divider
network is connected between VFB, VDRP and VOUT.
During no−load conditions, the VDRP pin is at the same
voltage as the VFB pin. As the output current increases, the
VDRP pin voltage increases proportionally. This drives the
VFB voltage higher, causing VOUT to “droop” according to
a loadline set by the resistor divider network.
The response during the first few microseconds of a load
transient is controlled primarily by power stage output
impedance, and by the ESR and ESL of the output filter. The
transition between fast and slow positioning is controlled by
the total ramp size and the error amp compensation. If the
ramp size is too large or the error amp too slow, there will be
a long transition to the final voltage after a transient. This
will be most apparent with low capacitance output filters.
Figure 20. Inductive Sensing Waveform During a
Load Step with Fast RC Time Constant (50 μs/div)
The waveforms in Figure 20 show a simulation of the
current sense signal and the actual inductor current during a
positive step in load current with values of L = 500 nH,
RL = 1.6 mΩ, RCSx = 20 kΩ and CCSx = .01 mF. In this case,
ideal current signal compensation would require RCSx to be
31 kΩ. Due to the faster than ideal RC time constant, there is
an overshoot of 50% and the overshoot decays with a 200 ms
time constant. With this compensation, the ILIM pin threshold
must be set more than 50% above the full load current to avoid
triggering current limit during a large output load step.
Normal
Fast Adaptive Positioning
Slow Adaptive Positioning
Limits
Transient Response and Adaptive Voltage Positioning
Figure 21. Adaptive Voltage Positioning
For applications with fast transient currents, the output
filter is frequently sized larger than ripple currents require in
order to reduce voltage excursions during load transients.
Adaptive voltage positioning can reduce peak−peak output
voltage deviations during load transients and allow for a
smaller output filter. The output voltage can be set higher
than nominal at light loads to reduce output voltage sag
when the load current is applied. Similarly, the output
voltage can be set lower than nominal during heavy loads to
reduce overshoot when the load current is removed. For low
current applications, a droop resistor can provide fast,
accurate adaptive positioning. However, at high currents,
the loss in a droop resistor becomes excessive. For example,
a 50 A converter with a 1 mΩ resistor would provide a
50 mV change in output voltage between no load and full
load and would dissipate 2.5 W.
Lossless adaptive voltage positioning (AVP) is an
alternative to using a droop resistor, but it must respond to
changes in load current. Figure 21 shows how AVP works.
The waveform labeled “normal” shows a converter without
AVP. On the left, the output voltage sags when the output
current is stepped up and later overshoots when current is
stepped back down. With fast (ideal) AVP, the peak−to−peak
excursions are cut in half. In the slow AVP waveform, the
Overvoltage Protection
Overvoltage protection (OVP) is provided as a result of
the normal operation of the Enhanced V2 control topology
with synchronous rectifiers. The control loop responds to an
overvoltage condition within 40 ns, causing the GATEx
output to shut off. The (external) MOSFET driver should
react normally to turn off the top MOSFET and turn on the
bottom MOSFET. This results in a “crowbar” action to
clamp the output voltage and prevent damage to the load.
The regulator will remain in this state until the fault latch is
reset by cycling power at the VCC pin.
Power Good
According to the latest specifications, the Power Good
(PWRGD) signal must be asserted when the output voltage
is within a window defined by the VID code, as shown in
Figure 22.
The PWRLS pin is provided to allow the PWRGD
comparators to accurately sense the output voltage. The
effect of the PWRGD lower threshold can be modified using
a resistor divider from the output to PWRLS to ground, as
shown in Figure 23.
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NCP5314
low until the COMP voltage reaches 0.6 V. Once this
threshold is reached, the GATE outputs are released to
operate normally.
Since the internally−set thresholds for PWRLS are VID/2
for the lower threshold and VID + 80 mV for the upper
threshold, a simple equation can be provided to assist the
designer in selecting a resistor divider to provide the desired
PWRGD performance.
Current Limit
Two levels of over−current protection are provided. First,
if the voltage between the Current Sense pins (CSxN and
CSxP) exceeds the fixed threshold (Single Pulse Current
Limit), the PWM comparator is turned off. This provides
fast peak current protection for individual phases. Second,
the individual phase currents are summed and externally
low−pass filtered to compare an averaged current signal to
a user adjustable voltage on the ILIM pin. If the ILIM voltage
is exceeded, the fault latch trips and the converter is latched
off. VCC must be recycled to reset the latch.
V
R ) R2
VLOWER + VID @ 1
2
R1
VUPPER + VVID ) 80 mV
The logic circuitry inside the chip sets PWRGD low only
after a delay period has been passed. A “power bad” event
does not cause PWRGD to go low unless it is sustained
through the delay time of 250 μs. If the anomaly disappears
before the end of the delay, the PWRGD output will never
be set low.
In order to use the PWRGD pin as specified, the user is
advised to connect external resistors as necessary to limit the
current into this pin to 4 mA or less.
Fault Protection Logic
The NCP5314 includes fault protection circuitry to
prevent harmful modes of operation from occurring. The
fault logic is described in Table 1.
PWRGD
HIGH
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÉÉÉ
PWRGD
low
LOW
−2.6% +2.6
%
VLOWER
PWRGD
high
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÉÉÉ
Gate Outputs
PWRGD
low
The NCP5314 is designed to operate with external gate
drivers. Accordingly, the gate outputs are capable of driving
a 100 pF load with typical rise and fall times of 5 ns.
Digital to Analog Converter (DAC)
The output voltage of the NCP5314 is set by means of a
6−bit, 0.5% DAC. The VID pins must be pulled high
externally. A 1.5 kΩ pullup to a maximum of 3.3 V is
recommended to meet Intel specifications. To ensure valid
logic signals, the designer should ensure at least 800 mV will
be present at the IC for a logic high.
The output of the DAC is described in the Electrical
Characteristics section of the data sheet. These outputs are
consistent with VR10.x and processor specifications. The
DAC output is 20 mV below the VID code specification.
The latest VRM and processor specifications require a
power supply to turn its output off in the event of a 11111X
VID code. When the DAC sees such a code, the GATE pins
stop switching and go low. This condition is described in
Table 1.
VOUT
−5.0% +5.0
%
VID + 80 mV
Figure 22. PWRGD Assertion Window
VOUT
R1
PWRLS
R2
Figure 23. Adjusting the PWRGD Threshold
Adjusting the Number of Phases
The NCP5314 was designed with a selectable−phase
architecture. Designers may choose any number of phases
up to four. The phase delay is automatically adjusted to
match the number of phases that will be used. This feature
allows the designer to select the number of phases required
for a particular application.
Four−phase operation is standard. All phases switch with
a 90 degree delay between pulses. No special connections
are required.
Three−phase operation is achieved by disabling phase 4.
Tie together CS4N and CS4P, and then pull both pins to VCC.
The remaining phases will continue to switch, but now there
Undervoltage Lockout
The NCP5314 includes an undervoltage lockout circuit.
This circuit keeps the IC’s output drivers low until VCC
applied to the IC reaches 9 V. The GATE outputs are disabled
when VCC drops below 8 V.
Soft−Start
At initial power−up, both SS and COMP voltages are zero.
The total SS capacitance will begin to charge with a current
of 40 μA. The error amplifier directly charges the COMP
capacitance. An internal clamp ensures that the COMP pin
voltage will always be less than the voltage at the SS pin,
ensuring proper startup behavior. All GATE outputs are held
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NCP5314
4 as the gate drivers. The other gate drives may switch, so
leave them unconnected.
Single phase is best accomplished by using only Phase 2
as the switch controller. Connect CS2P and CS2N pins to the
current sense capacitor and the gate drive to the driver IC.
Tie all other CSxx pins together and connect them to ground.
will be a 120 degree delay between pulses. The phase firing
order will become 1−2−3.
Two− and single−phase operation may be realized as well.
First, the designer must choose the proper phases. Two phase
operation must use phase 2 and 4 by tying CS1N, CS1P,
CS3N and CS3P to ground. This will then use phase 2 and
Table 1. Description of Fault Logic
Results
Stop
Switching
PWRGD Level
Driver
Enable
SS
Characteristics
Reset Method
Overvoltage Lockout
Yes
Low
High
−0.3 mA
Power On
Enable Low
Yes
Depends on output voltage level
Low
−0.3 mA
Not Affected
Module Overcurrent Limit
Yes
Depends on output voltage level
Low
−0.3 mA
Power On
DAC Code = 11111x
Yes
Depends on output voltage level
Low
−0.3 mA
Valid VID
VREF Undervoltage Lockout
Yes
Depends on output voltage level
Low
−0.3 mA
Power On
PWRLS Out of Range
No
Low
High
Not Affected
Not Affected
Faults
APPLICATIONS INFORMATION
1. Setting Converter Operating Frequency
Choose the number of bulk output capacitors to meet the
peak transient requirements. The formula below can be used
to provide a starting point for the minimum number of bulk
capacitors (NOUT,MIN):
The total resistance from ROSC to ground sets the
operating frequency for each phase of the converter. The
frequency can be set for either the three phase or four phase
mode by using Figure 7, “Oscillator Frequency versus Total
ROSC Value.” After choosing the desired operating
frequency and the number of phases, use the figure to
determine the necessary resistance. If two phase operation
is desired, use the value given for four phase operation.
The voltage from ROSC is closely regulated at 1 V. This
voltage can be used as the reference for the overcurrent limit
set point on the ILIM pin. Design a voltage divider with the
appropriate division ratio to give the desired ILIM voltage
and total resistance to set the operating frequency. Since
loading by the ILIM pin is very small, the frequency selection
will not be affected.
NOUT,MIN + ESR per capacitor @
DIO,MAX
DVO,MAX
(1)
In reality, both the ESR and ESL of the bulk capacitors
determine the voltage change during a load transient
according to:
DVO,MAX + (DIO,MAXńDt) @ ESL ) DIO,MAX @ ESR (2)
Unfortunately, capacitor manufacturers do not specify the
ESL of their components and the inductance added by the
PCB traces is highly dependent on the layout and routing.
Therefore, it is necessary to start a design with slightly more
than the minimum number of bulk capacitors and perform
transient testing or careful modeling/simulation to
determine the final number of bulk capacitors.
The latest Intel processor specifications discuss “dynamic
VID” (DVID), in which the VID codes are stepped up or
down to a new desired output voltage. Due to the timing
requirements at which the output must be in regulation, the
output capacitor selection becomes more complicated. The
ideal output capacitor selection has low ESR and low
capacitance. Too much output capacitance will make it
difficult to meet DVID timing specifications; too much ESR
will complicate the transient solution. The Sanyo 4SP560M
and Panasonic EEU−FL provide a good balance of
capacitance vs. ESR.
2. Output Capacitor Selection
The output capacitors filter the current from the output
inductor and provide a low impedance for transient load
current changes. Typically, microprocessor applications
require both bulk (electrolytic, tantalum) and low
impedance, high frequency (ceramic) types of capacitors.
The bulk capacitors provide “hold up” during transient
loading. The low impedance capacitors reduce steady−state
ripple and bypass the bulk capacitance when the output
current changes very quickly. The microprocessor
manufacturers usually specify a minimum number of
ceramic capacitors. The designer must determine the
number of bulk capacitors.
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3. Output Inductor Selection
For decreasing current:
The output inductor may be the most critical component
in the converter because it will directly effect the choice of
other components and dictate both the steady−state and
transient performance of the converter. When selecting an
inductor, the designer must consider factors such as DC
current, peak current, output voltage ripple, core material,
magnetic saturation, temperature, physical size and cost
(usually the primary concern).
In general, the output inductance value should be
electrically and physically as small as possible to provide the
best transient response at minimum cost. If a large
inductance value is used, the converter will not respond
quickly to rapid changes in the load current. On the other
hand, too low an inductance value will result in very large
ripple currents in the power components (MOSFETs,
capacitors, etc.) resulting in increased dissipation and lower
converter efficiency. Increased ripple currents force the
designer to use higher rated MOSFETs, oversize the thermal
solution, and use more, higher rated input and output
capacitors, adversely affecting converter cost.
One method of calculating an output inductor value is to
size the inductor to produce a specified maximum ripple
current in the inductor. Lower ripple currents will result in
less core and MOSFET losses and higher converter
efficiency. Equation 3 may be used to calculate the
minimum inductor value to produce a given maximum
ripple current (α) per phase. The inductor value calculated
by this equation is a minimum because values less than this
will produce more ripple current than desired. Conversely,
higher inductor values will result in less than the selected
maximum ripple current.
(VIN * VOUT) @ VOUT
LoMIN +
(a @ IO,MAX @ VIN @ fSW)
DtDEC + Lo @ DIOń(VOUT)
For typical processor applications with output voltages
less than half the input voltage, the current will be increased
much more quickly than it can be decreased. Thus, it may be
more difficult for the converter to stay within the regulation
limits when the load is removed than when it is applied and
excessive overshoot may result.
The output voltage ripple can be calculated using the
output inductor value derived in this Section (LoMIN), the
number of output capacitors (NOUT,MIN) and the per
capacitor ESR determined in the previous Section:
VOUT,P−P + (ESR per cap ń NOUT,MIN) @
NJ(VIN * #Phases @ VOUT) @ D ń (LoMIN @ fSW)Nj
(4)
This formula assumes steady−state conditions with no
more than one phase on at any time. The second term in
Equation 4 is the total ripple current seen by the output
capacitors. The total output ripple current is the “time
summation” of the four individual phase currents that are 90
degrees out−of−phase. As the inductor current in one phase
ramps upward, current in the other phase ramps downward
and provides a canceling of currents during part of the
switching cycle. Therefore, the total output ripple current
and voltage are reduced in a multi−phase converter.
4. Input Capacitor Selection
The choice and number of input capacitors is primarily
determined by their voltage and ripple current ratings. The
designer must choose capacitors that will support the worst
case input voltage with adequate margin. To calculate the
number of input capacitors, one must first determine the
total RMS input ripple current. To this end, begin by
calculating the average input current to the converter:
(3)
α is the ripple current as a percentage of the maximum
output current per phase (α = 0.15 for ±15%, α = 0.25 for
±25%, etc.). If the minimum inductor value is used, the
inductor current will swing ± α% about its value at the
center. Therefore, for a four−phase converter, the inductor
must be designed or selected such that it will not saturate
with a peak current of (1 + α) ⋅ IO,MAX/4.
The maximum inductor value is limited by the transient
response of the converter. If the converter is to have a fast
transient response, the inductor should be made as small as
possible. If the inductor is too large its current will change
too slowly, the output voltage will droop excessively, more
bulk capacitors will be required and the converter cost will
be increased. For a given inductor value, it is useful to
determine the times required to increase or decrease the
current.
For increasing current:
DtINC + Lo @ DIOń(VIN * VOUT)
(3.2)
IIN,AVG + IO,MAX @ Dńh
(5)
where:
D is the duty cycle of the converter, D = VOUT/VIN;
η is the specified minimum efficiency;
IO,MAX is the maximum converter output current.
The input capacitors will discharge when the control FET
is ON and charge when the control FET is OFF as shown in
Figure 24.
The following equations will determine the maximum and
minimum currents delivered by the input capacitors:
IC,MAX + ILo,MAXńh * IIN,AVG
(6)
IC,MIN + ILo,MINńh * IIN,AVG
(7)
ILo,MAX is the maximum output inductor current:
ILo,MAX + IO,MAXńf ) DILoń2
(8)
where φ is the number of phases in operation.
ILo,MIN is the minimum output inductor current:
(3.1)
ILo,MIN + IO,MAXńf * DILoń2
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(9)
NCP5314
IC,MAX
ΔIC,IN = IC,MAX − IC,MIN
inrush currents reduce the expected life of the input
capacitors. The inductor’s limiting effect on the input
current slew rate becomes increasingly beneficial during
load transients.
The worst case input current slew rate will occur during
the first few PWM cycles immediately after a step−load
change is applied as shown in Figure 25. When the load is
applied, the output voltage is pulled down very quickly.
Current through the output inductors will not change
instantaneously, so the initial transient load current must be
conducted by the output capacitors. The output voltage will
step downward depending on the magnitude of the output
current (IO,MAX), the per capacitor ESR of the output
capacitors (ESROUT) and the number of the output
capacitors (NOUT) as shown in Figure 25. Assuming the load
current is shared equally between all phases, the output
voltage at full transient load will be:
IC,MIN
0A
tON
T/4
FET Off,
Caps Charging
−IIN,AVG
FET On,
Caps Discharging
Figure 24. Input Capacitor Current for a
Four−Phase Converter
ΔILo is the peak−to−peak ripple current in the output
inductor of value Lo:
DILo + (VIN * VOUT) @ Dń(Lo @ fSW)
(10)
VOUT,FULL−LOAD +
For the four−phase converter, the input capacitor(s) RMS
current is then:
ICIN,RMS + [4D @ (IC,MIN2 ) IC,MIN @ DIC,IN
VOUT,NO−LOAD * (IO,MAXńf) @ ESROUTńNOUT
(11)
When the control MOSFET (Q1 in Figure 25) turns ON,
the input voltage will be applied to the opposite terminal of
the output inductor (the SWNODE). At that instant, the
voltage across the output inductor can be calculated as:
) DIC,IN2ń3) ) IIN,AVG2 @ (1 * 4D)]1ń2
Select the number of input capacitors (NIN) to provide the
RMS input current (ICIN,RMS) based on the RMS ripple
current rating per capacitor (IRMS,RATED):
NIN + ICIN,RMSńIRMS,RATED
(14)
DVLo + VIN * VOUT,FULL−LOAD
(15)
+ VIN * VOUT,NO−LOAD
(12)
) (IO,MAXńf) @ ESROUTńNOUT
For a four−phase converter with perfect efficiency (η = 1),
the worst case input ripple−current will occur when the
converter is operating at a 12.5% duty cycle. At this
operating point, the parallel combination of input capacitors
must support an RMS ripple current equal to 12.5% of the
converter’s DC output current. At other duty cycles, the
ripple−current will be less. For example, at a duty cycle of
either 6% or 19%, the four−phase input ripple−current will
be approximately 10% of the converter’s DC output current.
In general, capacitor manufacturers require derating to the
specified ripple−current based on the ambient temperature.
More capacitors will be required because of the current
derating. The designer should know the ESR of the input
capacitors. The input capacitor power loss can be calculated
from:
The differential voltage across the output inductor will
cause its current to increase linearly with time. The slew rate
of this current can be calculated from:
dILońdt + DVLońLo
(16)
Current changes slowly in the input inductor so the input
capacitors must initially deliver the vast majority of the
input current. The amount of voltage drop across the input
capacitors (ΔVCi) is determined by the number of input
capacitors (NIN), their per capacitor ESR (ESRIN) and the
current in the output inductor according to:
DVCi + ESRINńNIN @ dILońdt @ tON
(17)
+ ESRINńNIN @ dILońdt @ DńfSW
Before the load is applied, the voltage across the input
inductor (VLi) is very small and the input capacitors charge
to the input voltage VIN. After the load is applied, the voltage
drop across the input capacitors, ΔVCi, appears across the
input inductor as well. Knowing this, the minimum value of
the input inductor can be calculated from:
PCIN + ICIN,RMS2 @ ESR_per_capacitorńNIN (13)
Low ESR capacitors are recommended to minimize losses
and reduce capacitor heating. The life of an electrolytic
capacitor is reduced 50% for every 10°C rise in the
capacitor’s temperature.
LiMIN + VLi ń dIINńdtMAX
5. Input Inductor Selection
The use of an inductor between the input capacitors and
the power source will accomplish two objectives. First, it
will isolate the voltage source and the system from the noise
generated in the switching supply. Second, it will limit the
inrush current into the input capacitors at power up. Large
(18)
+ DVCi ń dIINńdtMAX
dIIN/dtMAX is the maximum allowable input current slew
rate.
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6. MOSFET and Heatsink Selection
The input inductance value calculated from Equation 18
is relatively conservative. It assumes the supply voltage is
very “stiff” and does not account for any parasitic elements
that will limit dI/dt such as stray inductance. Also, the ESR
values of the capacitors specified by the manufacturer’s data
sheets are worst case high limits. In reality, input voltage
“sag,” lower capacitor ESRs and stray inductance will help
reduce the slew rate of the input current.
As with the output inductor, the input inductor must
support the maximum current without saturating the
inductor. Also, for an inexpensive iron powder core, such as
the −26 or −52 from Micrometals, the inductance “swing”
with DC bias must be taken into account and inductance will
decrease as the DC input current increases. At the maximum
input current, the inductance must not decrease below the
minimum value or the dI/dt will be higher than expected.
Power dissipation, package size and thermal requirements
drive MOSFET selection. To adequately size the heat sink,
the design must first predict the MOSFET power
dissipation. Once the dissipation is known, the heat sink
thermal impedance can be calculated to prevent the
specified maximum case or junction temperatures from
being exceeded at the highest ambient temperature. Power
dissipation has two primary contributors: conduction losses
and switching losses. The control or upper MOSFET will
display both switching and conduction losses. The
synchronous or lower MOSFET will exhibit only
conduction losses because it switches into nearly zero
voltage. However, the body diode in the synchronous
MOSFET will suffer diode losses during the non−overlap
time of the gate drivers.
VOUT
MAX dI/dt occurs in
first few PWM cycles.
ILi
Vi(t = 0) = 12 V
Q1
SWNODE
Li
TBD
ILo
Vo(t = 0) = 1.745 V
Lo
NCi × Ci
+ VCi
+
NCo × Co
Q2
+ Vi
− 12 V
14 u(t)
ESRCi/NCi
ESRCo/NCo
Figure 25. Calculating the Input Inductance
For the upper or control MOSFET, the power dissipation
can be approximated from:
ID
PD,CONTROL + (IRMS,CNTL2 @ RDS(on))
) (ILo,MAX @ QswitchńIg @ VIN @ fSW)
VGATE
) (Qossń2 @ VIN @ fSW) ) (VIN @ QRR @ fSW)
The first term represents the conduction or IR losses when
the MOSFET is ON while the second term represents the
switching losses. The third term is the loss associated with
the control and synchronous MOSFET output charge when
the control MOSFET turns ON. The output losses are caused
by both the control and synchronous MOSFET but are
dissipated only in the control FET. The fourth term is the loss
due to the reverse recovery time of the body diode in the
synchronous MOSFET. The first two terms are usually
adequate to predict the majority of the losses.
VGS_TH
QGS1
QGS2
QGD
(19)
VDRAIN
Figure 26. MOSFET Switching Characteristics
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NCP5314
IRMS,CNTL is the RMS value of the trapezoidal current in
the control MOSFET:
IRMS,CNTL + ǸD
When the MOSFET power dissipations are known, the
designer can calculate the required thermal impedance to
maintain a specified junction temperature at the worst case
ambient operating temperature.
(20)
@ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2)ń3]1ń2
qT t (TJ * TA)ńPD
ILo,MAX is the maximum output inductor current:
ILo,MAX + IO,MAXńf ) DILoń2
where:
θT is the total thermal impedance (θJC + θSA);
θJC is the junction−to−case thermal impedance of the
MOSFET;
θSA is the sink−to−ambient thermal impedance of the
heatsink assuming direct mounting of the MOSFET (no
thermal “pad” is used);
TJ is the specified maximum allowed junction temperature;
TA is the worst case ambient operating temperature.
For TO−220 and TO−263 packages, standard FR−4
copper clad circuit boards will have approximate thermal
resistances (θSA) as shown below:
(21)
ILo,MIN is the minimum output inductor current:
ILo,MIN + IO,MAXńf * DILoń2
(22)
IO,MAX is the maximum converter output current.
D is the duty cycle of the converter:
D + VOUTńVIN
(23)
ΔILo is the peak−to−peak ripple current in the output
inductor of value Lo:
DILo + (VIN * VOUT) @ Dń(Lo @ fSW)
(24)
RDS(on) is the ON resistance of the MOSFET at the
applied gate drive voltage.
Qswitch is the post gate threshold portion of the
gate−to−source charge plus the gate−to−drain charge. This
may be specified in the data sheet or approximated from the
gate−charge curve as shown in the Figure 26.
Qswitch + Qgs2 ) Qgd
(25)
Pad Size (in2/mm2)
Single−Sided
1 oz Copper
0.50/323
60−65°C/W
0.75/484
55−60°C/W
1.00/645
50−55°C/W
1.50/968
45−50°C/W
As with any power design, proper laboratory testing
should be performed to insure the design will dissipate the
required power under worst case operating conditions.
Variables considered during testing should include
maximum ambient temperature, minimum airflow,
maximum input voltage, maximum loading and component
variations (i.e., worst case MOSFET RDS(on)). Also, the
inductors and capacitors share the MOSFET’s heatsinks and
will add heat and raise the temperature of the circuit board
and MOSFET. For any new design, it is advisable to have as
much heatsink area as possible. All too often, new designs are
found to be too hot and require re−design to add heatsinking.
Ig is the output current from the gate driver IC.
VIN is the input voltage to the converter.
fsw is the switching frequency of the converter.
QG is the MOSFET total gate charge to obtain RDS(on);
commonly specified in the data sheet.
Vg is the gate drive voltage.
QRR is the reverse recovery charge of the lower MOSFET.
Qoss is the MOSFET output charge specified in the data
sheet.
For the lower or synchronous MOSFET, the power
dissipation can be approximated from:
PD,SYNCH + (IRMS,SYNCH2 @ RDS(on))
(28)
7. Adaptive Voltage Positioning
) (Vfdiode @ IO,MAXń2 @ t_nonoverlap @ fSW)
(26)
Two resistors program the Adaptive Voltage Positioning
(AVP): RFB and RDRP. These components form a resistor
divider, shown in Figures 27 and 28, between VDRP, VFB,
and VOUT.
Resistor RFB is connected between VOUT and the VFB pin
of the controller. At no load, this resistor will conduct the
very small internal bias current of the VFB pin. Therefore
VFB should be kept below 10 kΩ to avoid output voltage
error due to the input bias current. If the RFB resistor is kept
small, the VFB bias current can be ignored.
Resistor RDRP is connected between the VDRP and VFB
pins of the controller. At no load, these pins should be at an
equal potential, and no current should flow through RDRP. In
reality, the bias current coming out of the VDRP pin is likely
to have a small positive voltage with respect to VFB. This
current produces a small decrease in output voltage at no
load, which can be minimized by keeping the RDRP resistor
where:
Vfdiode is the forward voltage of the MOSFET’s intrinsic
diode at the converter output current.
t_nonoverlap is the non−overlap time between the upper
and lower gate drivers to prevent cross conduction.
This time is usually specified in the data sheet for the
control IC.
The first term represents the conduction or IR losses when
the MOSFET is ON and the second term represents the diode
losses that occur during the gate non−overlap time.
All terms were defined in the previous discussion for the
control MOSFET with the exception of:
(27)
IRMS,SYNCH + Ǹ1 * D
@ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2)ń3]1ń2
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NCP5314
The output voltage droop will follow the equation:
below 30 kΩ. As load current increases, the voltage at the
VDRP pin rises. The ratio of the RDRP and RFB resistors
causes the voltage at the VFB pin to rise, reducing the output
voltage. Figure 29 shows the DC effect of AVP, given an
appropriate resistor ratio.
To choose components, recall that the two resistors RFB
and RDRP form a voltage divider. Select the appropriate
resistor ratio to achieve the desired loadline. At no load, the
output voltage is positioned 20 mV below the DAC output
setting.
L1
0A
CS1P
CCS1
where:
g = current sense amplifier to VDRP gain (V/V);
RL = ESR of Lo inductor (mΩ);
RLL = load line resistance (mΩ).
+−
+
−
GVDRP
COMP
Σ
Lx
0A
CSxP
CCSx
VID − 20 mV
Error
Amp
CS1N
RCSx
−
+
RCS1
RDRP + g @ RL @ RFB
RLL
RDRP
+
−
GVDRP
VDRP = VID
RFB
VFB = VID − 20 mV
IDRP = 0
CSxN
VCORE
IFB = 0
VCORE = VID + IBIASVFB w RFB
Figure 27. AVP Circuitry at No−Load
L1
IMAX/2
CS1P
+−
+
−
GVDRP
COMP
Σ
CS1N
Lx
IMAX/n
CSxP
RDRP
+
−
GVDRP
VID − 20 mV
Error
Amp
CCS1
RCSx
−
+
RCS1
RFB
VDRP = VID +
VFB = VID − 20 mV VCORE
IMAX • RL • GVDRP
CCSx
IDRP
CSxN
IFB
IDRP = IMAX • RL • GVDRP/RDRP
IFBK = IDRP
VCORE = VID − IDRP w RFB
= VID − IMAX w RL w GVDRP w RFB/RDRP
Figure 28. AVP Circuitry at Full−Load
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(29)
NCP5314
0
−0.02
Spec Max
VOUT (V)
−0.04
VID − VOUT
−0.06
−0.08
Spec Min
−0.10
−0.12
−0.14
0
10
20
30
IOUT (A)
40
50
60
Figure 30. VDRP Tuning Waveforms. The RC Time
Constant of the Current Sense Network Is Too Long
(Slow): VDRP and VOUT Respond Too Slowly.
Figure 29. The DC Effects of AVP vs. Load
It is easiest to select a value for RFB and then evaluate the
equation to find RDRP. RLL is simply the desired output
voltage droop divided by the output current. If inductor
sensing is used, RL will be the resistance of the inductor,
assuming that the current sense network equation (eq. 30) is
valid. Refer to the discussion on Current Sensing for further
information.
8. Current Sensing
Current sensing is used to balance current between
different phases, to limit the maximum phase current and to
limit the maximum system current. Since the current
information, sensed across the inductor, is a part of the
control loop, better stability is achieved if the current
information is accurate and noise−free. The NCP5314
introduces a novel feature to achieve the best possible
performance: differential current sense amplifiers.
Two sense lines are routed for each phase, as shown in
Figure 28.
For inductive current sensing, choose the current sense
network (RCSx, CCSx, x = 1, 2, 3 or 4) to satisfy
RCSx @ CCSx + Loń(RL ) RPCB)
Figure 31. VDRP Tuning Waveforms. The RC Time
Constant of the Current Sense Network Is Too Short
(Fast): VDRP and VOUT Both Overshoot.
(30)
This will provide an adequate starting point for RCSx and
CCSx. After the converter is constructed, the value of RCSx
(and/or CCSx) should be fine−tuned in the lab by observing
the VDRP signal during a step change in load current. Tune
the RCSx ⋅ CCSx network by varying RCSx to provide a
“square−wave” at the VDRP output pin with maximum rise
time and minimal overshoot as shown in Figure 32.
Figure 32. VDRP Tuning Waveforms. The RC Time
Constant of the Current Sense Network Is Optimal:
VDRP and VOUT Respond to the Load Current Quickly
Without Overshooting.
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NCP5314
9. Error Amplifier Tuning
case, the output voltage will transition more slowly because
COMP spikes upward as shown in Figure 34. Too much loop
gain/bandwidth increases the risk of instability. In general,
one should use the lowest loop gain/bandwidth possible to
achieve acceptable transient response. This will insure good
stability. If CAMP is optimal, the COMP pin will slew
quickly but not overshoot and the output voltage will
monotonically settle as shown in Figure 35.
After the control loop is tuned to provide an acceptable
transient response, the steady−state voltage ripple on the
COMP pin should be examined. When the converter is
operating at full steady−state load, the peak−to−peak voltage
ripple (VPP) on the COMP pin should be less than 20 mVPP
as shown in Figure 36. Less than 10 mVPP is ideal. Excessive
ripple on the COMP pin will contribute to jitter.
After the steady−state (static) AVP has been set and the
current sense network has been optimized, the Error
Amplifier must be tuned. The gain of the Error Amplifier
should be adjusted to provide an acceptable transient
response by increasing or decreasing the Error Amplifier’s
feedback capacitor (CAMP in the Applications Diagram).
The bandwidth of the control loop will vary directly with the
gain of the error amplifier.
If CAMP is too large, the loop gain/bandwidth will be low,
the COMP pin will slew too slowly and the output voltage
will overshoot as shown in Figure 33. On the other hand, if
CAMP is too small, the loop gain/bandwidth will be high, the
COMP pin will slew very quickly and overshoot will occur.
Integrator “wind up” is the cause of the overshoot. In this
Figure 33. The Value of CAMP Is Too High and the
Loop Gain/Bandwidth Too Low. COMP Slews Too
Slowly Which Results in Overshoot in VOUT.
Figure 34. The Value of CAMP Is Too Low and the
Loop Gain/Bandwidth Too High. COMP Moves Too
Quickly, Which Is Evident from the Small Spike in Its
Voltage When the Load Is Applied or Removed. The
Output Voltage Transitions More Slowly Because of
the COMP Spike.
Figure 35. The Value of CAMP Is Optimal. COMP Slews
Quickly Without Spiking or Ringing. VOUT Does Not
Overshoot and Monotonically Settles to Its Final Value.
Figure 36. At Full−Load the Peak−to−Peak Voltage
Ripple on the COMP Pin Should Be Less than 20 mV
for a Well−Tuned/Stable Controller. Higher COMP
Voltage Ripple Will Contribute to Output Voltage Jitter.
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NCP5314
10. Current Limit Setting
where:
IOUT,LIM is the current limit threshold of the converter;
ΔILo/2 is half the inductor ripple current;
R is RLMAX + RPCB;
GILIM is the current sense to ILIM gain.
For the overcurrent protection to work properly, the
current sense time constant (RC) should be slightly larger
than the RL time constant. If the RC time constant is too fast,
a step load change will cause the sensed current waveform
to appear larger than the actual inductor current and will trip
the current limit at a lower level than expected.
When the output of the current sense amplifier (COx in the
block diagram) exceeds the voltage on the ILIM pin, the part
will latch off. For inductive sensing, the ILIM pin voltage
should be set based on the inductor’s maximum resistance
(RLMAX). The design must consider the inductor’s
resistance increase due to current heating and ambient
temperature rise. Also, depending on the current sense
points, the circuit board may add additional resistance. In
general, the temperature coefficient of copper is +0.39% per
_C. To set the level of the ILIM pin:
VILIM + (IOUT,LIM ) DILoń2) @ R @ GILIM
(31)
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NCP5314
PACKAGE DIMENSIONS
32 PIN QFN, 7 x 7 mm
MN SUFFIX
CASE 485J−02
ISSUE C
A B
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN 1
LOCATION
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
2X
0.15 C
2X
0.15 C
TOP VIEW
(A3)
0.10 C
A
0.08 C
SEATING
PLANE
A1
SIDE VIEW
C
D2
EXPOSED PAD
e
L
9
32X
K
16
4X
17
8
8
e
1
24
32
b
E2
25
32X NOTE 3
0.10
C A B
0.05
C
BOTTOM VIEW
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MILLIMETERS
MIN
NOM MAX
0.800 0.900 1.000
0.000 0.025 0.050
0.200 REF
0.250 0.250 0.350
7.00 BSC
5.160 5.260 5.360
7.00 BSC
5.160 5.260 5.360
0.650 BSC
0.200
−−−
−−−
0.300 0.400 0.500
NCP5314
PACKAGE DIMENSIONS
A
32
A1
−T−, −U−, −Z−
32 LEAD LQFP
CASE 873A−02
ISSUE C
4X
25
0.20 (0.008) AB T−U Z
1
AE
−U−
−T−
B
P
V
17
8
BASE
METAL
DETAIL Y
V1
ÉÉ
ÉÉ
ÉÉ
−Z−
9
S1
4X
0.20 (0.008) AC T−U Z
F
S
8X
M_
J
R
D
DETAIL AD
G
SECTION AE−AE
−AB−
C E
−AC−
H
W
K
X
DETAIL AD
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT
INCLUDE MOLD PROTRUSION.
ALLOWABLE PROTRUSION IS 0.250
(0.010) PER SIDE. DIMENSIONS A AND
B DO INCLUDE MOLD MISMATCH AND
ARE DETERMINED AT DATUM PLANE
−AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER
MAY VARY FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
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MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.450
0.750
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.018
0.030
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
Q_
0.250 (0.010)
0.10 (0.004) AC
GAUGE PLANE
SEATING
PLANE
M
N
9
0.20 (0.008)
DETAIL Y
AC T−U Z
AE
B1
NCP5314
V2 is a trademark of Switch Power, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP5314/D