Philips Semiconductors Product specification Dual octal latch (3-State) 74F604 FEATURES PIN CONFIGURATION • High impedance NPN base inputs for reduced loading (20µA in High and Low states) • Stores 16-bit–wide Data inputs, multiplexed 8-bit outputs • 3-State outputs • Power supply current 75mA typical LE 1 28 VCC SELECT A/B 2 27 A4 A0 3 26 B4 B0 4 25 A5 A1 5 24 B5 B1 6 23 A6 A2 7 22 B6 B2 8 21 A7 A3 9 20 B7 DESCRIPTION The 74F604 multiplexed latch is ideal for storing data from two input buses, A or B, and providing data from either the A or B latches to the output bus. Organized as 8-bit A and B latches, the latch outputs are connected by pairs to eight 2-input multiplexers. A Select (SELECT A/B) input determines whether the A or B latch contents are multiplexed to the eight 3-State outputs. Data entered from the B inputs are selected when SELECT A/B is Low; data from the A inputs are selected when SELECT A/B is High. Data enters the latches when the Latch Enable (LE) input is Low and is latched on the LE rising edge. The outputs are enabled when LE is High and disabled when LE is Low. B3 10 19 Q7 Q3 11 18 Q6 Q2 12 17 Q5 Q1 13 16 Q4 GND 14 15 Q0 SF01115 TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74F604 7.5ns 75mA ORDERING INFORMATION DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 28-pin plastic DIP N74F604N 28-pin plastic SOL N74F604D INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW A0–A7, B0–B7 Data inputs 1.0/0.033 20µA/20µA SELECT A/B Select input 1.0/0.033 20µA/20µA Latch Enable input (active Low) 1.0/0.033 20µA/20µA 150/40 3mA/24mA LE Q0–Q7 Data outputs NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. 1990 Mar 01 1 853–0029 98991 Philips Semiconductors Product specification Dual octal latch (3-State) 74F604 LOGIC SYMBOL IEC/IEEE SYMBOL (IEEE/IEC) 2 3 4 5 6 7 8 9 10 27 26 25 24 23 22 21 20 G2 1 E1 EN A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 3 1 LE 2 SELECT A/B 4 Q0 15 Q1 13 Q2 Q3 12 11 Q4 Q5 16 17 5 6 7 Q6 Q7 18 8 9 19 VCC = Pin 28 GND = Pin 14 10 27 26 25 24 SF01116 23 22 21 1D 2 ≥1 15 1D 2 13 12 11 16 17 18 19 20 SF01117 FUNCTION TABLE INPUTS A0–A7 B0–B7 SELECT A/B LE A data B data L ↑ B data A data B data H ↑ B data X X X L Z X X L H B latched data X H H A latched data X H L X Z ↑ OUTPUTS = = = = = Q0–Q7 High voltage level Low voltage level Don’t care High impedance “off” state Low-to-High clock transition 1990 Mar 01 2 Philips Semiconductors Product specification Dual octal latch (3-State) 74F604 LOGIC DIAGRAM SELECT A/B LE A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 2 1 3 4 D E D E 5 6 D E D E D E 16 Q4 17 Q5 D E D E 18 Q6 D E D E 19 VCC = Pin 28 GND = Pin 14 1990 Mar 01 Q3 D E D E 21 20 Q2 11 D E 23 22 12 D E 25 24 Q1 D E 27 26 13 D E 9 10 Q0 D E 7 8 15 Q7 SF01118 3 Philips Semiconductors Product specification Dual octal latch (3-State) 74F604 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) PARAMETER SYMBOL RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to +VCC V IOUT Current applied to output in Low output state Tamb Operating free-air temperature range Tstg Storage temperature range 48 mA 0 to +70 °C –65 to +150 °C RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER UNIT MIN NOM MAX 5.0 5.5 VCC Supply voltage 4.5 VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –3 mA IOL Low-level output current 24 mA Tamb Operating free-air temperature range 70 °C 1990 Mar 01 0 4 V V Philips Semiconductors Product specification Dual octal latch (3-State) 74F604 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL LIMITS TEST CONDITIONS1 PARAMETER VCC = MIN, VIL = MAX, VIH = MIN, IOH = MAX VOH High-level output voltage VOL Low-level output voltage VIK Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage IIH TYP2 MIN ±10%VCC 2.4 ±5%VCC 2.7 MAX UNIT V 3.4 V ±10%VCC 0.35 0.50 V ±5%VCC 0.35 0.50 V –0.73 –1.2 V VCC = 0.0V, VI = 7.0V 100 µA High-level input current VCC = MAX, VI = 2.7V 20 µA IIL Low-level input current VCC = MAX, VI = 0.5V –20 µA IOZH Off state output current, High-level voltage applied VCC = MAX, VO = 2.7V 50 µA IOZL Off state output current, Low-level voltage applied VCC = MAX, VO = 0.5V –50 µA IOS Short-circuit output current3 VCC = MAX –150 mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX ICCH ICC S Supply l current (total) ( l) ICCL VCC = MAX ICCZ –60 An, Bn, SELECT A/B = 4.5V, LE = ↑ 60 82 mA An, Bn, SELECT A/B=GND, LE = ↑ 75 100 mA An, Bn, SELECT A/B = GND, LE = GND 75 100 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5V Tamb = +25°C CL = 50pF, RL = 500Ω VCC = +5V ± 10% Tamb = 0°C to +70°C CL = 50pF, RL = 500Ω UNIT MIN TYP MAX MIN MAX Waveform 1 5.0 6.0 7.0 8.5 9.0 10.5 4.5 5.5 10.0 11.5 ns Propagation delay SELECT A/B to Qn (A latch) Waveform 2 6.0 4.0 8.0 6.5 10.0 8.5 5.5 3.5 11.5 9.0 ns tPZH tPZL Output Enable time to High or Low level Waveform 4 Waveform 5 5.0 5.0 7.5 7.5 9.5 9.5 4.5 4.5 10.5 11.0 ns tPHZ tPLZ Output Disable time from High or Low level Waveform 4 Waveform 5 5.0 5.0 7.0 7.0 9.5 9.5 4.5 4.5 11.0 11.0 ns tPLH tPHL Propagation delay SELECT A/B to Qn (B latch) tPLH tPHL 1990 Mar 01 5 Philips Semiconductors Product specification Dual octal latch (3-State) 74F604 AC SETUP REQUIREMENTS LIMITS SYMBOL VCC = +5V Tamb = +25°C CL = 50pF, RL = 500Ω TEST CONDITION PARAMETER MIN TYP MAX VCC = +5V ± 10% Tamb = 0°C to +70°C CL = 50pF, RL = 500Ω MIN UNIT MAX ts(H) ts(L) Setup time, High or Low An, Bn to LE Waveform 3 1.0 2.0 2.0 3.0 ns th(H) th(L) Hold time, High or Low An, Bn to LE Waveform 3 0 1.0 0 1.5 ns tW(L) LE Pulse width, Low Waveform 3 5.0 6.0 ns AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. SELECT A/B VM SELECT A/B VM VM tPLH tPHL VM Qn VM tPLH tPHL VM VM Qn VM SF01120 SF01119 Waveform 1. Propagation Delay, SELECT A/B To Output (B latched data=Low. LE=H) An, Bn VM VM ts(H) th(H) VM ts(L) Waveform 2. Propagation Delay, SELECT A/B to Output (A latched data=Low. LE=H) VM th(L) tw(L) LE VM VM VM SF01121 Waveform 3. Data Setup and Hold Times, Latch Enable Pulse Width LE VM tPZH Qn LE VM tPHZ VOH -0.3V VM VM tPZL Qn VM 0V tPLZ VM VOL +0.3V SF01122 SF01123 Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level 1990 Mar 01 6 Philips Semiconductors Product specification Dual octal latch (3-State) 74F604 TEST CIRCUIT AND WAVEFORMS VCC 7.0V VIN RL VOUT PULSE GENERATOR tw 90% NEGATIVE PULSE VM CL AMP (V) VM 10% D.U.T. RT 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V RL AMP (V) 90% 90% Test Circuit for 3-State Outputs POSITIVE PULSE VM VM 10% TEST tPLZ tPZL All other SWITCH closed closed open DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 10% tw SWITCH POSITION 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00777 1990 Mar 01 7