CY62167G Automotive 16-Mbit (1M Words × 16 Bit) Static RAM with Error-Correcting Code (ECC) 16-Mbit (1 M words × 16 bit) Static RAM with Error-Correcting Code (ECC) Features Data writes are performed by asserting the Write Enable input (WE) LOW, and providing the data and address on device data (I/O0 through I/O15) and address (A0 through A19) pins respectively. The Byte High/Low Enable (BHE, BLE) inputs control byte writes, and write data on the corresponding I/O lines ■ Ultra-low standby power ❐ Typical standby current: 5.5 A ❐ Maximum standby current: 75 A ■ High speed: 45 ns / 55 ns ■ Embedded error-correcting code (ECC) for single-bit error correction ■ Temperature Ranges: ❐ Automotive-A: -40 C to +85 C ❐ Automotive-E: -40 C to +125 C ■ Operating voltage range: 2.2 V to 3.6 V ■ 1.0-V data retention ■ TTL-compatible inputs and outputs ■ Available in Pb-free 48-ball VFBGA and 48-pin TSOP I packages to the memory location specified. BHE controls I/O8 through I/O15; BLE controls I/O0 through I/O7. Data reads are performed by asserting the Output Enable (OE) input and providing the required address on the address lines. Read data is accessible on I/O lines (I/O0 through I/O15). Byte accesses can be performed by asserting the required byte enable signal (BHE, BLE) to read either the upper byte or the lower byte of data from the specified address location. All I/Os (I/O0 through I/O15) are placed in a HI-Z state when the device is deselected (CE1 HIGH / CE2 LOW for dual chip-enable device), or control signals are de-asserted (OE, BLE, and BHE). Functional Description CY62167G is high-performance CMOS low-power (MoBL) SRAM devices with embedded ECC. This device is offered in dual chip-enable. Devices with dual chip-enable are accessed by asserting both chip-enable inputs – CE1 as LOW and CE2 as HIGH. These devices also have a unique “Byte Power down” feature where if both the Byte Enables (BHE and BLE) are disabled, the devices seamlessly switches to standby mode irrespective of the state of the chip enable(s), thereby saving power. The CY62167G device is available in a Pb-free 48-ball VFBGA and 48-pin TSOP I packages. The device in the 48-pin TSOP I package can also be configured to function as a 2 M words × 8 bit device.The logic block diagram is on page 2. Refer to Pin Configurations on page 4 and the associated footnotes for details. Note 1. This device does not support automatic write-back on error detection. Cypress Semiconductor Corporation Document Number: 001-84902 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 12, 2016 CY62167G Automotive DATAIN DRIVERS 1M x 16 / 2M x 8 RAM ARRAY ECC DECODE ECC ENCODE SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER Logic Block Diagram – CY62167G I/O0-I/O7 I/O8-I/O15 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 COLUMN DECODER CE POWER DOWN CIRCUIT BYTE BHE BHE BLE WE CE2 OE CE1 BLE Document Number: 001-84902 Rev. *D Page 2 of 19 CY62167G Automotive Contents Pin Configurations ........................................................... 4 Product Portfolio .............................................................. 4 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 DC Electrical Characteristics .......................................... 5 Capacitance ...................................................................... 6 Thermal Resistance .......................................................... 6 AC Test Loads and Waveforms ....................................... 6 Data Retention Characteristics ....................................... 7 Data Retention Waveform ................................................ 7 Switching Characteristics ................................................ 8 Switching Waveforms ...................................................... 9 Truth Table – CY62167G ................................................ 13 Document Number: 001-84902 Rev. *D Ordering Information ...................................................... 14 Ordering Code Definitions ......................................... 14 Package Diagram ............................................................ 15 Acronyms ........................................................................ 17 Document Conventions ................................................. 17 Units of Measure ....................................................... 17 Document History Page ................................................. 18 Sales, Solutions, and Legal Information ...................... 19 Worldwide Sales and Design Support ....................... 19 Products .................................................................... 19 PSoC® Solutions ...................................................... 19 Cypress Developer Community ................................. 19 Technical Support ..................................................... 19 Page 3 of 19 CY62167G Automotive Pin Configurations Figure 1. 48-ball VFBGA pinout [2] CY62167G 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A I/O8 BHE A3 A4 CE1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 VCC D VCC I/O12 NC A16 I/O4 Vss E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 A19 A12 A13 WE I/O7 G A18 A8 A9 A10 A11 NC H Figure 2. 48-pin TSOP I pinout (Dual Chip Enable without ERR) – CY62167G [2, 3] A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE CE2 NC BHE BLE A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE Vss I/O15/A20 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 Vcc I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE Vss CE1 A0 Product Portfolio Power Dissipation Product CY62167G30 Range Automotive-E Automotive-A VCC Range (V) 2.2 V–3.6 V Speed (ns) Operating ICC, (mA), f = fmax Standby, ISB2 (µA) Typ [4] Max Typ [4] Max 55 29.0 40.0 5.5 75.0 45 29.0 36.0 5.5 16.0 Notes 2. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin configuration. 3. The BYTE pin in the 48-pin TSOP I package must be tied to VCC to use the device as a 1 M × 16 SRAM. The 48-pin TSOP I package can also be used as a 2 M × 8 SRAM by tying the BYTE signal to VSS. In the 2 M × 8 configuration, pin 45 is A20, while BHE, BLE and I/O8 to I/O14 pins are not used. 4. Indicates the value for the center of Distribution at 3.0 V, 25 °C and not 100% tested. Document Number: 001-84902 Rev. *D Page 4 of 19 CY62167G Automotive Maximum Ratings Output current into outputs (LOW) ............................. 20 mA Static discharge voltage (MIL-STD-883, Method 3015) ................................. >2001 V Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Latch-up current ..................................................... >140 mA Storage temperature ............................... –65 °C to + 150 °C Operating Range Ambient temperature with power applied ......................................... –55 °C to + 125 °C Supply voltage to ground potential [5] .......................... –0.5 V to VCC + 0.5 V DC voltage applied to outputs in HI-Z state [5] .................................... –0.5 V to VCC + 0.5 V Grade Ambient Temperature VCC Automotive-E –40 C to +125 C 2.2 V to 3.6 V Automotive-A –40 C to +85 C DC input voltage [5] ............................. –0.5 V to VCC + 0.5 V DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH 2.2 V to 2.7 V VCC = Min, IOH = –0.1 mA voltage 2.7 V to 3.6 V VCC = Min, IOH = –1.0 mA VOL Output LOW voltage 2.2 V to 2.7 V VCC = Min, IOL = 0.1 mA 2.7 V to 3.6 V VCC = Min, IOL = 2.1 mA VIH Input HIGH voltage[5] 2.2 V to 2.7 V – VIL Input LOW voltage[5] IIX Input leakage current GND < VIN < VCC IOZ Output leakage current GND < VOUT < VCC, Output disabled ICC VCC operating supply current 55 ns (Automotive -E) 55 ns (Automotive-A) Min Typ [6] 2.0 – Max Min Typ [6] – 2.0 – – 2.2 – – – – 0.4 – – 0.4 0.4 – – 0.4 – VCC + 0.3 – – – VCC + 0.3 2.0 2.7 V to 3.6 V – 2.0 – VCC + 0.3 2.0 2.2 V to 2.7 V – –0.3 – –0.3 –4.0 Automatic power down current – CMOS inputs; VCC = 2.2 to 3.6 V ISB2[7] Automatic power down current – CMOS inputs; VCC = 2.2 to 3.6 V Unit V V V – VCC + 0.3 0.6 –0.3 – 0.6 – 0.8 –0.3 – 0.8 – +4.0 –1.0 – +1.0 A –4.0 – +4.0 –1.0 – +1.0 A f = fMAX – 29.0 40.0 – 29.0 36.0 mA f =1 MHz – 7.0 18.0 – 7.0 9.0 mA – 5.5 75.0 – 5.5 16.0 A – 5.5 75.0 – 5.5 16.0 A 2.7 V to 3.6 V – ISB1[7] – 2.2 2.0 VCC = Max, IOUT = 0 mA, CMOS levels – Max CE1 > VCC – 0.2 V or CE2 < 0.2 V or (BHE and BLE) > VCC – 0.2 V, VIN > VCC – 0.2 V, VIN < 0.2 V, f = fmax (address and data only), f = 0 (OE, and WE), VCC = VCC(max) V CE1 > VCC – 0.2V or CE2 < 0.2 V or (BHE and BLE) > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0, VCC = VCC(max) Notes 5. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 2 ns. 6. Indicates the value for the center of Distribution at 3.0 V, 25 °C and not 100% tested. 7. Chip enables (CE1 and CE2) and BHE, BLE and BYTE must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. Document Number: 001-84902 Rev. *D Page 5 of 19 CY62167G Automotive Capacitance Parameter [8] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max Unit 10 pF 10 pF Thermal Resistance Parameter [8] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions 48-ball VFBGA 48-pin TSOP I Unit Still air, soldered on a 3 × 4.5 inch, 4-layer printed circuit board 31.50 57.99 °C/W 15.75 13.42 °C/W AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms VCC OUTPUT R1 VHIGH GND R2 30 pF INCLUDING JIG AND SCOPE 10% ALL INPUT PULSES 90% 90% 10% Rise Time = 1 V/ns Fall Time = 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V Parameters 3.0 V Unit R1 317 R2 351 VHIGH 3.0 V Note 8. Tested initially and after any design or process changes that may affect these parameters. Document Number: 001-84902 Rev. *D Page 6 of 19 CY62167G Automotive Data Retention Characteristics Over the Operating Range Parameter Description Conditions 55 ns (Automotive -E) 45 ns (Automotive -A) Unit Min Typ [9] Max Min Typ [9] Max Unit 1 – – 1 – – V – 5.5 75.0 – 5.5 16.0 A VDR VCC for data retention ICCDR[10] Data-retention current tCDR[11] Chip deselect to data-retention time 0 – – 0 – – – tR[12] Operation-recovery time 55 – – 45 – – ns 2.2 V < VCC < 3.6 V CE1 > VCC 0.2 V or CE2 < 0.2 V or (BHE and BLE) > VCC – 0.2 V, VIN > VCC 0.2 V or VIN < 0.2 V Data Retention Waveform Figure 4. Data-Retention Waveform [13] V CC V CC(m in) t CD R D ATA RETEN TIO N M O D E V D R = 1.0 V V CC(m in) tR CE 1 or BH E. BLE (or) CE 2 Notes 9. Indicates the value for the center of distribution at 3.0 V, 25°C and not 100% tested. 10. Chip enables (CE1 and CE2) and BYTE must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. 11. Tested initially and after any design or process changes that may affect these parameters. 12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 13. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE. Document Number: 001-84902 Rev. *D Page 7 of 19 CY62167G Automotive Switching Characteristics Parameter [14] 55 ns (Automotive-E) 45 ns (Automotive-A) Description Unit Min Max Min Max 55 – 45 – ns Read Cycle tRC Read cycle time tAA Address to data valid – 55 – 45 ns tOHA Data hold from address change 10 – 10 – ns tACE CE1 LOW and CE2 HIGH to data valid / CE LOW – 55 – 45 ns tDOE OE LOW to data valid / OE LOW – 25 – 22 ns 5 – 5 – ns – 20 – 18 ns 10 – 10 – ns – 20 – 18 ns [15] tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z [15, 16] CE1 LOW and CE2 HIGH to Low Z [15] tHZCE CE1 HIGH and CE2 LOW to High Z [15, 16] tPU CE1 LOW and CE2 HIGH to power-up 0 – 0 – ns tPD CE1 HIGH and CE2 LOW to power-down – 55 – 45 ns tDBE BLE / BHE LOW to data valid – 55 – 45 ns [15] 5 – 5 – ns – 20 – 18 ns tLZCE tLZBE tHZBE BLE / BHE LOW to Low Z BLE / BHE HIGH to High Z [15, 16] Write Cycle [17] tWC Write cycle time 55 – 45 – ns tSCE CE1 LOW and CE2 HIGH to write end 40 – 35 – ns tAW Address setup to write end 40 – 35 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 40 – 35 – ns tBW BLE / BHE LOW to write end 40 – 35 – ns tSD Data setup to write end 25 – 25 – ns tHD Data hold from write end 0 – 0 – ns – 20 – 18 ns 10 – 10 – ns tHZWE tLZWE WE LOW to High Z [15, 16] WE HIGH to Low Z [15] Notes 14. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Test conditions for the read cycle use output loading shown in AC Test Loads and Waveforms section, unless specified otherwise. 15. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 16. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 17. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write. Any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write. Document Number: 001-84902 Rev. *D Page 8 of 19 CY62167G Automotive Switching Waveforms Figure 5. Read Cycle No. 1 of CY62167G (Address Transition Controlled) [18, 19] tRC ADDRESS tAA tOHA DATA I/O PREVIOUS DATAOUT VALID DATAOUT VALID Figure 6. Read Cycle No. 2 (OE Controlled) [19, 20, 21] ADDRESS tRC CE tPD tHZCE tACE OE tHZOE tDOE tLZOE BHE/ BLE tDBE tLZBE DATA I/O HIGH IMPEDANCE tHZBE DATAOUT VALID HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU ISB Notes 18. The device is continuously selected. OE = VIL, CE = VIL, BHE or BLE or both = VIL. 19. WE is HIGH for read cycle. 20. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 21. Address valid prior to or coincident with CE LOW transition. Document Number: 001-84902 Rev. *D Page 9 of 19 CY62167G Automotive Switching Waveforms (continued) Figure 7. Write Cycle No. 1 (WE Controlled) [22, 23, 24] tWC ADDRESS tSCE CE tBW BHE/ BLE tSA tAW tHA tPWE WE t DATA I/O HZWE tSD tLZWE tHD DATAIN VALID Notes 22. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 23. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write. 24. Data I/O is in HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH. Document Number: 001-84902 Rev. *D Page 10 of 19 CY62167G Automotive Switching Waveforms (continued) Figure 8. Write Cycle No. 2 (CE Controlled) [25, 26, 27] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE tBW BHE/ BLE OE tHZOE DATA I/O tSD tHD DATAIN VALID Notes 25. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 26. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write. 27. Data I/O is in high impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH. Document Number: 001-84902 Rev. *D Page 11 of 19 CY62167G Automotive Switching Waveforms (continued) Figure 9. Write Cycle No. 3 (BHE/BLE controlled, OE LOW) [28, 29, 30] tWC ADDRESS tSCE CE tAW tSA tHA tBW BHE/ BLE tPWE WE tHZWE DATA I/O tSD tHD tLZWE DATAIN VALID Notes 28. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 29. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write. 30. Data I/O is in high impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH. Document Number: 001-84902 Rev. *D Page 12 of 19 CY62167G Automotive Truth Table – CY62167G CE1 CE2 WE OE BHE BLE H X[31] X X X X X[31] L X X X X[31] X[31] X X L H H L H L Inputs/Outputs Mode Power HI-Z Deselect/Power-down Standby (ISB) X HI-Z Deselect/Power-down Standby (ISB) H H HI-Z Deselect/Power-down Standby (ISB) L L L Data Out (I/O0–I/O15) Read Active (ICC) H L H L Data Out (I/O0–I/O7); HI-Z (I/O8–I/O15) Read Active (ICC) H H L L H HI-Z (I/O0–I/O7); Data Out (I/O8–I/O15) Read Active (ICC) L H H H X X HI-Z Output disabled Active (ICC) L H L X L L Data In (I/O0–I/O15) Write Active (ICC) L H L X H L Data In (I/O0–I/O7); HI-Z (I/O8–I/O15) Write Active (ICC) L H L X L H HI-Z (I/O0–I/O7); Data In (I/O8–I/O15) Write Active (ICC) Note 31. The ‘X’ (Don’t care) state for the chip enables refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted. Document Number: 001-84902 Rev. *D Page 13 of 19 CY62167G Automotive Ordering Information Speed (ns) 55 45 Package Diagram Ordering Code Package Type CY62167G30-55BVXE 51-85150 48-ball VFBGA (6 × 8 × 1 mm) (Pb-free), Package Code: BZ48 CY62167G30-55ZXE 51-85183 48-pin TSOP I (12 × 18.4 × 1 mm) (Pb-free), Package Code: Z48A CY62167G30-45ZXA 51-85183 48-pin TSOP I (12 × 18.4 × 1 mm) (Pb-free), Package Code: Z48A CY62167G30-45BVXA 51-85150 48-ball VFBGA (6 × 8 × 1 mm) (Pb-free), Package Code: BZ48 Operating Range Automotive-E Automotive-A Ordering Code Definitions CY 621 6 7 G XX - XX XX X X Temperature Grade: X = E or A E = Automotive-E; A = Automotive-A Pb-free Package Type: XX = BV or Z BV = 48-ball VFBGA; Z = 48-pin TSOP I Speed Grade: XX = 45 or 55 45 = 45 ns; 55 = 55 ns Voltage Range: 30 = 3 V typ Process Technology: G = 65 nm Bus width: 7 = × 16 Density: 6 = 16-Mbit Family Code: 621 = MoBL SRAM family Company ID: CY = Cypress Document Number: 001-84902 Rev. *D Page 14 of 19 CY62167G Automotive Package Diagram Figure 10. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150 51-85150 *H Document Number: 001-84902 Rev. *D Page 15 of 19 CY62167G Automotive Package Diagram (continued) Figure 11. 48-pin TSOP I (12 × 18.4 × 1.0 mm) Z48A Package Outline, 51-85183 51-85183 *D Document Number: 001-84902 Rev. *D Page 16 of 19 CY62167G Automotive Acronyms Acronym Document Conventions Description Units of Measure BHE byte high enable BLE byte low enable °C Degrees Celsius CE chip enable MHz megahertz CMOS complementary metal oxide semiconductor A microamperes I/O input/output s microseconds OE output enable mA milliamperes SRAM static random access memory mm millimeters VFBGA very fine-pitch ball grid array ns nanoseconds WE write enable ohms % percent pF picofarads V volts W watts Document Number: 001-84902 Rev. *D Symbol Unit of Measure Page 17 of 19 CY62167G Automotive Document History Page Document Title: CY62167G Automotive, 16-Mbit (1M Words × 16 Bit) Static RAM with Error-Correcting Code (ECC) Document Number: 001-84902 Rev. ECN No. Orig. of Change Submission Date *C 5083752 NILE 01/13/2016 Changed status from Preliminary to Final. *D 5130998 NILE 02/12/2016 Updated Logic Block Diagram – CY62167G. Updated Pin Configurations: Added Note 3 and referred the same note in Figure 2. Updated DC Electrical Characteristics: Updated Note 7. Updated Data Retention Characteristics: Updated Note 10. Document Number: 001-84902 Rev. *D Description of Change Page 18 of 19 CY62167G Automotive Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2013-2016. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-84902 Rev. *D Revised February 12, 2016 Page 19 of 19 MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.