PD - 96906C
IRFB4610
IRFS4610
IRFSL4610
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
HEXFET® Power MOSFET
VDSS
RDS(on) typ.
max.
ID
D
G
S
G DS
G DS
G DS
D2Pak
TO-220AB
IRFB4610
100V
11m:
14m:
73A
TO-262
IRFSL4610
IRFS4610
Absolute Maximum Ratings
Symbol
Parameter
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V
Max.
Units
73
A
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V
52
IDM
Pulsed Drain Current f
290
PD @TC = 25°C
Maximum Power Dissipation
190
W
W/°C
V
Linear Derating Factor
1.3
VGS
Gate-to-Source Voltage
± 20
dV/dt
TJ
Peak Diode Recovery e
7.6
Operating Junction and
-55 to + 175
TSTG
Storage Temperature Range
V/ns
°C
300
Soldering Temperature, for 10 seconds
(1.6mm from case)
10lbxin (1.1Nxm)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
EAS (Thermally limited)
Single Pulse Avalanche Energy d
IAR
Avalanche Currentc
EAR
Repetitive Avalanche Energy f
mJ
370
See Fig. 14, 15, 16a, 16b,
A
mJ
Thermal Resistance
Symbol
Parameter
Typ.
Max.
RθJC
Junction-to-Case j
–––
0.77
RθCS
Case-to-Sink, Flat Greased Surface , TO-220
0.50
–––
RθJA
Junction-to-Ambient, TO-220 j
–––
62
RθJA
Junction-to-Ambient (PCB Mount) , D2Pak ij
–––
40
www.irf.com
Units
°C/W
1
5/22/08
IRF/B/S/SL4610
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Min. Typ. Max. Units
–––
–––
ΔV(BR)DSS/ΔTJ Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
–––
0.085
–––
V/°C Reference to 25°C, ID = 1mAc
–––
11
14
mΩ VGS = 10V, ID = 44A f
VGS(th)
Gate Threshold Voltage
2.0
–––
4.0
V
IDSS
Drain-to-Source Leakage Current
μA
RG
–––
–––
20
–––
–––
250
Gate-to-Source Forward Leakage
–––
–––
200
Gate-to-Source Reverse Leakage
–––
–––
-200
Gate Input Resistance
–––
1.5
–––
V
Conditions
100
IGSS
Drain-to-Source Breakdown Voltage
VGS = 0V, ID = 250μA
VDS = VGS, ID = 100μA
VDS = 100V, VGS = 0V
VDS = 100V, VGS = 0V, TJ = 125°C
nA
VGS = 20V
VGS = -20V
Ω
f = 1MHz, open drain
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
Conditions
gfs
Qg
Forward Transconductance
73
–––
–––
S
Total Gate Charge
–––
90
140
nC
Qgs
Gate-to-Source Charge
–––
20
–––
Qgd
Gate-to-Drain ("Miller") Charge
–––
36
–––
td(on)
Turn-On Delay Time
–––
18
–––
tr
Rise Time
–––
87
–––
ID = 44A
td(off)
Turn-Off Delay Time
–––
53
–––
RG = 5.6Ω
tf
Fall Time
–––
70
–––
Ciss
Input Capacitance
–––
3550
–––
Coss
Output Capacitance
–––
260
–––
VDS = 50V
Reverse Transfer Capacitance
–––
Coss eff. (ER) Effective Output Capacitance (Energy Related) –––
Coss eff. (TR) Effective Output Capacitance (Time Related)
–––
150
–––
ƒ = 1.0MHz
330
–––
VGS = 0V, VDS = 0V to 80V h, See Fig.11
380
–––
VGS = 0V, VDS = 0V to 80V g, See Fig. 5
Crss
VDS = 50V, ID = 44A
ID = 44A
VDS = 80V
VGS = 10V f
ns
VDD = 65V
VGS = 10V f
pF
VGS = 0V
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
73
ISM
(Body Diode)
Pulsed Source Current
–––
–––
290
VSD
(Body Diode)c
Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
Reverse Recovery Current
ton
Forward Turn-On Time
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.39mH
RG = 25Ω, IAS = 44A, VGS =10V. Part not recommended for use
above this value.
ISD ≤ 44A, di/dt ≤ 660A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400μs; duty cycle ≤ 2%.
2
–––
A
1.3
V
–––
35
53
ns
–––
42
63
–––
44
66
65
98
–––
2.1
–––
D
MOSFET symbol
showing the
integral reverse
–––
–––
Conditions
S
p-n junction diode.
TJ = 25°C, IS = 44A, VGS = 0V f
VR = 85V,
TJ = 25°C
TJ = 125°C
nC
G
TJ = 25°C
IF = 44A
di/dt = 100A/μs f
TJ = 125°C
A
TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C
www.irf.com
IRF/B/S/SL4610
1000
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
100
BOTTOM
10
4.5V
≤ 60μs PULSE WIDTH
Tj = 25°C
1
BOTTOM
100
4.5V
≤ 60μs PULSE WIDTH
Tj = 175°C
10
0.1
1
10
100
0.1
VDS , Drain-to-Source Voltage (V)
10
100
Fig 2. Typical Output Characteristics
1000.0
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current(Α)
1
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
100.0
TJ = 175°C
10.0
TJ = 25°C
1.0
VDS = 25V
≤ 60μs PULSE WIDTH
0.1
2.0
3.0
4.0
5.0
6.0
7.0
ID = 73A
VGS = 10V
2.5
2.0
1.5
1.0
0.5
8.0
-60 -40 -20
VGS, Gate-to-Source Voltage (V)
6000
VGS, Gate-to-Source Voltage (V)
Coss = Cds + Cgd
4000
Ciss
3000
2000
1000
Coss
Crss
10
100
VDS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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ID= 44A
VDS = 80V
16
VDS= 50V
VDS= 20V
12
8
4
0
0
1
20 40 60 80 100 120 140 160 180
Fig 4. Normalized On-Resistance vs. Temperature
20
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
5000
0
TJ , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
C, Capacitance (pF)
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
0
20
40
60
80
100
120
140
QG Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
IRF/B/S/SL4610
1000
100.0
ID, Drain-to-Source Current (A)
ISD , Reverse Drain Current (A)
1000.0
TJ = 175°C
10.0
TJ = 25°C
1.0
OPERATION IN THIS AREA
LIMITED BY R DS (on)
100μsec
100
10
1msec
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
1
2.0
V(BR)DSS , Drain-to-Source Breakdown Voltage
ID , Drain Current (A)
80
60
40
20
0
50
75
100
125
150
1000
125
120
115
110
105
100
175
-60 -40 -20
TJ , Junction Temperature (°C)
0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Drain-to-Source Breakdown Voltage
1600
EAS, Single Pulse Avalanche Energy (mJ)
2.0
1.5
Energy (μJ)
100
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
25
10
VDS , Drain-toSource Voltage (V)
VSD , Source-to-Drain Voltage (V)
1.0
0.5
ID
4.6A
6.3A
BOTTOM 44A
TOP
1200
800
400
0
0.0
0
20
40
60
80
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
DC
0.1
0.1
100
25
50
75
100
125
150
175
Starting TJ, Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
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IRF/B/S/SL4610
1
Thermal Response ( Z thJC )
D = 0.50
0.20
0.10
0.1
0.05
R1
R1
0.02
0.01
τJ
0.01
τJ
τ1
R2
R2
τ2
τ1
τC
τ
Ri (°C/W) τi (sec)
0.4367 0.001016
0.3337
τ2
0.009383
Ci= τi/Ri
Ci i/Ri
0.001
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Avalanche Current (A)
1000
Duty Cycle = Single Pulse
100
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ΔTj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
0.05
10
0.10
1
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
400
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 44A
300
200
100
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
www.irf.com
5
IRF/B/S/SL4610
16
ID = 1.0A
ID = 1.0mA
ID = 250μA
ID = 100μA
4.0
12
IRRM - (A)
VGS(th) Gate threshold Voltage (V)
5.0
3.0
8
IF = 29A
VR = 85V
4
2.0
TJ = 125°C
TJ = 25°C
0
1.0
-75
-50
-25
0
25
50
75
100 200 300 400 500 600 700 800 900 1000
100 125 150 175
dif / dt - (A / μs)
TJ , Temperature ( °C )
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage Vs. Temperature
16
300
12
QRR - (nC)
IRRM - (A)
200
8
100
4
IF = 44A
VR = 85V
IF = 29A
VR = 85V
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
0
0
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
dif / dt - (A / μs)
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
300
QRR - (nC)
200
100
0
IF = 44A
VR = 85V
TJ = 125°C
TJ = 25°C
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRF/B/S/SL4610
D.U.T
Driver Gate Drive
-
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
DRIVER
L
VDS
tp
D.U.T
RG
+
V
- DD
IAS
VGS
20V
tp
A
0.01Ω
I AS
Fig 22a. Unclamped Inductive Test Circuit
LD
Fig 22b. Unclamped Inductive Waveforms
VDS
VDS
90%
+
VDD -
10%
D.U.T
VGS
VGS
Pulse Width < 1μs
Duty Factor < 0.1%
td(on)
Fig 23a. Switching Time Test Circuit
tr
td(off)
tf
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
L
DUT
0
VCC
Vgs(th)
1K
Qgs1 Qgs2
Fig 24a. Gate Charge Test Circuit
www.irf.com
Qgd
Qgodr
Fig 24b. Gate Charge Waveform
7
IRF/B/S/SL4610
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
EXAMPLE: T HIS IS AN IRF 1010
LOT CODE 1789
AS S EMBLED ON WW 19, 2000
IN T HE AS S EMBLY LINE "C"
Note: "P" in as s embly line pos ition
indicates "Lead - Free"
INT ERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 0 = 2000
WEEK 19
LINE C
TO-220AB packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
8
www.irf.com
IRF/B/S/SL4610
TO-262 Package Outline (Dimensions are shown in millimeters (inches))
TO-262 Part Marking Information
EXAMPLE: T HIS IS AN IRL3103L
LOT CODE 1789
AS S EMBLED ON WW 19, 1997
IN T HE AS S EMBLY LINE "C"
INT ERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 7 = 1997
WEEK 19
LINE C
OR
INT ERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
DAT E CODE
P = DES IGNAT ES LEAD-F REE
PRODUCT (OPT IONAL)
YEAR 7 = 1997
WEEK 19
A = AS S EMBLY S IT E CODE
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
www.irf.com
9
IRF/B/S/SL4610
D2Pak Package Outline (Dimensions are shown in millimeters (inches))
D2Pak Part Marking Information
T HIS IS AN IRF530S WIT H
LOT CODE 8024
AS S EMBLED ON WW 02, 2000
IN T HE AS S EMBLY LINE "L"
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBER
F530S
DAT E CODE
YEAR 0 = 2000
WEEK 02
LINE L
AS S EMBLY
LOT CODE
T HIS IS AN IRF530S WIT H
LOT CODE 8024
For GB Production
AS S EMBLED ON WW 02, 2000
IN T HE AS S EMBLY LINE "L"
INT ERNAT IONAL
RECT IFIER
LOGO
LOT CODE
10
PART NUMBER
F530S
DAT E CODE
www.irf.com
IRF/B/S/SL4610
D2Pak Tape & Reel Information
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
1.65 (.065)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 5/08
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11