LINER LTC6405 2.7ghz, 5v, low noise, rail-to-rail input differential amplifier/driver Datasheet

LTC6405
2.7GHz, 5V, Low Noise,
Rail-to-Rail Input Differential
Amplifier/Driver
Features
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Description
Low Noise: 1.6nV/√Hz RTI
Low Power: 18mA at 5V
Low Distortion (HD2/HD3):
–82dBc/–65dBc at 50MHz, 2VP-P
–97dBc/–91dBc at 25MHz, 2VP-P
Rail-to-Rail Differential Input
4.5V to 5.25V Supply Voltage Range
Fully Differential Input and Output
Adjustable Output Common Mode Voltage
800MHz –3dB Bandwidth with AV = 1
Gain-Bandwidth Product: 2.7GHz
Low Power Shutdown
Available in 8-Lead MSOP and 16-Lead
3mm × 3mm × 0.75mm QFN Packages
The LTC®6405 is a very low noise, low distortion, fully
differential input/output amplifier optimized for 5V, single
supply operation. The LTC6405 input common mode range
is rail-to-rail, while the output common mode voltage is
independently adjustable by applying a voltage on the
VOCM pin. This makes the LTC6405 ideal for level shifting
signals with a wide common mode range for driving 12-bit
to 16-bit single supply, differential input ADCs.
A 2.7GHz gain-bandwidth product results in 65dB linearity
for 50MHz input signals. The LTC6405 is unity gain stable
and the closed-loop bandwidth extends from DC to 800MHz.
The output voltage swing extends from near-ground to
4V, to be compatible with a wide range of ADC converter
input requirements. The LTC6405 draws only 18mA, and
has a hardware shutdown feature which reduces current
consumption to 400µA.
Applications
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Differential Input ADC Driver
Single-Ended to Differential Conversion
Level-Shifting Ground-Referenced Signals
Level-Shifting VCC-Referenced Signals
High-Linearity Direct Conversion Receivers
The LTC6405 is available in a compact 3mm × 3mm 16‑pin
leadless QFN package, as well as an 8-lead MSOP package,
and operates over a –40°C to 85°C temperature range.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical Application
Single-Ended Input to Differential Output
with Common Mode Level Shifting
50Ω
196Ω
200Ω
5V 0.1µF
61.9Ω
SIGNAL
GENERATOR
1VP-P
VOCM
0.01µF
+
2.5V
LTC6405UD
–
2.5V
1VP-P
INPUT VOLTAGE NOISE DENSITY (nV/ Hz)
VS
4
1.8pF
0V
200Ω
221Ω
1.8pF
4
VS = 5V
NOISE MEASURED AT f = 1MHz
3
3
in
2
2
en
1
1
0
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5
INPUT COMMON MODE VOLTAGE (V)
5
INPUT CURRENT NOISE DENSITY (pA/ Hz)
2VP-P
Input Noise Density vs Input
Common Mode Voltage
0
6405 TA01b
6405 TA01
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LTC6405
Absolute Maximum Ratings
(Note 1)
Total Supply Voltage (V+ to V–).................................5.5V
Input Current
(+IN, –IN, VOCM, SHDN, V TIP) (Note 2)............. ±10mA
Output Short-Circuit Duration (Note 3)............. Indefinite
Operating Temperature Range
(Note 4)................................................–40°C to 85°C
Specified Temperature Range (Note 5)
LTC6405I..............................................–40°C to 85°C
LTC6405C................................................. 0°C to 70°C
Junction Temperature............................................ 150°C
Storage Temperature Range................... –65°C to 150°C
Pin Configuration
2
V–
3
VOCM
4
TJMAX = 150°C, θJA = 40°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 9) IS V –, MUST BE SOLDERED TO PCB
–OUTF
12 V–
11 V+
17
10 V+
9
5
6
7
V–
8
+OUTF
MS8E PACKAGE
8-LEAD PLASTIC MSOP
V+
+OUT
+IN
SHDN
V–
–OUT
1
–IN
8
7
6
5
SHDN
VTIP
9
–OUT
16 15 14 13
TOP VIEW
–IN 1
VOCM 2
V+ 3
+OUT 4
+IN
NC
TOP VIEW
UD PACKAGE
16-LEAD (3mm × 3mm) PLASTIC QFN
TJMAX = 150°C, θJA = 68°C/W, θJC = 4.2°C/W
EXPOSED PAD (PIN 17) IS V–, MUST BE SOLDERED TO PCB
order information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
LTC6405CMS8E#PBF
LTC6405CMS8E#TRPBF
LTDKN
8-Lead Plastic MSOP
0°C to 70°C
LTC6405IMS8E#PBF
LTC6405IMS8E#TRPBF
LTDKN
8-Lead Plastic MSOP
–40°C to 85°C
LTC6405CUD#PBF
LTC6405CUD#TRPBF
LDKP
16-Lead (3mm × 3mm) Plastic QFN
0°C to 70°C
LTC6405IUD#PBF
LTC6405IUD#TRPBF
LDKP
16-Lead (3mm × 3mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
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LTC6405
DC Electrical Characteristics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, V– = 0V, VCM = VOCM = VICM = 2.5V, VSHDN = open,
circuit component values in Figure 1 used, unless otherwise noted. VS is defined as (V+ – V–). VOUTCM is defined as (V+OUT + V–OUT)/2.
VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT).
SYMBOL
PARAMETER
CONDITIONS
VOSDIFF
Differential Offset Voltage (Input Referred)
∆VOSDIFF/∆T
Differential Offset Voltage Drift (Input Referred)
IB
Input Bias Current (Note 6)
VICM = 5V (Note 12)
VICM = 2.5V
VICM = 0V (Note 12)
VICM = 5V (Note 12)
VICM = 2.5V
VICM = 0V (Note 12)
VICM = 5V
VICM = 2.5V
VICM = 0V
VICM = 5V
VICM = 2.5V
VICM = 0V
Common Mode
Differential Mode
Differential
IOS
Input Offset Current (Note 6)
RIN
Input Resistance
CIN
Input Capacitance
en
Differential Input Referred Noise Voltage Density
in
Input Noise Current Density
enVOCM
VICMR (Note 7)
Input Referred Common Mode Output Noise Voltage
Density
Input Signal Common Mode Range
CMRRI
(Note 8)
CMRRIO
(Note 8)
PSRR
(Note 9)
PSRRCM
(Note 9)
GCM
Input Common Mode Rejection Ratio
(Input Referred) ∆VICM/∆VOSDIFF
Output Common Mode Rejection Ratio
(Input Referred) ∆VOCM/∆VOSDIFF
Differential Power Supply Rejection
(∆VS/∆VOSDIFF)
Output Common Mode Power Supply Rejection
(∆VS/∆VOSCM)
Common Mode Gain (∆VOUTCM/∆VOCM)
∆GCM
Common Mode Gain Error 100 • (GCM – 1)
BAL
Output Balance (∆VOUTCM/∆VOUTDIFF)
∆VOUTDIFF = 2V
Single-Ended Input
Differential Input
MIN
TYP
MAX
UNITS
±7
±3.5
±7
–24
±1
±0.5
±1
1.5
1
3
8
–7
–14
±0.5
±0.5
±0.5
230
3.5
1
mV
mV
mV
µV/°C
µV/°C
µV/°C
µA
µA
µA
µA
µA
µA
kΩ
kΩ
pF
l
l
l
l
l
l
l
l
f = 1MHz, Not Including RI/RF
Noise
f = 1MHz, Not Including RI/RF
Noise
f = 1MHz
1.6
nV/√Hz
2.4
pA/√Hz
9.5
nV/√Hz
Op-Amp Inputs
l
V–
V+
VICM from 0V to 5V
l
50
75
dB
VOCM from 0.5V to 3.9V
l
50
75
dB
VS = 4.5V to 5.25V
l
50
75
dB
VS = 4.5V to 5.25V
l
55
70
dB
VOCM from 0.5V to 3.9V
l
1
VOCM from 0.5V to 3.9V
l
±0.25
±0.8
%
l
l
–40
–40
±15
dB
dB
mV
VOSCM
Common Mode Offset Voltage (VOUTCM – VOCM)
l
–60
–65
±6
∆VOSCM/∆T
Common Mode Offset Voltage Drift
l
20
VOUTCMR
(Note 7)
RINVOCM
Output Signal Common Mode Range
(Voltage Range for the VOCM Pin)
Input Resistance, VOCM Pin
l
0.5
l
13
VOCM
Self-Biased Voltage at the VOCM Pin
VOCM = Open
l
VOUT
Output Voltage, High, +OUT/–OUT Pins
IL = 0
IL = –5mA
IL = 0
IL = 5mA
l
l
Output Voltage, Low, +OUT/–OUT Pins
ISC
±4
Output Short-Circuit Current, +OUT/–OUT Pins
(Note 10)
V/V
µV/°C
3.9
V
19
25
kΩ
2.35
2.5
2.65
3.9
3.85
4
3.95
0.3
0.42
±60
l
l
l
V
±40
0.45
0.54
V
V
V
V
V
mA
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LTC6405
DC Electrical Characteristics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, V– = 0V, VCM = VOCM = VICM = 2.5V, VSHDN = open,
circuit component values in Figure 1 used, unless otherwise noted. VS is defined as (V+ – V–). VOUTCM is defined as (V+OUT + V–OUT)/2.
VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
AVOL
Large-Signal Open Loop Voltage Gain
VS
Supply Voltage Range
l
IS
Supply Current
l
18
23
mA
ISHDN
Supply Current in Shutdown
VSHDN = 0V
l
0.4
1
mA
RSHDN
SHDN Pull-Up Resistor
VSHDN = 0V to 0.5V
l
30
50
70
kΩ
VIL
SHDN Input Logic Low
l
1.25
1.8
l
90
4.5
UNITS
dB
5.25
2
V
V
VIH
SHDN Input Logic High
tON
Turn-On Time
200
2.55
ns
V
tOFF
Turn-Off Time
50
ns
AC Electrical Characteristics
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, V– = 0V, VCM = VOCM = VICM = 2.5V, VSHDN = open,
RLOAD = 400Ω, circuit component values in Figure 2 used, unless otherwise noted. VS is defined as (V+ – V–). VICM is defined as (V+IN
+ V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT).
SYMBOL
PARAMETER
CONDITIONS
SR
Slew Rate
Differential Output
GBW
Gain-Bandwidth Product
fTEST = 27MHz
f–3dB
–3dB Frequency (See Figure 2)
QFN Package
MSOP Package
50MHz Distortion
Differential Input, VOUTDIFF = 2VP-P
(Note 13)
VOCM = 2.5V, VS = 5V
2nd Harmonic
3rd Harmonic
MIN
TYP
MAX
690
500
400
l
UNITS
V/µS
2.7
GHz
800
750
MHz
MHz
–80
–64
–53
dBc
dBc
VOCM = 2.5V, VS = 5V, RLOAD = 800Ω
2nd Harmonic
3rd Harmonic
–82
–66
dBc
dBc
VOCM = 2.5V, VS = 5V, RLOAD = 800Ω,
RI = RF = 499Ω
2nd Harmonic
3rd Harmonic
–82
–64
dBc
dBc
50MHz Distortion
Single-Ended Input, VOUTDIFF = 2VP-P
(Note 13)
VOCM = 2.5V, VS = 5V, RLOAD = 800Ω,
RI = RF = 499Ω
2nd Harmonic
3rd Harmonic
–72
–77
dBc
dBc
3rd-Order IMD at 49.5MHz, 50.5MHz
VOUTDIFF = 2VP-P Envelope,
RLOAD = 800Ω
–63
dBc
Equivalent OIP3 at 50MHz (Note 11)
RLOAD = 800Ω
35.5
dBm
tS
Settling Time
VOUTDIFF = 2V Step
1% Settling
0.1% Settling
NF
Noise Figure at 50MHz
Shunt-Terminated to 50Ω, RS = 50Ω
ZIN = 200Ω (RI = 100Ω, RF = 300Ω)
6
11
ns
ns
14.4
7.5
dB
dB
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LTC6405
Electrical Characteristics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Input pins (+IN, –IN, VOCM, SHDN and VTIP) are protected by
steering diodes to either supply. If the inputs should exceed either supply
voltage, the input current should be limited to less than 10mA. In addition,
the inputs +IN, –IN are protected by a pair of back-to-back diodes. If the
differential input voltage exceeds 1.4V, the input current should be limited
to less than 10mA.
Note 3: A heat sink may be required to keep the junction temperature
below the Absolute Maximum Rating when the output is shorted
indefinitely.
Note 4: The LTC6405C/LTC6405I are guaranteed functional over the
operating temperature range –40°C to 85°C.
Note 5: The LTC6405C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6405C is designed, characterized, and expected
to meet specified performance from –40°C to 85°C but is not tested or
QA sampled at these temperatures. The LTC6405I is guaranteed to meet
specified performance from –40°C to 85°C.
Note 6: Input bias current is defined as the average of the input currents
flowing into the inputs (–IN, and +IN). Input Offset current is defined as
the difference between the input currents (IOS = IB+ – IB–).
Note 7: Input common mode range is tested using the test circuit of Figure
1 by taking 3 measurements of differential gain with a ±1VDC differential
output with VICM = 0V; VICM = 2.5V; VICM = 5V, verifying that the
differential gain has not deviated from the VICM = 2.5V case by more than
0.5%, and that the common mode offset (VOSCM) has not deviated from
the common mode offset at VICM = 2.5V by more than ±35mV.
The voltage range for the output common mode range is tested using the
test circuit of Figure 1 by applying a voltage on the VOCM pin and testing at
both VOCM = 2.5V and at the Electrical Characteristics table limits to verify
that the common mode offset (VOSCM) has not deviated by more than
±20mV from the VOCM = 2.5V case.
Note 8: Input CMRR is defined as the ratio of the change in the input
common mode voltage at the pins +IN or –IN to the change in differential
input referred voltage offset. Output CMRR is defined as the ratio of
the change in the voltage at the VOCM pin to the change in differential
input referred voltage offset. This specification is strongly dependent on
feedback ratio matching between the two outputs and their respective
inputs, and it is difficult to measure actual amplifier performance. (See
the “Effects of Resistor Pair Mismatch” in the Applications Information
section of this data sheet.) For a better indicator of actual amplifier
performance independent of feedback component matching, refer to the
PSRR specification.
Note 9: Differential Power Supply Rejection (PSRR) is defined as the
ratio of the change in supply voltage to the change in differential input
referred voltage offset. Common mode power supply rejection (PSRRCM)
is defined as the ratio of the change in supply voltage to the change in the
common mode offset, VOUTCM – VOCM.
Note 10: Extended operation with the output shorted may cause the
junction temperature to exceed the 150°C limit.
Note 11: Because the LTC6405 is a feedback amplifier with low output
impedance, a resistive load is not required when driving an ADC.
Therefore, typical output power can be very small in many applications. In
order to compare the LTC6405 with “RF style” amplifiers that require 50Ω
load, the output voltage swing is converted to dBm as if the outputs were
driving a 50Ω load. For example, 2VP-P output swing is equal to 10dBm
using this convention.
Note 12: Includes offset/drift induced by feedback resistors mismatch. See
the Applications Information section for more details.
Note 13: QFN package only—refer to datasheet curves for MSOP package
numbers.
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LTC6405
Typical Performance Characteristics
Differential Input Referred
Offset Voltage vs Input Common
Mode Voltage
1.0
1.0
0.4
0.6
0.2
0
0.4
0.2
0
–0.2
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
–1.0
–50
–25
25
50
0
TEMPERATURE (°C)
75
100
–1.0
TA = –40°C
TA = 0°C
TA = 25°C
TA = 70°C
TA = 85°C
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5
INPUT COMMON MODE VOLTAGE (V)
Supply Current vs Supply Voltage
20
VSHDN = OPEN
TA = –40°C
TA = 0°C
TA = 25°C
TA = 70°C
TA = 85°C
10
5
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
SUPPLY VOLTAGE (V)
6405 G04
5
4
3
–25
25
50
0
TEMPERATURE (°C)
600
15
10
0
TA = –40°C
TA = 0°C
TA = 25°C
TA = 70°C
TA = 85°C
0
0.5
1
1.5 2 2.5 3 3.5
SHDN VOLTAGE (V)
4
4.5
100
Shutdown Supply Current
vs Supply Voltage
VS = 5V
5
75
6405 G03
Supply Current vs SHDN Voltage
TOTAL SUPPLY CURRENT (mA)
TOTAL SUPPLY CURRENT (mA)
15
6
6405 G02
6405 G01
20
VS = 5V
VOCM = 2.5V
8 VICM = 2.5V
FIVE REPRESENTATIVE UNITS
7
2
–50
5
SHUTDOWN SUPPLY CURRENT (µA)
DIFFERENTIAL VOS (mV)
0.6
9
VS = 5V
0.1% FEEDBACK NETWORK
VOCM = 2.5V
RESISTORS REPRESENTRI = RF = 200Ω ATIVE UNIT
0.8
DIFFERENTIAL VOS (V)
0.8
VS = 5V
VOCM = 2.5V
VICM = 2.5V
RI = RF = 200Ω
FIVE REPRESENTATIVE UNITS
Common Mode Offset Voltage
vs Temperature
COMMON MODE OFFSET VOLTAGE (mV)
Differential Input Referred Offset
Voltage vs Temperature
5
6405 G05
500
400
VSHDN = V –
TA = – 40°C
TA = 0°C
TA = 25°C
TA = 70°C
TA = 85°C
300
200
100
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
SUPPLY VOLTAGE (V)
6405 G06
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LTC6405
Typical Performance Characteristics
Input Noise Density vs Input
Common Mode Voltage
100
10
in
1k
10k
100k
FREQUENCY (Hz)
1
10M
1M
in
2
2
en
1
1
0
6405 G07
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5
INPUT COMMON MODE VOLTAGE (V)
5
VS = 5V
RI = RF = 200Ω
10
1
1
10
100
FREQUENCY (MHz)
680
660
640
620
600
–50
0
1000 2000
6405 G10
–25
25
50
0
TEMPERATURE (°C)
100
75
6405 G09
Differential PSRR vs Frequency
90
80
80
70
70
60
60
50
40
0.1
VS = 5V
700
CMRR vs Frequency
100
0.01
720
6405 G08
CMRR (dB)
OUTPUT IMPEDANCE (Ω)
3
3
Differential Output Impedance
vs Frequency
1000
4
VS = 5V
NOISE MEASURED AT f = 1MHz
PSRR (dB)
1
100
en
INPUT VOLTAGE NOISE DENSITY (nV/ Hz)
10
4
INPUT CURRENT NOISE DENSITY (pA/ Hz)
VS = 5V
VICM = 2.5V
INPUT CURRENT NOISE DENSITY (pA/ Hz)
INPUT VOLTAGE NOISE DENSITY (nV/ Hz)
100
Differential Slew Rate
vs Temperature
SLEW RATE (V/µs)
Input Noise Density vs Frequency
VS = 5V
VOCM = 2.5V
30
RI = RF = 200Ω, CF = 1.8pF
0.1% FEEDBACK NETWORK RESISTORS
20
1
10
100
1000 2000
FREQUENCY (MHz)
6405 G11
VS = 5V
50
40
30
20
10
1
10
100
FREQUENCY (MHz)
1000 2000
6405 G12
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LTC6405
Typical Performance Characteristics
Small Signal Step Response
(QFN Package)
Overdriven Output
Transient Response
Large Signal Step Response
4.5
+OUT
VOLTAGE (V)
0.2V/DIV
20mV/DIV
3.5
–OUT
6405 G13
10ns/DIV
VS = 5V
RLOAD = 400Ω
VIN = 2VP-P, DIFFERENTIAL
30
GAIN (dB)
20
10
0
30
AV = 100
AV = 20
20
10
AV = 10
AV = 5
0
AV = 2
AV = 1
–10
–20
–30
VS = 5V
–40 VOCM = VICM = 2.5V
RLOAD = 400Ω
–50
1
10
100
FREQUENCY (MHz)
AV (V/V) RI (Ω)
1
2
5
10
20
100
200
200
200
200
200
200
2.5
2.0
1.5
0
6405 G14
1000 2000
RF (Ω)
CF (pF)
200
400
1k
2k
4k
20k
1.8
1.5
0.6
0.2
0
0
+OUT
6405 G15
100ns/DIV
VS = 5V
VOCM = 2.5V
RLOAD = 400Ω TO GROUND PER OUTPUT
Frequency Response
vs Load Capacitance
GAIN (dB)
40
3.0
0.5
Frequency Response vs Input
Common Mode Voltage
10
CL = 0pF
CL = 2pF
CL = 3pF
CL= 4.7pF
CL = 10pF
5
0
–5
–10
–20
VS = 5V
–30 VOCM = VICM = 2.5V
RLOAD = 400Ω
–40 RI = RF = 200Ω, CF = 1.8pF
CAPACITOR VALUES ARE FROM EACH
–50 OUTPUT TO GROUND.
NO SERIES RESISTORS ARE USED.
–60
1
10
100
1000 2000
FREQUENCY (MHz)
6405 G17
GAIN (dB)
Frequency Response
vs Closed Loop Gain
–OUT
1.0
–OUT
10ns/DIV
RI = RF = 200Ω
VS = 5V
VOCM = VICM = 2.5V CF = 1.8pF
RLOAD = 400Ω
CL = 0pF
50
4.0
+OUT
–10
–15
–20
VICM = 0V
VICM = 0.5V
VICM = 1.25V
VICM = 2.5V
VICM = 4V
VICM = 5V
–25
VS = 5V
VOCM = 2.5V
–35 RLOAD = 400Ω
RI = RF = 200Ω, CF = 1.8pF
–40
1
10
100
FREQUENCY (MHz)
–30
1000 2000
6405 G18
6405 G16
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LTC6405
Typical Performance Characteristics
Harmonic Distortion
vs Input Common Mode Voltage
Harmonic Distortion vs Frequency
–60
–70
HD3
RI = RF = 499Ω
–80
HD3
RI = RF = 200Ω
–90
–100
–110
HD2
RI = RF = 499Ω
1
–70
–80
–90
HD2
RI = RF = 200Ω
10
FREQUENCY (MHz)
RLOAD = 800Ω
VS = 5V
VOCM = 2.5V
VOUTDIFF = 2VP-P
–50 VTIP = OPEN (2.8V) DIFFERENTIAL INPUTS
fIN = 50MHz
RI = RF = 200Ω
HD3
–60
–100
100
RI = RF = 499Ω
HD2
RI = RF = 499Ω
RI = RF = 200Ω
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
INPUT COMMON MODE VOLTAGE (V)
HD2, RI = RF = 200Ω
HD2, RI = RF = 499Ω
HD3, RI = RF = 200Ω
HD3, RI = RF = 499Ω
10
FREQUENCY (MHz)
–60
–70
–100
6405 G22
RLOAD = 800Ω
RI = RF = 499Ω
VOUTDIFF = 2VP-P
SINGLE-ENDED INPUT
HD2
–80
HD3
–90
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
INPUT COMMON MODE VOLTAGE (V)
–100
–4
–2
(0.4VP-P)
5
THIRD ORDER IMD (dBc)
–100
100
6405 G25
8
10
(2VP-P)
Intermodulation Distortion
vs Input Amplitude
–40
–50
–90
0
2
4
6
INPUT AMPLITUDE (dBm)
6405 G24
–40
–80
10
FREQUENCY (MHz)
VS = 5V
VOCM = 2.5V
VTIP = 2.35V
fIN = 50MHz
–70
Intermodulation Distortion
vs Input Common Mode Voltage
–30
10
(2VP-P)
VS = 5V
VOCM = VICM = 2.5V
–50 VTIP = 2.35V
fIN = 50MHz
RLOAD = 800Ω
–60 RI = RF = 499Ω
SINGLE-ENDED INPUT
6405 G23
Intermodulation Distortion
vs Frequency
1
HD3
–80
–90
100
VS = 5V
–40 VOCM = VICM = 2.5V
VTIP = OPEN (2.8V)
RLOAD = 800Ω
–50
RI = RF = 200Ω
2 TONES, 1MHz TONE SPACING,
–60
2VP-P COMPOSITE
DIFFERENTIAL INPUTS
–70
8
6405 G21
DISTORTION (dBc)
DISTORTION (dBc)
DISTORTION (dBc)
–80
0
2
4
6
INPUT AMPLITUDE (dBm)
Harmonic Distortion
vs Input Amplitude
HD2
1
–100
–4
–2
(0.4VP-P)
–50
–70
THIRD ORDER IMD (dBc)
5
–40
–50
–110
–90
–40
RLOAD = 800Ω
VS = 5V
–40 VOCM = VICM = 2.5V VOUTDIFF = 2VP-P
SINGLE-ENDED INPUT
VTIP = 2.35V
–110
–80
Harmonic Distortion
vs Input Common Mode Voltage
–30
–60
HD3
6405 G20
Harmonic Distortion vs Frequency
–100
–70
HD2
6405 G19
–90
VS = 5V
VOCM = VICM = 2.5V
–50 VTIP = OPEN (2.8V)
fIN = 50MHz
RLOAD = 800Ω
–60 RI = RF = 200Ω
DIFFERENTIAL INPUTS
THIRD ORDER IMD (dBc)
–120
DISTORTION (dBc)
DISTORTION (dBc)
–50
–40
–40
VS = 5V
VOCM = VICM = 2.5V
VTIP = OPEN (2.8V)
RLOAD = 800Ω, VOUTDIFF = 2VP-P
DIFFERENTIAL INPUTS
–40
Harmonic Distortion
vs Input Amplitude
DISTORTION (dBc)
–30
(QFN Package)
–60
VS = 5V
VOCM = 2.5V
VTIP = OPEN (2.8V)
–80 fIN = 50MHz
RLOAD = 800Ω
RI = RF = 200Ω
–90 2 TONES, 1MHz TONE SPACING,
2VP-P COMPOSITE
DIFFERENTIAL INPUTS
–100
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
INPUT COMMON MODE VOLTAGE (V)
–70
VS = 5V
VOCM = VICM = 2.5V
–50 VTIP = OPEN (2.8V)
fIN = 50MHz
RLOAD = 800Ω
–60 RI = RF = 200Ω
2 TONES, 1MHz TONE SPACING
DIFFERENTIAL INPUTS
–70
–80
–90
5
6405 G26
–100
–4
–2
(0.4VP-P)
0
2
4
6
INPUT AMPLITUDE (dBm)
8
10
(2VP-P)
6405 G27
6405fb
For more information www.linear.com/6405
9
LTC6405
Typical Performance Characteristics
Frequency Response
vs Load Capacitance
Harmonic Distortion
vs Input Amplitude
Harmonic Distortion vs Frequency
–30
CL = 10pF
20
0
CL = 0pF
–10
VS = 5V
VOCM = VICM = 2.5V
= 400Ω
R
–30 RLOAD
I = RF = 300Ω, CF = 1pF
CAPACITOR VALUES ARE FROM EACH
–40 OUTPUT TO GROUND.
NO SERIES RESISTORS ARE USED.
–50
1
10
100
1000 2000
FREQUENCY (MHz)
–20
DISTORTION (dBc)
10
–40
VS = 5V
–40 VOCM = VICM = 2.5V
VTIP = OPEN (2.8V)
RLOAD = 800Ω
–50
RI = RF = 300Ω
= 2VP-P
V
–60 OUTDIFF
DIFFERENTIAL INPUTS
DISTORTION (dBc)
30
GAIN (dB)
(MSOP Package)
–70
–80
HD3
–90
HD2
–100
–110
1
10
FREQUENCY (MHz)
6405 G28
–80
HD2
HD3
–80
–90
100
6405 G29
–40
DISTORTION (dBc)
DISTORTION (dBc)
–30
–70
HD2
–70
–100
–4
–2
(0.4VP-P)
0
2
4
6
INPUT AMPLITUDE (dBm)
8
10
(2VP-P)
6405 G30
Harmonic Distortion
vs Input Amplitude
Harmonic Distortion vs Frequency
VS = 5V
–40 VOCM = VICM = 2.5V
VTIP = OPEN (2.8V)
RLOAD = 800Ω
–50
RI = RF = 300Ω
= 2VP-P
V
–60 OUTDIFF
SINGLE-ENDED INPUT
VS = 5V
VOCM = VICM = 2.5V
–50 VTIP = OPEN (2.8V)
fIN = 50MHz
RLOAD = 800Ω
–60 RI = RF = 300Ω
DIFFERENTIAL INPUTS
VS = 5V
VOCM = VICM = 2.5V
–50 VTIP = OPEN (2.8V)
fIN = 50MHz
RLOAD = 800Ω
–60
–70
RI = RF = 300Ω
SINGLE-ENDED INPUT
HD2
HD3
–80
–90
HD3
–100
–110
1
10
FREQUENCY (MHz)
–90
100
6405 G31
–100
–4
–2
(0.4VP-P)
0
2
4
6
INPUT AMPLITUDE (dBm)
8
10
(2VP-P)
6405 G32
6405fb
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LTC6405
pin functions
(MSOP/QFN)
VOCM (Pin 2/Pin 4): Output Common Mode Reference
Voltage. The voltage on VOCM sets the output common
mode voltage level (which is defined as the average of the
voltages on the +OUT and –OUT pins). The VOCM voltage
is internally set by a resistive divider between the supplies,
developing a default voltage potential of 2.5V with a 5V
supply. The VOCM pin can be over-driven by an external
voltage capable of driving the 19kΩ Thevenin equivalent
impedance presented by the pin. The VOCM pin should be
bypassed with a high quality ceramic bypass capacitor of at
least 0.01µF, to minimize common mode noise from being
converted to differential noise by impedance mismatches
both externally and internally to the IC.
V+ (Pin 3/Pins 2, 10, 11):
V– (Pin 6/Pins 3, 9, 12):
Power Supply Pins. It is critical that close attention be
paid to supply bypassing. For single supply applications,
it is recommended that a high quality 0.1µF surface mount
ceramic bypass capacitor be placed between V+ and V– with
direct short connections. In addition, V– should be tied
directly to a low impedance ground plane with minimal
routing. For dual (split) power supplies, it is recommended
that additional high quality, 0.1µF ceramic capacitors are
used to bypass V+ to ground and V– to ground, again
with minimal routing. For driving large loads (<200Ω),
additional bypass capacitance may be needed for optimal
performance. Keep in mind that small geometry (e.g., 0603
or smaller) surface mount ceramic capacitors have a much
higher self resonant frequency than do leaded capacitors,
and perform best in high speed applications.
+OUT, –OUT (Pins 4, 5/Pins 7, 14): Unfiltered Output
Pins. Besides driving the feedback network, each pin
can drive an additional 50Ω to ground with typical short
circuit current limiting of ±60mA. Each amplifier output
is designed to drive a load capacitance of 5pF. Larger
capacitive loads should be decoupled with at least 15Ω
resistors from each output.
VTIP (Pin 5) QFN Only: This pin can normally be left floating. It determines which pair of input transistors (NPN or
PNP or both) is sensing the input signal. The VTIP pin is
set by an internal resistive divider between the supplies,
developing a default 2.8V voltage with a 5V supply. VTIP
has a Thevenin equivalent resistance of approximately
17k and can be over-driven by an external voltage. The
VTIP pin should be bypassed with a high quality ceramic
bypass capacitor of at least 0.01µF. See the Applications
Information section for more details.
SHDN (Pin 7/Pin 1): When SHDN is floating or directly
tied to V+, the LTC6405 is in the normal (active) operating
mode. When the SHDN pin is connected to V–, the LTC6405
enters into a low power shutdown state with Hi-Z outputs.
+IN, –IN (Pins 8, 1/Pins 15, 6): Noninverting and Inverting
Input Pins of the Amplifier, Respectively. For best performance, it is highly recommended that stray capacitance
be kept to an absolute minimum by keeping printed circuit
connections as short as possible.
+OUTF, –OUTF (Pins 8, 13) QFN Only: Filtered Output
Pins. These pins have a series RC network (R = 50Ω,
C = 3.75pF) connected between the filtered and unfiltered
outputs. See the Applications Information section for
more details.
NC (Pin 16) QFN Only: No Connection. This pin is not
connected internally.
Exposed Pad (Pin 9/Pin 17): Tie the bottom pad to V–.
If split supplies are used, DO NOT tie the pad to ground.
6405fb
For more information www.linear.com/6405
11
LTC6405
block diagrams
LTC6405 Block Diagram/Pinout in MSOP Package
8
+IN
7
6
SHDN
5
V–
–OUT
V–
V+
V+
37k
+
37k
–
V–
V–
V+
1
–IN
2
VOCM
3
V+
4
+OUT
6405 BD01
LTC6405 Block Diagram/Pinout in QFN Package
16
15
NC
14
+IN
–OUT
13
–OUTF
1.25pF
SHDN
V–
12
1
V+
2
V–
3
4
V+
V+
V–
V+
+
37k
V+
V+
11
V+
V+
10
1.25pF
V+
–
37k
30k
VOCM
V–
50Ω
V–
50Ω
V–
V–
V–
9
38k
1.25pF
V–
5
VTIP
6
–IN
7
+OUT
8
+OUTF
6405 BD02
6405fb
12
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LTC6405
applications information
Functional Description
The LTC6405 is a small outline, wideband, low noise, and
low distortion fully-differential amplifier with accurate
output phase balancing. The LTC6405 is optimized to
drive low voltage, single-supply, differential input analogto-digital converters (ADCs). The LTC6405 input common
mode range is rail-to-rail, while the output common mode
voltage is independently adjustable by applying a voltage
on the VOCM pin. The output voltage swing extends from
near-ground to 4V, to be compatible with a wide range of
ADC converter input requirements. This makes the LTC6405
ideal for level shifting signals with a wide common mode
range for driving 12-bit to 16-bit single supply, differential
input ADCs. The differential output allows for twice the
signal swing in low voltage systems when compared to
single-ended output amplifiers. The balanced differential
nature of the amplifier also provides even-order harmonic
distortion cancellation, and less susceptibility to common
mode noise (like power supply noise). The LTC6405 can be
used as a single ended input to differential output amplifier,
or as a differential input to differential output amplifier.
The LTC6405 output common mode voltage, defined as
the average of the two output voltages, is independent of
the input common mode voltage, and is adjusted by applying a voltage on the VOCM pin. If the pin is left open, there
is an internal resistive voltage divider, which develops a
potential of 2.5V (if the supply is 5V). It is recommended
that a high quality ceramic cap is used to bypass the VOCM
pin to a low impedance ground plane. The LTC6405’s
internal common mode feedback path forces accurate
output phase balancing to reduce even order harmonics,
and centers each individual output about the potential set
by the VOCM pin.
VOUTCM = VOCM =
V+OUT + V–OUT
2
CF
RI
V+IN
+
VINP
16
–
15
NC
RF
+IN
14
13
–OUT
SHDN
1
2
0.1µF
VCM
+
V–
V–
3
VVOCM
4
1.25pF
–
V–
V+
V–
RBAL
100k
0.1µF
0.1µF
V+
–IN
7
0.01µF
RI
V–IN
RF
+OUT
8
0.1µF
V – 0.1µF
V–
9
6
VOUTCM
10
–
1.25pF V V –
VTIP
V–
V+
50Ω
VOCM
5
–
V – V+
11
VOCM
0.01µF
+
VINM
50Ω
V+
V+
–OUTF
LTC6405
1.25pF
V–
12
SHDN
VSHDN
V–OUT
V–OUTF
RBAL
100k
0.1µF
+OUTF
6405 F01
V+OUTF
V+OUT
DEFAULT VALUES
PACKAGE
RI
RF
CF
MSOP*
300Ω
300Ω
1.0pF
QFN
200Ω
200Ω
1.8pF
CF
(RI, RF : 0.1% RESISTORS)
*TO OPTIMIZE THE HIGH FREQUENCY PERFORMANCE FOR THE PIN CONFIGURATION OF THE LTC6405
IN THE SMALL MSOP PACKAGE, A FEEDBACK RESISTANCE OF AT LEAST 300Ω IS RECOMMENDED.
Figure 1. DC Test Circuit
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13
LTC6405
Applications Information
The outputs (+OUT and –OUT) of the LTC6405 are capable
of swinging from close-to-ground to typically 1V below
V+. They can source or sink up to approximately 60mA of
current. Each output is designed to directly drive up to 5pF
to ground. Higher load capacitances should be decoupled
with at least 15Ω of series resistance from each output.
IC. The LTC6405 also has clamping diodes to either power
supply on the VOCM, VTIP and SHDN pins and if driven to
voltages which exceed either supply, they too, should be
current limited to under 10mA.
SHDN Pin
The SHDN pin is a CMOS logic input with a 50k internal
pull-up resistor. If the pin is driven low, the LTC6405 powers down with Hi-Z outputs. If the pin is left unconnected
or driven high, the part is in normal active operation.
Some care should be taken to control leakage currents
at this pin to prevent inadvertently putting the LTC6405
into shutdown. The turn-on and turn-off time between the
shutdown and active states are typically less than 1µs.
Input Pin Protection
The LTC6405 input stage is protected against differential
input voltages which exceed 1.4V by two pairs of series
diodes connected back to back between +IN and –IN. In
addition, the input pins have clamping diodes to either
power supply. If the input pins are over-driven, the current
should be limited to under 10mA to prevent damage to the
CF
0.1µF
RI
RF
RT
16
NC
15
+IN
V–OUTF
13
–OUTF
V–OUT
14
–OUT
LTC6405
1.25pF
V–
12
SHDN
VIN
•
•
VSHDN
1
–
+
2
0.1µF
V–
V–
3
VVOCM
RT CHOSEN SO
THAT RT||RI = 100Ω
50Ω
V+
V+
4
1.25pF
–
0.1µF
V – V+
11
V+
VOCM
V–
V–
50Ω
V–
0.1µF
50Ω
V+
V+
10
V – 0.1µF
–
1.25pF V V –
VOCM
MINI-CIRCUITS
TCM4-19
•
+
SHDN
•
50Ω
MINI-CIRCUITS
TCM4-19
0.1µF
100Ω
V+IN
0.1µF
V–
9
0.1µF
0.01µF
5
VTIP
6
–IN
7
+OUT
0.01µF
RT 0.1µF
RI
V–IN
8
+OUTF
V+OUTF
RF
V+OUT
100Ω
0.1µF
6405 F02
DEFAULT VALUES
PACKAGE
RI
RF
CF
MSOP*
300Ω
300Ω
1.0pF
QFN
200Ω
200Ω
1.8pF
CF
(RI, RF : 0.1% RESISTORS)
*TO OPTIMIZE THE HIGH FREQUENCY PERFORMANCE FOR THE PIN CONFIGURATION OF THE LTC6405
IN THE SMALL MSOP PACKAGE, A FEEDBACK RESISTANCE OF AT LEAST 300Ω IS RECOMMENDED.
Figure 2. AC Test Circuit (–3dB BW Testing)
6405fb
14
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LTC6405
Applications Information
General Amplifier Applications
∆b is defined as the difference in feedback factors:
As levels of integration have increased and correspondingly, system supply voltages decreased, there has been
a need for ADCs to process signals differentially in order
to maintain good signal to noise ratios. These ADCs are
typically supplied from a single supply voltage which
can be as low as 3V, and will have an optimal common
mode input range of 1.25V or 1.5V. The LTC6405 makes
interfacing to these ADCs easy, by providing both singleended to differential conversion as well as common mode
level shifting. The gain to VOUTDIFF from VINM and VINP is:
R
VOUTDIFF = V+OUT – V–OUT ≈ F • ( VINP – VINM )
RI
Note from the above equation, the differential output voltage (V+OUT – V–OUT) is completely independent of input
and output common mode voltages, or the voltage at the
common mode pin. This makes the LTC6405 ideally suited
for pre-amplification, level shifting and conversion of single
ended signals to differential output signals in preparation
for driving differential input ADCs.∆
Effects of Resistor Pair Mismatch
Figure 3 shows a circuit diagram which takes into consideration that real world resistors will not match perfectly.
Assuming infinite open loop gain, the differential output
relationship is given by the equation:
R
VOUTDIFF = V+OUT – V–OUT ≅ F • VINDIFF +
RI
∆b
∆b
• VICM –
•V
b AVG OCM
b AVG
∆b =
RI2
RI1
–
RI2 +RF2 RI1 +RF1
VICM is defined as the average of the two input voltages VINP
and VINM (also called the input common mode voltage):
1
VICM = • ( VINP + VINM )
2
and VINDIFF is defined as the difference of the input voltages:
VINDIFF = VINP – VINM
VOCM is defined as the average of the two output voltages
V+OUT and V–OUT:
VOCM =
V+OUT + V−OUT
2
When the feedback ratios mismatch (∆b), common mode
to differential conversion occurs.
Setting the differential input to zero (VINDIFF = 0), the degree of common mode to differential conversion is given
by the equation:
VOUTDIFF = V+OUT – V–OUT ≈ ( VICM – VOCM ) •
RI2
V+IN
VINP
–
+
VOCM
–
–
VINM
RF is the average of RF1, and RF2, and RI is the average
of RI1, and RI2.
bAVG is defined as the average feedback factor from the
outputs to their respective inputs:
V–OUT
+
VVOCM
where:
RF2
+
∆b
b AVG
RI1
V–IN
RF1
6405 F03
V+OUT
Figure 3. Real-World Application with
Feedback Resistor Pair Mismatch
RI2 
1  RI1
b AVG = • 
+
2  RI1 + RF1 RI2 + RF2 
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For more information www.linear.com/6405
15
LTC6405
Applications Information
In general, the degree of feedback pair mismatch is a
source of common mode to differential conversion of both
signals and noise. Using 1% resistors or better will mitigate
most problems, and will provide about 34dB worst case of
common mode rejection. Using 0.1% resistors will provide
about 54dB of common mode rejection. A low impedance
ground plane should be used as a reference for both the
input signal source and the VOCM pin. Bypassing the VOCM
with a high quality 0.1µF ceramic capacitor to this ground
plane will further help prevent common mode signals from
being converted to differential signals.
There may be concern on how feedback factor mismatch
affects distortion. Feedback factor mismatch from using
1% resistors or better, has a negligible effect on distortion.
However, in single supply level shifting applications where
there is a voltage difference between the input common
mode voltage and the output common mode voltage,
resistor mismatch can make the apparent voltage offset
of the amplifier appear worse than specified.
The apparent input referred offset induced by feedback
factor mismatch is derived from the above equation:
the balanced differential case. The input impedance looking
into either input is:
RINP = RINM =
RI
 1  RF  
 1– 2 •  R + R  
 I F 

Input signal sources with non-zero output impedances can
also cause feedback imbalance between the pair of feedback
networks. For the best performance, it is recommended
that the input source output impedance be compensated
for. If input impedance matching is required by the source,
a termination resistor R1 should be chosen (see Figure 4):
R1=
RINM • RS
RINM – RS
According to Figure 4, the input impedance looking into
RINM
RS
RI
R1
VS
VOSDIFF(APPARENT) ≈ (VICM – VOCM) • ∆b
Using the LTC6405 in a single supply application on a
single 5V supply with 1% resistors, and the input common
mode grounded, with the VOCM pin biased at 2.5V, the
worst case DC offset can induce 25mV of apparent offset
voltage. With 0.1% resistors, the worst case apparent
offset reduces to 2.5mV.
Input Impedance and Loading Effects
The input impedance looking into the VINP or VINM input
of Figure 1 depends on whether or not the sources VINP
and VINM are fully differential or not. For balanced input
sources (VINP = –VINM), the input impedance seen at either
input is simply:
RINP = RINM = RI
For single ended inputs, because of the signal imbalance
at the input, the input impedance actually increases over
RF
R1 CHOSEN SO THAT R1 || RINM = RS
R2 CHOSEN TO BALANCE R1 || RS
RI
–
+
+
–
RF
6405 F04
R2 = RS || R1
Figure 4. Optimal Compensation for Signal Source Impedance
the differential amp (RINM) reflects the single ended source
case, thus:
RINM =
RI
 1  RF  
 1– 2 •  R + R  
 I F 

R2 is chosen to equal R1 || RS:
R2 =
R1• RS
R1+ RS
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16
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LTC6405
Applications Information
Input Common Mode Voltage Range
Manipulating the Rail-to-Rail Input Stage with VTIP
The LTC6405’s input common mode voltage (VICM) is
defined as the average of the two input voltages, V+IN, and
V–IN. At the inputs to the actual op amp, the range extends
from V– to V+. This makes it easy to interface to a wide
range of common mode signals, from ground referenced to
VCC referenced signals. Moreover, due to external resistive
divider action of the gain and feedback resistors, the effective
range of signals that can be processed is even wider. The
input common mode range at the op amp inputs depends
on the circuit configuration (gain), VOCM and VCM (refer to
Figure 5). For fully differential input applications, where
VINP = –VINM, the common mode input is approximately:
To achieve rail-to-rail input operation, the LTC6405 features
an NPN input stage in parallel with a PNP input stage. When
the input common mode voltage is near V+, the NPNs are
active while the PNPs are off. When the input common
mode is near V–, the PNPs are active while the NPNs are
off. At some range in the middle, both input stages are
active. This ‘hand-off’ operation happens automatically.
VICM =
 RI 
V+IN + V–IN
+
≈ VOCM • 
2
 RI + RF 
 RF 
VCM • 
 RF + RI 
RI
V+IN
RF
V–OUT
+
VINP
–
+
VVOCM
+
VCM
–
VOCM
–
–
VINM
+
RI
V–IN
RF
6405 F05
V+OUT
In the QFN package, a special pin, VTIP, is made available
that can be used to manipulate the ‘hand-off’ operation
between the NPN and PNP input stages. By default, the
VTIP pin is internally biased by an internal resistive divider
between the supplies, developing a default 2.8V voltage
with a 5V supply. If desired, VTIP can be over-driven by
an external voltage (the Thevenin equivalent resistance is
approximately 17k).
If VTIP is pulled closer to V–, the range over which the NPN
input pair remains active is increased, while the range over
which the PNP input pair is active is reduced. In applications where the input common mode does not come close
to V– , this mode can be used to further improve linearity
beyond the specified performance (see Figure 6).
If VTIP is pulled closer to V+, the range over which the PNP
input pair remains active is increased, while the range over
which the NPN input pair is active is reduced. In applications where the input common mode does not come close
to V+, this mode can be used to further improve linearity
beyond the specified performance.
Figure 5. Circuit for Common Mode Range
 RI 
V + V–IN
+
VICM = +IN
≈ VOCM • 
2
 RI + RF 
 RF
VCM • 
 R +R
F
I
 VINP
 + 2
 RF 
•
 RF + RI 
DISTORTION (dBc)
With single ended inputs, there is an input signal component to the input common mode voltage. Applying only
VINP (setting VINM to zero), the input common voltage is
approximately:
–30
RI = RF = 499Ω
VS = 5V
–40 VOCM = VICM = 2.5V VOUTDIFF = 2VP-P
RLOAD = 800Ω
SINGLE-ENDED INPUT
QFN PACKAGE
–50
HD2
VTIP = OPEN
–60
HD3
–70
VTIP = OPEN
–80
HD3
VTIP = 1V
–100
–110
Use the equations above to check that the VICM at the op
amp inputs is within range (V– to V+).
HD2
VTIP = 1V
–90
1
10
FREQUENCY (MHz)
100
6405 F06
Figure 6. Manipulating VTIP to Improve Harmonic Distortion
6405fb
For more information www.linear.com/6405
17
LTC6405
Applications Information
Output Common Mode Voltage Range
Output Filter Considerations and Use
The output common mode voltage is defined as the average of the two outputs:
Filtering at the output of the LTC6405 is often desired to
provide anti-aliasing or to improve signal to noise ratio.
To simplify this filtering, the LTC6405 in the QFN package
includes an additional pair of differential outputs (+OUTF
and –OUTF) which incorporate an internal lowpass RC
network with a –3dB bandwidth of 850MHz (Figure 7).
VOUTCM = VOCM =
V+OUT + V–OUT
2
The VOCM pin sets this average by an internal common
mode feedback loop which internally forces VOUTCM = VOCM.
The output common mode range extends from 0.5V above
V– to typically 1V below V+. The VOCM voltage is internally
set by a resistive divider between the supplies, developing
a default voltage potential of 2.5V with a 5V supply.
In single supply applications, where the LTC6405 is used
to interface to an ADC, the optimal common mode input
range to the ADC is often determined by the ADC’s reference. If the ADC makes a reference available for setting the
input common mode voltage, it can be directly tied to the
VOCM pin (as long as it is able to drive the 19kΩ Thevenin
equivalent input impedance presented by the VOCM pin).
The VOCM pin should be bypassed with a high quality
ceramic bypass capacitor of at least 0.01µF to filter any
common mode noise rather than being converted to differential noise and to prevent common mode signals on
this pin from being inadvertently converted to differential
signals by impedance mismatches both externally and
internally to the IC.
These pins each have an output resistance of 50Ω (tolerance ±12%). Internal capacitances are 1.25pF (tolerance
±15%) to V– on each filtered output, plus an additional
1.25pF (tolerance ±15%) capacitor connected between the
two filtered outputs. This resistor/capacitor combination
creates filtered outputs that look like a series 50Ω resistor
with a 3.75pF capacitor shunting each filtered output to
AC ground, providing a –3dB bandwidth of 850MHz, and
a noise bandwidth of 1335MHz. The filter cutoff frequency
is easily modified with just a few external components. To
increase the cutoff frequency, simply add two equal value
resistors, one between +OUT and +OUTF and the other
between –OUT and –OUTF (Figure 8). These resistors, in
parallel with the internal 50Ω resistors, lower the overall
resistance and therefore increase filter bandwidth. For
example, to double the filter bandwidth, add two external
50Ω resistors to lower the series filter resistance to 25Ω.
The 3.75pF of capacitance remains unchanged, so filter
bandwidth doubles. Keep in mind, the series resistance
also serves to decouple the outputs from load capaci49.9Ω
–OUTF
–OUTF
LTC6405
14
–OUT
13
LTC6405
–OUTF
1.25pF
50Ω
–OUT
13
–OUTF
1.25pF
V–
12
50Ω
V–
+
FILTERED OUTPUT
1.25pF
–
14
V–
+
50Ω
–
1.25pF V V –
–
1.25pF V V –
9
9
7
+OUT
8
+OUTF
6405 F07
7
+OUTF
+OUT
49.9Ω
Figure 7. LTC6405 Internal Filter Topology
18
FILTERED OUTPUT
(1.7GHz)
1.25pF
–
50Ω
V–
12
8
+OUTF
6405 F08
+OUTF
Figure 8. LTC6405 Filter Topology Modified for 2x Filter
Bandwidth (Two External Resistors)
For more information www.linear.com/6405
6405fb
LTC6405
Applications Information
tance. The outputs of the LTC6405 are designed to drive
5pF to ground, so care should be taken to not lower the
effective impedance between +OUT and +OUTF or –OUT
and –OUTF below 15Ω.
To decrease filter bandwidth, add two external capacitors,
one from +OUTF to ground, and the other from –OUTF to
ground. A single differential capacitor connected between
+OUTF and –OUTF can also be used, but since it is being
driven differentially it will appear at each filtered output
as a single-ended capacitance of twice the value. To halve
the filter bandwidth, for example, two 3.9pF capacitors
could be added (one from each filtered output to ground).
Alternatively, one 1.8pF capacitor could be added between
the filtered outputs, which also halves the filter bandwidth.
Combinations of capacitors could be used as well; a three
capacitor solution of 1.2pF from each filtered output to
ground plus a 1.2pF capacitor between the filtered outputs
would also halve the filter bandwidth (Figure 9).
the amplifier and the feedback components is governed
by the equation:
2
eno =

 RF  
2
e
•
 ni  1+ R   + 2 • (In • RF ) +


I 
2

 R 
2 •  enRI •  F   + 2 • enRF 2
 RI  

A plot of this equation, and a plot of the noise generated
by the feedback components for the LTC6405 is shown
in Figure 11.
enRI2
encm2
–OUT
–OUTF
–OUTF
1.25pF
50Ω
–
7
8
eni2
RI
RF
enRF2
Figure 10. Noise Model of the LTC6405
1.2pF
FILTERED OUTPUT
(425MHz)
1.2pF
9
6405 F09
–
6405 F10
TOTAL (AMPLIFIER AND
FEEDBACK NETWORK)
OUTPUT NOISE
10
–
1.25pF V V –
+OUT
eno2
100
1.2pF
1.25pF
50Ω
enRI2
V–
12
V–
+
+
in–2
+OUTF
nV/ Hz
LTC6405
enRF2
VOCM
The LTC6405’s input referred voltage noise is 1.6nV/√Hz.
Its input referred current noise is 2.4pA/√Hz. In addition
to the noise generated by the amplifier, the surrounding
feedback resistors also contribute noise. A noise model is
shown in Figure 10. The output noise generated by both
13
RF
in+2
Noise Considerations
14
RI
FEEDBACK NETWORK
NOISE ALONE
1
+OUTF
Figure 9. LTC6405 Filter Topology Modified for 1/2x Filter
Bandwidth (Three External Capacitors)
0.1
10
100
1000
RI = RF (Ω)
10000
6405 F11
Figure 11. LTC6405 Output Spot Noise vs Spot Noise
Contributed by Feedback Network Alone
6405fb
For more information www.linear.com/6405
19
LTC6405
Applications Information
The LTC6405’s input referred voltage noise contributes the
equivalent noise of a 155Ω resistor. When the feedback
network is comprised of resistors whose values are less
than this, the LTC6405’s output noise is voltage noise
dominant (see Figure 11):
 R 
eno ≈ eni •  1+ F 
 RI 
Feedback networks consisting of resistors with values
greater than about 200Ω will result in output noise which
is resistor noise and amplifier current noise dominant.
eno ≈ 2 •


(In • RF )2 +  1+ RRF  • 4 • k • T • RF
I
Lower resistor values (<100Ω) always result in lower noise
at the penalty of increased distortion due to increased
loading of the feedback network on the output. Higher
resistor values (but still less than <500Ω) will result in
higher output noise, but typically improved distortion due
to less loading on the output. The optimal feedback resistance for the LTC6405 runs in between 100Ω to 500Ω.
The differential filtered outputs +OUTF and –OUTF will
have a little higher noise than the unfiltered outputs (due
to the two 50Ω resistors which contribute 0.9nV/√Hz
each), but can provide superior signal-to-noise due to the
output noise filtering.
Layout Considerations
Because the LTC6405 is a very high speed amplifier, it is
sensitive to both stray capacitance and stray inductance.
In the QFN package, three pairs of power supply pins are
provided to keep the power supply inductance as low
as possible to prevent any degradation of amplifier 2nd
harmonic performance. It is critical that close attention be
paid to supply bypassing. For single supply applications
it is recommended that high quality 0.1µF surface mount
ceramic bypass capacitor be placed directly between each
V+ and V– pin with direct short connections. The V– pins
should be tied directly to a low impedance ground plane
with minimal routing. For dual (split) power supplies, it is
recommended that additional high quality, 0.1µF ceramic
capacitors are used to bypass V+ to ground and V– to
ground, again with minimal routing. For driving large
loads (<200Ω), additional bypass capacitance may be
needed for optimal performance. Keep in mind that small
geometry (e.g., 0603) surface mount ceramic capacitors
have a much higher self resonant frequency than do leaded
capacitors, and perform best in high speed applications.
Any stray parasitic capacitances to ground at the summing
junctions, +IN and –IN, should be minimized. This becomes
especially true when the feedback resistor network uses
resistor values >500Ω in circuits with RF = RI. Always keep
in mind the differential nature of the LTC6405, and that it
is critical that the load impedances seen by both outputs
(stray or intended), should be as balanced and symmetric
as possible. This will help preserve the natural balance
of the LTC6405, which minimizes the generation of even
order harmonics, and improves the rejection of common
mode signals and noise.
It is highly recommended that the VOCM pin be bypassed
to ground with a high quality ceramic capacitor whose
value exceeds 0.01µF. This will help stabilize the common
mode feedback loop as well as prevent thermal noise from
the internal voltage divider and other external sources of
noise from being converted to differential noise due to
divider mismatches in the feedback networks. It is also
recommended that the resistive feedback networks be
comprised of 1% resistors (or better) to enhance the
output common mode rejection. This will also prevent
VOCM input referred common mode noise of the common
mode amplifier path (which cannot be filtered) from being
converted to differential noise, degrading the differential
noise performance.
Feedback factor mismatch has a weak effect on distortion.
Using 1% or better resistors will limit any mismatch from
impacting amplifier linearity. However, in single supply
level shifting applications where there is a voltage difference between the input common mode voltage and the
output common mode voltage, resistor mismatch can
make the apparent voltage offset of the amplifier appear
worse than specified.
6405fb
20
For more information www.linear.com/6405
LTC6405
Applications Information
Interfacing the LTC6405 to A/D Converters
Rail-to-rail input and fast settling time make the LTC6405
ideal for interfacing to low voltage, single supply, differential input ADCs. The sampling process of ADCs create
a sampling glitch caused by switching in the sampling
capacitor on the ADC front end which momentarily “shorts”
the output of the amplifier as charge is transferred between
the amplifier and the sampling capacitor. The amplifier
must recover and settle from this load transient before
this acquisition period ends for a valid representation of
the input signal. In general, the LTC6405 will settle much
more quickly from these periodic load impulses than from
a 2V input step, but it is a good idea to place an R-C filter
network between the differential outputs of the LTC6405
and the input of the ADC to help absorb the charge injection
that comes out of the ADC from the sampling process.
The capacitance of the filter network serves as a charge
reservoir to provide high frequency charging during the
sampling process, while the resistors of the filter network
are used to dampen and attenuate any charge kickback
from the ADC. The selection of the R-C time constant is
trial and error for a given ADC, but the following guidelines
are recommended: Choosing too large of a resistor in the
decoupling network leaving insufficient settling time will
create a voltage divider between the dynamic input impedance of the ADC and the decoupling resistors. Choosing
too small of a resistor will possibly prevent the resistor
from properly dampening the load transient caused by
the sampling process, prolonging the time required for
settling. In 16-bit applications, this will typically require
a minimum of 11 R-C time constants. It is recommended
that the capacitor chosen have a high quality dielectric
(such as C0G multilayer ceramic).
1.8pF
VIN, 2VP-P
200Ω
16
NC
20Ω
200Ω
15
+IN
14
–OUT
13
SHDN
SHDN
50Ω
V+
+
2
0.1µF
V–
3
4
V– V +
11
1.25pF
V+
VOCM
–
V–
50Ω
5
V+
10
–
1.25pF V V–
VOCM
0.1µF
CONTROL
12
1
5V
–OUTF
LTC6405
1.25pF
V–
0.1µF
5V
+INA
4.7pF
0.1µF
4.7pF
4.7pF
LTC2208
–INA
VCM GND VDD
D15
•
•
D0
1µF
3.3V
1µF
9
VTIP
6
–IN
7
+OUT
8
+OUTF
6405 F12
2.2µF
0.1µF
200Ω
200Ω
20Ω
100Ω
1.8pF
Figure 12. Interfacing the LTC6405 to an ADC
6405fb
For more information www.linear.com/6405
21
LTC6405
Typical Application
Attenuating and Level Shifting a Single-Ended ±5V Signal to a
Differential 2VP-P Signal at a 1.25V Common Mode
C1, 2.7pF
2VP-P DIFF OUTPUT
LEVEL-SHIFTED TO 1.25V
R3, 100Ω
R5
511Ω
±5V SINE WAVE
(10VP-P)
CENTERED AT 0V
VIN
R6
511Ω
5V
– +
LTC6405
+ –
3.3V
R1
51.1Ω
R2
51.1Ω
LTC2207
6405 TA03
R4, 100Ω
VCM = 1.25V
2.2µF
C2, 2.7pF
6405fb
22
For more information www.linear.com/6405
LTC6405
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MS8E Package
8-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1662 Rev J)
BOTTOM VIEW OF
EXPOSED PAD OPTION
1.88
(.074)
1
1.88 ±0.102
(.074 ±.004)
0.29
REF
1.68
(.066)
0.889 ±0.127
(.035 ±.005)
0.05 REF
5.23
(.206)
MIN
DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
1.68 ±0.102 3.20 – 3.45
(.066 ±.004) (.126 – .136)
8
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
0.65
(.0256)
BSC
0.42 ±0.038
(.0165 ±.0015)
TYP
8
7 6 5
0.52
(.0205)
REF
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
DETAIL “A”
0° – 6° TYP
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
DETAIL “A”
1
2 3
4
1.10
(.043)
MAX
0.86
(.034)
REF
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.65
(.0256)
BSC
0.1016 ±0.0508
(.004 ±.002)
MSOP (MS8E) 0911 REV J
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
6405fb
For more information www.linear.com/6405
23
LTC6405
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691 Rev Ø)
0.70 ±0.05
3.50 ±0.05
1.45 ±0.05
2.10 ±0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 ±0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
R = 0.115
TYP
0.75 ±0.05
15
PIN 1
TOP MARK
(NOTE 6)
16
0.40 ±0.10
1
1.45 ± 0.10
(4-SIDES)
2
(UD16) QFN 0904
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.25 ±0.05
0.50 BSC
6405fb
24
For more information www.linear.com/6405
LTC6405
Revision History
(Revision history begins at Rev B)
REV
DATE
DESCRIPTION
B
02/13
Changed operating voltage upper range from 5.5V to 5.25V
PAGE NUMBER
Changed voltage max spec from 0.4V to 0.45V
1, 3, 4
3
6405fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
its circuits
as described
herein will not infringe on existing patent rights.
Forofmore
information
www.linear.com/6405
25
LTC6405
Typical Application
DC-Coupled Level Shifting of Demodulator Output
5V
LT5575
5V
5V
C5, 10pF
DIFF OUTPUT Z
130Ω| |2.5pF
DC LEVEL
1.5V
R5, 324Ω
5pF
I
65Ω
5pF
65Ω
DC LEVEL
3.8V
5V
15nH
LTC6405
15nH
RF IN
900MHz
–7dBm
5V
5V
C1
4.7pF
4.7pF
5pF
LO
OdBm
Q
65Ω
R7
49.9Ω
+ –
– +
C2
4.7pF
3.3V
C8
4.7pF
R8
49.9Ω
R9
10Ω 10dBm
C6
R10
4.7pF 10Ω
LTC2249
14-BIT ADC
VCM
C7
4.7pF
5pF
6405 TA02
VOCM = 1.5V
65Ω
R6, 324Ω
3.9pF
C4, 10pF
IDENTICAL
Q CHANNEL
GAIN: 3dB
INPUT NF: 13dB
OIP3: 31dBm
80MHz
SAMPLE
CLOCK
GAIN: 14dB
INPUT NF: 11dB
OIP3: 44dBm AT 30MHz
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LT1993-2/LT1993-4/
LT1993-10
800MHz/900MHz/700MHz Low Distortion, Low Noise
Differential Amplifier/ADC Driver
A V = 2V/V / A V = 4V/V / A V = 10V/V, NF = 12.3dB/14.5dB/
12.7dB, OIP3 = 38dBm/40dBm/40dBm at 70MHz
LT1994
Low Noise, Low Distortion Fully differential Input/Output
Amplifier/Driver
Low Distortion, 2VP-P , 1MHz: –94dBc, 13mA,
Low Noise: 3nV/√Hz
LTC6400-8/LTC6400-14/
LTC6400-20/LTC6400-26
1.8GHz Low Noise, Low Distortion, Differential ADC Driver
300MHz IF Amplifier, A V = 20dB/26dB
LTC6401-8/LTC6401-14/
LTC6401-20/LTC6401-26
1.3GHz Low Noise, Low Distortion, Differential ADC Driver
140MHz IF Amplifier, A V = 20dB/26dB
LT6402-6/LT6402-12/
LT6402-20
300MHz/300MHz/300MHz Low Distortion, Low Noise
Differential Amplifier/ADC Driver
A V = 6dB/A V = 12dB/A V = 20dB, NF = 18.6dB/15dB/12.4dB,
OIP3 = 49dBm/43dBm/51dBm at 20MHz
LTC6404-1/ LTC6404-2/
LTC6404-4
600MHz Low Noise, Low Distortion, Differential ADC Driver
1.5nV/√Hz Noise, –90dBc Distortion at 10MHz
LTC6406
3GHz Low Noise, 3V, Rail-to-Rail Input Differential Amplifier/
Driver
1.6nV/√Hz Noise, –70dBc Distortion at 50MHz, 18mA, 3V Supply
LTC6411
Low Power Differential ADC Driver/Dual Selectable Gain
Amplifier
16mA Supply Current, IMD3 = –83dBC at 70MHz, AV = 1, –1,
or 2
LT6600-2.5/LT6600-5/
LT6600-10/LT6600-20
Very Low Noise, Fully Differential Amplifier and 4th
Order Filter
2.5MHz/5MHz/10MHz/20MHz Integrated Filter, 3V Supply,
SO-8 Package
LTC6403-1
200MHz Low Noise, Low Power Differential ADC Driver
–95dBc Distortion at 3MHz, 10.8mA Supply Current
6405fb
26 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/6405
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/6405
LT 0213 REV B • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2012