CY62167DV18 MoBL2™ PRELIMINARY 16M (1024K x 16) Static RAM Features • Very high speed: 55 ns and 70 ns • Voltage range: 1.65V to 1.95V • Ultra-low active power — Typical active current: 1.5 mA @ f = 1 MHz — Typical active current: 15 mA @ f = fMAX • Ultra-low standby power • Easy memory expansion with CE</>1</>, CE2</> and OE</> Writing to the device is accomplished by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then das pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the ad features • Automatic power-down when deselected • CMOS for optimum speed/power • Packages offered in a 48-ball FBGA Functional Description[1] The CY62167DV18 is a high-performance CMOS static RAM organized as 1024K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not Reading from the device is accomplished by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (<>O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. DATA IN DRIVERS 1024K x 16 RAM ARRAY 2048 x 512 x 16 SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER Logic Block Diagram toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW or both BHE and BLE are HIGH. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or during a write operation (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and WE LOW). I/O0 –I/O7 I/O8 –I/O15 COLUMN DECODER A11 A12 A13 A14 A15 A16 A17 A18 A19 BHE WE CE2 CE1 OE BLE Power-down Circuit CE2 BHE BLE CE1 Note: 1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05326 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised February 10, 2003 CY62167DV18 MoBL2™ PRELIMINARY Pin Configuration[2] FBGA Top View 1 2 3 4 5 6 BLE OE A0 A1 A2 CE 2 A I/O8 BH E A3 A4 CE 1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 Vcc D VCC I/O12 DNU A16 I/O4 Vss E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 A19 A12 A13 WE I/O7 G A18 A8 A9 A10 A11 DNU H Note: 2. DNU pins are to be connected to VSS or left open. Document #: 38-05326 Rev. *A Page 2 of 11 CY62167DV18 MoBL2™ PRELIMINARY DC Input Voltage[3] ................................ −0.2V to VCC + 0.2V Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch-up Current..................................................... > 200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage to Ground Potential .......................................... −0.2V to VCCMAX + 0.2V DC Voltage Applied to Outputs in High-Z State[3] ....................................−0.2V to VCC + 0.2V Range Ambient Temperature (TA) VCC[4] Industrial −40°C to +85°C 1.65V to 1.95V Product Portfolio Power Dissipation Operating, Icc (mA) VCC Range(V) Product Min. Typ. Max. Speed (ns) CY62167DV18L 1.65 1.8 1.95 55 CY62167DV18LL 1.65 1.8 1.95 f = 1 MHz f = fMAX Typ. Max. Typ. Max. Typ. Max. 1.5 5 15 30 2.5 30 12 25 2.5 30 1.5 5 15 30 2.5 20 12 25 2.5 20 70 55 Standby, ISB2 (µA) 70 DC Electrical Characteristics (over the operating range) CY62167DV18-55 Parameter Description Test Conditions Min. Typ. Max. VOH Output HIGH Voltage IOH = −0.1 mA VCC = 1.65V VOL Output LOW Voltage IOL = 0.1 mA VCC = 1.65V VIH Input HIGH Voltage 1.4 VCC + 0.2 VIL Input LOW Voltage –0.2 IIX Input Leakage Current GND < VI < VCC –1 IOZ Output Leakage Current –1 ICC VCC Operating Supply f = fMAX = 1/tRC Current f = 1 MHz ISB1 ISB2 GND < VO < VCC, Output Disabled Vcc = 1.95V, IOUT = 0mA, CMOS level 1.4 CY62167DV18-70 Min. Typ. Max. 1.4 Unit V 0.2 0.2 V 1.4 VCC + 0.2 V 0.4 –0.2 0.4 V +1 –1 +1 µA +1 –1 +1 µA mA 15 30 12 25 1.5 5 1.5 5 Automatic CE Power-down Current − CMOS Inputs CE1 > VCC − 0.2V, CE2 < L 0.2V, VIN > VCC − 0.2V, LL VIN < 0.2V, f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE) 2.5 30 2.5 30 2.5 20 2.5 20 Automatic CE Power-down Current − CMOS Inputs CE1 > VCC − 0.2V, CE2 < L 0.2V, VIN > VCC − 0.2V or LL VIN < 0.2V, f = 0, VCC=1.95V 2.5 30 2.5 30 2.5 20 2.5 20 µA µA Capacitance[5] Parameter Description CIN Input Capacitance COUT Output Capacitance Document #: 38-05326 Rev. *A Test Conditions TA = 25°C, f = 1 MHz VCC = VCC(typ) Max. Unit 6 pF 8 pF Page 3 of 11 CY62167DV18 MoBL2™ PRELIMINARY Capacitance[5] Parameter Description Test Conditions Max. Unit Notes: 3. VIL(min.) = −2.0V for pulse durations less than 20 ns. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. 5. Tested initially and after any design or proces changes that may affect these parameters. Thermal Resistance Parameter Description θJA Thermal Resistance (Junction to Ambient)[5] θJC Thermal Resistance (Junction to Case)[5] Test Conditions BGA Unit Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board 55 C/W 16 C/W AC Test Loads and Waveforms R1 ALL INPUT PULSES VCC VCC Typ UTPUT 10% 90% 10% 90% GND R2 CL = 30 pF Rise Time: 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: OUTPUT Fall Time: 1 V/ns THÉVENIN EQUIVALENT RTH V Parameters 1.8V UNIT R1 1350 0 Ω R2 1080 0 Ω R TH 6000 Ω VT H 0.80 V Data Retention Characteristics Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[5] Chip Deselect to Data Retention Time tR[6] Operation Recovery Time Document #: 38-05326 Rev. *A Conditions Min. Max. Unit 1.95 V L 15 µA LL 10 1.0 VCC=1.0V, CE1 > VCC − 0.2V, CE2 < 0.2V, VIN > VCC − 0.2V or VIN < 0.2V Typ. 0 ns tRC ns Page 4 of 11 CY62167DV18 MoBL2™ PRELIMINARY Data Retention Waveform[7] VCC VCC(min.) tCDR DATA RETENTION MODE VDR > 1.0V VCC(min.) tR CE1 or BHE . BLE or CE2 Notes: 6. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs. 7. 7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. Switching Characteristics (over the operating range)[8] Parameter Description CY62167DV18-55 CY62167DV18-70 Min. Min. Max. Max. Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW or CE2 HIGH to Data Valid 55 70 ns tDOE OE LOW to Data Valid 25 35 ns tLZOE OE LOW to Low 55 70 55 Z[9] 10 10 5 Z[9, 11] ns 70 ns 5 ns tHZOE OE HIGH to High tLZCE CE1 LOW or CE2 HIGH to Low Z[9] tHZCE CE1 HIGH or CE2 LOW to High Z[9, 11] tPU CE1 LOW or CE2 HIGH to Power-up tPD CE1 HIGH or CE2 LOW to Power-down 55 70 ns tDBE BLE/BHE LOW to Data Valid 55 70 ns tLZBE[10] BLE/BHE LOW to Low tHZBE BLE/BHE HIGH to High-Z[9, 11] Z[9] 20 ns 10 25 10 20 0 ns 25 0 5 ns ns 5 20 ns ns 25 ns Write Cycle[12] tWC Write Cycle Time 55 70 ns tSCE CE1 LOW or CE2 HIGH to Write End 40 60 ns tAW Address Set-up to Write End 40 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-up to Write Start 0 0 ns tPWE WE Pulse Width 40 45 ns tBW BLE/BHE LOW to Write End 45 60 ns tSD Data Set-up to Write End 25 30 ns tHD Data Hold from Write End 0 0 ns Z[9, 11] tHZWE WE LOW to High tLZWE WE HIGH to Low Z[9] Document #: 38-05326 Rev. *A 20 10 25 10 ns ns Page 5 of 11 CY62167DV18 MoBL2™ PRELIMINARY Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[13, 14] tRC ADDRESS tAA tOHA ATA OUT PREVIOUS DATA VALID DATA VALID Notes: 8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. If both byte enables are toggled together, this value is 10 ns. 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 12. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL. 13. Device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, CE2<Def> 14. WE is HIGH for Read cycle. Read Cycle No. 2 (OE Controlled)[14, 15] ADDRESS t RC CE 1 t PD t HZCE CE2 tACE BHE /BLE t DBE t HZBE t LZBE OE t HZOE t DOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID t LZCE VCC SUPPLY CURRENT tPU Document #: 38-05326 Rev. *A 50% 50% I CC I SB Page 6 of 11 CY62167DV18 MoBL2™ PRELIMINARY Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled)[12, 16, 17, 18] t WC ADDRESS tSCE CE1 CE2 tAW t HA t SA t PWE WE tBW BHE /BLE OE tSD ATA I/O t HD DATAIN VALID DON’T CARE t HZOE Note: 15. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH. Write Cycle No. 2 (CE</>1</> or CE</>2</> Controlled)[12, 16, 17, 18] t WC ADDRESS t SCE CE 1 CE 2 t SA t AW t HA t PWE WE t BW BHE /BLE OE t SD DATA I/O t HD DATA IN VALID DON’T CARE t HZOE Document #: 38-05326 Rev. *A Page 7 of 11 CY62167DV18 MoBL2™ PRELIMINARY Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[17, 18] tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA tPWE WE tHD tSD DATA I/O DATAIN VALID DON’T CARE tLZWE tHZWE Write Cycle No. 4 (BHE</>/BLE</> Controlled, OE</> LOW)</>[17] t WC ADDRESS CE 1 CE 2 t SCE t AW t HA t BW BHE /BLE t SA t PWE WE t SD DATA I/O DON’T CARE t HD DATAIN VALID Notes: 16. Data I/O is high-impedance if OE = VIH. 17. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state. 18. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Document #: 38-05326 Rev. *A Page 8 of 11 CY62167DV18 MoBL2™ PRELIMINARY Truth Table CE 1 CE 2 WE OE BHE BLE H X X X X X High Z Deselect/Power-down Standby(I SB ) X L X X X X High Z Deselect/Power-down Standby(I SB ) X X X X H H High Z Deselect/Power-down Standby(I SB ) L H H L L L Data Out(I/O0– I/O15) Read Active(I CC) L H H L H L Data Out(I/O0– I/O7); High Z (I/O8– I/O15) Read Active(I CC) L H H L L H High Z (I/O0– I/O7); Data Out(I/O8– I/O15) Read Active(I CC) L H H H L H High Z Output Disabled Active(I CC) L H H H H L High Z Output Disabled Active(I CC) L H H H L L High Z Output Disabled Active(I CC) L H L X L L Data In (I/O0– I/O15) Write Active(I CC) L H L X H L Data In (I/O0– I/O7); High Z (I/O8– I/O15) Write Active(I CC) L H L X L H High Z (I/O0– I/O7); Data In (I/O8– I/O15) Write Active(I CC) Document #: 38-05326 Rev. *A Input / Outputs Mode Power Page 9 of 11 CY62167DV18 MoBL2™ PRELIMINARY Ordering Information Speed (ns) 55 70 Ordering Code Package Name Package Type Operating Range Industrial CY62167DV18L-55**I TBD 48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm) CY62167DV18LL-55**I TBD 48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm) CY62167DV18L-70**I TBD 48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm) CY62167DV18LL-70**I TBD 48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm) Industrial Package Diagram 48-lead VFBGA (8 x 9.5 x 1 mm) BV48B 51-85178-** MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05326 Rev. *A Page 10 of 11 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY62167DV18 MoBL2™ PRELIMINARY Document History Page Document Title: CY62167DV18MoBL2™ 16M (1024K x 16) Static RAM Document Number: 38-05326 ECN NO. Issue Date Orig. of Change ** 118406 09/30/02 GUG New Data Sheet *A 123690 02/11/03 DPM Changed Advance to Preliminary Added package diagram REV. Document #: 38-05326 Rev. *A Description of Change Page 11 of 11