Cypress CY7C1480V33 72-mbit (2 m x 36) pipelined sync sram Datasheet

CY7C1480V33
72-Mbit (2 M × 36) Pipelined Sync SRAM
72-Mbit (2 M × 36) Pipelined Sync SRAM
Features
Functional Description
■
Supports bus operation up to 200 MHz
■
Available speed grades are 200 and 167 MHz
■
Registered inputs and outputs for pipelined operation
■
3.3 V core power supply
■
2.5 V/3.3 V I/O operation
■
Fast clock-to-output times
❐ 3.0 ns (for 200 MHz device)
The CY7C1480V33 SRAM integrates 2 M × 36 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE1), depth-expansion
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,
ADSP, and ADV), Write Enables (BWX, and BWE), and Global
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
■
Provide high performance 3-1-1-1 access rate
■
User selectable burst counter supporting Intel® Pentium®
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self timed writes
■
Asynchronous output enable
■
Single cycle chip deselect
■
CY7C1480V33 available in JEDEC-standard Pb-free 100-pin
TQFP package
■
IEEE 1149.1 JTAG-Compatible Boundary Scan
■
“ZZ” Sleep Mode option
Addresses and chip enables are registered at the rising edge of
the clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle.This part supports byte write
operations (see "Pin Definitions" on page 5 and "Truth Table" on
page 8 for further details). Write cycles can be one to two or four
bytes wide as controlled by the byte write control inputs. GW
when active LOW causes all bytes to be written.
The CY7C1480V33 operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All inputs and outputs are JEDEC standard JESD8-5 compatible.
Selection Guide
200 MHz
167 MHz
Unit
Maximum Access Time
Description
3.0
3.4
ns
Maximum Operating Current
500
450
mA
Maximum CMOS Standby Current
120
120
mA
Errata: For information on silicon errata, see "Errata" on page 21. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-05283 Rev. *N
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 19, 2013
CY7C1480V33
Logic Block Diagram – CY7C1480V33
A 0, A1, A
ADDRESS
REGISTER
2
A [1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
CLR AND
LOGIC
ADSC
Q0
ADSP
BW D
DQ D ,DQP D
BYTE
WRITE REGISTER
DQ D ,DQPD
BYTE
WRITE DRIVER
BW C
DQ C ,DQP C
BYTE
WRITE REGISTER
DQ C ,DQP C
BYTE
WRITE DRIVER
DQ B ,DQP B
BYTE
WRITE REGISTER
DQ B ,DQP B
BYTE
WRITE DRIVER
BW B
BW A
BWE
ZZ
ENABLE
REGISTER
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP A
DQP B
DQP C
DQP D
DQ A ,DQP A
BYTE
WRITE DRIVER
DQ A ,DQP A
BYTE
WRITE REGISTER
GW
CE 1
CE 2
CE 3
OE
MEMORY
ARRAY
PIPELINED
ENABLE
INPUT
REGISTERS
SLEEP
CONTROL
Document Number: 38-05283 Rev. *N
Page 2 of 25
CY7C1480V33
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Single Write Accesses Initiated by ADSP ................... 6
Single Write Accesses Initiated by ADSC ................... 7
Burst Sequences ......................................................... 7
Sleep Mode ................................................................. 7
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics ................................. 7
Truth Table ........................................................................ 8
Truth Table for Read/Write .............................................. 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Electrical Characteristics ............................................... 10
Capacitance .................................................................... 11
Thermal Resistance ........................................................ 11
Document Number: 38-05283 Rev. *N
AC Test Loads and Waveforms ..................................... 12
Switching Characteristics .............................................. 13
Switching Waveforms .................................................... 14
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagrams .......................................................... 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Errata ............................................................................... 21
Part Numbers Affected .............................................. 21
Product Status ........................................................... 21
Ram9 Sync/NoBL ZZ Pin Issues Errata Summary .... 21
Document History Page ................................................. 22
Sales, Solutions, and Legal Information ...................... 25
Worldwide Sales and Design Support ....................... 25
Products .................................................................... 25
PSoC Solutions ......................................................... 25
Page 3 of 25
CY7C1480V33
Pin Configurations
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) Pinout[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1480V33
(2 M × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
A
A
A
A
A
A
A
A
A
MODE
A
A
A
A
A1
A0
A
A
VSS
VDD
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQPC
DQC
DQc
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
Note
1. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see“Errata” on page 21.This issue is fixed in the CY7C1480BV33 device.
Document Number: 38-05283 Rev. *N
Page 4 of 25
CY7C1480V33
Pin Definitions
Pin Name
I/O
Description
A0, A1, A
InputAddress Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK
Synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1:A0 are fed to the two-bit
counter.
BWA,BWB,
BWC,BWD
InputByte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
GW
InputGlobal Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write
Synchronous is conducted (all bytes are written, regardless of the values on BWX and BWE).
BWE
InputByte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be asserted
Synchronous LOW to conduct a byte write.
CLK
InputClock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW during a burst operation.
CE1
InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2
InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded.
CE3
InputChip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.
OE
InputOutput Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
InputAdvance Input Signal, Sampled on the Rising Edge of CLK, Active LOW. When asserted, it
Synchronous automatically increments the address in a burst cycle.
ADSP
InputAddress Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
ADSC
InputAddress Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ[2]
InputZZ “Sleep” Input, Active HIGH. When asserted HIGH places the device in a non-time-critical “sleep”
Asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull-down.
DQs, DQPs
I/OBidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed
in a tri-state condition.
VDD
Power Supply Power supply inputs to the core of the device.
VSS
Ground
Ground for the core of the device.
VSSQ[3]
I/O Ground Ground for the I/O circuitry.
VDDQ
I/O Power
Supply
Power supply for the I/O circuitry.
Notes
2. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see“Errata” on page 21.This issue is fixed in the CY7C1480BV33
device.
3. Applicable for TQFP package.
Document Number: 38-05283 Rev. *N
Page 5 of 25
CY7C1480V33
Pin Definitions (continued)
Pin Name
MODE
I/O
Description
Input Static Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and must remain static during device operation.
Mode Pin has an internal pull up.
TDO
JTAG Serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is
Output
not used, this pin must be disconnected. This pin is not available on TQFP packages.
Synchronous
TDI
JTAG Serial Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used,
Input
this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
Synchronous
TMS
JTAG Serial Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not used,
this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
Input
Synchronous
TCK
JTAG Clock Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be connected to VSS.
This pin is not available on TQFP packages.
NC
–
No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion
pins and are not internally connected to the die.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 3.0 ns (200 MHz device).
The CY7C1480V33 supports secondary cache in systems using
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486 processors. The linear
burst sequence is suited for processors that use a linear burst
sequence. The burst order is user selectable, and is determined
by sampling the MODE input. Accesses can be initiated with
either the Processor Address Strobe (ADSP) or the Controller
Address Strobe (ADSC). Address advancement through the
burst sequence is controlled by the ADV input. A two-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide easy bank selection
and output tri-state control. ADSP is ignored if CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is
HIGH. The address presented to the address inputs (A) is stored
into the address advancement logic and the Address Register
while being presented to the memory array. The corresponding
data is allowed to propagate to the input of the Output Registers.
At the rising edge of the next clock the data is allowed to
Document Number: 38-05283 Rev. *N
propagate through the output register and onto the data bus
within 3.0 ns (250-MHz device) if OE is active LOW. The only
exception occurs when the SRAM is emerging from a deselected
state to a selected state, its outputs are always tri-stated during
the first cycle of the access. After the first cycle of the access,
the outputs are controlled by the OE signal. Consecutive single
read cycles are supported. After the SRAM is deselected at clock
rise by the chip select and either ADSP or ADSC signals, its
output tri-states immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1,
CE2, CE3 are all asserted active. The address presented to A is
loaded into the address register and the address advancement
logic while being delivered to the memory array. The write signals
(GW, BWE, and BWX) and ADV inputs are ignored during this
first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the
corresponding address location in the memory array. If GW is
HIGH, then the write operation is controlled by BWE and BWX
signals.
The CY7C1480V33 provides byte write capability that is
described in the "Truth Table for Read/Write" on page 9.
Asserting the Byte Write Enable input (BWE) with the selected
Byte Write (BWX) input, will selectively write to only the desired
bytes. Bytes not selected during a Byte Write operation will
remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.
Because CY7C1480V33 is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQs inputs. Doing so will tri-state the output drivers. As a
safety precaution, DQs are automatically tri-stated whenever a
Write cycle is detected, regardless of the state of OE.
Page 6 of 25
CY7C1480V33
Single Write Accesses Initiated by ADSC
Sleep Mode
ADSC Write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the
appropriate combination of the Write inputs (GW, BWE, and
BWX) are asserted active to conduct a Write to the desired
byte(s). ADSC-triggered Write accesses require a single clock
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global Write is conducted, the data presented to
the DQs is written into the corresponding address location in the
memory core. If a Byte Write is conducted, only the selected
bytes are written. Bytes not selected during a Byte Write
operation will remain unaltered. A synchronous self-timed Write
mechanism has been provided to simplify the Write operations.
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected before entering the “sleep” mode. CE1, CE2,
CE3, ADSP, and ADSC must remain inactive for the duration of
tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
Because CY7C1480V33 is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQs inputs. Doing so will tri-state the output drivers. As a
safety precaution, DQs are automatically tri-stated whenever a
Write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1480V33 provides a two-bit wraparound counter, fed
by A1:A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed
specifically to support Intel Pentium applications. The linear
burst sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
Asserting ADV LOW at clock rise will automatically increment the
burst counter to the next address in the burst sequence. Both
Read and Write burst operations are supported.
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
tZZREC
ZZ recovery time
ZZ < 0.2 V
tZZI
ZZ Active to Sleep current
tRZZI
Min
Max
Unit
–
120
mA
–
2tCYC
ns
2tCYC
–
ns
This parameter is sampled
–
2tCYC
ns
ZZ Inactive to exit Sleep current This parameter is sampled
0
–
ns
Document Number: 38-05283 Rev. *N
Page 7 of 25
CY7C1480V33
Truth Table
The Truth Table for CY7C1480V33 follows. [4, 5, 6, 7, 8]
Operation
Add. Used
CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselect Cycle, Power Down
None
H
X
X
L
X
L
X
X
X
L–H Tri-State
Deselect Cycle, Power Down
None
L
L
X
L
L
X
X
X
X
L–H Tri-State
Deselect Cycle, Power Down
None
L
X
H
L
L
X
X
X
X
L–H Tri-State
Deselect Cycle, Power Down
None
L
L
X
L
H
L
X
X
X
L–H Tri-State
L–H Tri-State
Deselect Cycle, Power Down
None
L
X
H
L
H
L
X
X
X
Sleep Mode, Power Down
None
X
X
X
H
X
X
X
X
X
X
Tri-State
READ Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L–H
Q
READ Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L–H Tri-State
WRITE Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L–H
D
READ Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L–H
Q
READ Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L–H Tri-State
Next
X
X
X
L
H
H
L
H
L
L–H
READ Cycle, Continue Burst
Q
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L–H Tri-State
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L–H
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L–H Tri-State
WRITE Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L–H
WRITE Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L–H
D
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L–H
Q
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L–H Tri-State
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L–H
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L–H Tri-State
WRITE Cycle,Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L–H
D
WRITE Cycle,Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L–H
D
Q
D
Q
Notes
4. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
5. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
6. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to allow the outputs to tri-state. OE is a “don't care”
for the remainder of the write cycle.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 38-05283 Rev. *N
Page 8 of 25
CY7C1480V33
Truth Table for Read/Write
The following is a Truth Table for Read/Write for the CY7C1480V33. [9]
Function
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
H
L
H
H
H
L
H
L
H
H
L
H
Write Bytes B, A
H
L
H
H
L
L
Write Byte C – (DQC and DQPC)
H
L
H
L
H
H
Write Bytes C, A
H
L
H
L
H
L
Write Bytes C, B
H
L
H
L
L
H
Write Bytes C, B, A
H
L
H
L
L
L
Write Byte D – (DQD and DQPD)
H
L
L
H
H
H
Write Bytes D, A
H
L
L
H
H
L
Write Bytes D, B
H
L
L
H
L
H
Write Bytes D, B, A
H
L
L
H
L
L
Write Bytes D, C
H
L
L
L
H
H
Write Bytes D, C, A
H
L
L
L
H
L
Write Bytes D, C, B
H
L
L
L
L
H
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
Note
9. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
Document Number: 38-05283 Rev. *N
Page 9 of 25
CY7C1480V33
Maximum Ratings
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Latch-up Current .................................................... > 200 mA
Operating Range
Supply Voltage on VDD Relative to GND .....–0.3 V to +4.6 V
Range
Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD
DC Voltage Applied to Outputs
in Tri-State ........................................–0.5 V to VDDQ + 0.5 V
Commercial
Ambient
Temperature
0 C to +70 C
VDD
VDDQ
3.3 V– 5% / 2.5 V – 5% to
+ 10%
VDD
Electrical Characteristics
Over the Operating Range
Parameter [10, 11]
Description
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
VIH
Output LOW Voltage
Input HIGH
Voltage[10]
Voltage[10]
Test Conditions
Min
Max
Unit
3.135
3.6
V
For 3.3 V I/O
3.135
VDD
V
For 2.5 V I/O
2.375
2.625
V
For 3.3 V I/O, IOH = –4.0 mA
2.4
–
V
For 2.5 V I/O, IOH = –1.0 mA
2.0
–
V
For 3.3 V I/O, IOL = 8.0 mA
–
0.4
V
For 2.5 V I/O, IOL = 1.0 mA
–
0.4
V
For 3.3 V I/O
2.0
VDD + 0.3 V
V
For 2.5 V I/O
1.7
VDD + 0.3 V
V
For 3.3 V I/O
–0.3
0.8
V
For 2.5 V I/O
VIL
Input LOW
–0.3
0.7
V
IX
Input Leakage Current except ZZ GND  VI  VDDQ
and MODE
–5
5
A
Input Current of MODE
–30
–
A
Input = VSS
Input = VDD
–
5
A
Input Current of ZZ
Input = VSS
–5
–
A
Input = VDD
–
30
A
IOZ
Output Leakage Current
GND  VI  VDDQ, Output Disabled
–5
5
A
IDD
VDD Operating Supply Current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
5.0-ns cycle,
200 MHz
–
500
mA
6.0-ns cycle,
167 MHz
–
450
mA
VDD = Max, Device Deselected, 5.0-ns cycle,
VIN  VIH or VIN  VIL,
200 MHz
f = fMAX = 1/tCYC
6.0-ns cycle,
167 MHz
–
245
mA
–
245
mA
VDD = Max, Device Deselected, All speeds
VIN  0.3 V or VIN > VDDQ – 0.3 V,
f=0
–
120
mA
ISB1
ISB2
Automatic CE Power Down
Current – TTL Inputs
Automatic CE Power Down
Current – CMOS Inputs
Notes
10. Overshoot: VIH(AC) < VDD +1.5 V (Pulse width less than tCYC/2). Undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
11. Power up: Assumes a linear ramp from 0 V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05283 Rev. *N
Page 10 of 25
CY7C1480V33
Electrical Characteristics (continued)
Over the Operating Range
Parameter [10, 11]
ISB3
Description
Automatic CE Power Down
Current – CMOS Inputs
ISB4
Automatic CE Power Down
Current – TTL Inputs
Test Conditions
Min
Max
Unit
VDD = Max, Device Deselected, 5.0-ns cycle,
VIN  0.3 V or VIN > VDDQ – 0.3 V, 200 MHz
f = fMAX = 1/tCYC
6.0-ns cycle,
167 MHz
–
245
mA
–
245
mA
VDD = Max, Device Deselected, All speeds
VIN  VIH or VIN  VIL, f = 0
–
135
mA
Capacitance
Parameter [12]
Description
CADDRESS
Address input capacitance
CDATA
Data input capacitance
CCTRL
CCLK
CI/O
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
100-pin TQFP Unit
Max
6
pF
5
pF
Control input capacitance
8
pF
Clock input capacitance
6
pF
Input/Output capacitance
5
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, according
to EIA/JESD51.
24.63
C/W
2.28
C/W
Thermal Resistance
Parameter [12]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Note
12. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05283 Rev. *N
Page 11 of 25
CY7C1480V33
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317 
3.3 V
OUTPUT
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50 
Z0 = 50 
10%
90%
10%
90%
GND
5 pF
R = 351 
 1 ns
 1 ns
VL = 1.5 V
INCLUDING
JIG AND
SCOPE
(a)
(c)
(b)
2.5 V I/O Test Load
R = 1667 
2.5V
OUTPUT
Z0 = 50 
10%
R = 1538 
VL = 1.25 V
Document Number: 38-05283 Rev. *N
INCLUDING
JIG AND
SCOPE
90%
10%
90%
GND
5 pF
(a)
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50 
(b)
 1 ns
 1 ns
(c)
Page 12 of 25
CY7C1480V33
Switching Characteristics
Over the Operating Range
Parameter [13, 14]
tPOWER
Description
VDD(Typical) to the First Access [15]
200 MHz
167 MHz
Unit
Min
Max
Min
Max
1
–
1
–
ms
Clock
tCYC
Clock Cycle Time
5.0
–
6.0
–
ns
tCH
Clock HIGH
2.0
–
2.4
–
ns
tCL
Clock LOW
2.0
–
2.4
–
ns
Output Times
tCO
Data Output Valid After CLK Rise
–
3.0
–
3.4
ns
tDOH
Data Output Hold After CLK Rise
1.3
–
1.5
–
ns
Clock to Low Z
[16, 17, 18]
1.3
–
1.5
–
ns
tCHZ
Clock to High Z
[16, 17, 18]
–
3.0
–
3.4
ns
tOEV
OE LOW to Output Valid
–
3.0
–
3.4
ns
0
–
0
–
ns
–
3.0
–
3.4
ns
tCLZ
tOELZ
tOEHZ
OE LOW to Output Low Z
[16, 17, 18]
OE HIGH to Output High Z
[16, 17, 18]
Setup Times
tAS
Address Setup Before CLK Rise
1.4
–
1.5
–
ns
tADS
ADSC, ADSP Setup Before CLK Rise
1.4
–
1.5
–
ns
tADVS
ADV Setup Before CLK Rise
1.4
–
1.5
–
ns
tWES
GW, BWE, BWX Setup Before CLK Rise
1.4
–
1.5
–
ns
tDS
Data Input Setup Before CLK Rise
1.4
–
1.5
–
ns
tCES
Chip Enable Setup Before CLK Rise
1.4
–
1.5
–
ns
tAH
Address Hold After CLK Rise
0.4
–
0.5
–
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.4
–
0.5
–
ns
tADVH
ADV Hold After CLK Rise
0.4
–
0.5
–
ns
tWEH
GW, BWE, BWX Hold After CLK Rise
0.4
–
0.5
–
ns
tDH
Data Input Hold After CLK Rise
0.4
–
0.5
–
ns
tCEH
Chip Enable Hold After CLK Rise
0.4
–
0.5
–
ns
Hold Times
Notes
13. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
14. Test conditions shown in (a) of Figure 2 on page 12 unless otherwise noted.
15. This part has an internal voltage regulator; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can
be initiated.
16. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 12. Transition is measured ±200 mV from steady-state voltage.
17. At any possible voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve High-Z before Low-Z under the same system conditions.
18. This parameter is sampled and not 100% tested.
Document Number: 38-05283 Rev. *N
Page 13 of 25
CY7C1480V33
Switching Waveforms
Figure 3. Read Cycle Timing [19]
t CYC
CLK
t
t
ADS
CH
t
CL
t
ADH
ADSP
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
t WES
A3
Burst continued with
new base address
tWEH
GW, BWE,
BWx
t CES
Deselect
cycle
tCEH
CE
t ADVS
tADVH
ADV
ADV
suspends
burst.
OE
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t OEV
t CO
t OELZ
t DOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
t CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note
19. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
Document Number: 38-05283 Rev. *N
Page 14 of 25
CY7C1480V33
Switching Waveforms (continued)
Figure 4. Write Cycle Timing [20, 21]
t CYC
CLK
tCH
t ADS
tCL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
BW X
t WES tWEH
GW
t CES
tCEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
t DS
Data In (D)
High-Z
t
OEHZ
tDH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
20. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
21. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW, and BWX LOW.
Document Number: 38-05283 Rev. *N
Page 15 of 25
CY7C1480V33
Switching Waveforms (continued)
Figure 5. Read/Write Cycle Timing [22, 23, 24]
tCYC
CLK
tCL
tCH
t ADS
tADH
t AS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
t WES tWEH
BWE,
BW X
t CES
tCEH
CE
ADV
OE
t DS
tCO
tDH
t OELZ
Data In (D)
High-Z
tCLZ
Data Out (Q)
High-Z
Q(A1)
Back-to-Back READs
tOEHZ
D(A5)
D(A3)
Q(A4)
Q(A2)
Single WRITE
Q(A4+1)
Q(A4+2)
Q(A4+3)
BURST READ
DON’T CARE
D(A6)
Back-to-Back
WRITEs
UNDEFINED
Notes
22. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
23. The data bus (Q) remains in high Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.
24. GW is HIGH.
Document Number: 38-05283 Rev. *N
Page 16 of 25
CY7C1480V33
Switching Waveforms (continued)
Figure 6. ZZ Mode Timing [25, 26]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
25. Device must be deselected when entering ZZ mode. See "Truth Table" on page 8 for all possible signal conditions to deselect the device.
26. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05283 Rev. *N
Page 17 of 25
CY7C1480V33
Ordering Information
Speed
(MHz)
Package
Diagram
Ordering Code
Part and Package Type
Operating
Range
167
CY7C1480V33-167AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
200
CY7C1480V33-200AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
Ordering Code Definitions
CY 7
C 1480 V33 - XXX A
X
C
Temperature Range:
C = Commercial
Pb-free
Package Type:
A = 100-pin TQFP
Frequency Range: XXX = 167 MHz or 200 MHz
VDD = 3.3 V
Part Identifier: 1480 = SCD, 2 Mb × 36 (72 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAMs
Company ID: CY = Cypress
Document Number: 38-05283 Rev. *N
Page 18 of 25
CY7C1480V33
Package Diagrams
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *D
Document Number: 38-05283 Rev. *N
Page 19 of 25
CY7C1480V33
Acronyms
Document Conventions
Acronym
Description
Units of Measure
BGA
Ball Grid Array
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
FBGA
Fine-Pitch Ball Grid Array
MHz
megahertz
I/O
Input/Output
µA
microampere
JTAG
Joint Test Action Group
mA
milliampere
LSB
Least Significant Bit
mm
millimeter
MSB
Most Significant Bit
ms
millisecond
OE
Output Enable
ns
nanosecond
SRAM
Static Random Access Memory

ohm
TAP
Test Access Port
%
percent
TCK
Test Clock
pF
picofarad
TDI
Test Data-In
V
volt
TDO
Test Data-Out
W
watt
TMS
Test Mode Select
TQFP
Thin Quad Flat Pack
TTL
Transistor Transistor Logic
WE
Write Enable
Document Number: 38-05283 Rev. *N
Symbol
Unit of Measure
Page 20 of 25
CY7C1480V33
Errata
This section describes the Ram9 Sync/NoBL ZZ pin, JTAG, and Chip Enable issues. Details include trigger conditions, the devices
affected, proposed workaround and silicon revision applicability. Please contact your local Cypress sales representative if you have
further questions.
Part Numbers Affected
Density & Revision
72Mb-Ram9 Synchronous SRAMs: CY7C148*V33
Package Type
Operating Range
All packages
Commercial/Industrial
Product Status
All of the devices in the Ram9 72Mb Sync/NoBL family are qualified and available in production quantities.
Ram9 Sync/NoBL ZZ Pin Issues Errata Summary
The following table defines the errata applicable to available Ram9 72Mb Sync/NoBL family devices.
Item
1.
Issues
ZZ Pin
Description
Device
Fix Status
When asserted HIGH, the ZZ pin places device in
a “sleep” condition with data integrity
preserved.The ZZ pin currently does not have an
internal pull-down resistor and hence cannot be
left floating externally by the user during normal
mode of operation.
72M-Ram9 (90nm)
For the 72M Ram9 (90 nm)
devices, this issue was fixed in
the new revision. Please
contact your local sales rep for
availability.
1. ZZ Pin Issue
■
PROBLEM DEFINITION
The problem occurs only when the device is operated in the normal mode with ZZ pin left floating. The ZZ pin on the SRAM
device does not have an internal pull-down resistor. Switching noise in the system may cause the SRAM to recognize a HIGH
on the ZZ input, which may cause the SRAM to enter sleep mode. This could result in incorrect or undesirable operation of the
SRAM.
■
TRIGGER CONDITIONS
Device operated with ZZ pin left floating.
■
SCOPE OF IMPACT
When the ZZ pin is left floating, the device delivers incorrect data.
■
WORKAROUND
Tie the ZZ pin externally to ground.
■
FIX STATUS
Fix was done for the 72Mb RAM9 Synchronous SRAMs and 72M RAM9 NoBL SRAMs devices. Fixed devices have a new
revision. The following table lists the devices affected and the new revision after the fix.
Table 1. List of Affected Devices and the new revision
Revision before the Fix
New Revision after the Fix
CY7C148*V33
CY7C148*BV33
Document Number: 38-05283 Rev. *N
Page 21 of 25
CY7C1480V33
Document History Page
Document Title: CY7C1480V33, 72-Mbit (2 M × 36) Pipelined Sync SRAM
Document Number: 38-05283
Rev.
ECN No.
Submission
Date
Orig. of
Change
Description of Change
**
114670
08/06/02
PKS
New data sheet.
*A
118281
01/21/03
HGK
Changed status from Advanced Information to Preliminary.
Updated Features (Removed 300 MHz frequency related information, updated
package offering).
Updated Selection Guide (Removed 300 MHz frequency related information).
Updated Electrical Characteristics (Removed 300 MHz frequency related
information).
Updated Switching Characteristics (Removed 300 MHz frequency related
information, changed maximm value of tCO parameter from 2.4 ns to 2.6 ns for
250 MHz).
Updated Ordering Information (Updated part numbers).
*B
233368
See ECN
NJY
Updated Features (Removed 250 MHz frequency related information and
included 225 MHz frequency related information).
Updated Functional Description.
Updated Logic Block Diagrams (Corresponding to CY7C1480V33,
CY7C1482V33, CY7C1486V33).
Updated Selection Guide (Removed 250 MHz frequency related information
and included 225 MHz frequency related information).
Updated Functional Overview.
Added Boundary Scan Exit Order (For all packages (Corresponding to
CY7C1480V33, CY7C1482V33, CY7C1486V33)).
Updated Electrical Characteristics (Removed 250 MHz frequency related
information and included 225 MHz frequency related information, replaced the
TBD’s with their respective values for IDD, ISB1, ISB2, ISB3 and ISB4 parameters).
Updated Capacitance (Replaced values for all parameters for all Packages).
Updated Thermal Resistance (Replaced values of JA and JC parameters
from TBD to respective Thermal Values for all Packages).
Updated Switching Characteristics (Removed 250 MHz frequency related
information and included 225 MHz frequency related information).
Updated Switching Waveforms.
Updated Package Diagrams (Changed package outline for 165-ball FBGA
package and 209-ball BGA package, removed 119-BGA package offering).
*C
299452
See ECN
SYT
Updated Features (Removed 225 MHz frequency related information and
included 250 MHz frequency related information).
Updated Selection Guide (Removed 225 MHz frequency related information
and included 250 MHz frequency related information).
Updated Electrical Characteristics (Removed 225 MHz frequency related
information and included 250 MHz frequency related information).
Updated Thermal Resistance (Changed values of JA parameter from
16.8 C/W to 24.63 C/W and JC parameter from 3.3 C/W to 2.28 C/W for
100-pin TQFP Package).
Updated Switching Characteristics (Removed 225 MHz frequency related
information and included 250 MHz frequency related information, changed
minimum value of tCYC parameter from 4.4 ns to 4.0 ns for 250 MHz frequency).
Updated Ordering Information (Updated part numbers (Added Pb-free
information for 100-pin TQFP, 165-ball FBGA and 209-ball BGA Packages),
added ‘Pb-free BG packages availability’ comment below the Ordering
Information).
Document Number: 38-05283 Rev. *N
Page 22 of 25
CY7C1480V33
Document History Page (continued)
Document Title: CY7C1480V33, 72-Mbit (2 M × 36) Pipelined Sync SRAM
Document Number: 38-05283
Rev.
ECN No.
Submission
Date
Orig. of
Change
Description of Change
*D
323080
See ECN
PCI
Updated Selection Guide (Unshaded 200 MHz and 167 MHz frequency related
information).
Updated Pin Configurations (Modified Address expansion pins/balls in the
pinouts for all packages as per JEDEC standard).
Updated Pin Definitions.
Added Truth Table for Read/Write (Corresponding to CY7C1486V33). Added
Note “BWx represents any byte write signal BW[0..7].To enable any byte write
BWx, a Logic LOW signal should be applied at clock rise. Any number of bye
writes can be enabled at the same time for any given write.” and referred the
same note in that table).
Updated Operating Range (Added Industrial Operating Range).
Updated Electrical Characteristics (Unshaded 200 MHz and 167 MHz
frequency related information, Updated test conditions for VOL, VOH
parameters).
Updated Switching Characteristics (Unshaded 200 MHz and 167 MHz
frequency related information).
Updated Ordering Information (Updated part numbers, removed ‘Pb-free BG
packages availability’ comment below the Ordering Information).
*E
416193
See ECN
NXR
Changed status from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation from “3901 North
First Street” to “198 Champion Court”.
Updated Electrical Characteristics (Updated Note 11 (Changed test condition
from VIH < VDD to VIH VDD), changed “Input Load Current except ZZ and
MODE” to “Input Leakage Current except ZZ and MODE”, changed minimum
value of IX parameter (corresponding to Input current of MODE (Input = VSS))
from –5 A to –30 A, changed maximum value of IX parameter (corresponding
to Input current of MODE (Input = VDD)) from 30 A to 5 A respectively,
changed minimum value of IX parameter (corresponding to Input current of ZZ
(Input = VSS)) from –30 A to –5 A, changed maximum value of IX parameter
(corresponding to Input current of ZZ (Input = VDD)) from 5 A to 30 A
respectively).
Updated Ordering Information (Updated part numbers, replaced Package
Name column with Package Diagram in the Ordering Information table).
*F
470723
See ECN
VKN
Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage
on VDDQ Relative to GND).
Updated TAP AC Switching Characteristics (Changed minimum value of tTH
and tTL parameters from 25 ns to 20 ns, changed maximum value of tTDOV
parameter from 5 ns to 10 ns).
Updated Ordering Information (Updated part numbers).
*G
486690
See ECN
VKN
Updated Pin Configurations (Corrected the typo in the figure 209-ball FBGA
pinout (Corrected the ball name H9 to VSS from VSSQ)).
*H
1026720
See ECN
VKN
Updated Pin Definitions (Added Note 3 and referred the same note in VSSQ
pin).
*I
2898501
03/24/2010
NJY
Updated Ordering Information (Removed inactive parts from Ordering
Information table)
Updated Package Diagrams.
*J
3067398
10/20/10
NJY
Updated Ordering Information (The part CY7C1480V33-250AXC found to be
in “EOL Prune” state in Oracle PLM is removed from the ordering information
table) and added Ordering Code Definitions.
*K
3257192
05/14/2011
NJY
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Updated in new template.
Document Number: 38-05283 Rev. *N
Page 23 of 25
CY7C1480V33
Document History Page (continued)
Document Title: CY7C1480V33, 72-Mbit (2 M × 36) Pipelined Sync SRAM
Document Number: 38-05283
Rev.
ECN No.
Submission
Date
Orig. of
Change
Description of Change
*L
3596931
04/23/2012
NJY
Updated Features (Removed 250 MHz frequency related information, removed
CY7C1482V33, CY7C1486V33 related information, removed 165-ball FBGA
pakcage, 209-ball FBGA package related information).
Updated Functional Description (Removed CY7C1482V33, CY7C1486V33
related information, removed the Note “For best practices recommendations,
please refer to the Cypress application note AN1064, SRAM System
Guidelines.” and its reference).
Updated Selection Guide (Removed 250 MHz frequency related information).
Removed Logic Block Diagram – CY7C1482V33.
Removed Logic Block Diagram – CY7C1486V33.
Updated Pin Configurations (Removed CY7C1482V33, CY7C1486V33 related
information, removed 165-ball FBGA pakcage, 209-ball FBGA package related
information).
Updated Functional Overview (Removed CY7C1482V33, CY7C1486V33
related information).
Updated Truth Table (Removed CY7C1482V33, CY7C1486V33 related
information).
Removed Truth Table for Read/Write (Corresponding to CY7C1482V33,
CY7C1486V33).
Removed IEEE 1149.1 Serial Boundary Scan (JTAG).
Removed TAP Controller State Diagram.
Removed TAP Controller Block Diagram.
Removed TAP Timing.
Removed TAP AC Switching Characteristics.
Removed 3.3 V TAP AC Test Conditions.
Removed 3.3 V TAP AC Output Load Equivalent.
Removed 2.5 V TAP AC Test Conditions.
Removed 2.5 V TAP AC Output Load Equivalent.
Removed TAP DC Electrical Characteristics and Operating Conditions.
Removed Identification Register Definitions.
Removed Scan Register Sizes.
Removed Identification Codes.
Removed Boundary Scan Exit Order (Corresponding to CY7C1480V33,
CY7C1482V33, CY7C1486V33).
Updated Operating Range (Removed Industrial Temperature Range).
Updated Electrical Characteristics (Removed 250 MHz frequency related
information).
Updated Capacitance (Removed 165-ball FBGA pakcage, 209-ball FBGA
package related information).
Updated Thermal Resistance (Removed 165-ball FBGA pakcage, 209-ball
FBGA package related information).
Updated Switching Characteristics (Removed 250 MHz frequency related
information).
Updated Package Diagrams (Removed 165-ball FBGA pakcage (spec
51-85165), 209-ball FBGA package (spec 51-85167) related information).
Replaced all instances of IO with I/O across the document.
*M
3971185
04/23/2013
NJY
Added Errata.
*N
4033875
06/19/2013
NJY
Completing Sunset Review.
Document Number: 38-05283 Rev. *N
Added Errata Footnotes.
Updated in new template.
Page 24 of 25
CY7C1480V33
Sales, Solutions, and Legal Information
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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Products
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cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
cypress.com/go/plc
Memory
cypress.com/go/memory
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cypress.com/go/psoc
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cypress.com/go/support
cypress.com/go/touch
USB Controllers
Wireless/RF
Technical Support
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2002-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05283 Rev. *N
Revised June 19, 2013
Page 25 of 25
i486 is a trademark and Intel and Pentium are registered trademarks of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.