ON NVMFD5853NL Power mosfet 40 v, 10 m , 34 a, dual n.channel logic level, dual so.8fl Datasheet

NVMFD5853NL,
NVMFD5853NLWF
Power MOSFET
40 V, 10 mW, 34 A, Dual N−Channel Logic
Level, Dual SO−8FL
Features
•
•
•
•
•
•
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Small Footprint (5x6 mm) for Compact Designs
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
NVMFD5853NLWF − Wettable Flanks Product
AEC−Q101 Qualified and PPAP Capable
This is a Pb−Free Device
V(BR)DSS
Value
Unit
Drain−to−Source Voltage
VDSS
40
V
Gate−to−Source Voltage
VGS
"20
V
ID
34
A
Power Dissipation
RYJ−mb (Notes 1, 2, 3)
Continuous Drain Current RqJA (Notes 1, 3
& 4)
Power Dissipation
RqJA (Notes 1 & 3)
Pulsed Drain Current
Tmb = 25°C
Steady
State
Tmb = 100°C
Tmb = 25°C
24
PD
Steady
State
Operating Junction and Storage Temperature
Source Current (Body Diode)
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VGS = 10 V, IL(pk) = 28.3 A,
L = 0.1 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
3.0
IDM
165
A
TJ, Tstg
−55 to
175
°C
IS
34
A
EAS
40
mJ
TL
260
°C
W
1.5
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Parameter
Junction−to−Mounting Board (top) − Steady
State (Notes 2, 3)
Junction−to−Ambient − Steady State (min footprint)
Value
RYJ−mb
6.2
Unit
51
RqJA
°C/W
162
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi (Y) is used as required per JESD51−12 for packages in which
substantially less than 100% of the heat flows to single case surface.
3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
4. Continuous DC current rating. Maximum current for pulses as long as 1
second are higher but are dependent on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2013
April, 2013 − Rev. 3
DFN8 5x6
(SO8FL)
CASE 506BT
1
D1 D1
S1
G1
S2
G2
5853xx
AYWZZ
D1
D1
D2
D2
D2 D2
5853NL = Specific Device Code
for NVMFD5853NL
5853LW = Specific Device Code
for NVMFD5853NLWF
A
= Assembly Location
Y
= Year
W
= Work Week
ZZ
= Lot Traceability
ORDERING INFORMATION
Device
Symbol
Junction−to−Ambient − Steady State (Note 3)
MARKING DIAGRAM
1
PD
S2
S1
A
8.5
TA = 100°C
TA = 25°C, tp = 10 ms
W
12
TA = 100°C
TA = 25°C
G2
12
ID
D2
D1
G1
24
Tmb = 100°C
TA = 25°C
34 A
15 mW @ 4.5 V
Dual N−Channel
Symbol
Continuous Drain Current RYJ−mb (Notes 1,
2, 3, 4)
ID MAX
10 mW @ 10 V
40 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
RDS(on) MAX
Package
Shipping†
NVMFD5853NLT1G
DFN8
1500 / Tape &
(Pb−Free)
Reel
NVMFD5853NLWFT1G
DFN8
1500 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NVMFD5853NL/D
NVMFD5853NL, NVMFD5853NLWF
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
40
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
37.1
VGS = 0 V,
VDS = 40 V
mV/°C
TJ = 25°C
1.0
TJ = 125°C
100
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
±100
mA
nA
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temperature
Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
RDS(on)
Forward Transconductance
gFS
1.4
2.4
5.9
V
mV/°C
VGS = 10 V, ID = 15 A
8.4
10
VGS = 4.5 V, ID = 15 A
12.7
15
VDS = 5 V, ID = 5 A
22
S
1100
pF
mW
CHARGES AND CAPACITANCES
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
100
Total Gate Charge
QG(TOT)
12.8
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
QG(TOT)
VGS = 0 V, f = 1.0 MHz, VDS = 25 V
VGS = 4.5 V, VDS = 32 V,
ID = 15 A
152
nC
1.0
3.7
7.0
VGS = 10 V, VDS = 32 V, ID = 15 A
23
nC
td(on)
10
ns
tr
53
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(off)
VGS = 4.5 V, VDS = 20 V,
ID = 15 A, RG = 2.5 W
17
tf
30
td(on)
9.0
tr
td(off)
VGS = 10 V, VDS = 20 V,
ID = 15 A, RG = 2.5 W
tf
ns
23
22
4.3
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.84
TJ = 125°C
0.69
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 20 A
20
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 15 A
QRR
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2
V
ns
12
8.1
12.1
5. Pulse Test: pulse width = 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
1.1
nC
NVMFD5853NL, NVMFD5853NLWF
TYPICAL CHARACTERISTICS
70
10 V
7.5 V
ID, DRAIN CURRENT (A)
50
3.8 V
40
30
3.4 V
20
10
1.0
2.0
3.0
4.0
30
3.0
3.5
4.0
4.5
Figure 2. Transfer Characteristics
0.015
0.010
3
4
5
6
7
8
9
VGS, GATE−TO−SOURCE VOLTAGE (V)
10
0.0200
TJ = 25°C
0.0175
0.0150
VGS = 4.5 V
0.0125
0.0100
VGS = 10 V
0.0075
0.0050
0
5
10
15
20
25
30
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. VGS
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
10000
2.2
VGS = 0 V
ID = 15 A
VGS = 10 V
TJ = 150°C
IDDS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
2.5
Figure 1. On−Region Characteristics
0.020
1.8
TJ = −55°C
TJ = 125°C
VGS, GATE−TO−SOURCE VOLTAGE (V)
0.025
2.0
TJ = 25°C
20
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
ID = 15 A
TJ = 25°C
2
40
0
2.0
5.0
0.030
0.005
50
10
3.0 V
0
0.0
VDS ≥ 10 V
60
4.2 V
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (A)
60
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
70
TJ = 25°C
4.5 V
1.6
1.4
1.2
1.0
TJ = 125°C
1000
0.8
0.6
−50
−25
0
25
50
75
100
125
150
175
100
5
10
15
20
25
30
35
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
40
NVMFD5853NL, NVMFD5853NLWF
TYPICAL CHARACTERISTICS
C, CAPACITANCE (pF)
VGS = 0 V
TJ = 25°C
Ciss
1250
VGS, GATE−TO−SOURCE VOLTAGE (V)
1500
1000
750
500
Coss
250
Crss
0
0
10
20
30
40
8
6
Qgs
4
Qgd
TJ = 25°C
VDS = 32 V
ID = 15 A
2
0
0
5
10
15
20
25
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
70
IS, SOURCE CURRENT (A)
VDS = 20 V
ID = 15 A
VGS = 4.5 V
tr
100
td(on)
tf
td(off)
10
1
10
100
60
VGS = 0 V
TJ = 25°C
50
40
30
20
10
0
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95 1.00
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
100
ID, DRAIN CURRENT (A)
t, TIME (ns)
QT
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
1000
1
10
10 ms
10
100 ms
1
0.1
VGS = 10 V
Single Pulse
TC = 25°C
RDS(on) Limit
Thermal Limit
Package Limit
0.1
1 ms
dc
1
10 ms
10
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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4
100
NVMFD5853NL, NVMFD5853NLWF
TYPICAL CHARACTERISTICS
100
Duty Cycle = 50%
RqJA (°C/W)
10
1
20%
10%
5%
2%
1%
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
PULSE TIME (sec)
Figure 12. Thermal Response
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5
1
10
100
1000
NVMFD5853NL, NVMFD5853NLWF
PACKAGE DIMENSIONS
DFN8 5x6, 1.27P Dual Flag (SO8FL−Dual)
CASE 506BT
ISSUE E
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. PROFILE TOLERANCE APPLIES TO THE EXPOSED PAD AS WELL
AS THE TERMINALS.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS.
6. SEATING PLANE IS DEFINED BY THE TERMINALS. A1 IS DEFINED
AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
7. A VISUAL INDICATOR FOR PIN 1 MUST BE LOCATED IN THIS AREA.
0.20 C
D
A
B
D1
8
PIN ONE
IDENTIFIER
NOTE 7
7
ÉÉ
ÉÉ
1
2
6
2X
0.20 C
5
E1 E
4X
h
c
3
A1
4
TOP VIEW
DETAIL B
0.10 C
0.10 C
NOTE 4
SIDE VIEW
C
DETAIL A
4X
4X
1.40
2.30
b1
5
K1
BOTTOM VIEW
MILLIMETERS
MIN
MAX
MAX
0.90
1.10
−−−
−−−
−−−
0.05
0.33
0.42
0.51
0.33
0.42
0.51
0.20
−−−
0.33
5.15 BSC
4.70
4.90
5.10
3.90
4.10
4.30
1.50
1.70
1.90
6.15 BSC
5.70
5.90
6.10
3.90
4.15
4.40
1.27 BSC
0.45
0.55
0.65
−−−
−−−
12 _
0.51
−−−
−−−
0.56
−−−
−−−
0.48
0.61
0.71
3.25
3.50
3.75
1.80
2.00
2.20
6.59
3.70
4X
8
2X
0.56
L
4.84
N
G
2X
2.08
K
4
DETAIL B
4X
4.56
0.75
e
M
SOLDERING FOOTPRINT*
SEATING
PLANE
NOTE 6
8X
D2
D3
1
ALTERNATE
CONSTRUCTION
DETAIL A
A
DIM
A
A1
b
b1
c
D
D1
D2
D3
E
E1
E2
e
G
h
K
K1
L
M
N
E2
0.70
8X
b
0.10
C A B
0.05
C
4X
1.27
PITCH
5.55
1.00
NOTE 3
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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