November 1998
PRELIMINARY
ML4805
Variable Feedforward PFC/PWM Controller Combo
GENERAL DESCRIPTION
FEATURES
The ML4805 is a controller for power factor corrected,
switched mode power supplies. Similar to the ML4801,
the ML4805 may be used for voltage mode operation. Key
features of this combined PFC and PWM controller are
low start-up and operating currents. Power Factor
Correction (PFC) allows the use of smaller, lower cost
bulk capacitors, reduces power line loading and stress on
the switching FETs, and results in a power supply that
fully complies with IEC1000-2-3 specifications. The
ML4805 includes circuits for the implementation of a
leading edge, average current “boost” type power factor
correction and a trailing edge pulse width modulator.
■
Internally synchronized PFC and PWM in one IC
■
Low start-up current (200µA typ.)
■
Low operating current (5.5mA typ.)
■
Low total harmonic distortion
■
Reduces ripple current in the storage capacitor
between the PFC and PWM sections
■
Average current continuous boost leading edge PFC
The PFC frequency of the ML4805 is automatically set at
half that of the PWM frequency generated by the internal
oscillator. This technique allows the user to design with
smaller output components while maintaining the
optimum operating frequency for the PFC. An overvoltage comparator shuts down the PFC section in the
event of a sudden decrease in load. The PFC section also
includes peak current limiting and input voltage brownout protection.
■
High efficiency trailing edge PWM optimized for
voltage mode operation
■
Current fed gain modulator for improved noise
immunity
■
Brown-out control, overvoltage protection, UVLO, and
soft start
BLOCK DIAGRAM
18
VFB
17
POWER FACTOR CORRECTOR
VCC
+
+
2.75V
+
–
-
-
2
-1V
-
Q
R
Q
S
Q
R
Q
16
PFC OUT
1.6kΩ
ISENSE
S
VREF
+
GAIN
MODULATOR
4
7.5V
REFERENCE
+
IEA
1.6kΩ
IAC
VRMS
VCC
OVP
VEA
-
2.5V
15
1
IEAO
VEAO
PFC ILIMIT
14
3
RAMP 1
8
RTCT
÷2
OSCILLATOR
7
PGND
RAMP 2
12
DUTY CYCLE
LIMIT
9
8V
VDC
6
1.25V
VCC
SS
PWM OUT
-
25µA
5
AGND
+
+
VIN OK
VFB
-
2.5V
+
+
1.5V
8V
-
S
Q
R
Q
13
ILIM
DC ILIMIT
10
11
PULSE WIDTH MODULATOR
VCC
UVLO
REV. 1.1 3/9/2001
ML4805
PIN CONFIGURATION
ML4805
18-Pin PDIP (P18)
18-Pin SOIC (S18)
IEAO
1
18
VEAO
IAC
2
17
VFB
ISENSE
3
16
VREF
VRMS
4
15
VCC
SS
5
14
PFC OUT
VDC
6
13
PWM OUT
RTCT
7
12
PGND
RAMP 1
8
11
AGND
RAMP 2
9
10
ILIM
TOP VIEW
PIN DESCRIPTION
PIN
NAME
FUNCTION
1
IEAO
PFC transconductance current error
amplifier output
2
IAC
PFC gain control reference input
3
I SENSE
Current sense input to the PFC current
limit comparator
4
V RMS
Input for PFC RMS line voltage
compensation
5
SS
Connection point for the PWM soft start
capacitor
6
VDC
PWM voltage feedback input
7
RTCT
Connection for oscillator frequency
setting components
8
RAMP 1
PFC ramp input
2
PIN
NAME
FUNCTION
9
RAMP 2
PWM ramp sense input
10
ILIM
PWM current limit sense input
11
AGND
Analog ground
12
PGND
Power ground
13
PWM OUT PWM driver output
14
PFC OUT
PFC driver output
15
VCC
Positive supply (connected to an
internal shunt regulator).
16
V REF
Buffered output for the internal 7.5V
reference
17
V FB
PFC transconductance voltage error
amplifier input
18
VEAO
PFC transconductance voltage error
amplifier output
REV. 1.1 3/9/2001
ML4805
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
VCC .............................................................................................. 18V
ISENSE Voltage .................................................. -3V to 5V
Voltage on Any Other Pin ...... GND - 0.3V to VCC + 0.3V
I REF ........................................................................................... 20mA
IAC Input Current ..................................................... 10mA
Peak PFC OUT Current, Source or Sink ................. 500mA
Peak PWM OUT Current, Source or Sink ............... 500mA
PFC OUT, PWM OUT Energy Per Cycle ................... 1.5µJ
Junction Temperature ............................................. 150°C
Storage Temperature Range ...................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ..................... 260°C
Thermal Resistance (θJA)
Plastic DIP ........................................................ 70°C/W
Plastic SOIC ................................................... 100°C/W
OPERATING CONDITIONS
Temperature Range
ML4805CX ................................................. 0°C to 70°C
ML4805IX ............................................... -40°C to 85°C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VCC = 15V, RT = 29.4kΩ, RRAMP1 = 15.4kΩ, CT = 270pF, CRAMP1 = 620pF,
TA = Operating Temperature Range (Note 1)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
5
V
VOLTAGE ERROR AMPLIFIER
Transconductance
0
VNON INV = VINV, VEAO = 3.75V
Feedback Reference Voltage
Input Bias Current
40
65
80
µ
2.43
2.50
2.57
V
-0.5
-1.0
µA
Note 2
Output High Voltage
6.0
Output Low Voltage
6.7
Ω
Input Voltage Range
V
0.1
0.4
V
Source Current
∆VIN = ±0.5V, VOUT = 6V
-40
-70
-150
µA
Sink Current
∆VIN = ±0.5V, VOUT = 1.5V
40
70
150
µA
60
70
dB
60
70
dB
Open Loop Gain
PSRR
11V < VCC < 16.5V
CURRENT ERROR AMPLIFIER
Transconductance
-1.5
VNON INV = VINV, VEAO = 3.75V
Input Offset Voltage
V
60
100
120
µ
0
8
15
mV
-0.5
-1.0
µA
Input Bias Current
Output High Voltage
2
6.0
Output Low Voltage
6.7
Ω
Input Voltage Range
V
0.65
1.0
V
Source Current
∆VIN = ±0.5V, VOUT = 6V
-40
-70
-150
µA
Sink Current
∆VIN = ±0.5V, VOUT = 1.5V
40
70
150
µA
55
65
dB
60
75
dB
Open Loop Gain
PSRR
REV. 1.1 3/9/2001
11V < VCC < 16.5V
3
ML4805
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Threshold Voltage
2.65
2.75
2.85
V
Hysteresis
175
250
325
mV
Threshold Voltage
-0.9
-1.0
-1.1
V
∆PFC ILIMIT Threshold - Gain Modulator Output
120
220
OVP COMPARATOR
PFC ILIMIT COMPARATOR
Delay to Output
mV
150
300
ns
1.5
1.6
V
Input Bias Current
±0.3
±1
µA
Delay to Output
150
300
ns
DC ILIMIT COMPARATOR
Threshold Voltage
1.4
VIN OK COMPARATOR
Threshold Voltage
2.4
2.5
2.6
V
Hysteresis
0.8
1.0
1.2
V
IAC = 100µA, VRMS = VFB = 0V
0.65
0.85
1.05
IAC = 50µA, VRMS = 1V, VFB = 0V
1.90
2.20
2.40
IAC = 50µA, VRMS = 1.8V, VFB = 0V
0.90
1.05
1.25
IAC = 100µA, VRMS = 3.3V, VFB = 0V
0.20
0.30
0.40
GAIN MODULATOR
Gain (Note 3)
Bandwidth
IAC = 100µA
10
MHz
Output Voltage
IAC = 350µA, VRMS = 1V,
VFB = 0V
0.65
0.75
0.85
V
Initial Accuracy
TA = 25ºC
188
200
212
kHz
Voltage Stability
11V < VCC < 16.5V
OSCILLATOR
Temperature Stability
Total Variation
Line, Temp
2
%
218
2.5
PFC Dead Time
4
%
182
Ramp Valley to Peak Voltage
CT Discharge Current
1
VRAMP 2 = 0V, VRAMP 1 = 2.5V
kHz
V
350
470
600
ns
3.5
5.5
7.5
mA
REV. 1.1 3/9/2001
ML4805
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
7.4
7.5
7.6
V
REFERENCE
Output Voltage
TA = 25ºC, I(VREF) = 1mA
Line Regulation
11V < VCC < 16.5V
10
25
mV
Load Regulation
1mA < I(VREF) < 10mA
10
20
mV
Temperature Stability
0.4
7.35
%
Total Variation
Line, Load, Temp
Long Term Stability
TJ = 125ºC, 1000 Hours
Minimum Duty Cycle
VIEAO > 6.7V
Maximum Duty Cycle
VIEAO < 1.2V
Output Low Voltage
IOUT = -20mA
0.4
0.8
V
IOUT = -100mA
0.7
2.0
V
IOUT = -10mA, VCC = 9V
0.4
0.8
V
5
7.65
V
25
mV
0
%
PFC
Output High Voltage
Rise/Fall Time
90
95
%
IOUT = 20mA
VCC - 0.8
V
IOUT = 100mA
VCC - 2.0
V
CL = 1000pF
50
ns
PWM
DC
Duty Cycle Range
VOL
Output Low Voltage
VOH
Output High Voltage
0-44
0-47
0-50
%
IOUT = -20mA
0.4
0.8
V
IOUT = -100mA
0.7
2.0
V
IOUT = -10mA, VCC = 9V
0.4
0.8
V
IOUT = 20mA
VCC - 0. 8
V
IOUT = 100mA
VCC - 2.0
V
Rise/Fall Time
CL = 1000pF
50
ns
Start-up Current
VCC = 12V, CL = 0
200
350
µA
Operating Current
VCC = 14V, CL = 0
5.5
7.0
mA
SUPPLY
Undervoltage Lockout Threshold
12.4
13.0
13.6
V
Undervoltage Lockout Hysteresis
2.7
3.0
3.3
V
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: Includes all bias currents to other circuits connected to the VFB pin.
Note 3: Gain = K x 5.3V; K = (IMULO - IOFFSET) x IAC x (VEAO - 0.625V)-1.
REV. 1.1 3/9/2001
5
ML4805
FUNCTIONAL DESCRIPTION
The ML4805 consists of a combined average-currentcontrolled, continuous boost Power Factor Corrector (PFC)
front end and a synchronized Pulse Width Modulator
(PWM) back end. It is distinguished from earlier combo
controllers by its dramatically reduced start-up and
operating currents. The PWM section can be used in either
current or voltage mode. In voltage mode, feedforward
from the PFC output buss can be used to improve the
PWM’s line regulation. In either mode, the PWM stage
uses conventional trailing-edge duty cycle modulation,
while the PFC uses leading-edge modulation. This
patented leading/trailing edge modulation technique
results in a higher useable PFC error amplifier bandwidth,
and can significantly reduce the size of the PFC DC buss
capacitor.
The synchronization of the PWM with the PFC simplifies
the PWM compensation due to the reduced ripple on the
PFC output capacitor (the PWM input capacitor). The
PWM section of the ML4805 runs at twice the frequency
of the PFC, which allows the use of smaller PWM output
magnetics and filter capacitors while holding down the
losses in the PFC stage power components.
In addition to power factor correction, a number of
protection features have been built into the ML4805.
These include soft-start, PFC over-voltage protection, peak
current limiting, brown-out protection, duty cycle limit,
and under-voltage lockout.
No filtering is applied following the bridge rectifier, so the
input voltage to the boost converter ranges, at twice line
frequency, from zero volts to the peak value of the AC
input and back to zero. By forcing the boost converter to
meet two simultaneous conditions, it is possible to ensure
that the current which the converter draws from the power
line matches the instantaneous line voltage. One of these
conditions is that the output voltage of the boost converter
must be set higher than the peak value of the line
voltage. A commonly used value is 385VDC, to allow for
a high line of 270VACrms. The other condition is that the
current which the converter is allowed to draw from the
line at any given instant must be proportional to the line
voltage. The first of these requirements is satisfied by
establishing a suitable voltage control loop for the
converter, which sets an average operating current level
for a current error amplifier and switching output driver.
The second requirement is met by using the rectified AC
line voltage to modulate the input of the current control
loop. Such modulation causes the current error amplifier
to command a power stage current which varies directly
with the input voltage. In order to prevent ripple which
will necessarily appear at the output of the boost circuit
(typically about 10VAC on a 385V DC level), from
introducing distortion back through the voltage error
amplifier, the bandwidth of the voltage loop is
deliberately kept low. A final refinement is to adjust the
overall gain of the PFC such to be proportional to 1/VIN2,
which linearizes the transfer function of the system as the
AC input voltage varies.
POWER FACTOR CORRECTION
Power factor correction makes a non-linear load look like
a resistive load to the AC line. For a resistor, the current
drawn from the line is in phase with, and proportional to,
the line voltage, so the power factor is unity (one). A
common class of non-linear load is the input of most
power supplies, which use a bridge rectifier and
capacitive input filter fed from the line. The peakcharging effect which occurs on the input filter capacitor
in such a supply causes brief high-amplitude pulses of
current to flow from the power line, rather than a
sinusoidal current in phase with the line voltage. Such a
supply presents a power factor to the line of less than one
(another way to state this is that it causes significant
current harmonics to appear at its input). If the input
current drawn by such a supply (or any other non-linear
load) can be made to follow the input voltage in
instantaneous amplitude, it will appear resistive to the AC
line and a unity power factor will be achieved.
To maintain the input current of a device drawing power
from the AC line in phase with, and proportional to, the
input voltage, a way must be found to cause that device
to load the line in proportion to the instantaneous line
voltage. The PFC section of the ML4805 uses a boostmode DC-DC converter to accomplish this. The input to
the converter is the full wave rectified AC line voltage.
6
Since the boost converter topology in the ML4805 PFC is
of the current-averaging type, no slope compensation is
required.
PFC SECTION
Gain Modulator
Figure 1 shows a block diagram of the PFC section of the
ML4805. The gain modulator is the heart of the PFC, as it
is this circuit block which controls the response of the
current loop to line voltage waveform and frequency, rms
line voltage, and PFC output voltage. There are three
inputs to the gain modulator. These are:
1) A current representing the instantaneous input voltage
(amplitude and waveshape) to the PFC. The rectified
AC input sine wave is converted to a proportional
current via an external resistor and is then fed into the
gain modulator at IAC. Sampling current in this way
minimizes ground noise, as is required in high power
switching power conversion environments. The gain
modulator responds linearly to this current.
2) A voltage proportional to the long-term rms AC line
voltage, derived from the rectified line voltage after
scaling and filtering. This signal is presented to the
gain modulator at VRMS. The gain modulator’s output is
REV. 1.1 3/9/2001
ML4805
FUNCTIONAL DESCRIPTION
18
VFB
VEA
2.5V
POWER FACTOR CORRECTOR
2.75V
IEA
1.6kΩ
-
15
1
IEAO
VEAO
17
(Continued)
-
+
+
–
IAC
2
8V
GAIN
MODULATOR
VRMS
4
PFC
CONTROLLER
7.5V
REFERENCE
VREF
16
PFC ILIMIT
-1V
+
-
PFC
OUTPUT
DRIVER
1.6kΩ
ISENSE
VCC
OVP
+
3
PFC OUT
14
RAMP 1
OSCILLATOR
8
RTCT
÷2
7
DUTY CYCLE
LIMIT
Figure 1. PFC Section Block Diagram
inversely proportional to VRMS2 (except at unusually
low values of VRMS where special gain contouring
takes over to limit power dissipation of the circuit
components under heavy brownout conditions). The
relationship between VRMS and gain is designated as K.
3) The output of the voltage error amplifier, VEAO. The
gain modulator responds linearly to variations in this
voltage.
The output of the gain modulator is a current signal, in the
form of a full wave rectified sinusoid at twice the line
frequency. This current is applied to the virtual-ground
(negative) input of the current error amplifier. In this way
the gain modulator forms the reference for the current
error loop, and ultimately controls the instantaneous
current draw of the PFC from the power line. The general
form for the output of the gain modulator is:
IGAINMOD =
IAC ´ VEAO
VRMS 2
´ 1V
exactly, the
the output
output current
current of
of the
the gain
gain modulator
modulator is
More exactly,
given by:
by:
given
IGAINMOD = K × (VEAO − 0.625V) × IAC
where K is in units of V-1.
Note that the output current of the gain modulator is
limited to ≅ 500µA.
REV. 1.1 3/9/2001
(1)
Current Error Amplifier
The current error amplifier’s output controls the PFC duty
cycle to keep the current through the boost inductor a
linear function of the line voltage. At the inverting input
to the current error amplifier, the output current of the
gain modulator is summed with a current which results
from a negative voltage being impressed upon the ISENSE
pin (current into ISENSE ≅ VSENSE/1.6kΩ). The negative
voltage on ISENSE represents the sum of all currents
flowing in the PFC circuit, and is typically derived from a
current sense resistor in series with the negative terminal
of the input bridge rectifier. In higher power applications,
two current transformers are sometimes used, one to
monitor the ID of the boost MOSFET(s) and one to monitor
the IF of the boost diode. As stated above, the inverting
input of the current error amplifier is a virtual ground.
Given this fact, and the arrangement of the duty cycle
modulator polarities internal to the PFC, an increase in
positive current from the gain modulator will cause the
output stage to increase its duty cycle until the voltage on
ISENSE is adequately negative to cancel this increased
current. Similarly, if the gain modulator’s output
decreases, the output duty cycle will decrease to achieve
a less negative voltage on the ISENSE pin.
Cycle-By-Cycle Current Limiter
The ISENSE pin, as well as being a part of the current
feedback loop, is a direct input to the cycle-by-cycle
current limiter for the PFC section. Should the input
voltage at this pin ever be more negative than -1V, the
output of the PFC will be disabled until the protection
flip-flop is reset by the clock pulse at the start of the next
PFC power cycle.
7
ML4805
FUNCTIONAL DESCRIPTION
(Continued)
Overvoltage Protection
The OVP comparator serves to protect the power circuit
from being subjected to excessive voltages if the load
should suddenly change. A resistor divider from the high
voltage DC output of the PFC is fed to VFB. When the
voltage on VFB exceeds 2.75V, the PFC output driver is
shut down. The PWM section will continue to operate. The
OVP comparator has 250mV of hysteresis, and the PFC
will not restart until the voltage at VFB drops below 2.5V.
The OVP trip level should be set at a level where the
active and passive external power components and the
ML4805 are within their safe operating voltages, but not
so low as to interfere with the regular operation of the
boost voltage regulation loop.
Error Amplifier Compensation
The PWM loading of the PFC can be modeled as a
negative resistor; an increase in input voltage to the PWM
causes a decrease in the input current. This response
dictates the proper compensation of the two
transconductance error amplifiers. Figure 2 shows the
types of compensation networks most commonly used for
the voltage and current error amplifiers, along with their
respective return points. The current loop compensation is
returned to VREF to produce a soft-start characteristic on
the PFC: as the reference voltage comes up from zero
volts, it creates a differentiated voltage on IEAO which
prevents the PFC from immediately demanding a full duty
cycle on its boost converter.
There are two major concerns when compensating the
voltage loop error amplifier; stability and transient
response. Optimizing interaction between transient
response and stability requires that the error amplifier’s
open-loop crossover frequency should be 1/2 that of the
line frequency, or 23Hz for a 47Hz line (lowest
anticipated international power frequency). Rapid
perturbations in line or load conditions will cause the
input to the voltage error amplifier (VFB) to deviate from
its 2.5V (nominal) value. If this happens, the
transconductance of the voltage error amplifier will
increase significantly. This increases the gain-bandwidth
product of the voltage loop, resulting in a much more
rapid voltage loop response to such perturbations than
would occur with a conventional linear gain
characteristic. The current amplifier compensation is
similar to that of the voltage error amplifier with the
exception of the choice of crossover frequency. The
crossover frequency of the current amplifier should be at
least 10 times that of the voltage amplifier, to prevent
interaction with the voltage loop. It should also be limited
to less than 1/6th that of the switching frequency, e.g.
16.7kHz for a 100kHz switching frequency.
There is also a degree of gain contouring applied to the
transfer characteristic of the current error amplifier, to
increase its speed of response to current-loop
perturbations. However, the boost inductor will usually be
8
the dominant factor in overall current loop response.
Therefore, this contouring is significantly less marked than
that of the voltage error amplifier.
For more information on compensating the current and
voltage control loops, see Application Notes 33, 34, and
55. Application Note 16 also contains valuable
information for the design of this class of PFC.
Oscillator (RTCT)
The oscillator frequency is determined by the values of RT
and CT, which determine the ramp and off-time of the
ML4805's master oscillator:
fOSC =
t RAMP
1
+ t DEADTIME
(2)
(2)
The
The deadtime
deadtime of the oscillator is derived from the
following
following equation:
FG V
HV
REF
t RAMP = CT ´ RT ´ ln
REF
IJ
K
- 125
.
- 375
.
(3)
(3)
at
at V
VREF
REF = 7.5V:
t RAMP = C T ´ R T ´ 0.51
The
The ramp
ramp of
of the
the oscillator may be determined using:
t DEADTIME =
. V
25
´ C T = 455 ´ C T
55
. mA
(4)
(4)
The deadtime is so small (tRAMP >> tDEADTIME) that the
VREF
GND
PFC
OUTPUT
18
1
IEAO
VEAO
VFB
17
VEA
IEA
-
2.5V
+
+
-
IAC
+
-
2
VRMS
4
GAIN
MODULATOR
ISENSE
3
Figure 2. Compensation Network Connections for the
Voltage and Current Error Amplifiers
REV. 1.1 3/9/2001
ML4805
FUNCTIONAL DESCRIPTION
(Continued)
operating frequency
frequency can
can typically
typically be
beapproximated
approximatedby:
by:
fOSC =
1
t RAMP
(5)
EXAMPLE:
EXAMPLE:
For the application circuit shown in the data sheet, with
the oscillator running at:
fOSC = 100kHz =
1
t RAMP
t RAMP = 0.51 ´ R T ´ C T = 1 ´ 10 - 5
Solving for RT x CT yields 2 x 10-4. Selecting standard
components values, CT = 270pF, and RT = 36.5kΩ.
PWM SECTION
Pulse Width Modulator
The PWM section of the ML4805 is straightforward, but
there are several points which should be noted. Foremost
Foremost
among these is its inherent synchronization to the PFC
section of the
the device.
device. The PWM is capable of currentmode or voltage mode operation. In current-mode
applications, the PWM ramp (RAMP 2) is usually derived
directly from a current sensing resistor or current
transformer in the primary of the output stage, and is
thereby representative of the current flowing in the
converter’s output stage. DC ILIMIT
which provides
LIMIT, which
cycle-by-cycle current limiting, is typically connected to
RAMP 22 in
in such
such applications.
applications. For
For voltage-mode
voltage-mode operation
or certain specialized applications, RAMP 2 can be
connected to a separate RC timing network to generate a
voltage ramp against which VDC will be compared. Under
these conditions, the use of voltage feedforward from the
PFC buss can assist in line regulation accuracy and
response. As in current mode operation, the DC ILIMIT
LIMIT
input is used for output stage overcurrent protection.
No voltage error amplifier is included in the PWM stage
of the ML4805, as this function is generally performed on
the output side
side of
of the
the PWM’s
PWM’s isolation
isolation boundary.
boundary. To
facilitate the design of optocoupler feedback circuitry, an
offset has been built into
into the
the PWM’s
PWM’s RAMP 22 input
input which
which
allows VDC to command a zero percent duty cycle for
input voltages below 1.25V.
PWM Current Limit
VIN
IN OK Comparator
monitors the
the DC
DC output
output of
of the
the
The V IN OK comparator monitors
PFC and inhibits the
the PWM
PWM ifif this
this voltage
voltage on
on VFB is less
than its nominal 2.5V. Once this voltage reaches 2.5V,
which corresponds to the PFC output capacitor being
charged to its rated boost voltage, the soft-start
commences.
PWM Control (RAMP 2)
When the PWM section is used in current mode, RAMP 2
is generally used as the sampling point for a voltage
representing the current in the primary
primary of
of the
the PWM’s
PWM’s
output transformer, derived either by a current sensing
resistor or a current transformer. In voltage mode, it is the
input for a ramp voltage generated by a second set of
timing components (RRAMP2
RAMP2, CRAMP2), which will have a
minimum value of zero volts and should have a peak
value of approximately 5V. In voltage mode operation,
feedforward from the PFC output buss is an excellent way
to derive the timing ramp for the PWM stage.
Soft Start
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 25µA
supplies the charging current for the capacitor, and startup of the PWM begins at 1.25V.
1.25V. Start-up delay can be
programmed by the following equation:
25µA
(6)
C SS = t DELAY ×
. V
125
where CSS is the required soft start capacitance, and
tDELAY is the desired start-up
start-up delay.
delay.
It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section.
section. The PWM start-up delay should be at
least 5ms.
Solving for the minimum value of CSS:
25µA
= 100nF
C SS = 5ms ×
125
. V
In the ML4805, the operating frequency of the PFC
section is fixed at 1/2 of the
the PWM's
PWM's operating
operating frequency.
frequency.
This is done through the use of a 2:1 digital
digital frequency
frequency
divider ("T" flip-flop) linking the two functional sections of
the IC.
The DC ILIMIT pin is a direct input to the
the cycle-by-cycle
cycle-by-cycle
current limiter for the PWM section. Should the input
voltage at this pin ever exceed 1.5V, the output of the
PWM will be disabled until the output flip-flop is reset by
the clock pulse at the start of the next PWM power cycle.
REV. 1.1 3/9/2001
9
ML4805
FUNCTIONAL DESCRIPTION
(Continued)
Generating VCC
The ML4805 is a voltage-fed part. It requires an external
15V±10% or better Zener shunt voltage regulator, or some
other controlled supply, to regulate the voltage supplied
to the part at 15V nominal. This allows a low power
dissipation while at the same time delivering 13V
nominal of gate drive at the PWM OUT and PFC OUT
outputs. If using a Zener diode, it is important to limit the
current through the Zener to avoid overheating or
destroying it. This can be easily done with a single resistor
in series with the Vcc pin, returned to a bias supply of
typically 18V to 20V. The resistor’s value must be chosen
to meet the operating current requirement of the ML4805
itself (8.5mA max.) plus the current required by the two
gate driver outputs.
EXAMPLE:
With a VBIAS of 20V, a VCC limit of 16.5V (max) and
driving a total gate charge of 110nC at 100kHz (1 IRF840
MOSFET and 2 IRF830 MOSFETs), the gate driver current
required is:
IGATEDRIVE = 100kHz ´ 110nC = 11mA
R BIAS =
20V - 16.5V
= 180Ω
7.5mA + 11mA
The ML4805 should be locally bypassed with a 10nF and
a 1µF ceramic capacitor. In most applications, an
electrolytic capacitor of between 100µF and 330µF is also
required across the part, both for filtering and as part of
the start-up bootstrap circuitry.
SW2
L1
I2
I1
+
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock.
The error amplifier output voltage is then compared with
the modulating ramp. When the modulating ramp reaches
the level of the error amplifier output voltage, the switch
will be turned OFF. When the switch is ON, the inductor
current will ramp up. The effective duty cycle of the
trailing edge modulation is determined during the ON
time of the switch. Figure 3 shows a typical trailing edge
control scheme.
In the case of leading edge modulation, the switch is
turned OFF right at the leading edge of the system clock.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned ON.
The effective duty-cycle of the leading edge modulation
is determined during the OFF time of the switch. Figure 4
shows a leading edge control scheme.
One of the advantages of this control technique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to
minimize the momentary “no-load” period, thus lowering
ripple voltage generated by the switching action. With
such synchronized switching, the ripple voltage of the
first stage is reduced. Calculation and evaluation have
shown that the 120Hz component of the PFC’s output
ripple voltage can be reduced by as much as 30% using
this method.
I3
L1
I4
SW2
I2
I4
VIN
RL
SW1
DC
SW1
RAMP
C1
I3
I1
+
RL
VIN
DC
LEADING/TRAILING MODULATION
RAMP
C1
VEAO
VEAO
REF
U3
+
–EA
DFF
RAMP
OSC
U4
CLK
+
–
U1
TIME
VSW1
RAMP
R
Q
D U2
Q
CLK
OSC
U4
TIME
Figure 3. Typical Trailing Edge Control Scheme
10
REF
U3
+
–EA
CLK
VEAO
+
–
CMP
U1
TIME
DFF
VSW1
R
Q
D U2
Q
CLK
TIME
Figure 4. Leading/Trailing Edge Control Scheme
REV. 1.1 3/9/2001
ML4805
180
Ω
0
µ
IVEAO (µA)
160
–160
0
1
3
2
4
90
0
5
0
1
3
2
4
5
4
5
VFB (V)
VFB (V)
Figure 5. IVEAO vs. VFB
Figure 6. gM of VOTA
200
500
160
120
µ
K
Ω
80
40
0
0
1
3
2
VFB (V)
Figure 7. gM of IOTA
REV. 1.1 3/9/2001
4
5
0
0
1
3
2
VFB (V)
Figure 8. K of Multiplier
11
ML4805
PHYSICAL DIMENSIONS
inches (millimeters)
Package: P18
18-Pin PDIP
0.890 - 0.910
(22.60 - 23.12)
18
0.240 - 0.260 0.295 - 0.325
(6.09 - 6.61) (7.49 - 8.26)
PIN 1 ID
1
0.045 MIN
(1.14 MIN)
(4 PLACES)
0.050 - 0.065
(1.27 - 1.65)
0.100 BSC
(2.54 BSC)
0.015 MIN
(0.38 MIN)
0.170 MAX
(4.32 MAX)
SEATING PLANE
0.016 - 0.022
(0.40 - 0.56)
0.125 MIN
(3.18 MIN)
0º - 15º
0.008 - 0.012
(0.20 - 0.31)
Package: S18
18-Pin SOIC
0.449 - 0.463
(11.40 - 11.76)
18
0.291 - 0.301 0.398 - 0.412
(7.39 - 7.65) (10.11 - 10.47)
PIN 1 ID
1
0.024 - 0.034
(0.61 - 0.86)
(4 PLACES)
0.050 BSC
(1.27 BSC)
0.095 - 0.107
(2.41 - 2.72)
0º - 8º
0.090 - 0.094
(2.28 - 2.39)
12
0.012 - 0.020
(0.30 - 0.51)
SEATING PLANE
0.005 - 0.013
(0.13 - 0.33)
0.022 - 0.042
(0.56 - 1.07)
0.009 - 0.013
(0.22 - 0.33)
REV. 1.1 3/9/2001
ML4805
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
PACKAGE
ML4805CP
ML4805CS
0°C to 70°C
0°C to 70°C
18-Pin Plastic DIP (P18)
18-Pin Wide SOIC (S18)
ML4805IP
ML4805IS
-40°C to 85°C
-40°C to 85°C
18-Pin Plastic DIP (P18)
18-Pin Wide SOIC (S18)
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
www.fairchildsemi.com
REV. 1.1 3/9/2001
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
© 2000 Fairchild Semiconductor Corporation
13