PD - 96187
IRFS3006-7PPbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
D
G
S
VDSS
60V
RDS(on) typ.
1.5m:
max.
2.1m:
ID (Silicon Limited) 293A
ID (Package Limited) 240A
c
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
D
S
G
S
S
S
S
D2Pak 7 Pin
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TC = 25°C
IDM
PD @TC = 25°C
VGS
Parameter
Max.
293
207
240
1172
375
2.5
± 20
11
-55 to + 175
d
Pulsed Drain Current
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
Mounting torque, 6-32 or M3 screw
f
dv/dt
TJ
TSTG
Avalanche Characteristics
EAS (Thermally limited)
IAR
EAR
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
d
e
Units
c
c
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Package Limited)
A
W
W/°C
V
V/ns
°C
300
x
x
10lb in (1.1N m)
303
See Fig. 14, 15, 22a, 22b,
g
mJ
A
mJ
Thermal Resistance
Symbol
RθJC
RθJA
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Parameter
kl
Junction-to-Case
Junction-to-Ambient (PCB Mount)
jk
Typ.
Max.
Units
–––
–––
0.4
40
°C/W
1
10/06/08
IRFS3006-7PPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
V(BR)DSS
∆V(BR)DSS/∆TJ
RDS(on)
VGS(th)
IDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
IGSS
RG(int)
Min. Typ. Max. Units
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
60
–––
–––
2.0
–––
–––
–––
–––
–––
0.07
1.5
–––
–––
–––
–––
–––
Internal Gate Resistance
–––
2.1
Conditions
–––
V VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 5mA
2.1
mΩ VGS = 10V, ID = 168A
4.0
V VDS = VGS, ID = 250µA
VDS = 60V, VGS = 0V
20
µA
250
VDS = 60V, VGS = 0V, TJ = 125°C
VGS = 20V
100
nA
VGS = -20V
-100
d
g
–––
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
Qsync
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min. Typ. Max. Units
i
h
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
290
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
200
37
60
140
14
61
118
69
8850
1007
525
1460
1915
–––
300
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Conditions
S
VDS = 25V, ID = 168A
ID = 168A
VDS = 30V
nC
VGS = 10V
ID = 168A, VDS =0V, VGS = 10V
VDD = 39V
ID = 168A
ns
RG = 2.7Ω
VGS = 10V
VGS = 0V
VDS = 50V
pF ƒ = 1.0MHz (See Fig 5)
VGS = 0V, VDS = 0V to 48V (See Fig 11)
VGS = 0V, VDS = 0V to 48V
g
g
i
h
Diode Characteristics
Symbol
IS
Parameter
Continuous Source Current
VSD
trr
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
ISM
d
Notes:
Calcuted continuous current based on maximum allowable junction
temperature Bond wire current limit is 240A. Note that current
limitation arising from heating of the device leds may occur with
some lead mounting arrangements.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.021mH
RG = 25Ω, IAS = 168A, VGS =10V. Part not recommended for use
above this value .
ISD ≤ 168A, di/dt ≤ 1410 A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
2
Min. Typ. Max. Units
–––
–––
–––
–––
293
c
1172
Conditions
MOSFET symbol
A
showing the
integral reverse
D
G
S
p-n junction diode.
––– –––
1.3
V TJ = 25°C, IS = 168A, VGS = 0V
TJ = 25°C
VR = 51V,
–––
44
–––
ns
TJ = 125°C
IF = 168A
–––
48
–––
di/dt = 100A/µs
TJ = 25°C
–––
51
–––
nC
TJ = 125°C
–––
62
–––
––– 2.03 –––
A TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
g
g
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For
recommended footprint and soldering techniquea refer to applocation
note # AN-994 echniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C
RθJC value shown is at time zero
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IRFS3006-7PPbF
1000
1000
100
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
8.0V
6.0V
5.0V
4.5V
4.0V
3.5V
10
1
3.5V
≤60µs PULSE WIDTH
100
BOTTOM
VGS
15V
10V
8.0V
6.0V
5.0V
4.5V
4.0V
3.5V
3.5V
10
≤60µs PULSE WIDTH
Tj = 175°C
Tj = 25°C
0.1
1
0.1
1
10
100
0.1
100
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
10
V DS, Drain-to-Source Voltage (V)
1000
T J = 175°C
100
T J = 25°C
10
1
VDS = 25V
≤60µs PULSE WIDTH
0.1
2
3
4
5
6
1.5
1.0
-60 -40 -20 0 20 40 60 80 100120140160180
Fig 4. Normalized On-Resistance vs. Temperature
16.0
VGS, Gate-to-Source Voltage (V)
ID= 168A
C oss = C ds + C gd
Ciss
Coss
Crss
1000
2.0
T J , Junction Temperature (°C)
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
10000
VGS = 10V
0.5
Fig 3. Typical Transfer Characteristics
100000
ID = 168A
7
VGS, Gate-to-Source Voltage (V)
C, Capacitance (pF)
1
100
VDS= 48V
VDS= 30V
12.0
8.0
4.0
0.0
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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0
40
80
120
160
200
240
280
QG, Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFS3006-7PPbF
10000
T J = 175°C
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
100
T J = 25°C
10
OPERATION IN THIS AREA
LIMITED BY R DS(on)
1000
100µsec
100
1msec
LIMITED BY PACKAGE
10
10msec
DC
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
1.0
0.1
0.0
0.4
0.8
1.2
1.6
2.0
0.1
VSD, Source-to-Drain Voltage (V)
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
350
Limited By Package
ID, Drain Current (A)
300
250
200
150
100
50
0
50
75
100
125
10
150
175
80
Id = 5mA
75
70
65
60
55
-60 -40 -20 0 20 40 60 80 100120140160180
T C , Case Temperature (°C)
T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Drain-to-Source Breakdown Voltage
1400
EAS , Single Pulse Avalanche Energy (mJ)
2.5
ID
35A
70A
BOTTOM 168A
1200
2.0
TOP
Energy (µJ)
1000
1.5
1.0
0.5
800
600
400
200
0
0.0
0
10
20
30
40
50
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
100
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
25
1
VDS, Drain-to-Source Voltage (V)
60
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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IRFS3006-7PPbF
Thermal Response ( Z thJC ) °C/W
1
D = 0.50
0.1
0.20
0.10
0.05
0.02
0.01
0.01
τJ
SINGLE PULSE
( THERMAL RESPONSE )
0.001
0.0001
1E-006
R1
R1
τJ
τ1
R2
R2
R3
R3
τC
τ
τ2
τ1
τ2
τ3
τ3
Ci= τi/Ri
Ci i/Ri
1E-005
Ri (°C/W)
R4
R4
0.0001
τ4
τ4
τi (sec)
0.0062
0.000005
0.0431
0.000045
0.1462
0.001067
0.2047
0.010195
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
100
0.01
0.05
0.10
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
350
300
EAR , Avalanche Energy (mJ)
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 168A
250
200
150
100
50
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFS3006-7PPbF
20
ID = 250µA
ID = 1.0mA
ID = 1.0A
4.0
IF = 112A
V R = 51V
16
TJ = 25°C
TJ = 125°C
3.5
3.0
IRR (A)
VGS(th), Gate threshold Voltage (V)
4.5
2.5
12
8
2.0
4
1.5
0
1.0
-75 -50 -25
0
0
25 50 75 100 125 150 175
200
600
800
1000
1200
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
20
600
16
IF = 168A
V R = 51V
500
TJ = 25°C
TJ = 125°C
IF = 112A
V R = 51V
400
TJ = 25°C
TJ = 125°C
12
QRR (A)
IRR (A)
400
diF /dt (A/µs)
T J , Temperature ( °C )
8
300
200
4
100
0
0
0
200
400
600
800
1000
1200
0
200
diF /dt (A/µs)
400
600
800
1000
1200
diF /dt (A/µs)
Fig. 19 - Typical Stored Charge vs. dif/dt
Fig. 18 - Typical Recovery Current vs. dif/dt
QRR (A)
600
500
IF = 168A
V R = 51V
400
TJ = 25°C
TJ = 125°C
300
200
100
0
0
200
400
600
800
1000
1200
diF /dt (A/µs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFS3006-7PPbF
Driver Gate Drive
D.U.T
-
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
DRIVER
L
VDS
tp
D.U.T
RG
VGS
20V
+
V
- DD
IAS
A
0.01Ω
tp
I AS
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
Fig 22b. Unclamped Inductive Waveforms
VDS
90%
VGS
D.U.T.
RG
+
- VDD
V10V
GS
10%
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
Fig 23a. Switching Time Test Circuit
tr
t d(off)
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
12V
tf
.2µF
.3µF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
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Qgs1 Qgs2
Qgd
Qgodr
Fig 24b. Gate Charge Waveform
7
IRFS3006-7PPbF
D2Pak (TO-263CB) 7 Long Leads Package Outline
Dimensions are shown in milimeters (inches)
D2Pak - 7 Pin Part Marking Information
14
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
8
www.irf.com
IRFS3006-7PPbF
D2Pak - 7 Pin Tape and Reel
Dimensions are shown in milimeters (inches)
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
www.irf.com
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 10/2008
9