ASAHI KASEI [AKD5701-A] AKD5701-A AK5701 Evaluation board Rev.0 GENERAL DESCRIPTION AKD5701-A is an evaluation board for the portable digital audio 16bit A/D converter, AK5701. AKD5701-A also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide AKD5701-A --- Evaluation board for AK5701 (Cable for connecting with printer port of IBM-AT compatible PC and control software are packed with this. This control software does not support Windows NT.) FUNCTION • DIT with optical output • RCA connector for an external clock input • 10pin Header for serial control interface AVDD 3.3V Regulator 5V DVDD VD AGND DGND Control Data 10pin Header LIN1/ LIN2 DSP 2 10pin Header AK5701 MIC RIN1/ RIN2 DSP 1 10pin Header AK4114 (DIT) Opt Out EXT/LRCK EXT/BCLK CLOCK GEN Figure 1. AKD5701-A Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. <KM076903> 2005/04 -1- ASAHI KASEI [AKD5701-A] Evaluation Board Manual Operation sequence 1) Set up the power supply lines. 1-1) When AVDD, DVDD and VD are supplied from the regulator. [REG] [AVDD] [DVDD] [VD] [AGND] [DGND] (Red) (Orange) (Orange) (Orange) (Black) (Black) = 5V = open = open = open (for logic) = 0V : for analog ground = 0V : for logic ground 1-2) When AVDD, DVDD and VD are not supplied from the regulator. [REG] [AVDD] [DVDD] [VD] [AGND] [DGND] (Red) (Orange) (Orange) (Orange) (Black) (Black) = “REG” jack should be open. = 2.4 ∼ 3.6V : for AVDD of AK5701 (typ. 3.0V) = 1.6 ∼ 3.6V : for DVDD of AK5701 (typ. 3.0V) = 2.7 ∼ 3.6V : for logic (typ. 3.0V) = 0V : for analog ground = 0V : for logic ground Each supply line should be distributed from the power supply unit. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK5701 and AK4114 should be reset once by bringing SW1, 2 “L” upon power-up. Evaluation mode In case of AK5701 evaluation using AK4114, same audio interface format should be set for both AK5701 and AK4114. About AK5701’s audio interface format, refer to datasheet of AK5701. About AK4114’s audio interface format, refer to Table 2 in this manual. Applicable Evaluation Mode (1) Evaluation of PLL, Master Mode (Default) (2) Evaluation of PLL, Slave Mode (PLL Reference CLOCK: MCKI pin) (3) Evaluation of PLL, Slave Mode (PLL Reference CLOCK: BCLK or LRCK pin) (4) Evaluation of using DIT of AK4114 (opt-connector): EXT, Slave Mode (5) Slave & Bypass Mode (6) Bypass Mode <KM076903> 2005/04 -2- ASAHI KASEI [AKD5701-A] (1) Evaluation of PLL, Master Mode (Default) *Connect PORT2（DSP1） with DSP. Figure below shows PORT2 pin assign. PORT2 MCKO GND BCLK GND LRCK NC SDTO NC VD NC a) Set up jumper pins of MCKI clock When using X’tal as MCKI clock, X’tal of 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz can be set to X1. X’tal of 11.2896MHz (Default) is set on the AKD5701-A. When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz) is supplied through an RCA connector (J3: EXT/BCLK), select EXTCLK/BCLK on JP16 (XTI) and select EXTCLK/BCLK on JP19 (MCLK_SEL). JP14 (EXT1) and R20 should be properly selected in order to match the output impedance of the clock generator. JP16 JP19 JP11 XTI MCLK_SEL MKFS 5701- EXTCLK 4114- MCKO /BCLK MCKO MCKI EXTCLK /BCLK 256fs 512fs 1024fs MCKO b) Set up jumper pins of BCLK clock Output frequency (32fs/64fs) of BCLK should be set by “BCKO1-0 bit” in the AK5701. There is no necessity for set up JP12. JP17 JP12 BCLK_SEL BCLK 64fs 32fs 16fs EXT EXTBCLK/ BCLK/ EXT BCLK DIT DIT c) Set up jumper pins of LRCK clock JP18 JP13 LRCK_SEL LRCK EXT EXT 2fs 1fs EXTLRCK/ LRCK/ LRCK DIT DIT <KM076903> 2005/04 -3- ASAHI KASEI [AKD5701-A] (2) Evaluation of PLL, Slave Mode (PLL Reference CLOCK: MCKI pin) *Connect PORT4 (DSP2) with DSP. Figure below shows PORT4 pin assign. PORT4 MCKI GND EXBCLK GND EXLRCK NC EXSDTI NC VD SDTO a) Set up jumper pins of MCKI clock X’tal of 11.2896MHz (Default) is set on the AKD5701-A. In this case, the AK5701 corresponds to PLL reference clock of 11.2896MHz. In this evaluation mode, the output clock from MCKO pin of the AK5701 is supplied to a divider (U3: 74VHC4040), EXBCLK and LRCK clocks are generated by the divider. Then “MCKO bit” in the AK5701 should be set to “1”. When an external clock is supplied through an RCA connector (J3: EXT/BCLK), select EXTCLK/BCLK on JP16 (XTI) and select EXTCLK/BCLK on JP17 (MCLK_SEL). JP14 (EXT1) and R20 should be properly selected in order too match the output impedance of the clock generator. JP16 XTI JP19 JP11 MCLK_SEL MKFS 5701- EXTCLK 4114- MCKO /BCLK MCKO MCKI EXTCLK /BCLK 256fs 512fs 1024fs MCKO b) Set up jumper pins of BCLK clock EXT JP17 JP12 BCLK_SEL BCLK EXT EXTBCLK/ BCLK/ BCLK DIT 64fs 32fs 16fs DIT c) Set up jumper pins of LRCK clock JP18 JP13 LRCK_SEL LRCK EXT EXT EXTLRCK/ LRCK/ LRCK DIT 2fs 1fs DIT <KM076903> 2005/04 -4- ASAHI KASEI [AKD5701-A] (2-a) In the case of using AK4114. *This mode is BCLK=64fs, LRCK=1fs only. Set up jumper pins of MCKI clock *In the case of using X1, JP16 should be open. JP16 JP19 XTI MCLK_SEL 5701 EXT 4114 JP11 MKFS EXT 256fs 512fs 1024fs MCKO Set up jumper pins of BCLK clock JP18 LRCK_SEL EXT EXT JP13 LRCK EXTLRCK/ LRCK/ LRCK DIT 2fs 1fs DIT Set up jumper pins of LRCK clock EXT BCLK JP17 JP12 BCLK_SEL BCLK 64fs 32fs 16fs EXT EXTBCLK/ BCLK/ DIT DIT <KM076903> 2005/04 -5- ASAHI KASEI [AKD5701-A] (3) Evaluation of PLL, Slave Mode (PLL Reference CLOCK: BCLK or LRCK pin) *Connect PORT4 (DSP2) with DSP. Figure below shows PORT4 pin assign. PORT4 MCKI GND EXBCLK GND EXLRCK NC EXSDTI NC VD SDTO a) Set up jumper pins of MCKI clock JP16 XTI JP19 MCLK_SEL 5701- EXTCLK 4114- MCKO /BCLK MCKO MCKI EXTCLK /BCLK b) Set up jumper pins of BCLK clock When an external clock is supplied through a RCA connector J3 (EXT/BCLK), J4 (EXT/LRCK), JP14 (EXT1) and R20, JP15 (EXT2) and R21 should be properly selected in order to much the output impedance of the clock generator. JP17 JP12 BCLK_SEL BCLK EXT BCLK 64fs 32fs 16fs EXT EXTBCLK/ BCLK/ DIT DIT c) Set up jumper pins of LRCK clock JP18 JP13 LRCK_SEL LRCK EXT EXT 2fs 1fs EXTLRCK/ LRCK/ LRCK DIT DIT <KM076903> 2005/04 -6- ASAHI KASEI [AKD5701-A] (4) Evaluation of EXT, Slave Mode *Connect PORT4 (DSP2) with DSP. Figure below shows PORT4 pin assign. PORT4 MCKI GND EXBCLK GND EXLRCK NC EXSDTI NC VD SDTO a) Set up jumper pins of MCKI clock PORT4 (DSP2) is used. JP19 (MCKI_SEL) should be open. b) Set up jumper pins of BCLK clock JP17 JP12 BCLK_SEL BCLK 64fs 32fs 16fs EXT EXTBCLK/ BCLK/ EXT BCLK DIT DIT c) Set up jumper pins of LRCK clock JP18 JP13 LRCK_SEL LRCK EXT EXT 2fs 1fs EXTLRCK/ LRCK/ LRCK DIT DIT d) Set up jumper pins of DATA JP18 JP17 LRCK_SEL BCLK_SEL EXT EXT EXTLRCK/ LRCK/ LRCK DIT DIT EXT EXT EXTBCLK/ BCLK/ BCLK <KM076903> DIT DIT 2005/04 -7- ASAHI KASEI [AKD5701-A] (5) Slave & Bypass Mode * Connect PORT4 (DSP2) and PORT2 (DSP1) with DSP. Figure below shows PORT4 and PORT2 pin assign. PORT4 PORT2 MCKI GND MCKO GND EXBCLK GND BCLK GND EXLRCK NC LRCK NC EXSDTI NC SDTO NC VD SDTO VD NC a) Set up jumper pins of MCKI clock PORT4 (DSP2) is used. JP19 (MCKI_SEL) should be open. b) Set up jumper pins of BCLK clock JP17 JP12 BCLK_SEL BCLK EXT EXTBCLK/ BCLK/ EXT BCLK DIT 64fs 32fs 16fs DIT c) Set up jumper pins of LRCK clock JP18 JP13 LRCK_SEL LRCK EXT EXT 2fs 1fs EXTLRCK/ LRCK/ LRCK DIT DIT d) Set up jumper pins of DATA JP18 JP17 LRCK_SEL BCLK_SEL EXT EXT EXTLRCK/ LRCK/ LRCK DIT DIT EXT BCLK <KM076903> EXT EXTBCLK/ BCLK/ DIT DIT 2005/04 -8- ASAHI KASEI [AKD5701-A] (6) Bypass Mode * Connect PORT4 (DSP2) and PORT2 (DSP1) with DSP. Figure below shows PORT4 and PORT2 pin assign. PORT4 PORT2 MCKI GND MCKO GND EXBCLK GND BCLK GND EXLRCK NC LRCK NC EXSDTI NC SDTO NC VD SDTO VD NC a) Set up jumper pins of MCKI clock PORT4 (DSP2) is used. JP19 (MCKI_SEL) should be open. b) Set up jumper pins of BCLK clock JP17 JP12 BCLK_SEL BCLK EXT EXTBCLK/ BCLK/ EXT BCLK DIT 64fs 32fs 16fs DIT c) Set up jumper pins of LRCK clock JP18 JP13 LRCK_SEL LRCK EXT EXT 2fs 1fs EXTLRCK/ LRCK/ LRCK DIT DIT d) Set up jumper pins of DATA JP18 JP17 LRCK_SEL BCLK_SEL EXT EXT EXTLRCK/ LRCK/ LRCK DIT DIT EXT BCLK <KM076903> EXT EXTBCLK/ BCLK/ DIT DIT 2005/04 -9- ASAHI KASEI [AKD5701-A] DIP Switch set up [SW2] (MODE): Mode Setting of AK4114 ON is “H”, OFF is “L”. No. 1 2 3 4 Name DIF0 DIF1 OCKS0 OCKS1 ON (“H”) OFF (“L”) AK4114 Audio Format Setting See Table 2 Master Clock Frequency Select See Table 3 Table 1. Mode Setting Resistor for AK5701 M/S 0 0 1 1 Set up for AK4114 SW3 DIF1 DIF0 DIF1 DIF0 DAUX 1 0 0 0 24bit, Left justified Master 2 1 1 0 1 24bit, I S Master 1 0 1 0 24bit, Left justified Slave 1 1 1 1 24bit, I2S Slave Table 2. Setting for AK5701 and AK4114 Audio Interface Format No. 0 2 OCKS1 0 1 OCKS0 0 0 MCKO1 256fs 512fs X’tal 256fs 512fs Default Default Table 3. Master Clock Frequency Select for AK4114 (Stereo mode) Other jumper pins set up <KM076903> 2005/04 - 10 - ASAHI KASEI 1. JP1 (GND) OPEN SHORT [AKD5701-A] : Analog ground and Digital ground : Separated. : Common. (The connector “DGND” should be open.) <Default> 2. JP2 (AVDD_SEL) : AVDD of the AK5701 OPEN : AVDD is supplied from the regulator (“AVDD” jack should be open). < Default > SHORT : AVDD is supplied from “AVDD ” jack. 3. JP3 (DVDD_SEL) : DVDD of the AK5701 AVDD : DVDD is supplied from “AVDD”. < Default > DVDD : DVDD is supplied from “DVDD ” jack. 4. JP4 (CSP) H L : CSP signal Select (Hi or Low) : CSP= “Hi” : CSP= “Low”< Default > 5. JP5, JP6 (MPWR) : Connect to MPWR OPEN : No connect< Default > SHORT : Connect 6. JP7 (LVC_SEL) DVDD VD : Supply line selection of Logic block of LVC. : Logic block of LVC is supplied from “DVDD”. < Default > : Logic block of LVC is supplied from “VD ” jack. 7. JP20 (SDTO) OPEN SHORT : Select #4 pin of the PORT4 (DSP) : Input data for EXSDTI<Default> : Output data for SDTO of the PORT4 8. JP8 (CCLK) OPEN SHORT : CCLK select : No connect : CCLK connect <Default> <KM076903> 2005/04 - 11 - ASAHI KASEI [AKD5701-A] The function of the toggle SW [SW1] (DIT): Power control of AK4114. Keep “H” during normal operation. Keep “L” when AK4114 is not used. [SW3] (PDN): Power control of AK5701. Keep “H” during normal operation. Indication for LED [LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114. Serial Control The AK5701 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3 (CTRL) with PC by 10-wire flat cable packed with the AKD5701-A CSN Connect CCLK CDTI PC AKD5701-A 10 Wire Flat Cable 10pin Connector 10pin Header Figure 2. Connect of 10 wire flat cable <KM076903> 2005/04 - 12 - ASAHI KASEI [AKD5701-A] Analog Input / Output Circuits (1) Input Circuits a) LIN, RIN, MIC Input Circuit R38 (Open) J1 LIN JP9 LIN LIN1 LIN1 2 3 1 LIN2 MR-552LS LIN2 J5 4 6 3 MIC J2 RIN JP10 RIN RIN1 RIN1 2 3 1 RIN2 MR-552LS R39 (Open) RIN2 Figure 3. LIN, RIN, MIC Input Circuit (a-1) LIN1, RIN1 input JP10 RIN JP9 LIN LIN1 LIN2 RIN1 RIN2 (a-2) LIN2, RIN2 input JP9 JP10 RIN LIN LIN1 LIN2 RIN1 RIN2 ∗ AKM assumes no responsibility for the trouble when using the above circuit examples. <KM076903> 2005/04 - 13 - ASAHI KASEI [AKD5701-A] 2. Control Software Manual Set-up of evaluation board and control software 1. Set up the AKD5701-A according to previous term. 2. Connect IBM-AT compatible PC with AKD5701-A by 10-line type flat cable (packed with AKD5701-A). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled “AK5701 Evaluation Kit” into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of “akd5701-a.exe” to set up the control program. 5. Then please evaluate according to the follows. Operation flow Keep the following flow. 1. Set up the control program according to explanation above. 2. Click “Port Reset” button. 3. Click “Write default” button Explanation of each buttons 1. [Port Reset] : 2. [Write default] : 3. [All Write] : 4. [Function1] : 5. [Function2] : 6. [Function3] : 7. [Function4] : 8. [Function5]: 9. [SAVE] : 10. [OPEN] : 11. [Write] : Set up the USB interface board (AKDUSBIF-A) when using the board. Initialize the register of AK5701-A. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. Indication of data Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the part that is not defined in the datasheet. <KM076903> 2005/04 - 14 - ASAHI KASEI [AKD5701-A] Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes “H” or “1”. If not, “L” or “0”. If you want to write the input data to AK5701, click [OK] button. If not, click [Cancel] button. 2. [Function1 Dialog] : Dialog to write data by keyboard operation Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal. If you want to write the input data to AK5701, click [OK] button. If not, click [Cancel] button. 3. [Function2 Dialog] : Dialog to evaluate IVOL There are dialogs corresponding to register of 18h and 19h. Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK5701 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK5701, click [OK] button. If not, click [Cancel] button. <KM076903> 2005/04 - 15 - ASAHI KASEI [AKD5701-A] 4. [SAVE] and [OPEN] 4-1. [SAVE] All of current register setting values displayed on the main window are saved to the file. The extension of file name is “akr”. <Operation flow> (1) Click [SAVE] Button. (2) Set the file name and click [SAVE] Button. The extension of file name is “akr”. 4-2. [OPEN] The register setting values saved by [SAVE] are written to the AK5701. The file type is the same as [SAVE]. <Operation flow> (1) Click [OPEN] Button. (2) Select the file (*.akr) and Click [OPEN] Button. <KM076903> 2005/04 - 16 - ASAHI KASEI [AKD5701-A] 5. [Function3 Dialog] The sequence of register setting can be set and executed. (1) Click [F3] Button. The following is displayed. (2) Set the control sequence. Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused. (3) Click [START] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [SAVE] and [OPEN] button on the Function3 window. The extension of file name is “aks”. Figure 1. Window of [F3] <KM076903> 2005/04 - 17 - ASAHI KASEI [AKD5701-A] 6. [Function4 Dialog] The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed. When [F4] button is clicked, the window as shown in Figure 2 opens. Figure 2. [F4] window <KM076903> 2005/04 - 18 - ASAHI KASEI [AKD5701-A] 6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3]. The sequence file name is displayed as shown in Figure 3. ( In case that the selected sequence file name is “DAC_Stereo_ON.aks”) Figure 3. [F4] window(2) (2) Click [START] button, then the sequence is executed. 6-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of sequence file displayed on [Function4] window can be saved to the file. The file name is “*.ak4”. [OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded. 6-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect the change. <KM076903> 2005/04 - 19 - ASAHI KASEI [AKD5701-A] 7. [Function5 Dialog] The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to buttons and then executed. When [F5] button is clicked, the window as shown in Figure 4 opens. Figure 4. [F5] window 7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). The register setting file name is displayed as shown in Figure 5. (In case that the selected file name is “DAC_Output.akr”) (2) Click [WRITE] button, then the register setting is executed. <KM076903> 2005/04 - 20 - ASAHI KASEI [AKD5701-A] Figure 5. [F5] windows(2) 7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of register setting file displayed on [Function5] window can be saved to the file. The file name is “*.ak5”. [OPEN] : The name assign of register setting file(*.ak5) saved by [SAVE] is loaded. 7-3. Note (1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr) should be loaded again in order to reflect the change. <KM076903> 2005/04 - 21 - ASAHI KASEI [AKD5701-A] MEASUREMENT RESULTS 1.AK5701 Mode: EXT mode (Slave) [Measurement condition] • Measurement unit: AP2 (Audio Precision, System two, Cascade) • MCKI: 256fs • BCLK: 64fs • Bit: 16bit • Sampling Frequency: 44.1kHz • Measurement Frequency: 20 ∼ 20kHz • Power Supply: AVDD=DVDD=VD=3.0V • Temperature: Room • Input Frequency: 1kHz [Measurement Results] 1.ADC characteristics (MIC Gain = 0dB, IVOL=0dB, ALC = OFF, LIN/RIN Æ ADC) S/(N+D) (-0.5dBFS) D-Range (-60dBFS) S/N Result MGAIN=0dB LIN RIN 79.0dB 79.0dB 89.8dB 89.8dB 89.9dB 89.8dB MGAIN=+15dB LIN RIN 78.3dB 78.4dB 87.7dB 87.7dB 87.7dB 87.7dB 2.AK5701 Mode: PLL MASTER mode [Measurement condition] • Measurement unit: AP2 (Audio Precision, System two, Cascade) • MCKI: 12MHz • BCLK: 64fs • Bit: 16bit • Sampling Frequency: 44.0995kHz • Measurement Frequency: 20 ∼ 20kHz • Power Supply: AVDD=DVDD=VD=3.0V • Temperature: Room • Input Frequency: 1kHz [Measurement Results] ADC characteristics S/(N+D) (-0.5dBFS) D-Range (-60dBFS) S/N Result MGAIN=0dB LIN RIN 78.7dB 78.3dB 89.3dB 89.3dB 89.3dB 89.3dB <KM076903> MGAIN=+15dB LIN RIN 77.9dB 77.5dB 87.4dB 87.3dB 87.4dB 87.3dB 2005/04 - 22 - ASAHI KASEI [AKD5701-A] 3.Plot data [Gain = 0dB] AKM AK5701 THD+N vs Input Level (fin=1kHz, GAIN=0dB) -60 -64 -68 -72 -76 d B F S -80 -84 -88 -92 -96 -100 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dBr Figure 1. THD+N vs. Input Level AKM AK5701 THD+N vs Frequency (fin=1kHz, GAIN=0dB) -60 -64 -68 -72 -76 d B F S -80 -84 -88 -92 -96 -100 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 2. THD+N vs. Input Frequency <KM076903> 2005/04 - 23 - ASAHI KASEI [AKD5701-A] AKM AK5701 Linearity (fin=1kHz, GAIN=0dB) +0 TT T T T -12 -24 -36 -48 d B F S -60 -72 -84 -96 -108 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBr Figure 3. Linearity AKM AK5701 Freqency Responce (fin=1kHz, GAIN=0dB) +0 -0.2 -0.4 -0.6 -0.8 d B F S -1 -1.2 -1.4 -1.6 -1.8 -2 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 4. Frequency Response <KM076903> 2005/04 - 24 - ASAHI KASEI [AKD5701-A] AKM AK5701 Crosstalk (fin=1kHz, GAIN=0dB) -60 T T TT T T TT T T T T T T T T T T T -68 -76 -84 -92 d B -100 -108 -116 -124 -132 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 5. Crosstalk AKM AK5701 FFT S/(N+D) -0.5dBFS (fin=1kHz, GAIN=0dB) -0 -16 -32 -48 -64 d B F S -80 -96 -112 -128 -144 -160 20 50 100 200 500 1k 2k Hz Figure 6. FFT Plot <KM076903> 2005/04 - 25 - ASAHI KASEI [AKD5701-A] AKM AK5701 FFT DR (fin=1kHz, GAIN=0dB) -0 -16 -32 -48 -64 d B F S -80 -96 -112 -128 -144 -160 20 50 100 200 500 1k 2k 5k 10k 20k 2k 5k 10k 20k Hz Figure 7. FFT Plot AKM AK5701 FFT S/N MGAIN=0dB +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k Hz Figure 8. FFT Plot <KM076903> 2005/04 - 26 - ASAHI KASEI [AKD5701-A] [Gain = +15dB] AKM AK5701 THD+N vs Input Level MGAIN=+15dB -60 -64 -68 -72 -76 d B F S -80 -84 -88 -92 -96 -100 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dBr Figure 9. THD+N vs. Input Level AKM AK5701 THD+N vs Freqency (fin=1kHz, GAIN=+15dB) -60 -64 -68 -72 -76 d B F S -80 -84 -88 -92 -96 -100 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 10. THD+N vs. Input Frequency <KM076903> 2005/04 - 27 - ASAHI KASEI [AKD5701-A] AKM AK5701 Lineearity (fin=1kHz, GAIN=+15dB) +0 T TT -12 -24 -36 -48 d B F S -60 -72 -84 -96 -108 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBr Figure 11. Linearity AKM AK5701 Freqency Responce (fin=1kHz, GAIN=+15dB) +0 -0.2 -0.4 -0.6 -0.8 d B F S -1 -1.2 -1.4 -1.6 -1.8 -2 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 12.Freqency Response <KM076903> 2005/04 - 28 - ASAHI KASEI [AKD5701-A] AKM AK5701 Crosstalk (fin=1kHz, GAIN=+15dB) -60 T T T TT T T T T T T T T T T T T T T -68 -76 -84 -92 d B -100 -108 -116 -124 -132 -140 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure 13.Crosstalk AKM AK5701 FFT S/(N+D) -0.5dBFS MGAIN=+15dB +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k Hz Figure 14. FFT Plot <KM076903> 2005/04 - 29 - ASAHI KASEI [AKD5701-A] AKM AK5701 FFT DR MGAIN=+15dB +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k 2k 5k 10k 20k 2k 5k 10k 20k Hz Figure 15. FFT Plot AKM AK5701 FFT S/N MGAIN=+15dB +0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k Hz Figure 16. FFT Plot <KM076903> 2005/04 - 30 - ASAHI KASEI [AKD5701-A] Revision History Date 05/04/25 Manual Revision KM076903 Board Revision 0 Reason Contents First Edition IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. <KM076903> 2005/04 - 31 - A B C D E JP1 GND C3 + 47u REG JP2 AVDD_SEL AVDD C2 0.1u E BCLK 1 OUT 2 IN C1 0.1u DVDD GND REG_IN T1 TA48033F E AVDD1 L1 T45_BK T45_BK REG_IN C6 7 R5 9 R8 1 VCOM AVSS 3 AVDD 4 23 CSP RIN1 22 1 LIN2 21 1 RIN2 20 1 AK5701 MCKO EXSDTI MPWR R40 51 LVC R12 51 R13 51 CSN R14 51 R15 51 VD LIN1 22 RIN1 21 LIN2 20 RIN2 C C17 2 1u 19 JP5 MPWR 19 JP6 MPWR 24pin_4 R11 2.2k 18 JP7 DVDD LVC_SEL 23 C16 2 R10 2.2k PDN EXLRCK 13 12 C15 2 1u 51 17 R9 24 2 1u 12 24pin_2 CN4 C14 1u 51 11 5701_EXLRCK 1 LIN1 51 10 11 C13 4.7n SDTO CCLK 5701_EXSDTI R6 10 R4 24 10k 16 MCKO C11 (open) VCOC CDTI L 0.1u 51 9 C C10 0.1u + 8 C9 LRCK MCKI JP4 CSP D 51 8 H 2.2u + SDTO R7 1 10u + 7 2 + LRCK 6 51 DVDD R3 CN2 DVSS DVDD 14 (short) BCLK 1 + EXBCLK 47u DVDD 2 2 C12 U1 5 0.1u L2 1 C8 JP3 AVDD DVDD_SEL 15 R1 5.1 DVDD1 10u R2 51 VD1 + AVDD DVDD1 C7 2 2 1 + D 1 + C5 2 AVDD1 DGND1 1 AGND1 T45_O 1 VD1 T45_O 1 DVDD1 T45_O 1 AVDD1 T45_R 1 REG1 1 1 2 3 4 CN1 24pin_1 AVDD 6 47u 2 2 + (short) 5 1 1 C4 R16 51 R17 (open) R18 (open) B B 17 18 CSN PDN 15 CDTI 16 14 1 VD 5701_MCKI 47u 24pin_3 + 2 C18 CN3 2 13 L3 (short) 1 5701_EXBCLK VD1 JP8 CCLK A A CCLK Title Size A3 Date: A B C D AKD5701-A Document Number Rev AK5701 Tuesday, December 14, 2004 Sheet E 0 1 of 5 A B C D E R38 (Open) E E JP9 LIN LIN1 J1 LIN LIN1 2 3 1 LIN2 MR-552LS J5 MIC LIN2 6 4 3 D D JP10 RIN RIN1 J2 RIN RIN1 2 3 1 RIN2 MR-552LS R39 (Open) RIN2 C C B B A A Title Size A B C D AKD5701-A Document Number A3 Input Date: Tuesday, December 14, 2004 Rev 0 Sheet E 2 of 5 A B C D E for 74AC74,74VHC4040,74HC14 for 74LVC07ANS LVC C19 0.1u E C20 0.1u C21 0.1u 2 1 VD + C23 47u C22 0.1u E D D EXT_MCLK VD Q 5 12 11 1 CLK 6 74AC74 C D PR Q U3B Q CL 3 MCKI D Q 9 256fs 512fs 1024fs MCKO JP11 MKFS U2 CLK 13 2 PR 4 U3A CL R19 short 10 VD 8 74AC74 10 CLK 11 RST Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 9 7 6 5 3 2 4 13 12 14 15 1 JP12 64fs 32fs 16fs EXT_BCLK BLCK_SEL C JP13 2fs 1fs EXT_LRCK 74VHC4040 LRCK_SEL MCKO J3 EXT/BCLK 2 3 1 MR-552LS AVSS EXTCLK/BCLK R20 51 JP14 EXT1 B B J4 EXT/LRCK 2 3 1 MR-552LS EXTCLK/LRCK R21 51 JP15 EXT2 A A Title Size A3 Date: A B C D AKD5701-A Document Number Rev CLOCK Friday, January 28, 2005 Sheet E 0 3 of 5 A B C D E R22 10k A E K VD 4 74HC14 + VD E U4B 1 3 74HC14 L C26 0.1u H SW1 DIT 2 C25 0.1u 1 2 1 3 U4A C24 10u 2 D1 HSU119 1 MODE2 38 37 INT1 R VCOM AVDD 40 41 AVSS 42 RX0 43 NC 44 RX1 45 TEST1 46 47 NC RX2 8 7 6 5 RX3 1 2 3 4 48 U5 SW2 DIF0 DIF1 OCKS0 OCKS1 D R23 18k 39 C27 0.47u VD D R24 1k U4C IPS0 INT0 36 5 6 LED1 ERF K A VD 74HC14 2 NC OCKS0 35 OCKS0 3 DIF0 OCKS1 34 OCKS1 4 TEST2 CM1 33 5 DIF1 CM0 32 6 NC PDN 31 RP1 5 4 3 2 1 OCKS0 OCKS1 47k AK4114 VD C JP16 XTI EXTCLK/BCLK 7 DIF2 XTI 30 8 IPS1 XTO 29 9 P/SN DAUX 28 10 XTL0 MCKO2 27 11 XTL1 BICK 26 12 VIN SDTO 25 5701_MCKO C28(open) 1 C C29 (open) 2 X1 11.2896MHz DAUX 4114_BICK LRCK 24 MCKO1 4114_LRCK IN VCC GND 23 1 2 C33 10u VD PORT1 A 4114_MCKO 2 C32 10u VD 22 C31 0.1u + + C30 0.1u 1 DVSS DVDD 21 20 VOUT UOUT 19 COUT 18 BOUT 17 TX1 16 15 DVSS 14 13 TX0 B TVDD B 3 2 1 VD C34 0.1u TOTX141 A Title Size A3 Date: A B C D AKD5701-A Document Number Rev DIT Thursday, December 02, 2004 0 Sheet E 4 of 5 A B C D E VD U6 R25 R26 R27 R28 330 330 330 330 E 11 Y8 A8 9 5701_EXLRCK 12 Y7 A7 8 5701_MCKI 13 Y6 A6 7 5701_EXSDTI 14 Y5 A5 6 15 Y4 A4 5 CDTI 16 Y3 A3 4 CCLK 17 A2 3 CSN 18 A1 2 5701_EXBCLK U7A 1 MCKO 2 5701_MCKO 74LVC07ANS U7B 3 BCLK 4 74LVC07ANS U7C EXSDTI 5 LRCK PDN E 9 SDTO PORT2 6 MCKI BCLK LRCK SDTO VD 74LVC07ANS U7D 8 1 2 3 4 5 74LVC07ANS 10 9 8 7 6 DSP1 D D R29 Y2 VD 10k Y1 10 GND G2 19 20 VCC G1 1 JP17 BCLK-DIT EXBCLK-DIT EXT EXTBCLK 4114_BICK EXT_BCLK EXTCLK/BCLK BCLK_SEL C35 0.1u JP18 4114_LRCK LRCK-DIT EXLRCK-DIT EXTLRCLK EXT 74LVC541 EXTCLK/LRCK EXT_LRCK LRCK_SEL C C 2 1 LVC + C36 47u DAUX R30 R31 R33 VD 10k 10k 10k R32 R35 R34 470 470 470 4114_MCKO EXT_MCLK PORT3 1 2 3 4 5 B 10 9 8 7 6 MCKI EXBCLK EXLRCK EXSDTI VD MCKI EXTCLK/BCLK CSN CCLK CDTI JP19 MCKI_SEL PORT4 1 2 3 4 5 10 9 8 7 6 DSP2 SDTO B R36 CTRL VD 10k VD JP20 K EXSDTI A D2 HSU119 SDTO R37 10k U4D 9 74HC14 U4E 11 10 74HC14 1 H 3 L 8 SW3 PDN C37 0.1u U7E 11 10 A 2 A 74LVC07ANS U4F 13 U7F 12 13 12 74LVC07ANS 74HC14 Title Size A3 Date: A B C D AKD5701-A Document Number Rev LOGIC Friday, December 17, 2004 0 Sheet E 5 of 5