LAPIS FEDL610Q304-01 8-bit microcontroller with voice output function Datasheet

FEDL610Q304-01
Issue Date: Jul 16, 2014
ML610Q304
8-bit Microcontroller with Voice Output Function
■GENERAL DESCRIPTION
Equipped with a 8-bit CPU nX-U8/100, the ML610Q304 is a high-performance 8-bit CMOS microcontroller that integrates a
wide variety of peripherals such as timer, synchronous serial port, and voice output function. The nX-U8/100 CPU is capable
of executing instructions efficiently on a one-instruction-per-clock-pulse basis through parallel processing by the 3-stage
pipelined architecture. The ML610Q304 is also equipped with a flash memory that has achieved low voltage and low power
consumption (at read) equivalent to mask ROMs, so it is best suited to battery-driven applications such as alarm and portable
devices. In addition, it has an on-chip debugging function, which allows software debugging/rewriting with the LSI mounted on
the board.
■FEATURES
•CPU
− 8-bit RISC CPU (CPU name: nX-U8/100)
− Instruction system: 16-bit instructions
− Instruction set:
Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
− On-Chip debug function
− Minimum instruction execution time
Approx 30.5 µs (@32.768kHz system clock)
Approx 0.244 µs (@4.096 MHz system clock)@VDD=2.0 to 5.5V
Approx 0.122 µs (@8.192 MHz system clock)@VDD=2.2 to 5.5V
•Internal memory
− Has 96-Kbyte flash ROM(48K × 16-bits) built in. (1 K byte of test domain that it cannot be used is included)
− Has 2-Kbyte flash ROM built in. (area in which self rewriting is possible (512byte × 4))
− Internal 1Kbyte RAM (1K × 8 bits)
•Interrupt controller
− 2 non-maskable interrupt sources (Internal source: 1, External source: 1)
− 24 maskable interrupt sources (Internal source: 16, External source: 8)
•Time base counter
− Low-speed time base counter × 1 channel
− High-speed time base counter × 1 channel
•Watchdog timer
− Generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)
•Timers
− 8 bits × 4ch (16-bit configuration available)
•Voice output function
− Voice synthesis method: 4-bit ADPCM2 / non-linear PCM / straight 8-bit PCM / straight 16-bit PCM
− Sampling frequency: 8/16/32 kHz; 10.7/21.3 kHz; 6.4/12.8/25.6 kHz
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FEDL610Q304-01
ML610Q304
•Successive approximation type A/D converter
− 10-bit A/D converter
− Input: 3ch (ch0-2:External input)
− Conversion time: 24.4 µs per channel at 4.096MHz VDD≧2.2V
− Conversion time: 12.2 µs per channel at 8.192MHz VDD≧2.5V
•Synchronous serial port
− 2ch
− Master/slave selectable
− LSB first/MSB first selectable
− 8-bit length/16-bit length selectable
•UART
− Half-duplex × 1ch
− TXD/RXD
− Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
− Positive logic/negative logic selectable
− Built-in baud rate generator
•I2C bus interface
− Slave function and Master function
− Fast mode (400 kbps), standard mode (100 kbps)
•General-purpose ports
− Input-only port × 1ch
− Output-only port × 3ch (including secondary functions)
− Input/output × 11ch (including secondary functions)(P40 to P42 uses also as an A/D converter input port.)
•Speaker amplifier(D-class) output power
− 1.0W(at 5.0V)/0.45W(at 3.0V)
− Disconnection detection circuit
− Speaker pin short detection circuit
− PLL oscillation stop detection reset
•Reset
− Reset through the RESET_N pin
− Power-on reset generation when powered on
− Reset by the watchdog timer (WDT) overflow
− PLL oscillation stop detection reset
•Clock
− Low-speed clock
Built-in RC oscillation (32.768 kHz)
− High-speed clock
Built-in PLL oscillation (4.096MHz,8.192MHz,etc)
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FEDL610Q304-01
ML610Q304
•Power management
− STOP mode: Stop of oscillation (Operations of CPU and peripheral circuits are stopped.)
− HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).
− Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the
oscillation clock)
− Block control function: Operation of an intact functional block circuit is powerd down. (register reset and clock stop)
•Shipment
− 28-pin QFN
ML610Q304-xxxGD (blank product: ML610Q304-NNNGD)
xxx: ROM code number
•Guaranteed operating range
− Operating temperature: −40°C to 85°C
− Operating voltage: VDD = 2.0V to 5.5V, SPVDD = 2.0V to 5.5V
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FEDL610Q304-01
ML610Q304
■BLOCK DIAGRAM
Figure 1 is a block diagram of the ML610Q304.
CPU (nX-U8/100)
EPSW1～3
GREG
0～15
PSW
Timing
Controller
On-Chip
ICE
ALU
ELR1～3
ECSR1～3
LR
DSR/CSR
EA
PC
SP
Instruction
Decoder
VDD
VSS
Instruction
Register
Data-bus
Program
Memory
（Flash）
96Kbyte
BUS
Controller
INT
2
SSIO
RESET_N
TEST
LSCLK*
OUTCLK*
RESET &
TEST
Interrupt
Controller
INT
4
VDDL
INT
4
POWER
VOICECNT
SCK1*
SIN1*
SOUT1*
RAM
1KByte
OSC
TBC
8bit Timer
INT
1
INT
2
WDT
SCK0*
SIN0*
SOUT0*
INT
2
I2C
Master/Slave
INT
1
UART
INT
9
SDA*
SCL*
RXD0*
TXD0*
NMI
GPIO
P20 to P22
P40 to P42*1
P80 to P87
VREF
AIN0 to AIN2*1
SPVDD
SPVSS
INT
1
D-class
Speaker
50
to P57
Amplifier
10bit-ADC
SPP
SPM
* : Secondary or tertiary function
*1: I/O port or A/D converter input terminal
Figure 1-1
Block Diagram of ML610Q304
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FEDL610Q304-01
ML610Q304
■PIN CONFIGURATION
VDD
VDDL
VSS
P85/EXI5/SCK1
P84/EXI4/SIN1
SPVDD
SPVSS
21
20
19
18
17
16
15
● ML610Q304 QFN package product (Top View)
11
RESET_N
P86/EXI6/RXD0/SOUT1
26
10
P83/EXI3
P87/EXI7/TXD0
27
9
P82/EXI2/SOUT0
NMI 28
8
TEST0
7
25
TEST1_N
VREF
6
SPP
P81/EXI1/SCL/SCK0
12
5
24
P80/EXI0/SDA/SIN0
P40/AIN0
4
SPM
P20/LED0
13
3
23
VSS
P41/AIN1
2
(NC)
P21/LED1
14
1
22
P22/LED2
P42/AIN2
(NC): No Connection
Figure 1-2
Pin Layout of ML610Q304 Package
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FEDL610Q304-01
ML610Q304
■LIST OF PINS
In the I/O column, “—” denotes an input pin (for primary functions only), “I” an input pin, “O” an output pin, and “I/O” an
input/output pin.
Primary function
PAD
No
Pin name
I/O
12
SPP
O
13
SPM
O
15
SPVSS
⎯
16
SPVDD
⎯
3
VSS
⎯
19
VSS
⎯
20
VDDL
⎯
21
VDD
⎯
25
VREF
⎯
11
RESET_N
I
8
TEST0
I/O
7
TEST1_N
I
28
NMI
I
4
P20/LED0
2
Secondary function
Tertiary function
Description
Positive output pin of
the built-in speaker
amplifier
Negative output pin of
the built-in speaker
amplifier
Negative power
supply pin for built-in
speaker amplifier
Positive power supply
pin for built-in speaker
amplifier
Negative power
supply pin
Negative power
supply pin
Power supply for
internal logic
(internally generated)
Positive power supply
pin
Reference power
supply pin for
successive-approxima
tion type
ADC
Reset input pin
Input/output pin for
testing
Input pin for testing
Input port,
non-maskable
interrupt
Pin name
I/O
Description
Pin name
I/O
Description
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
O
Output port / LED port
LSCLK
O
⎯
⎯
⎯
P21/LED1
O
Output port / LED port
OUTCLK
O
⎯
⎯
⎯
1
P22/LED2
O
⎯
⎯
⎯
⎯
⎯
24
P40/AIN0
I/O
Output port / LED port
Input port/Output port
/Successive-approxi
mation type ADC
input
Input port/Output port
/Successive-approxi
mation type ADC
input
Input port/Output port
/Successive-approxi
mation type ADC
input
Low-speed
clock output
high-speed
clock output
⎯
⎯
⎯
⎯
SIN0
I
SSIO0 data
input
23
P41/AIN1
I/O
22
P42/AIN2
I/O
5
P80/EXI0
I/O
Input port/Output port /
External interrupt
⎯
⎯
⎯
SCK0
I/O
SSIO0
synchronous
clock
input/output
⎯
⎯
⎯
SOUT0
O
SSIO0 data
output
I/O
I2C
synchronous
data
input/output
SIN0
I
SSIO0 data
input
SDA
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FEDL610Q304-01
ML610Q304
Primary function
Secondary function
PAD
No
Pin name
I/O
Description
Pin name
I/O
6
P81/EXI1
I/O
Input port/Output port /
External interrupt
SCL
I/O
9
P82/EXI2
I/O
⎯
10
P83/EXI3
I/O
⎯
17
P84/EXI4
I/O
18
P85/EXI5
I/O
26
P86/EXI6
I/O
27
P87/EXI7
I/O
Input port/Output port /
External interrupt
Input port/Output port /
External interrupt
Input port/Output port /
External interrupt
Input port/Output port /
External interrupt
Input port/Output port /
External interrupt
Input port/Output port /
External interrupt
Tertiary function
Description
I2C
synchronous
clock
input/output
Pin name
I/O
SCK0
I/O
⎯
⎯
SOUT0
O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
SIN1
I
⎯
⎯
⎯
SCK1
I/O
RXD0
I
SOUT1
O
TXD0
O
⎯
⎯
UART0 data
input
UART0 data
output
Description
SSIO0
synchronous
clock
input/output
SSIO0 data
output
⎯
SSIO1 data
input
SSIO1
synchronous
clock
input/output
SSIO1 data
output
⎯
Note:
The function which is not chosen is lost when either a secondary function or a tertiary function is chosen. However, when
using it as an input, read-out of an input data is possible at a PnD
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FEDL610Q304-01
ML610Q304
■PIN DESCRIPTION
In the I/O column, “—” denotes an input pin, “I” an input pin, “O” an output pin, and “I/O” an input/output pin.
Pin name
I/O
Description
—
—
—
—
—
—
Negative power supply pin
Positive power supply pin
Positive power supply pin for internal logic (internally generated)
Negative power supply pin for built-in speaker amplifier
Positive power supply pin for built-in speaker amplifier
Primary/
Secondary/
Tertiary
Logic
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Negative
—
Negative
Secondary
—
Secondary
—
Primary
Positive
Primary
Positive
Primary
Positive
Power supply
VSS
VDD
VDDL
SPVSS
SPVDD
VREF
Reference power supply pin for successive-approximation type ADC
Test
TEST0
TEST1_N
I/O Input/output pin for testing. Has a pull-down resistor built in.
I Input pin for testing. Has a pull-up resistor built in.
Positive
System
RESET_N
I
LSCLK
O
OUTCLK
O
Reset input pin. When this pin is set to a “L” level, the device is
placed in system reset mode and the internal circuit is initialized.
If after that this pin is set to a “H” level, program execution starts.
This pin has a pull-up resistor built in.
Low-speed clock output. This function is allocated to the secondary
function of the P20 pin.
High-speed clock output. This function is allocated to the secondary
function of the P21 pin.
General-purpose Output port
General-purpose output ports.
P20 to P22
O Provided with a secondary function. Cannot be used as ports if
their secondary function is used.
General-purpose Input/output port
General-purpose input/output ports.
P40 to P42
I/O Provided with a tertiary function. Cannot be used as ports if their
tertiary function is used.
General-purpose input/output ports.
Provided with a secondary function or a tertiary function. Cannot
P80 to P87
I/O
be used as ports if their secondary function or tertiary function is
used.
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FEDL610Q304-01
ML610Q304
Pin name
I/O
Description
Primary/
Secondary/
Tertiary
Logic
Tertiary
Positive
Tertiary
—
Tertiary
Positive
Tertiary
Positive
Tertiary
—
Tertiary
Positive
Secondary
Positive
Secondary
Positive
Secondary
Positive
Secondary
Positive
Primary
Positive/
Negative
Primary
Positive/
Negative
Primary
Positive/
Negative
—
—
—
—
Primary
Positive/
Negative
Synchronous serial (SSIO)
SIN0
SCK0
SOUT0
SIN1
SCK1
SOUT1
Synchronous serial data input pin. Allocated to the tertiary
function of the P40 pin and P80 pin.
Synchronous serial clock input/output pin. Allocated to the
I/O
tertiary function of the P41 pin and P81 pin.
Synchronous serial data output pin. Allocated to the tertiary
O
function of the P42 pin and P82 pin.
Synchronous serial data input pin. Allocated to the tertiary
I
function of the P84 pin.
Synchronous serial clock input/output pin. Allocated to the
I/O
tertiary function of the P85 pin.
Synchronous serial data output pin. Allocated to the tertiary
O
function of the P86 pin.
I
2
I C bus interface
2
SDA
SCL
I C data input/output pin. This pin is used as the secondary
function of the P80 pin. This pin has an NMOS open drain
I/O
2
output. When using this pin as a function of the I C, externally
connect a pull-up resistor.
2
I C clock output pin. This pin is used as the secondary function
of the P81 pin. This pin has an NMOS open drain output. When
I/O
2
using this pin as a function of the I C, externally connect a
pull-up resistor.
UART
TXD0
O
RXD0
I
UART0 data output pin. Allocated to the secondary function of
the P87 pin.
UART0 data input pin. Allocated to the the secondary function of
the P86 pin.
External interrupt
NMI
I
EXI0 to 7
I
External non-maskable interrupt input pin. The interrupt occurs
on both the rising and falling edges.
External maskable interrupt input pins. It is possible, for each bit,
to specify whether the interrupt is enabled and select the
interrupt edge by software. Allocated to the primary function of
the P80 to P87 pins.
LED drive
LED0 to 2
O
Pins for LED driving. Allocated to the primary function of the P20
to P22 pins.
Voice output function
SPP
O Positive output pin of the internal speaker amplifier.
SPM
O Negative output pin of the internal speaker amplifier.
Successive-approximation type A/D converter
Analog inputs to Ch0 to Ch2 of the successive-approximation
AIN0 to 2
I type A/D converter. Allocated to the primary function of the P40
to P42 pins.
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FEDL610Q304-01
ML610Q304
■TERMINATION OF UNUSED PINS
●How to Terminate Unused Pins
Pin
RESET_N
TEST0
TEST1_N
VREF
P40 to P42 (AIN0 to AIN2)
SPVDD
SPVSS
SPP
SPM
P20 to P22
P80 to P87
NMI
Recommended pin termination
Open
Open
Open
Connect to VDD
Open
Connect to VDD
Connect to VSS
Open
Open
Open
Open
Open
Note:
For unused input ports or unused input/output ports, if the corresponding pins are configured as high-impedance inputs and left
open, the supply current may become excessively large. Therefore, it is recommended to configure those pins as either inputs
with a pull-down resistor/pull-up resistor or outputs.
10/28
FEDL610Q304-01
ML610Q304
■ELECTRICAL CHARACTERISTICS
●Absolute Maximum Ratings
(VSS= SPVSS=0V)
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage 1
VDD
Ta=25°C
−0.3 to +7.0
V
Power supply voltage 2
SPVDD
Ta=25°C
−0.3 to +7.0
V
Power supply voltage 3
VDDL
Ta=25°C
−0.3 to +3.6
V
Reference supply voltage
VREF
Ta=25°C
−0.3 to VDD+0.3
V
VIN
Ta=25°C
−0.3 to VDD+0.3
V
Output voltage
VOUT
Ta=25°C
−0.3 to VDD+0.3
V
Output current 1
IOUT1
Port 4,8, Ta=25°C
−12 to +11
mA
Output current 2
Input voltage
IOUT2
Port 2, Ta=25°C
−12 to +20
mA
Power dissipation
PD
Ta=25°C
1.0
W
Storage temperature
TSTG
―
−55 to +150
°C
●Recommended Operating Conditions
(VSS= SPVSS=0V)
Parameter
Operating temperature
Operating voltage
Reference supply voltage
Operating frequency (CPU)
Capacitor externally connected to
VDDL pin
Symbol
Condition
Range
Unit
°C
TOP
―
−40 to +85
VDD
―
2.0 to 5.5
SPVDD
―
2.0 to 5.5
VREF
―
2.2 to VDD
V
fOP
VDD = 2.0 to 5.5V
VDD = 2.2 to 5.5V
27k to 4.2M
4.2M to 8.4M
Hz
CL
―
10±30%
µF
V
11/28
FEDL610Q304-01
ML610Q304
●Operating Conditions of Flash Memory
Parameter
Symbol
Operating temperature
TOP
Operating voltage
VDD
CEPD
CEPP
YDR
Maximum rewrite count
Write cycles
Condition
At write/erase
(Data flash area)
At write/erase
(Program code area)
At write/erase
Data flash area(512Byte x 4)
Program code area
―
(VSS= SPVSS=0V)
Unit
Range
-40 to +85
°C
0 to +40
2.2 to 5.5
6,000
100
10
V
cycles
years
●DC Characteristics (1 of 5)
(VDD= 2.0 to 5.5V, SPVDD=2.0 to 5.5V, VSS= SPVSS=0V, Ta=−40 to +85°C, unless otherwise specified) (1/5)
Measuring
Rating
Parameter
Symbol
Condition
Unit
circuit
Min.
Typ.
Max.
High-speed oscillation start time
―
―
1.0
3.0
ms
TXTH
Typ
Typ
Ta = −10 to +50°C
-1.5%
+1.5%
Built-in RC oscillation frequency
kHz
32.768
fLCR
Typ
Typ
Ta = −40 to +85°C
1
+3.0%
-3.0%
Typ
Typ
4.098
Ta = −10 to +50°C
-1.5%
+1.5%
Source oscillation frequency
MHz
or
fHPLL
Typ
Typ
8.192
Ta = −40 to +85°C
+3.0%
-3.0%
●DC Characteristics (2 of 5)
(VDD= 2.0 to 5.5V, SPVDD=2.0 to 5.5V, VSS= SPVSS=0V, Ta=−40 to +85°C, unless otherwise specified) (2/5)
Rating
Symbol
Condition
Unit
Parameter
Min.
Typ.
Max.
SPM, SPP output load
resistance
RLSP
―
8
—
—
Ω
PSPO1
SPVDD=3.0V, f=1kHz
RSPO=8Ω, THD≥10%
—
0.45
—
W
PSPO2
SPVDD=5.0V, f=1kHz
RSPO=8Ω, THD≥10%
—
1.0
—
W
Speaker amp output power
12/28
FEDL610Q304-01
ML610Q304
●DC Characteristics (3 of 5)
Parameter
Supply current 1
Supply current 2
Supply current 3
Supply current 4
Supply current 5
(VDD= 2.0 to 5.5V, SPVDD=2.0 to 5.5V, VSS= SPVSS=0V, Ta=−40 to +85°C, unless otherwise specified) (3/5)
Rating
Measuring
Symbol
Condition
Unit
circuit
Min.
Typ.
Max.
CPU: In STOP state.
Ta≦+50°C
―
0.5
3.0
high-speed oscillation:
IDD1
Ta≦+85°C
―
0.5
8.0
stopped
IDD2
IDD3
IDD4
IDD5
CPU: In HALT state
Ta≦+50°C
(LTBC,WDT: Operating)
High-speed oscillation:
Ta≦+85°C
Stopped
1
CPU: Running at 32.768 kHz*
High-speed oscillation: Stopped
VDD=SPVDD=
3.0V
CPU: Running at 4.096MHz
CR oscillating mode
VDD=SPVDD=
5.0V
VDD=SPVDD=
3.0V
CPU: Running at 8.192MHz
CR oscillating mode
VDD=SPVDD=
5.0V
CPU: Running at 4.096MHz
CR oscillating mode
During voice playback of
1KHz,0db,SIN-wave (no
output load)
CPU: Running at 8.192MHz
CR oscillating mode
During voice playback of
1KHz,0db,SIN-wave (no
output load)
―
2.7
5.0
―
2.7
10
―
20
30
―
3.0
5.0
―
3.0
5.0
―
4.0
6.0
―
4.0
6.0
VDD=SPVDD=
3.0V
―
4.0
7.0
VDD=SPVDD=
5.0V
―
6.0
10
VDD=SPVDD=
3.0V
―
5.0
8.0
―
7.0
11
VDD=SPVDD=
5.0V
*1: Case when the CPU operating rate is 100% (no HALT state).
µA
1
mA
13/28
FEDL610Q304-01
ML610Q304
●DC Characteristics (4 of 5)
Parameter
Output voltage 1
(P20 to P22)
(P40 to P42)
(P80 to P87)
Output voltage 2
(P20 to P22)
Output voltage 3
(P80 to P81)
Output leakage
(P20 to P22)
(P40 to P42)
(P80 to P87)
Input current 1
(RESET_N)
(TEST1_N)
Input current 2
(NMI)
(P40 to P42)
(P80 to P87)
Input current 3
(TEST0)
(VDD= 2.0 to 5.5V, SPVDD=2.0 to 5.5V, VSS= SPVSS=0V, Ta=−40 to +85°C, unless otherwise specified) (4/5)
Rating
Measuring
Symbol
Condition
Unit
circuit
Min.
Typ.
Max.
VOH1
IOH1=−0.5mA
VDD
−0.5
―
―
VOL1
IOL1=+0.5mA
―
―
0.5
―
―
0.5
―
―
0.5
VOL2
(when LED drive mode
is selected)
IOL2=+5mA
VDD≧2.2V
IOL2=+8mA
VDD≧2.3V
VOL3
IOL3=+3mA
2
( I C bus input/output mode)
―
―
0.4
IOOH
VOH=VDD (in high-impedance state)
―
―
1.0
IOOL
VOL=VSS (in high-impedance state)
−1.0
―
―
IIH1
VIH1=VDD
0
―
1.0
IIL1
VIL1=VSS
−1500
−300
−20
IIH2
VIH2=VDD (when pulled-down)
2
30
250
IIL2
VIL2=VSS (when pulled-up)
−250
−30
−2
IIH2Z
VIH2=VDD (in high-impedance state)
―
―
1.0
IIL2Z
VIL2=VSS (in high-impedance state)
−1.0
―
―
IIH3
VIH3=VDD
20
300
1500
IIL3
VIL3=VSS
−1.0
―
―
V
2
µA
3
µA
4
14/28
FEDL610Q304-01
ML610Q304
●DC Characteristics (5 of 5)
(VDD= 2.0 to 5.5V, SPVDD=2.0 to 5.5V, VSS= SPVSS=0V, Ta=−40 to +85°C, unless otherwise specified) (5/5)
Rating
Measuring
Symbol
Condition
Unit
circuit
Min.
Typ.
Max.
Parameter
Input voltage 1
(RESET_N)
(TEST0)
(TEST1_N)
(NMI)
(P40 to P42)
(P80 to P87)
Hysteresis width
(RESET_N)
(TEST0)
(TEST1_N)
(NMI)
(P40 to P42)
(P80 to P87)
Input pin
capacitance
(NMI)
(P40 to P42)
(P80 to P87)
VIH1
―
0.7×VDD
―
VDD
VIL1
―
0
―
0.3×VDD
⊿VT
―
0.05×VDD
―
0.4×VDD
CIN
f=10kHz
Vrms=50mV
Ta=25°C
―
―
10
V
5
pF
―
●Hysteresis Width
Input signal
⊿VT
VDD
VSS
Internal signal
VDDL
VSS
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FEDL610Q304-01
ML610Q304
●Measuring Circuits
・Measuring circuit 1
VDD VREF SPVDD
VDDL
SPVSS
CL
CAV CSV
A
VSS
CV
CSV
CAV
CL
CV
：0.1µF
：0.1µF
：1.0µF
： 10µF
・Measuring circuit 2
(* 2)
VIH
Output pins
VIL
Input pins
(* 1)
VDD
VDDL
VREF SPVDD VSS
V
SPVSS
(* 1) Input logic circuit to determine the specified measuring conditions.
(* 2) Measured at the specified output pins.
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FEDL610Q304-01
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・Measuring circuit 3
(* 2)
VIH
Output pins
Input pins
(* 1)
VIL
VDD
VDDL
VREF SPVDD VSS
A
SPVSS
(* 1) Input logic circuit to determine the specified measuring conditions.
(* 2) Measured at the specified output pins.
・Measuring circuit 4
(* 3)
Output pins
Input pins
A
VDD
VDDL
VREF SPVDD VSS
SPVSS
(* 3) Measured at the specified output pins.
・Measuring circuit 5
Output pins
VIL
Input pins
(* 1)
VDD
VDDL
VREF SPVDD VSS
Waveform monitoring
VIH
SPVSS
(* 1) Input logic circuit to determine the specified measuring conditions.
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FEDL610Q304-01
ML610Q304
●AC Characteristics (Reset)
・Reset
(VDD= 2.0 to 5.5V, SPVDD=2.0 to 5.5V, VSS= SPVSS=0V, Ta=−40 to +85°C, unless otherwise specified)
Measuring
Rating
Parameter
Symbol
Condition
Unit
circuit
Min.
Typ.
Max.
Time until it starts SPVDD after
―
―
0
tVDD
―
ns
starting VDD
Reset pulse width
PRST
―
100
―
―
µs
1
Reset noise elimination pulse width
PNRST
―
―
―
0.4
Power-on reset activation
TPOR
―
―
―
10
ms
power rise time
VIL1
RESET_N
VIL1
PRST
RESET_N Pin Reset
0.9×VDD
VDD
0.1×VDD
TPOR
Power on reset
18/28
FEDL610Q304-01
ML610Q304
・AC Characteristics (Oscillation stable time after STOP release)
Parameter
(VDD= 2.0 to 5.5V, SPVDD=2.0 to 5.5V, VSS= SPVSS=0V, Ta=−40 to +85°C, unless otherwise specified)
Rating
Symbol
Condition
Unit
Min.
Typ.
Max.
Oscillation stable time
after STOP release
TPUP1
―
High-speed oscillation
waveform
2
High-speed oscillation waveform
―
―
ms
High-speed oscillation waveform
TPUP1
OSCLK, HSCLK
SYSCLK
OSCLK, HSCLK waveform
OSCLK, HSCLK waveform
HSCLK waveform
HSCLK waveform
Interruput request
Program operation mode
STOP mode
Program operation mode
・AC Characteristics (External Interrupt)
Parameter
(VDD= 2.0 to 5.5V, SPVDD=2.0 to 5.5V, VSS= SPVSS=0V, Ta=−40 to +85°C, unless otherwise specified)
Rating
Symbol
Condition
Unit
Min.
Typ.
Max.
External interrupt disable
period
TNUL
Interrupt: Enabled (MIE=1)
CPU: NOP operation
2.5×sysclk
―
3.5×sysclk
µs
P80 to P87
(Rising-edge interrupt)
tNUL
P80 to P87
(Falling-edge interrupt)
tNUL
NMI, P80 to P87
(Both-edge interrupt)
tNUL
19/28
FEDL610Q304-01
ML610Q304
・AC Characteristics (Synchronous Serial Port)
(VDD= 2.0 to 5.5V, SPVDD=2.0 to 5.5V, VSS= SPVSS=0V, Ta=−40 to +85°C, unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
When high-speed oscillation is not
10
―
―
µs
SCLK input cycle
active
tSCYC
(slave mode)
When high-speed oscillation is active
500
―
―
ns
VDD≧2.4V
―
4
―
SCLK output cycle
MHz
tSCYC
(master mode)
VDD≧2.0V
―
2
―
When high-speed oscillation is not
4
―
―
µs
SCLK input pulse width
active
tSW
(slave mode)
When high-speed oscillation is active
200
―
―
ns
1
1
1
SCLK*
SCLK*
SCLK*
SCLK output pulse width
s
―
tSW
(master mode)
×0.4
×0.5
×0.6
SOUT output delay time
tSD
―
―
―
180
ns
(slave mode)
SOUT output delay time
tSD
―
―
―
80
ns
(master mode)
SIN input
setup time
tSS
―
50
―
―
ns
(slave mode)
SIN input
tSH
―
50
―
―
ns
hold time
*1: Clock period selected with S0CK3–0 of the serial port 0 mode register (SIO0MOD1)
tSCYC
tSW
tSW
SCK0*
tSD
tSD
SOUT0*
tSS
tSH
SIN0*
*: Indicates the secondary function of the port.
20/28
FEDL610Q304-01
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・AC Characteristics (I2C Bus Interface: Standard Mode 100kHz)
(VDD= 2.0 to 5.5V, SPVDD=2.0 to 5.5V, VSS= SPVSS=0V, Ta=−40 to +85°C, unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
SCL clock frequency
⎯
0
⎯
100
kHz
fSCL
SCL hold time
tHD:STA
⎯
4.0
⎯
⎯
µs
(start/restart condition)
SCL ”L” level time
tLOW
⎯
4.7
⎯
⎯
µs
SCL ”H” level time
tHIGH
⎯
4.0
⎯
⎯
µs
SCL setup time
tSU:STA
⎯
4.7
⎯
⎯
µs
(restart condition)
SDA hold time
tHD:DAT
⎯
0
⎯
⎯
µs
SDA setup time
tSU:DAT
⎯
0.25
⎯
⎯
µs
SDA setup time
tSU:STO
⎯
4.0
⎯
⎯
µs
(stop condition)
Bus-free time
tBUF
⎯
4.7
⎯
⎯
µs
・AC Characteristics (I2C Bus Interface: Fast Mode 400kHz)
(VDD= 2.0 to 5.5V, SPVDD=2.0 to 5.5V, VSS= SPVSS=0V, Ta=−40 to +85°C, unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
SCL clock frequency
fSCL
⎯
0
⎯
400
kHz
SCL hold time
tHD:STA
⎯
0.6
⎯
⎯
µs
(start/restart condition)
SCL ”L” level time
tLOW
⎯
1.3
⎯
⎯
µs
SCL ”H” level time
⎯
0.6
⎯
⎯
µs
tHIGH
SCL setup time
tSU:STA
⎯
0.6
⎯
⎯
µs
(restart condition)
SDA hold time
tHD:DAT
⎯
0
⎯
⎯
µs
SDA setup time
tSU:DAT
⎯
0.1
⎯
⎯
µs
SDA setup time
tSU:STO
⎯
0.6
⎯
⎯
µs
(stop condition)
Bus-free time
tBUF
⎯
1.3
⎯
⎯
µs
Start
condition
Restart
condition
Stop
condition
P80/SDA
P81/SCL
tHD:STA
tLOW
tHIGH
tSU:STA tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tBUF
21/28
FEDL610Q304-01
ML610Q304
●Electrical Characteristics of Successive Approximation Type A/D Converter
(DVDD=SPVDD=2.2 to 5.5V, VREF=2.2 to 5.5V, VSS=SPVSS=0V, Ta=−40 to +85°C, unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
Resolution
n
―
―
―
10
bit
2.7V≦VREF≦5.5V
−4
―
+4
Integral non-linearity error
IDL
2.2V≦VREF≦2.7V
−5
―
+5
2.7V≦VREF≦5.5V
−3
―
+3
Differential non-linearity error
LSB
DNL
2.2V≦VREF≦2.7V
−4
―
+4
Zero-scale error
VOFF
RI≦5kΩ
−4
―
+4
Full-scale error
FSE
RI≦5kΩ
−4
―
+4
Input impedance
RI
―
―
―
5k
Ω
Reference supply voltage
VREF
―
2.2
VDD
V
Conversion time
tCONV
HSCLK=4M to 8.4MHz
―
102
―
φ/CH
φ: Period of high-speed clock (HSCLK)
Reference
supply voltage
VREF
VDD
VDDL
1µF
10µF
A
−
0.1µF
Analog input
RI≦5kΩ
+
0.1µF
AIN0
to
AIN2
VSS
22/28
FEDL610Q304-01
ML610Q304
●Power-on/Shutdown Sequence
・When the power rise time is 10 ms or less
Upon power-on
Upon shutdown
VDD
0V
SPVDD
0V
tVDD
・When the power rise time is more than 10 ms
Upon power-on
VDD
Upon shutdown
90%
tVDD
SPVDD
RESET_N
0V
90%
10 ms (min.)
0V
VIL
Recommended power-on/shutdown sequence
1 Turn on VDD and SPVDD simultaneously, or turn on SPVDD after turning on VDD.
2 Turn off VDD and SPVDD simultaneously, or turn off VDD after turning on SPVDD.
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FEDL610Q304-01
ML610Q304
■Example of Application Circuit
Supply voltage
SPVDD
uEASE
I/F
SPVss
VDD
UVDD_O
VTref
RESET_N
TEST
Vss
CSV
CV
TEST1_N
TEST0
Speaker
SPP
ML610Q304
SPM
RESET_N
CL
VDDL
NMI
RXD0 P86
TXD0 P87
P40/AIN0 to P42/AIN2
ANALOG
VREF
CAV
VSS
VSS
P20 to P22
LED
CV
CL
CAV
CSV
: 0.1uF
: 10uF
: 1uF
: 0.1uF
24/28
FEDL610Q304-01
ML610Q304
■ PACKAGE DIMENSIONS
[Unit:mm]
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact our responsible sales person for the product name, package
name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
The heat resistance (example) of this LSI is shown below. Heat resistance (θJa) changes with the size and the
number of layers of a substrate.
PCB
W/L/t=60 / 62 / 1.6（mm）
PCB Layer
1 Layers
Air cooling conditions
Calm（0m/sec）
Heat resistance（θJa）
56.6[℃/W]( back diepad contact)
Power consumption of Chip PMax
0.351[W]
TjMax of this LSI is 125℃. TjMax is expressed with the following formulas.
TjMax = TaMax + θJa × PMax
25/28
FEDL610Q304-01
ML610Q304
■Figure pf soldering department terminal existence range
Reference drawing
[Unit:mm]
Attention of the layout of a mounting board
Please take into consideration enough that there are not ease of a mounting, the reliability of contact, leading about of a
wiring, and a solder bridge generate in the case of layout of the foot pattern of a mounting board.
The optimal layout of a foot pattern changes by the board quality of material, the solder paste category to be used,
thickness, the soldering methodology, etc. Therefore, since the span where the terminator of this package may exist is
shown as a "soldering part terminator extent drawing", please give as reference data of a foot pattern design.
26/28
FEDL610Q304-01
ML610Q304
■Revision History
Page
Document No.
Date
FEDL610Q304-01
Jul 16,2014
Previous
Edition
―
Current
Edition
―
Description
Final edition 1
27/28
FEDL610Q304-01
ML610Q304
NOTES
No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co.,
Ltd.
The content specified herein is subject to change for improvement without notice.
Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and
operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any
damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall bear no responsibility for such
damage.
The technical information specified herein is intended only to show the typical functions of and examples of application circuits
for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual
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whatsoever for any dispute arising from the use of such technical information.
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visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
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malfunction for a variety of reasons.
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Copyright
2014 LAPIS Semiconductor Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku,
Yokohama 222-8575, Japan
http://www.lapis-semi.com/en/
28/28