ETC2 MBI5031 16-channel pwm-embedded led driver Datasheet

Macroblock
Preliminary Datasheet
MBI5031
16-Channel PWM-Embedded LED Driver
Features
z
Backward compatible with MBI5026 in package
z
16 constant-current output channels
z
12-bit grayscale PWM control
z
Scrambled-PWM technology to improve refresh rate
z
Open-Circuit Detection to detect individual LED errors
z
8-bit programmable output current gain
z
Constant output current range:
Small Outline Package
GF: SOP24-300-1.00
5 ~ 45mA at 3.3V supply voltage
5 ~ 60mA at 5.0V supply voltage
z
Output current accuracy:
between channels: <±3% (max.), and
between ICs: <±6% (max.)
z
Staggered output delay
z
Maximum data clock frequency: 25MHz
z
Schmitt trigger input
z
3.0V-5.5V supply voltage
Product Description
MBI5031 is designed for LED video applications using internal Pulse Width Modulation (PWM) control with 12-bit
gray scales. MBI5031 features a 16-bit shift register which converts serial input data into each 12-bit pixel gray scale
of output port. At MBI5031 output port, sixteen regulated current ports are designed to provide uniform and constant
current sinks for driving LEDs with a wide range of Vf variations. The output current can be preset through an
external resistor. Moreover, the preset current of MBI5031 can be further programmed up or down to 128 gain steps
for LED global brightness adjustment.
With Scrambled-PWM (S-PWMTM) technology, MBI5031 enhances Pulse Width Modulation by scrambling the “on”
time into several “on” periods. The enhancement equivalently increases the visual refresh rate. When building a
12-bit gray scale video, S-PWM™ reduces the flickers and improves the fidelity. MBI5031 offloads the signal timing
generation of the host controller which just needs to feed data into drivers. MBI5031 drives the corresponding LEDs
to the brightness specified by image data. With MBI5031, all output channels can be built with 12-bit color depths
(4,096 gray scales).
Macroblock, Inc. 2006
Floor 6-4, No.18, Pu-Ting Rd., Hsinchu, Taiwan 30077, ROC.
TEL: +886-3-579-0068, FAX: +886-3-579-7534 E-mail: [email protected]
-1March 2006, V1.00
MBI5031
16-channel PWM-Embedded LED Driver
Block Diagram
OUT0
OUT1
OUT14 OUT15
16-bit error status
IO Regulator
and DAC
R-EXT
VDD
16
16
Comparators
Comparators
Comparators
Comparators
12-bit
Counter
GCLK
16
16
SYNC
Gray Scale Pixel
Buffers
Gray Scale Pixel
Gray Scale Pixel
GND
Gray Scale Pixel
LE
Configuration
Register
Control
16
16
16
SDI
16-bit Shift Register (FIFO)
SDO
DCLK
Figure 1
-2-
March 2006, V1.00
MBI5031
16-channel PWM-Embedded LED Driver
Terminal Description
Pin Configuration
Pin Name
Function
GND
Ground terminal for control logic and current
sink
SDI
Serial-data input to the shift register
DCLK
LE
Clock input terminal used to shift data on
rising edge and carries command information
when LE is asserted.
Data strobe terminal and controlling
command with DCLK
OUT0 ~ OUT15 Constant current output terminals
GCLK
Gray scale clock terminal
Clock input for gray scale. The gray scale
display is counted by gray scale clock
comparing with input data.
SDO
Serial-data output to the receiver-end SDI of
next driver IC
R-EXT
VDD
1
2
3
4
5
6
7
8
9
10
11
12
GND
SDI
DCLK
LE
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
24
23
22
21
20
19
18
17
16
15
14
13
VDD
R-EXT
SDO
GCLK
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
Input terminal used to connect an external
resistor for setting up output current for all
output channels
3.3V/5V supply voltage terminal
Maximum Ratings
Characteristic
Symbol
Rating
Unit
Supply Voltage
VDD
7
V
Input Pin Voltage (SDI)
VIN
-0.4 ~ VDD + 0.4
V
Output Current
IOUT
+60
mA
Sustaining Voltage at OUT Port
VDS
17
V
Data Clock Frequency*
FDCLK
+25
MHz
Gray Scale Clock Frequency
FGCLK
+8
MHz
GND Terminal Current
IGND
+1000
mA
GF Type
PD
2.39
W
GF Type
Rth(j-a)
52.37
°C/W
Topr
-40 ~ +85
°C
Tstg
-55 ~ +150
°C
Power Dissipation
(On PCB, Ta=25°C)
Thermal Resistance
(On PCB, Ta=25°C)
Operating Temperature
Storage Temperature
* Supply Voltage is 5V.
-3-
March 2006, V1.00
MBI5031
16-channel PWM-Embedded LED Driver
Equivalent Circuits of Inputs and Outputs
LE terminal
GCLK, DCLK, SDI terminal
VDD
IN
VDD
IN
SDO terminal
VDD
OUT
-4-
March 2006, V1.00
MBI5031
16-channel PWM-Embedded LED Driver
Electrical Characteristics (VDD= 5.0V)
Characteristics
Supply Voltage
Sustaining Voltage at OUT
Ports
Symbol
Condition
Min.
Typ.
Max.
Unit
VDD
-
4.5
5.0
5.5
V
VDS
OUT0 ~ OUT15
-
-
17.0
V
5
-
60
mA
IOUT
Output Current
Refer to “Test Circuit for
Electrical Characteristics”
IOH
SDO
-
-
-1.0
mA
IOL
SDO
-
-
1.0
mA
“H” level
VIH
Ta = -40~85ºC
0.7*VDD
-
VDD
V
“L” level
VIL
Ta = -40~85ºC
GND
-
0.3*VDD
V
Output Leakage Current
IOH
VOL
VDS= 17.0V
IOL= +1.0mA
-
-
0.5
0.4
µA
V
Output Voltage
VOH
IOH= -1.0mA
4.6
-
-
V
-
-
±3
%
-
±0.1
-
%/V
-
±1.0
-
%/V
-
0.15
0.20
V
200
430
700
KΩ
Input Voltage
SDO
Current Skew
dIOUT
Output Current vs.
Output Voltage Regulation
Output Current vs.
Supply Voltage Regulation
LED Open Detection
Threshold
Pull-down Resistor
Supply
%/dVDS
%/dVDD
VDS,TH
IOUT= 10.5mA
VDS within 1.0V and 3.0V,
Rext=460Ω@21mA
VDD within 4.5V and 5.5V,
Rext=460Ω@21mA
-
RIN(down)
“Off”
Current
“On”
Rext= 920Ω
VDS= 1.0V
LE
IDD(off) 1
Rext= Open,
OUT0 ~ OUT15
= Off
-
3.5
5.3
IDD(off) 2
Rext= 920Ω,
OUT0 ~ OUT15
= Off
-
7.1
10.7
IDD(off) 3
Rext= 460Ω,
OUT0 ~ OUT15
= Off
-
7.5
11.3
IDD(on) 1
Rext= 920Ω,
OUT0 ~ OUT15
= On
-
11.0
16.5
IDD(on) 2
Rext= 460Ω,
OUT0 ~ OUT15
= On
-
11.5
17.3
-5-
mA
March 2006, V1.00
MBI5031
16-channel PWM-Embedded LED Driver
Electrical Characteristics (VDD= 3.3V)
Characteristics
Symbol
Supply Voltage
Sustaining Voltage at OUT
Ports
Condition
Min.
Typ.
Max.
Unit
VDD
-
3.0
3.3
3.6
V
VDS
OUT0 ~ OUT15
-
-
17.0
V
5
-
45
mA
Refer to “Test Circuit for
IOUT
Output Current
Electrical Characteristics”
IOH
SDO
-
-
-1.0
mA
IOL
SDO
-
-
1.0
mA
“H” level
VIH
Ta = -40~85ºC
0.7*VDD
-
VDD
V
“L” level
VIL
Ta = -40~85ºC
GND
-
0.3*VDD
V
Output Leakage Current
IOH
VOL
VDS= 17.0V
IOL= +1.0mA
-
-
0.5
0.4
µA
V
Output Voltage
VOH
IOH= -1.0mA
2.9
-
-
V
-
-
±3
%
-
±0.1
-
%/V
-
±1.0
-
%/V
-
0.15
0.20
V
200
430
700
KΩ
Input Voltage
SDO
Current Skew
dIOUT
Output Current vs.
%/dVDS
Output Voltage Regulation
Output Current vs.
%/dVDD
Supply Voltage Regulation
LED Open Detection
VDS,TH
Threshold
Pull-down Resistor
Current
“On”
Rext= 920Ω
VDS= 1.0V
VDS within 1.0V and 3.0V,
Rext=460Ω@21mA
VDD within 3.0V and 3.6V,
Rext=460Ω@21mA
-
RIN(down)
“Off”
Supply
IOUT= 10.5mA
LE
IDD(off) 1
Rext= Open,
OUT0 ~ OUT15
= Off
-
2.2
3.3
IDD(off) 2
Rext= 920Ω,
OUT0 ~ OUT15
= Off
-
4.4
6.6
IDD(off) 3
Rext= 460Ω,
OUT0 ~ OUT15
= Off
-
6.3
9.5
IDD(on) 1
Rext= 920Ω,
OUT0 ~ OUT15
= On
-
6.7
10.1
IDD(on) 2
Rext= 460Ω,
OUT0 ~ OUT15
= On
-
7.1
10.7
mA
Test Circuit for Electrical Characteristics
IDD
VDD
IOUT
VIH,VIL
Function
Generator
V DD
..
.
O UT0
SDI
DCLK
LE
VDS
O UT15
IOL
G CLK
R - EXT G ND
Logic input
SDO
I OH
waveform
VIH=VDD
R ext
V IL=GND
Figure 2
-6-
March 2006, V1.00
MBI5031
16-channel PWM-Embedded LED Driver
Switching Characteristics (VDD= 5.0V)
Characteristics
Setup Time
Hold Time
Symbol
Pulse Width
Min.
Typ.
Max.
Unit
SDI - DCLK↑
tSU0
1
-
-
ns
LE↑ – DCLK↑
tSU1
1
-
-
ns
LE↓ – DCLK↑
tSU2
5
-
-
ns
DCLK↑ - SDI
tH0
3
-
-
ns
DCLK↑ - LE↓
tH1
7.0
-
-
ns
DCLK - SDO
tPD0
15.0
22.0
35.0
ns
-
130
-
ns
16.0
24.0
37.0
ns
-
30.0
-
ns
-
60.0
-
ns
-
90.0
-
ns
VDD=5.0V
VIH=VDD
VIL=GND
Rext=460Ω
VLED=4.5V
RL=152Ω
CL=10pF
C1=100nF
C2=10μF
Propagation Delay Time GCLK – OUT 4n * tPD1
Stagger Delay Time
Condition
LE – SDO**
tPD2**
OUT 4n + 1 *
tDL1
OUT 4n + 2 *
tDL2
OUT 4n + 3 *
tDL3
LE
tw(L)
5.0
-
-
ns
DCLK
tw(DCLK)
20.0
-
-
ns
GCLK
tw(GCLK)
125.0
-
-
ns
Output Rise Time of Output Ports
tOR
-
90.0
-
ns
Output Fall Time of Output Ports
tOF
-
70.0
-
ns
Error Detection Minimum Duration
tEDD***
-
2.0
-
μs
*There will be one GCLK latency at the first PWM output data. Refer to the Timing Waveform, where n=0, 1, 2, 3.
**In timing of “Read Configuration” and “Read Error Status Code”, the next DCLK rising edge should be tPD2 after the
falling edge of LE.
***Refer to Figure 6.
-7-
March 2006, V1.00
MBI5031
16-channel PWM-Embedded LED Driver
Switching Characteristics (VDD= 3.3V)
Characteristics
Symbol
Setup Time
Hold Time
Condition
Typ.
Max.
Unit
SDI - DCLK↑
tSU0
1.0
-
-
ns
LE↑ – DCLK↑
tSU1
1.0
-
-
ns
LE↓ – DCLK↑
tSU2
5.0
-
-
ns
DCLK↑ - SDI
tH0
3.0
-
-
ns
DCLK↑ - LE↓
tH1
7.0
-
-
ns
-
40.0
-
ns
-
150
-
-
40.0
-
ns
ns
-
30.0
-
ns
-
60.0
-
ns
-
90.0
-
ns
VDD=3.3V
VIH=VDD
VIL=GND
Rext=460Ω
VLED=4.5V
RL=152Ω
CL=10pF
C1=100nF
C2=10μF
tPD0
DCLK – SDO
Propagation Delay Time GCLK – OUT 4n * tPD1
LE – SDO
tPD2**
OUT 4n + 1 *
tDL1
OUT 4n + 2 *
tDL2
OUT 4n + 3 *
tDL3
LE
tw(L)
5.0
-
-
ns
DCLK
tw(DCLK)
25.0
-
-
ns
GCLK
tw(GCLK)
125.0
-
-
ns
Stagger Delay Time
Pulse Width
Min.
Output Rise Time of Output Ports
tOR
-
90.0
-
ns
Output Fall Time of Output Ports
tOF
-
70.0
-
ns
Error Detection Minimum Duration
tEDD***
-
2.0
-
μs
*There will be one GCLK latency at the first PWM output data. Refer to the Timing Waveform, where n=0, 1, 2, 3.
**In timing of “Read Configuration” and “Read Error Status Code”, the next DCLK rising edge should be tPD2 after the
falling edge of LE.
***Refer to Figure 6.
Test Circuit for Switching Characteristics
V DD
IDD
C1
I OUT
V IH,VIL
Function
Generator
VDD
..
.
OUT0
SDI
DCLK
LE
RL
CL
OUT 15
RL
G CLK
R - EXT GND
SDO
CL
Logic input
VIH=VDD
VL ED
waveform
Rext
C2
CL
VIL=G ND
Figure 3
-8-
March 2006, V1.00
MBI5031
16-channel PWM-Embedded LED Driver
Timing Waveform
(1)
tW(DCLK)
DCLK
tSU1 tH1
LE
tSU2
tw(LE)
tSU0 tH0
SDI
tPD0
tPD2
SDO
(2)
GCLK
tPD1
1 clock latency
OUT4n
tDL1
OUT4n+1
tDL2
OUT4n+2
tDL3
OUT4n+3
(3)
tW(GCLK)
GCLK
Output
Ports
90%
10%
tOF
90%
10%
tOR
-9-
March 2006, V1.00
MBI5031
16-channel PWM-Embedded LED Driver
Principle of Operation
Control Command
Data Latch
Signals Combination
Number of DCLK
LE
Rising Edge when
LE is asserted
High
0 or 1
Global Latch
High
2 or 3
Read Configuration
High
4 or 5
Enable “Error detection”
High
6 or 7
Read “Error status code”
High
8 or 9
Write Configuration
High
10 or 11
Command Name
Description
The Action after a Falling Edge of LE
Serial data are transferred to the buffers
Buffer data are transferred to the
comparators
Move out “configuration register” to the
shift registers
Enable “open circuit detection” of each
output’s LED
Move out “error status code” of 16
outputs to the shift registers
Serial data are transferred to the
“configuration register”
Data Latch
DCLK
2
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D13
D14
D15
N1
N2
N3
LE
SDI
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
Previous Data
SDO
Next Data
D0
D1
D2
N1
N2
N3
Global Latch
DCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D13
D14
D15
LE
SDI
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
Previous Data
SDO
Next Data
D0
D1
D2
N1
N2
N3
Read Configuration
DCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D13
D14
D15
LE
SDI
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
Previous Data
SDO
Next Data
D0
D1
D2
N1
N2
N3
Write Configuration
DCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
LE
SDI
SDO
Previous Data
- 10 -
Next Data
D0
D1
D2
March 2006, V1.00
MBI5031
16-channel PWM-Embedded LED Driver
Setting Gray Scales of Pixels
MBI5031 implements the gray level of each output port using the S-PWMTM control algorithm. With the 16-bit data,
all output channels can be built with 4,096 gray scales. The 16-bit input shift register latches 15 times of the gray
scale data into each data buffer with a “data latch” command sequentially. With a “global latch” command for the 16th
gray scale data, the 256-bit data buffers will be clocked in with the MSB first, loading the data from port 15 to port 0.
Full Timing for Data Loading
Port 15
DCLK
00
01
02
0E
0F
Port 14
10
11
12
1E
1F
Port 1
20
21
22
EE
EF
Port 0
F0
F1
F2
FD
FE
FF
N0
N1
N2
LE
SDI
D00
SDO
Previous Data
D01
D02
D0E
D0F
Previous Data
D10
D11
D0F
D10
D12
D1E
D11
D1D
D1F
D1E
D20
D21
D1F
D20
D22
D21
DEE DEF
DF0
DF1
DED
DEF
DF0
DEE
Data latch
Data latch
DF2
DFD DFE
DF1
DFC
Data latch
DFF
DFD
DFE
DN0
DFF
DN1
DN2
DN0
DN1
Global latch
Figure 4
Open-Circuit Detection Principle
Iout
Given Rext
Iout, target
MBI5031 Output Characteristics Curve
Iout, effect
Loading Line
VDS, effect
Vknee
VDS, Th ~ Vknee + 0.2Volt
VDS
Figure 5
The principle of MBI5031 LED Open-Circuit Detection is based on the fact that the LED loading status is judged by
comparing the effective current value (Iout, effect) of each output port with the target current (Iout, target) set by Rext. As
shown in the above figure, the knee voltage (Vknee) is the one between triode region and saturation region. The cross
point between the loading line and MBI5031 output characteristics curve is the effective output point (VDS, effect, Iout,
effect).Thus,
after the command of “enabling error detection”, the output ports of MBI5031 will be turned on for a while.
It is required to obtain the stable error status result for 2µ second. Then, the error status saved in the built-in register
would be shifted out through SDO pin bit by bit by sending the command of “Read Error Status Code”. Thus, to
detect the status of LED correctly, the output ports of MBI5031 must be turned on. The relationship between the
Error Status code and the effective output point is shown below:
State of Output
Port
Condition of Effective Output Point
Off
Iout, effect = 0
Iout, effect ≦ Iout, target and Vout, effect < VDS, Th
On
Iout, effect = Iout, target and Vout, effect ≧ VDS, Th
Note: the threshold voltage VDS, Th is around Vknee + 0.2 Volt
- 11 -
Detected
Open-Circuit
Error Status
Code
“0”
“1”
“0”
Meaning
Open Circuit
Normal
March 2006, V1.00
MBI5031
16-channel PWM-Embedded LED Driver
1. Enable error detection
DCLK
T0
T1
T2
2. Start error detection
T5
4. Shift out error data
3. Read error status code
T6
T0
T1
T2
T7
T8
1
2
3
15
16
LE
SDO
Previous Data
Previous Data
Previous Data
D0
D1
D2
D14
D15
Next Data
GCLK
OUT0~15
All the output ports are turned “ON”
PWM current outputs
PWM current outputs
At least 2µ seconds
Note :
tEDD = 2 µs is required to obtain the stable error status result.
Definition of Configuration Register
Figure 6
Bit
Attribute
Definition
Value
Function
F
X
X
X
Reserved bit
E
X
X
X
Reserved bit
D
X
X
X
Reserved bit
00 (Default)
64 times of 6-bit PWM counting and once of PWM 6-bit
counting
C
Write
PWM counting
mode selection
01
16 times of 6-bit PWM counting by 1/4 GCLK and once
of 6-bit PWM counting
10
4 times of 6-bit PWM counting by 1/16 GCLK and once
B
A
of 6-bit PWM counting
Write
11
12-bit PWM counting
PWM data
0
Auto-synchronization
synchronization
1 (Default)
Self-synchronization
00000000
8’b10101011 (Default)
mode
9~2
Write
1
X
0
Write
Current gain
adjustment
~
11111111
X
X
Reserved bit
Time-out alert of
0 (Default)
Enable
GCLK disconnection
1
Disable
- 12 -
March 2006, V1.00
MBI5031
16-channel PWM-Embedded LED Driver
Setting the PWM Gray Scale Counter
MBI5031 provides a 12-bit color depth. The value of each 16-bit serial data input will be valid only for 12 bits and
implemented according 12-bit PWM counter.
Setting the PWM Counting Mode
MBI5031 defines the different counting algorithms that support S-PWMTM, scrambled PWM, technology. With
S-PWMTM , the total PWM cycles can be broken down into MSB ( Most Significant Bits) and LSB (Least Significant
Bits) of gray scale cycles, and the MSB information can be dithered across many refresh cycles to achieve overall
same high bit resolution. MBI5031 also allows changing different counting algorithms and provides the better output
linearity when there are fewer transitions of output.
Mode 00
6
6-bit x 2 + 6-bit counting
6
6
6
# of GCLKs=(2 -1)x2 +2
6-bit PWM Counting, 31 GCLKs
6-bit PWM counting
Total 64 times
6-bit PWM Counting, 252 GCLKs
6-bit PWM counting
Mode 01
2
4
6-bit x 2 x2 + 6-bit counting
6
2
4
6
# of GCLKs=(2 -1)x2 x2 +2
Total 16 times
Mode 10
4
2
6-bit x 2 x2 + 6-bit counting
6
4
2
6
# of GCLKs=(2 -1)x2 x2 +2
6-bit PWM Counting, 1008 GCLKs
6-bit PWM Counting
Total 4 times
Mode 10
12 direct counting
12
# of GCLKs=2
12-bit PWM Counting, 4096 GCLKs
Total 1 time
- 13 -
March 2006, V1.00
MBI5031
16-channel PWM-Embedded LED Driver
Synchronization for PWM Counting
Between the data frame and the video frame, when the bit “A” is set to “0”, MBI5031 will automatically handle the
synchronization of previous data and next data for PWM counting. The next image data will be updated to output
buffers and start PWM counting when the previous data has finished one internal PWM cycle. It will prevent the lost
count of image data resolution and guarantee the data accuracy. In this mode, system controller only needs to
provide a continuous running GCLK for PWM counter. The output will be renewed after finishing one of MSB PWM
cycles.
Update data in buffers
Load data from SDI
Move data form buffers to outputs
DCLK
LE
SDI
D0
GCLK
D1
D2
0
D3
D12
D13
D14
D15
Next Data
Next Data
1
N
N +1
N +2
N +3
OUT0~15
Outputs are switching according to previous
data value
Outputs are switching to finish one MSB
PWM cycle
One GCLK
latency
Outputs are switching according
to next data value
‘global latch’ command
Figure 7
When the bit “A” is set to “1” (Default), MBI5031 will update the next image data into output buffer immediately, no
matter the counting status of previous image data is. In this mode, system controller will synchronize the GCLK
according image data outside MBI5031 by itself. Otherwise, the conflict of previous image data and next image data
will cause the data lost.
DCLK
LE
SDI
GCLK
D0
D1
0
D2
D3
D12
1
D13
D14
D15
N
Next Data
N+ 1
N+ 2
N+ 3
N+ 4
OUT0~15
One GCLK
latency
Load data from SDI
Outputs are ON/OFF according to NEW data
‘global latch’ command
Figure 8
Time-Out Alert of GCLK Disconnection
When signal of GCLK is disconnected for around 1 second period, the all output ports will be turned off automatically.
This function will protect the LED display system to stay on always and prevent a big current to damage the power
system. The default is set to ‘enable” when bit “0” is 0. When the GCLK is active again, the driver resumes to work
after resetting the internal counters and comparators.
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March 2006, V1.00
MBI5031
16-channel PWM-Embedded LED Driver
Setting Output Current
The output current (IOUT) is set by an external resistor, Rext. The default relationship between IOUT and Rext is shown in
the following figure.
MBI5031 Rext vs. IOUT
IOUT(mA)
70
60
50
40
30
20
10
0
100
300
500
700
900
1100
Rext(Ω)
1300
1500
1700
1900
Figure 9
Also, the output current can be calculated from the equation:
VR-EXT=0.625Volt x G; IOUT= (VR-EXT/Rext) x15.5
Whereas Rext is the resistance of the external resistor connected to R-EXT terminal and VR-EXT is its voltage. G is the
digital current gain, which is set by the bit9 – bit2 of the configuration register. The default value of G is 1. For your
information, the output current is about 21mA when Rext=460Ω and 10.5mA when Rext=920Ω if G is set to default
value 1. The formula and setting for G are described in next section.
z
Current Gain Adjustment
…
Gain =1.9882
128 steps
…
…
…
…
Gain =1
128 steps
Gain = 1/8
(1,0,1,0,1,0,1,1)
(0,0,0,0,0,0,0,0)
(0,0,0,0,0,0,0,1
(0,0,0,0,0,0,1,0)
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(1,1,1,1,1,1,1,1)
March 2006, V1.00
MBI5031
16-channel PWM-Embedded LED Driver
The bit 9 to bit 2 of the configuration register set the gain of output current, i.e., G. As totally 8-bit in number, i.e.,
ranged from 8’b00000000 to 8’b11111111, these bits allow the user to set the output current gain up to 256 levels.
These bits can be further defined inside Configuration Register as follows:
F
-
E
-
D
-
C
-
B
-
A
-
9
HC
8
DA6
7
DA5
6
DA4
5
DA3
4
DA2
3
DA1
2
DA0
1
-
0
-
1. Bit 9 is HC bit. The setting is in low current band when HC=0, and in high current band when HC=1.
2. Bit 8 to bit 2 are DA6 ~ DA0.
The relationship between these bits and current gain G is:
G= [(1+3xHC)/4]x[(1+3xD/128)/2]
Whereas HC is 1 or 0 and
D=DA6x26+DA5x25+DA4x24+DA3x23+DA2x22+DA1x21+DA0x20
In other words, these bits can be looked as a floating number with 1-bit exponent HC and 7-bit mantissa DA6~DA0.
For example,
1. When the bit9 to bit2 of configuration register are set to 8’b11111111, the current gain G becomes
[(1+3x1)/4]x[(1+3x127/128)/2]=1.9882
2. When the bit9 to bit2 of configuration register are set to 8’b10000000, the current gain G becomes
[(1+3x1)/4]x[(1+3x0/128)/2]=0.5
3. when the bit9 to bit2 of configuration register are set to 8’b00000000, the current gain G becomes
[(1+3x0)/4]x[(1+3x0/128)/2]=1/8
Delay Time of Staggered Output
MBI5031 has a built-in staggered circuit to perform delay mechanism. Among output ports exist a graduated 30ns
delay time among OUT 4n , OUT 4n + 1 , OUT 4n + 2 , and OUT 4n + 3 , by which the output ports will be
divided to four groups at a different time so that the instant current from the power line will be lowered.
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March 2006, V1.00
MBI5031
16-channel PWM-Embedded LED Driver
Package Power Dissipation (PD)
The maximum allowable package power dissipation is determined as PD (max) = (Tj – Ta) / Rth(j-a). When 16 output
channels are turned on simultaneously, the actual package power dissipation is PD (act) = (IDD x VDD) + (IOUT x Duty x
VDS x 16). Therefore, to keep PD (act) ≤ PD (max), the allowable maximum output current as a function of duty cycle
is:
IOUT = { [ (Tj – Ta) / Rth(j-a) ] – (IDD x VDD) } / VDS / Duty / 16, where Tj = 150°C.
Max. IOUT(mA)
70
IOUT vs. Duty Cycle@ Rth(j-a)=52.37℃/W
60
50
VDS=1V@Ta=25℃
VDS=1V@Ta=85℃
VDS=2V@Ta=25℃
VDS=2V@Ta=85℃
40
30
20
10
0
10% 20% 30% 40% 50% 60% 70% 80% 90% 100%
Duty Cycle
Figure 10
Condition: IOUT=60mA, 16 output channels
Device Type
Rth(j-a) (°C /W)
GF
52.37
The maximum power dissipation, PD (max) = (Tj – Ta) / Rth(j-a), decreases as the ambient temperature increases.
MBI5031 Maximum Power Dissipation at Various Ambient Temperatures
Power Dissipation (W)
3.0
2.5
2.0
GF Type: Rth=52.37℃/W
1.5
1.0
Safe Operation Area
0.5
0.0
0
25
35
45
55
65
75
Ambient Temperature (℃)
85
95
105
Figure 11
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March 2006, V1.00
MBI5031
16-channel PWM-Embedded LED Driver
LED Supply Voltage (VLED)
MBI5031 are designed to operate with VDS ranging from 0.4V to 0.8V (depending on IOUT=5~60mA) considering the
package power dissipating limits. VDS may be higher enough to make PD (act) > PD (max) when VLED = 5V and VDS =
VLED – VF, in which VLED is the load supply voltage. In this case, it is recommended to use the lowest possible supply
voltage or to set an external voltage reducer, VDROP.
A voltage reducer lets VDS = (VLED –VF) – VDROP.
Resistors or Zener diode can be used in the applications as shown in the following figures.
VLED
Voltage Supply
Voltage Supply (VLED)
VDrop
VDrop
VF
VF
VDS
VDS
MBI5031
MBI5031
Figure 12
Switching Noise Reduction
LED drivers are frequently used in switch-mode applications which always behave with switching noise due to the
parasitic inductance on PCB. To eliminate switching noise, refer to “Application Note for 8-bit and 16-bit LED DriversOvershoot”.
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March 2006, V1.00
MBI5031
16-channel PWM-Embedded LED Driver
Package Outline
MBI5031GF Outline Drawing
Note: The unit for the outline drawing is mm.
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March 2006, V1.00
MBI5031
16-channel PWM-Embedded LED Driver
Product Top Mark Information
The first row of printing
●
MBIXXXX ○ ○○
Part number
ID number
The second row of printing
XXXXXXXX ○
or
MBIXXXX ○ ○
Manufacture
Code
Package Code
Product No.
Device Version Code
Process Code
G: Green and Pb-free
Product Revision History
Datasheet version
V1.00
Device Version Code
A
Product Ordering Information
Part Number
MBI5031GF
“Pb-free & Green”
Package Type
SOP24-300-1.00
Weight (g)
0.30
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March 2006, V1.00
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