LME49830 www.ti.com SNAS396D – JANUARY 2008 – REVISED APRIL 2013 LME49830 Mono High Fidelity 200 Volt MOSFET Power Amplifier Input Stage with Mute Check for Samples: LME49830 FEATURES DESCRIPTION • The LME49830 is a high fidelity audio power amplifier input stage designed for demanding consumer and pro-audio applications. Amplifier output power may be scaled by changing the supply voltage and number of output devices. The LME49830 is capable of driving an output stage in excess of 300 W single-ended into an 8Ω load in the presence of 10% high line headroom and 20% supply regulation. 1 2 • • • • • • High Output Current and Voltage for Use With MOSFET Output Stages Very High Voltage Range: ±20V to ±100V Scalable Output Power Minimum External Components External Compensation Thermal Shutdown of Input Stage Mute Control APPLICATIONS • • • • AV Receivers Audiophile Power Amps Pro Audio High Voltage Industrial Applications KEY SPECIFICATIONS • • • • • Wide Operating Voltage Range: ±20V to ±100V Output Voltage Noise – (BW = 30kHz): 44μV (Typ) PSRR (DC): 105dB (Typ) Slew Rate: 39V/μs (Typ) THD+N (f = 1kHz): 0.0006% (Typ) The LME49830 includes internal thermal shut down circuitry that activates when the LME49830 die temperature exceeds 150°C. The LME49830 has a mute function that mutes the input drive signal and forces the amplifier output to a quiescent state. The LME49830 has high drive current, 56mA typical, and high output voltage swing for maximum flexibility in output stage choice. With a bias voltage range up to 16V the LME49830 can be used to drive MOSFET output stages using a wide selection of MOSFETs. The LME49830 has a wide operating supply range of ±20V to ±100V, which allows lower cost, unregulated power supplies to be used. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2013, Texas Instruments Incorporated LME49830 SNAS396D – JANUARY 2008 – REVISED APRIL 2013 www.ti.com Typical Application +VCC RF 6.8 k: +5V CS10 0.1 PF +VCC RM 27 k: Mute Osense Mute Control +VCC RGN 120: NOUT QN BiasP Ci 220 PF Ri 240: IN- CIN RIN 10 PF 240: IN+ RBIAS 10 k: - RB1 1.2 k: CBIAS 20 pF + RS 6.8 k: RE1 0.1: CB1 20 pF QVBE TIP31C RB2 500: BiasM POUT -VEE -VEE RL 8: RE2 0.1: QP Comp GND RQ 12 k: RGP 120: CC 20 pF -VEE CS11 0.1 PF Figure 1. Typical Audio Amplifier Application Circuit LME49830 CONNECTION DIAGRAM 15 +VCC 14 NOUT 13 POUT 12 BiasP 11 10 9 8 7 6 5 4 3 2 1 BiasM -VEE NC Osense NC Comp ININ+ GND Mute NC Figure 2. Plastic Package (1) (Top View) (1) 2 The NDN0015A is a non-isolated package. The package's metal back and any heat sink to which it is mounted are connected to the VEE potential when using only thermal compound. If a mica washer is used in addition to thermal compound, θCS (case to sink) is increased, but the heat sink will be electrically isolated from VEE. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LME49830 LME49830 www.ti.com SNAS396D – JANUARY 2008 – REVISED APRIL 2013 PIN DESCRIPTIONS Pin Pin Name Description 1 NC 2 Mute No Connection, Pin electrically isolated Mute Control 3 GND Device Ground 4 IN+ Non-inverting input 5 IN- Inverting input 6 Comp 7 NC 8 Osense 9 NC No Connection, Pin electrically isolated 10 -VEE Negative Power Supply 11 BiasM Negative External Bias Control 12 BiasP Positive External Bias Control 13 POUT P-channel MOSFET Output 14 NOUT N-channel MOSFET Output 15 +VCC Positive Power Supply External Compensation Connection No Connection, Pin electrically isolated Output Sense BLOCK DIAGRAM +VCC Mute 1 k: Mute Control NOUT GND POUT - Gm IN- + Amp BiasP IN+ BiasM Reference and Protection + Osense Mute Amp Comp -VEE Figure 3. LME49830 Simplified Block Diagram Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LME49830 3 LME49830 SNAS396D – JANUARY 2008 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) (3) Supply Voltage |V+| + |V-| 200V Differential Input Voltage +/-6V Common Mode Input Range Power Dissipation 0.4 VEE to 0.4 VCC (4) 5.4W ESD Rating (5) 2.0kV ESD Rating (6) 200V Junction Temperature (TJMAX) Soldering Information 150°C NDN Package (10 seconds) Storage Temperature Thermal Resistance (1) (2) (3) (4) (5) (6) 260°C -40°C to +150°C θJA 73°C/W θJC 4°C/W The Electrical Characteristics tables list ensure specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower. For the LME49830, TJMAX = 150°C and the typical θJC is 4°C/W. Human body model, applicable std. JESD22-A114C. Machine model, applicable std. JESD22-A115-A. OPERATING RATINGS (1) (2) Temperature Range TMIN ≤ TA ≤ TMAX (1) (2) 4 −40°C ≤ TA ≤ +85°C ±20V ≤ VSUPPLY ≤ ±100V Supply Voltage The Electrical Characteristics tables list ensure specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LME49830 LME49830 www.ti.com SNAS396D – JANUARY 2008 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS VCC = +100V, VEE = –100V (1) (2) The following specifications apply for IMUTE = 150μA unless otherwise specified. Limits apply for TA = 25°C. Symbol Parameter Conditions LME49830 Typical (3) Limit (4) Units (Limits) 24 mA (max) ICC Total Positive Quiescent Power Supply Current VIN = 0V, VO = 0V, IO = 0A 19 IEE Total Negative Quiescent Power Supply Current VIN = 0V, VO = 0V, IO = 0A –21 mA THD+N Total Harmonic Distortion + Noise No load, f = 1kHz, AV = 30dB VOUT = 30VRMS, 30kHz BW 0.0006 % VBIAS Bias Voltage AV(CL) Closed Loop Voltage Gain 16 AV(OL) Open Loop Gain f = DC VIN = 1mVRMS, f = 1kHz, CC = 10pF VOM Output Voltage Swing THD = 0.05%, f = 20Hz to 20kHz 68 Output Noise RS = 10kΩ, AV = 30dB, 30kHz BW A-weighted 44 28 56 VNOISE IOUT Maximum Output Current Current from Output pins IMUTE Current into Mute Pin To put part in “play” mode SR Slew Rate VIN = 1.2VP-P, AV = 30dB, f = 10kHz square wave, CLOAD = 2,000pF VOS Input Offset Voltage IB Input Bias Current PSRRAC 112 88 15 V (min) 26 dB (min) 82 dB (min) VRMS 205 μV μV (max) 47 mA (min) 130 μA (min) 39 V/μs VCM = 0V, IO = 0mA, IMUTE = 150μA ±0.9 ±3 mV (max) VCM = 0V, IO = 0mA, IMUTE = 0μA ±0.4 ±4.2 mV (max) VCM = 0V, IO = 0mA 95 250 nA (max) Power Supply Rejection Ratio (AC) RS = 1kΩ, f = 100Hz,VRIPPLE = 1VRMS, Input Referred, AV = 30dB 104 PSRRDC Power Supply Rejection Ratio (DC) RS = 1kΩ, Input Referred, AV = 30dB 105 94 dB (min) IAB Bias Control Current Shorted output, shorted bias control 2 1.6 2.7 mA (min) mA (max) (1) (2) (3) (4) dB The Electrical Characteristics tables list ensure specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified. Typical values represent most likely parametric norms at TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization. Data sheet min and max specification limits are specified by test or statistical analysis. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LME49830 5 LME49830 SNAS396D – JANUARY 2008 – REVISED APRIL 2013 www.ti.com Test Circuit Diagram +VCC +5V CS10 0.1 PF +VCC RM 27 k: Mute Osense Mute Control NOUT BiasP RS RIN TEST SIGNAL INPUT 240: 6.8 k: Ci Ri 220 PF 240: R1 IN+ IN- 10: + OUTPUT R2 BiasM RF 10: POUT 6.8 k: Comp GND -VEE CC 10 pF -VEE CS11 0.1 PF Figure 4. LME49830 Test Circuit Diagram 6 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LME49830 LME49830 www.ti.com SNAS396D – JANUARY 2008 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS THD+N vs Frequency +VCC = -VEE = 20V, VO = 10V 10 10 1 1 THD+N (%) THD+N (%) THD+N vs Frequency +VCC = -VEE = 20V, VO = 5V 0.1 0.01 BW = 80 kHz 0.1 0.01 BW = 80 kHz 0.001 0.001 BW = 30 kHz BW = 30 kHz 0.0001 20 1k 100 0.0001 20 10k 20k Figure 5. Figure 6. THD+N vs Frequency +VCC = -VEE = 50V, VO = 14V THD+N vs Frequency +VCC = -VEE = 50V, VO = 20V 10 10 1 1 0.1 0.01 BW = 80 kHz 0.1 0.01 BW = 80 kHz 0.001 0.001 BW = 30 kHz BW = 30 kHz 1k 100 10k 20k 0.0001 20 10k 20k Figure 7. Figure 8. THD+N vs Frequency +VCC = -VEE = 100V, VO = 14V THD+N vs Frequency +VCC = -VEE = 100V, VO = 30V 10 10 1 1 THD+N (%) THD+N (%) 1k 100 FREQUENCY (Hz) FREQUENCY (Hz) 0.1 0.01 0.1 0.01 BW = 80 kHz BW = 80 kHz 0.001 0.001 BW = 30 kHz BW = 30 kHz 0.0001 20 10k 20k FREQUENCY (Hz) THD+N (%) THD+N (%) FREQUENCY (Hz) 0.0001 20 1k 100 100 1k 10k 20k 0.0001 20 FREQUENCY (Hz) 100 1k 10k 20k FREQUENCY (Hz) Figure 9. Figure 10. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LME49830 7 LME49830 SNAS396D – JANUARY 2008 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) THD+N vs Output Voltage +VCC = -VEE = 100V, f = 20Hz 10 10 1 1 THD+N (%) THD+N (%) THD+N vs Output Voltage +VCC = -VEE = 50V, f = 20Hz 0.1 BW = 80 kHz 0.01 0.001 0.1 BW = 80 kHz 0.01 0.001 BW = 30 kHz 0.0001 100m BW = 30 kHz 1 10 20 0.0001 100m 50 Figure 12. THD+N vs Output Voltage +VCC = -VEE = 50V, f = 1kHz THD+N vs Output Voltage +VCC = -VEE = 100V, f = 1kHz 10 10 1 1 THD+N (%) THD+N (%) Figure 11. 0.1 BW = 80 kHz 0.01 0.001 BW = 80 kHz 0.01 0.001 0.0001 100m BW = 30 kHz 1 10 20 0.0001 100m 50 OUTPUT VOLTAGE (VRMS) 1 10 50 100 OUTPUT VOLTAGE (VRMS) Figure 13. Figure 14. THD+N vs Output Voltage +VCC = -VEE = 50V, f = 20kHz THD+N vs Output Voltage +VCC = -VEE = 100V, f = 20kHz 10 10 1 1 THD+N (%) THD+N (%) 50 100 0.1 BW = 30 kHz 0.1 BW = 80 kHz 0.01 0.001 0.1 BW = 80 kHz 0.01 0.001 BW = 30 kHz BW = 30 kHz 1 10 20 50 0.0001 100m OUTPUT VOLTAGE (VRMS) 1 10 50 100 OUTPUT VOLTAGE (VRMS) Figure 15. 8 10 OUTPUT VOLTAGE (VRMS) OUTPUT VOLTAGE (VRMS) 0.0001 100m 1 Figure 16. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LME49830 LME49830 www.ti.com SNAS396D – JANUARY 2008 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) THD+N vs Output Voltage +VCC = -VEE = 20V, f = 1kHz 10 10 1 1 0.1 THD+N (%) THD+N (%) THD+N vs Output Voltage +VCC = -VEE = 20V, f = 20Hz BW = 80 kHz 0.01 0.001 BW = 80 kHz 0.01 0.001 BW = 30 kHz 0.0001 100m 0.1 1 10 20 BW = 30 kHz 0.0001 100m OUTPUT VOLTAGE (VRMS) 1 10 20 OUTPUT VOLTAGE (VRMS) Figure 17. Figure 18. THD+N vs Output Voltage +VCC = -VEE = 20V, f = 20kHz Closed Loop Frequency Response +VCC = -VEE = 50V, VIN = 1VRMS 3 10 2 0.1 1 GAIN (dB) THD+N (%) 1 BW = 80 kHz 0 0.01 -1 0.001 -2 BW = 30 kHz 0.0001 100m 1 10 -3 20 20 100 1k 10k 200k FREQUENCY (Hz) OUTPUT VOLTAGE (VRMS) Figure 19. Figure 20. Closed Loop Frequency Response +VCC = -VEE = 100V, VIN = 1VRMS PSRR vs Frequency +VCC = -VEE = 100V, No Filters, Input Referred VRIPPLE = 200mVRMS on VCC pin 0 3 -20 2 PSRR (dB) GAIN (dB) -40 1 0 -1 -60 -80 -100 -120 -2 -3 20 -140 100 1k 10k 200k -160 20 FREQUENCY (Hz) 100 1k 10k 100k FREQUENCY (Hz) Figure 21. Figure 22. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LME49830 9 LME49830 SNAS396D – JANUARY 2008 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) PSRR vs Frequency +VCC = -VEE = 100V, No Filters, Input Referred VRIPPLE = 200mVRMS on VEE pin 20 -20 0 MUTE ATTENUATION (dB) 0 PSRR (dB) -40 -60 -80 -100 -120 Mute Attenuation vs IMUTE +VCC = -VEE = 100V -20 -40 fIN = 1 kHz -60 -80 -100 -140 -120 -160 20 100 10k 1k fIN = 20 kHz -140 40 100k 60 80 FREQUENCY (Hz) 160 Figure 24. Output Voltage vs Supply Voltage Slew Rate vs Compensation Capacitor +VCC = -VEE = 100V, VIN = 1.2VP, No Load 80 60 SLEW RATE (V/Ps) OUTPUT VOLTAGE (VRMS) 140 80 THD+N = 10% 40 THD+N = 0.05% 60 40 20 20 0 0 20 40 60 80 0 100 0 SUPPLY VOLTAGE (±V) 10 Supply Current vs Supply Voltage 40 50 60 Input Offset Voltage vs Supply Voltage 1.2 25 20 IEE 15 ICC 10 5 0 20 30 Figure 26. INPUT OFFSET VOLTAGE (mV) 30 20 COMPENSATION CAPACITANCE (pF) Figure 25. SUPPLY CURRENT (mA) 120 Figure 23. 100 30 40 50 60 70 80 90 100 SUPPLY VOLTAGE (rV) 1.0 0.8 0.6 0.4 0.2 0 0 20 40 60 80 100 120 SUPPLY VOLTAGE (±V) Figure 27. 10 100 IMUTE (PA) Figure 28. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LME49830 LME49830 www.ti.com SNAS396D – JANUARY 2008 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) 180 160 140 140 120 120 100 100 80 80 60 60 40 40 20 20 0 100 80 60 40 20 0 100 1k 10k 100k -20 10M 100M 1M CMRR vs Frequency +VCC = -VEE = 100V 120 CMRR (dB) 180 160 -20 10 140 200 PHASE MARGIN (°) GAIN (dB) 200 Open Loop Gain and Phase Margin +VCC = -VEE = 100V 0 10 100 100k 10k Figure 29. Figure 30. Noise Floor +VCC = -VEE = 50V, VIN = 0V Noise Floor +VCC = -VEE = 100V, VIN = 0V 1m 1m 500P 500P 200P BW = 30 kHz 100P 50P 20P 1M 200P BW = 30 kHz 100P 50P 20P A-WEIGHTED 10P 20 1k FREQUENCY (Hz) OUTPUT NOISE (VRMS) OUTPUT NOISE (VRMS) FREQUENCY (Hz) 100 A-WEIGHTED 1k 10k 200k 10P 20 100 1k 10k FREQUENCY (Hz) FREQUENCY (Hz) Figure 31. Figure 32. 200k Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LME49830 11 LME49830 SNAS396D – JANUARY 2008 – REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION MUTE FUNCTION The mute function of the LME49830 is controlled by the amount of current that flows into the MUTE pin. If there is less than 100μA of current flowing into the MUTE pin, the part will be in mute mode. This can be achieved by shorting the MUTE pin to ground. It is recommended to connect a capacitor CM (its value not less than 47μF) between the MUTE pin and ground for reducing voltage fluctuation when switching between ‘play’ and ‘mute’ mode. If there is between 130μA and 2mA of current flowing into the MUTE pin, the part will be in ‘play’ mode. This can be done by connecting a power supply, VMUTE, to the MUTE pin through a resister, RM. The current into the MUTE pin can be determined by the equation IMUTE = (VMUTE – VBE) / (1kΩ +RM) (A), where VBE ≅ 0.7V. For example, if a 5V power supply is connected through a 27kΩ resistor to the MUTE pin, then the mute current will be 154μA, at the center of the specified range. It is also possible to use VCC as the power supply for the MUTE pin, though RM will have to be recalculated accordingly. It is not recommended to flow more than 2mA of current into the MUTE pin because damage to the LME49830 may occur. THERMAL PROTECTION When the temperature on the die exceeds 150°C, the LME49830 shuts down. It starts operating again when the die temperature drops to about 145°C. When in thermal shutdown, the current supply internal to the LME49830 will be cut-off. There will be no signal generated to the output while in thermal shutdown. After the die temperature decreases, the LME49830 will power up again and resume normal operation. If the fault conditions continue, thermal protection will be activated and repeat the cycle preventing the LME49830 from over heating. Since the die temperature is directly dependent upon the heat sink used, the heat sink should be chosen so that thermal shutdown is not activated during normal operation. Using the best heat sink possible within the cost and space constraints of the system will improve the long-term reliability of any power semiconductor device, as discussed in the DETERMINING THE CORRECT HEAT SINK section. It is recommended to use a separate heat sink from the output stage heat sink for the LME49830. A heat sink may not be needed if the supply voltages are low. POWER DISSIPATION AND HEAT SINKING When in “play” mode, the LME49830 draws a constant amount of current, regardless of the input signal amplitude. Consequently, the power dissipation is constant for a given supply voltage and can be computed with the equation PDMAX = ICC x (VCC – VEE) (W). For a quick calculation of PDMAX, approximate the current to be 20mA and multiply it by the total supply voltage (the current varies slightly from this value over the operating range). DETERMINING THE CORRECT HEAT SINK The choice of a heat sink for any power IC is made entirely to keep the die temperature at a level such that the thermal protection circuitry is not activated under normal circumstances. The thermal resistance from the die to the outside air, θJA (junction to ambient), is a combination of three thermal resistances, θJC (junction to case), θCS (case to sink), and θSA (sink to ambient). The thermal resistance, θJC (junction to case), of the LME49830TB is 4°C/W. Using Thermalloy Thermacote thermal compound, the thermal resistance, θCS (case to sink), is about 0.2°C/W. Since convection heat flow (power dissipation) is analogous to current flow, thermal resistance is analogous to electrical resistance, and temperature drops are analogous to voltage drops, the power dissipation out of the LME49830 is equal to the following: PDMAX = (TJMAX−TAMB) / θJA (W) where • • • 12 TJMAX = 150°C TAMB is the system ambient temperature θJA = θJC + θCS + θSA Submit Documentation Feedback (1) Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LME49830 LME49830 www.ti.com SNAS396D – JANUARY 2008 – REVISED APRIL 2013 Once the maximum package power dissipation has been calculated, the maximum thermal resistance, θSA, (heat sink to ambient) in °C/W for a heat sink can be calculated. This calculation is made using Equation (2) which is derived by solving for θSA in Equation (1). θSA = [(TJMAX−TAMB)−PDMAX(θJC +θCS)] / PDMAX (°C/W) (2) Again it must be noted that the value of θSA is dependent upon the system designer's amplifier requirements. If the ambient temperature that the audio amplifier is to be working under is higher, then the thermal resistance for the heat sink, given all other things are equal, will need to be smaller (better heat sink). PROPER SELECTION OF EXTERNAL COMPONENTS Proper selection of external components is required to meet the design targets of an application. The choice of external component values that will affect gain and low frequency response are discussed below. The gain is set by resistors Rf and Ri for the non-inverting configuration shown in Figure 1. The gain is found by Equation 3 below: AV = 1 + Rf / Ri (V/V) (3) For best noise performance, lower values of resistors are used. For the LME49830 the gain should be set no lower than 26dB. Gain settings below 26dB may experience instability. The combination of Ri with Ci (see Figure 1) creates a high-pass filter. The low frequency response is determined by these two components. The -3dB point can be found from Equation 4 shown below: fi = 1 / (2πRiCi) (Hz) (4) If an input coupling capacitor is used to block DC from the inputs as shown in Figure 1, there will be another high-pass filter created with the combination of CIN and RIN. When using a input coupling capacitor RIN is needed to set the DC bias point on the amplifier's input terminal. The resulting -3dB frequency response due to the combination of CIN and RIN can be found from Equation 5 shown below: fIN = 1 / (2πRINCIN) (Hz) (5) With large values of RIN oscillations may be observed on the outputs when the inputs are left floating. Decreasing the value of RIN or not letting the inputs float will remove the oscillations. If the value of RIN is decreased then the value of CIN will need to increase in order to maintain the same -3dB frequency response. AVOIDING THERMAL RUNAWAY WHEN USING BIPOLAR OUTPUT STAGES When using a bipolar output stage with the LME49830, the designer must beware of thermal runaway. Thermal runaway is a result of the temperature dependence of VBE (an inherent property of the transistor). As temperature increases, VBE decreases. In practice, current flowing through a bipolar transistor heats up the transistor, which lowers the VBE. This in turn increases the current again, and the cycle repeats. If the system is not designed properly, this positive feedback mechanism can destroy the bipolar transistors used in the output stage. One of the recommended methods of preventing thermal runaway is to use a heat sink on the bipolar output transistors. This will keep the temperature of the transistors lower. A second recommended method is to use emitter degeneration resistors. As current increases, the voltage across the emitter degeneration resistor also increases, which decreases the voltage across the base and emitter. This mechanism helps to limit the current and counteracts thermal runaway. A third recommended method is to use a “VBE multiplier” to bias the bipolar output stage. The VBE multiplier consists of a bipolar transistor and two resistors, one from the base to the collector and one from the base to the emitter. The voltage from the collector to the emitter (also the bias voltage of the output stage) is VBIAS = VBE(1+RCB/RBE), which is why this circuit is called the VBE multiplier. When VBE multiplier transistor (QVBE in Figure 1) is mounted to the same heat sink as the bipolar output transistors, its temperature will track that of the output transistors. The bias voltage will be reduced as the QVBE heats up reducing bias current in the output stage. The bias circuit used in Figure 1 is a modified VBE multiplier circuit. The additional resistor, RB1, sets a temperature independent portion of the bias voltage while the rest of the VBE multiplier circuit will adjust bias voltage with temperature. This reduces the amount of bias voltage change with heat sink temperature for steady bias current with the output devices shown. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LME49830 13 LME49830 SNAS396D – JANUARY 2008 – REVISED APRIL 2013 www.ti.com BIAS SETTING Setting the bias voltage and resulting output stage bias current is done by adjusting the RBIAS resistor. If temperature compensation is not needed for the bias stage, the bias stage can consist of just a resistor and a sufficient capacitor. The output current from the two BIAS pins is typically 2mA and setting the output stage bias voltage is a simple Ohm's Law calculation. The bias voltage can be set up to 16V for maximum flexibility for use with a wide range of different MOSFET types. The wide range of bias voltage also allows for setting the output stage bias current for different performance levels. OPTIMIZING EXTERNAL COMPONENTS External component values, types and placement are highly design dependent. Values affect performance such as stability, THD+N, noise, slew rate and sonic performance. Optimizing the values can have a significant effect on total audio performance. In a simple output stage design with one MOSFET device per side, as shown in Figure 1, the RE resistors are often considered optional. The RDS(on) of the devices serve a similar purpose. As the output stage is scaled up in number of devices the value of RE will need to be optimized for best performance. Typical values range from 0.1Ω to 0.5Ω. The value of the gate resistors affect stability and slew rate. The capacitance of the output device should be considered when determining the value of the gate resistor. The values shown in Figure 1 represent a typical value or a starting value from which optimization can occur. The compensation capacitor (CC) is one of the most critical external components in value, placement and type. The capacitor should be placed close to the LME49830 and a silver mica type will give good performance. The value of the capacitor will affect slew rate and stability. The highest slew rate possible while also maintaining stability through out the power and frequency range of operation results in the best audio performance. The value shown in Figure 1 should be considered a starting value with optimization done on the bench and in listening testing. The input capacitor (CIN) is shown in Figure 1 for protection against sources that may have a DC bias. For best audio performance, the input capacitor should not be used. Without the input capacitor, any DC bias from the source will be transferred to the load. The feedback capacitor (Ci) is used to set the gain at DC to unity. Because a large value is required for a low frequency -3dB point, the capacitor is an electrolytic type. An additional small value, high quality film capacitor may be used in parallel to improve high frequency sonic performance. If DC offset in the output stage is acceptable without the feedback capacitor, it may be removed but DC gain will now be equal to AC gain. SUPPLY BYPASSING The LME49830 has excellent power supply rejection and does not require a regulated supply. However, to eliminate possible oscillations all op amps and power op amps should have their supply leads bypassed with low inductance capacitors having short leads and located close to the package terminals. Inadequate power supply bypassing will manifest itself by a low frequency oscillation known as “motorboating” or by high frequency instabilities. These instabilities can be eliminated through multiple bypassing utilizing a large tantalum or electrolytic capacitor (10μF minimum) which is used to absorb low frequency variations and a small capacitor (0.1μF) to prevent any high frequency feedback through the power supply lines. These capacitors should be located as close as possible to the supply pins of the LME49830. An additional 0.1μF - 1μF capacitor connected between the VCC to VEE pins of the LME49830 is recommended and each output device should have adequate bypassing at each supply terminal. OUTPUT SENSING The Output Sense pin Osense must be connected to the system output as shown in Figure 1. This connection completes the return path to feedback the output voltage to the mute gain circuitry inside LME49830. If the Osense pin is not connected to the output or it is floated, high voltage generated from the output stage may cause damage to the speaker or load. 14 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LME49830 LME49830 www.ti.com SNAS396D – JANUARY 2008 – REVISED APRIL 2013 Demonstration Board Schematic +VCC LVDD S1 RV 1W 10 k: JP1 JP1 short to use internal LVDD CS5 100 PF LVDD +VCC + CS10 0.1 PF U1 RF 6.8 k: +VCC RM 27 k: CM 47 PF DZ 5V + Mute Osense Mute Control +VCC RGN 120: NOUT N-FET IRFP240 + CS6 100 PF CS9 0.1 PF Power GND LVDD BiasP Ci 220 PF J3 Ri 240: IN- CIN RIN 10 PF 240: RBIAS 10 k: - IN+ CBIAS 22 pF + RS 6.8 k: +VCC CS3 0.1 PF +C CS4 0.1 PF RG 10: CN 22 pF CS2 470 PF -VEE -VEE GND CS13 0.1 PF RQ 12 k: QVBE TIP31C CS7 100 PF + -VEE RSN 10 : CSN 0.1 PF POUT Comp 470 PF + CB1 22 pF RB2 500: BiasM S1 J1 RB1 1.2 k: CC 22 pF CS11 0.1 PF Power GND RL 8: P-FET IRFP9240 RGP 120: CS8 100 PF + -VEE CS12 Power 0.1 PF GND Power GND Figure 33. LME49830 Demo Board with Mute Function Schematic Demonstration Board Layout Figure 34. Top Silkscreen Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LME49830 15 LME49830 SNAS396D – JANUARY 2008 – REVISED APRIL 2013 www.ti.com Figure 35. Top Layer Figure 36. Bottom Silkscreen Layer 16 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LME49830 LME49830 www.ti.com SNAS396D – JANUARY 2008 – REVISED APRIL 2013 Figure 37. Bottom Layer Demonstration Board Bill of Materials Item 1 Description High Perf MOSFET Power Amplifier Input Stage Designator Part Number Quantity Value Supplier Texas Instruments U1 LME49830TB 1 200V, 60mA Mica Capacitor CBIAS, CC, CN, CB1 495–666 4 22pF 3 Aluminum Electrolytic Capacitor Ci EEUFC1C221 1 220μF, 16V Panasonic 4 Metal Polyester Film Cap Cin ECQE1106KF 1 10μF, 100V Panasonic 5 Aluminum Electrolytic Capacitor Cs1, Cs2 EEUFC2A471 2 470μF, 100V Panasonic Metal Polyester Film Cap Cs3, Cs4, Cs9, Cs10, Cs11, Cs12, Cs13 ECQE2104KF 7 0.1μF, 200V Panasonic 7 Zener Diode Dz TZX5V1C 1 5V Vishay 8 RCA Jack INPUT RCA N/A 1 N/A N/A 9 Header, 3-pin J1 N/A 1 N/A N/A 10 Header, 2-Pin J2 N/A 1 N/A N/A 11 Female Bannana Jack - Red +VCC 2142-2 1 N/A Pomona Electronics 12 Female Bannana Jack - Red -VEE 2142-2 1 N/A Pomona Electronics 13 Female Bannana Jack - Black GND 2142-0 1 N/A Pomona Electronics 14 Female Bannana Jack - Black PGND 2142-0 1 N/A Pomona Electronics 15 Female Bannana Jack - Red OUT 2142-2 1 N/A Pomona Electronics 16 Header, 2–Pin JPI, J3 5-826646-0 2 N/A Tyco Electronics 17 HEXFET Power N-MOSFET N-FET IRFP240 1 250V, 15A International Rectifier 18 HEXFET Power P-MOSFET P-FET IRFP9240 1 –200V, –12A International Rectifier 19 Resistor RB1 ERO-25PHF1201 1 1.2kΩ Panasonic 20 Resistor RB2 ERO-25PHF5000 1 500Ω Panasonic 21 Potentiometer RBIAS 63M-T607-103 1 10kΩ Vishay 22 Resistor RF, RS ERO-25PHF6801 2 6.8kΩ Panasonic 23 Resistor RGN, RGP ERG-12SJ121 2 120Ω, 0.5W Panasonic 2 6 RS Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LME49830 17 LME49830 SNAS396D – JANUARY 2008 – REVISED APRIL 2013 Item 18 Description www.ti.com Quantity Value 24 Resistor Ri, RIN Designator ERO-25PHF2400 Part Number 2 240Ω Panasonic 25 Resistor RM ERO-25PHF2702 1 27kΩ Panasonic 26 Resistor RV ERG1SJ103 1 10kΩ, 1W Panasonic 27 Resistor RQ ERO-25PHF1202 1 12kΩ Panasonic 28 Resistor RG ERG-12SJ100 1 10Ω, 0.5W Panasonic 29 Single-Pole, Double-Throw Switch S1 SS40010F-0102-2.5GNN 1 N/A 30 Metal Polyester Film Cap Csn ECQE2104KF 1 0.1μF, 200V Panasonic 31 Resistor Rsn ERO-25PHF10R0 1 10Ω,0.25W Panasonic 32 Heat Sink for N-FET, P-FET, QVBE N/A 150018 1 0.85°C/W 33 Heat Sink Clip for U1 N/A 403-207 1 N/A RS 34 Sil-pad Insulator N/A 169-2177 4 N/A RS 35 Heat Sink for U1–LME49830 N/A 403178 1 10°C/W RS 36 Aluminum Electrolytic Capacitor Cs5, Cs6, Cs7, Cs8 EEUFC2A101 4 100μF, 100V RS 37 Aluminum Electrolytic Capacitor CM EEUFC1E470 1 47μF, 25V 38 Transistor QVBE TIP31C 1 100V Submit Documentation Feedback Supplier Alpha Farnell Newark Panasonic On Semiconductor Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LME49830 LME49830 www.ti.com SNAS396D – JANUARY 2008 – REVISED APRIL 2013 REVISION HISTORY Rev Date 1.0 01/09/08 Initial release. Description 1.01 01/16/08 Deleted the Limit values on Vnoise (EC table).. 1.02 01/22/08 Changed limit values on Vnoise, IB, and IAB. 1.03 01/24/08 Updated the Typical demo ckt diagram and the App ckt diagram. D 04/05/13 Changed layout of National Data Sheet to TI format. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LME49830 19 PACKAGE OPTION ADDENDUM www.ti.com 16-Oct-2015 PACKAGING INFORMATION Orderable Device Status (1) LME49830TB/NOPB LIFEBUY Package Type Package Pins Package Drawing Qty TO-OTHER NDN 15 24 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM Op Temp (°C) Device Marking (4/5) -20 to 75 LME49830 TB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 16-Oct-2015 Addendum-Page 2 MECHANICAL DATA NDN0015A TB15A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2015, Texas Instruments Incorporated