AD AD7980 16-bit, 1 msps, pulsar adc in msop/lfcsp Datasheet

Data Sheet
16-Bit, 1 MSPS, PulSAR ADC in MSOP/LFCSP
AD7980
TYPICAL APPLICATION CIRCUIT
2.5V TO 5V
16-bit resolution with no missing codes
Throughput: 1 MSPS
Low power dissipation
4 mW at 1 MSPS (VDD only)
7 mW at 1 MSPS (total)
70 µW at 10 kSPS
INL: ±0.6 LSB typical, ±1.25 LSB maximum
SINAD: 91.25 dB at 10 kHz
THD: −110 dB at 10 kHz
Pseudo differential analog input range
0 V to VREF with VREF between 2.5 V to 5 V
No pipeline delay
Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V
logic interface
Proprietary serial interface
SPI/QSPI/MICROWIRE™/DSP compatible
Daisy-chain multiple ADCs and busy indicator
10-lead MSOP and 10-lead, 3 mm × 3 mm LFCSP,
same space as SOT-23
Wide operating temperature range: −40°C to +125°C
0 TO VREF
IN+
IN–
2.5V
REF VDD VIO
SDI
AD7980
SCK
SDO
GND
1.8V TO 5.0V
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
CNV
06392-001
FEATURES
Figure 1.
GENERAL DESCRIPTION
The AD7980 1 is a 16-bit, successive approximation, analog-todigital converter (ADC) that operates from a single power supply,
VDD. It contains a low power, high speed, 16-bit sampling ADC
and a versatile serial interface port. On the CNV rising edge, it
samples an analog input, IN+, between 0 V to REF with respect
to a ground sense, IN−. The reference voltage, REF, is applied
externally and can be set independent of the supply voltage,
VDD. Its power scales linearly with throughput.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single,
3-wire bus and provides an optional busy indicator. It is compatible
with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate supply VIO.
APPLICATIONS
Battery-powered equipment
Communications
Automatic test equipment (ATE)
Data acquisitions
Medical instruments
The AD7980 is housed in a 10-lead MSOP or a 10-lead LFCSP
with operation specified from −40°C to +125°C.
1
Protected by U.S. Patent 6,703,961.
Table 1. MSOP, LFCSP 14-/16-/18-/20-Bit Precision SAR ADCs and Integrated SAR ADC µModules
Type
20-Bit
18-Bit
100 kSPS
250 kSPS
400 kSPS to 500 kSPS
AD7989-1 1
AD76911
AD40111
AD76901
AD7989-51
16-Bit
AD7680
AD7683
AD7684
AD7988-11
AD76851
AD76871
AD7694
14-Bit
AD7940
AD79421
AD76861
AD76881
AD76931
AD7988-51
AD79161
AD40081
AD79461
1
≥1000 kSPS
AD40201
AD40031
AD40071
AD79821
AD79841
AD40011
AD40051
AD40001
AD40041
AD79801
AD79831
µModule Data
Acquisition System
ADAQ7980
ADAQ7988
Pin for pin compatible.
Rev. F
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AD7980* PRODUCT PAGE QUICK LINKS
Last Content Update: 11/02/2017
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EVALUATION KITS
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at electronica 2012
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DOCUMENTATION
Application Notes
• AN-742: Frequency Domain Response of SwitchedCapacitor ADCs
• Most Power Efficient Drivers For 12-, 14- And 16-bit A/D
Converters Unveiled
Product Selection Guide
• SAR ADC & Driver Quick-Match Guide
Technical Articles
• Explaining SAR ADC Power Specifications
• AN-931: Understanding PulSAR ADC Support Circuitry
• Exploring Different SAR ADC Analog Input Architectures
• AN-932: Power Supply Sequencing
• Introduction to Dynamic Power Scaling
Data Sheet
• MS-1779: Nine Often Overlooked ADC Specifications
• AD7980-DSCC: Military Data Sheet
• MS-2210: Designing Power Supplies for High Speed ADC
• AD7980-EP: Enhanced Product Data Sheet
• Powering A Precision SAR ADC Using A High Efficiency,
Ultralow Power Switcher in Power Sensitive Applications
• AD7980: 16-Bit, 1 MSPS, PulSAR ADC in MSOP/LFCSP Data
Sheet
Tutorials
Product Highlight
• MT-001: Taking the Mystery out of the Infamous Formula,
"SNR=6.02N + 1.76dB", and Why You Should Care
• [NO TITLE FOUND] Product Highlight
• Lowest-Power 16-Bit ADC Optimizes Portable Designs
(eeProductCenter, 10/4/2006)
User Guides
• UG-340: Evaluation Board for the 10-Lead Family 14-/16-/
18-Bit PulSAR ADCs
• UG-682: 6-Lead SOT-23 ADC Driver for the 8-/10-Lead
Family of 14-/16-/18-Bit PulSAR ADC Evaluation Boards
• MT-002: What the Nyquist Criterion Means to Your
Sampled Data System Design
• MT-031: Grounding Data Converters and Solving the
Mystery of "AGND" and "DGND"
DESIGN RESOURCES
• AD7980 Material Declaration
• PCN-PDN Information
SOFTWARE AND SYSTEMS REQUIREMENTS
• Quality And Reliability
• AD7980 - No-OS Driver for Microchip Microcontroller
Platforms
• Symbols and Footprints
• AD7980 - No-OS Driver for Renesas Microcontroller
Platforms
DISCUSSIONS
View all AD7980 EngineerZone Discussions.
• AD7980 FMC-SDP Interposer & Evaluation Board / Xilinx
KC705 Reference Design
SAMPLE AND BUY
• BeMicro FPGA Project for AD7980 with Nios driver
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TOOLS AND SIMULATIONS
TECHNICAL SUPPORT
• AD7980 IBIS Models
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number.
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AD7980
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Driver Amplifier Choice ........................................................... 16
Applications ....................................................................................... 1
Voltage Reference Input ............................................................ 17
Typical Application Circuit ............................................................. 1
Power Supply............................................................................... 17
General Description ......................................................................... 1
Digital Interface .......................................................................... 17
Revision History ............................................................................... 2
3-Wire CS Mode Without Busy Indicator .............................. 18
Specifications..................................................................................... 3
3-Wire CS Mode with Busy Indicator ..................................... 19
Timing Specifications .................................................................. 5
4-Wire CS Mode Without Busy Indicator .............................. 20
Absolute Maximum Ratings ............................................................ 7
4-Wire CS Mode with Busy Indicator ..................................... 21
ESD Caution .................................................................................. 7
Chain Mode Without Busy Indicator ...................................... 22
Pin Configurations and Function Descriptions ........................... 8
Chain Mode with Busy Indicator ............................................. 23
Terminology ...................................................................................... 9
Applications Information .............................................................. 24
Typical Performance Characteristics ........................................... 10
Layout .......................................................................................... 24
Theory of Operation ...................................................................... 14
Evaluating the Performance of the AD7980 .............................. 24
Circuit Information .................................................................... 14
Outline Dimensions ....................................................................... 25
Converter Operation .................................................................. 14
Ordering Guide .......................................................................... 26
Typical Application Circuit with Multiple Supplies............... 15
Analog Input ............................................................................... 16
REVISION HISTORY
10/2017—Rev. E to Rev. F
Changes to Table 1 ............................................................................ 1
Changes to Figure 5 .......................................................................... 8
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 26
Changes to AC Accuracy Parameter, Table 2 ................................3
Change to Standby Current Parameter, Table 3 ............................4
Changes to Figure 25...................................................................... 13
Changes to Table 8.......................................................................... 15
Changes to Power Supply Section ................................................ 16
7/2016—Rev. D to Rev. E
Changed VIO = 2.3 V to 5.5 V to VIO = 1.71 V to
5.5 V................................................................................. Throughout
Change to Features Section ............................................................. 1
Changes to Conversion Rate Parameter, Table 2 .......................... 3
Changes to VIO Parameter, Table 3 ............................................... 4
Deleted VIO Range Parameter, Table 3 ......................................... 4
Added Table 5; Renumbered Sequentially .................................... 6
Changes to Table 7 ............................................................................ 8
Changes to Table 9 .......................................................................... 16
Changes to Voltage Reference Input Section .............................. 17
Changes to Figure 32 ...................................................................... 18
Changes to Figure 34 ...................................................................... 19
Changes to Figure 36 ...................................................................... 20
Changes to Figure 38 ...................................................................... 21
Changes to Figure 40 ...................................................................... 22
Changes to Figure 42 ...................................................................... 23
8/2013—Rev. B to Rev. C
Change to Features Section ..............................................................1
Changes to Table 3.............................................................................4
Change to Figure 5 ............................................................................7
Added EPAD Row, Table 6 ...............................................................7
Changes to Evaluating the Performance of the
AD7980 Section .............................................................................. 23
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 25
7/2014—Rev. C to Rev. D
Changed QFN (LFCSP) to LFCSP .............................. Throughout
Changes to Features Section and Table 1 ...................................... 1
Added Patent Note, Note 1 .............................................................. 1
6/2009—Rev. A to Rev. B
Changes to Table 5.............................................................................6
Changes to Figure 25...................................................................... 13
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 25
9/2008—Rev. 0 to Rev. A
Deleted QFN Endnote .................................................. Throughout
Changes to Ordering Guide .......................................................... 24
8/2007—Revision 0: Initial Version
Rev. F | Page 2 of 26
Data Sheet
AD7980
SPECIFICATIONS
VDD = 2.5 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, TA = −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Absolute Input Voltage
Analog Input CMRR
Leakage Current at 25°C
Input Impedance
ACCURACY
No Missing Codes
Differential Linearity Error
Integral Linearity Error
Transition Noise
Gain Error, TMIN to TMAX 2
Gain Error Temperature Drift
Zero Error, TMIN to TMAX2
Zero Temperature Drift
Power Supply Sensitivity
THROUGHPUT
Conversion Rate
Transient Response
AC ACCURACY
Dynamic Range
Oversampled Dynamic Range
Signal-to-Noise Ratio, SNR
Spurious-Free Dynamic Range, SFDR
Total Harmonic Distortion, THD
Signal-to-Noise-and-Distortion Ratio,
SINAD
Test Conditions/Comments
Min
16
IN+ − IN−
IN+
IN−
fIN = 100 kHz
Acquisition phase
0
−0.1
−0.1
A Grade
Typ
Max
VREF
VREF + 0.1
+0.1
Min
16
0
−0.1
−0.1
60
1
See the
Analog Input section
16
−1.0
REF = 5 V
REF = 2.5 V
REF = 5 V
REF = 2.5 V
REF = 5 V
REF = 2.5 V
−2.5
−1.0
VDD = 2.5 V ± 5%
VIO ≥ 2.3 V up to 85°C, VIO ≥
3.3 V above 85°C up to 125°C
VIO ≥ 1.71 V, VIO ≤ 3.3 V up
to 125°C
Full-scale step
±0.5
±0.7
±1.5
±1.65
0.75
1.2
±2
±0.35
±0.08
0.54
±0.1
0
VREF = 5 V
VREF = 2.5 V
fO = 10 kSPS
fIN = 10 kHz, VREF = 5 V
fIN = 10 kHz, VREF = 2.5 V
fIN = 10 kHz
fIN = 10 kHz
fIN = 10 kHz, VREF = 5 V
91
86
110
90.5
86.0
−103.5
−101
90
fIN = 10 kHz, VREF = 2.5 V
85.5
B Grade
Typ
Max
VREF
VREF + 0.1
+0.1
60
1
See the
Analog Input section
+2.0
16
−0.9
+2.5
−1.25
+1.0
−0.5
1
0
±0.4
±0.55
±0.6
±0.65
0.6
1.0
±2
±0.35
±0.08
0.54
±0.1
+0.9
+1.25
+0.5
2
Rev. F | Page 3 of 26
V
V
V
dB
nA
Bits
LSB 1
LSB1
LSB1
LSB1
LSB1
LSB1
LSB1
ppm/°C
mV
ppm/°C
LSB1
1
MSPS
833
833
kSPS
290
290
ns
90
92
87
111
91.5
87.0
−110
−114
91
dB 3
dB3
dB3
dB3
dB3
dB3
dB3
dB3
86.5
dB3
LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 µV.
See the Terminology section. These specifications include full temperature range variation, but not the error contribution from the external reference.
3
All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
1
Unit
Bits
AD7980
Data Sheet
VDD = 2.5 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, TA = −40°C to +125°C, unless otherwise noted.
Table 3.
Parameter
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
VIL
VIH
VIL
VIH
IIL
IIH
DIGITAL OUTPUTS
Data Format
Pipeline Delay
Test Conditions/Comments
VOL
VOH
POWER SUPPLIES
VDD
VIO
Standby Current 1, 2
Power Dissipation
Total
ISINK = 500 µA
ISOURCE = −500 µA
VDD Only
REF Only
VIO Only
Energy per Conversion
TEMPERATURE RANGE 3
Specified Performance
Min
Typ
2.4
Max
Unit
5.1
1 MSPS, REF = 5 V
330
V
µA
VDD = 2.5 V
10
2.0
MHz
ns
VIO > 3V
VIO > 3V
VIO ≤ 3V
VIO ≤ 3V
–0.3
0.7 × VIO
–0.3
0.9 × VIO
−1
−1
Serial 16 bits straight binary
Conversion results available immediately
after completed conversion
0.4
VIO − 0.3
2.375
1.71
VDD and VIO = 2.5 V, 25°C
VDD = 2.625 V, VREF = 5 V, VIO = 3 V
10 kSPS throughput
1 MSPS throughput, B grade
1 MSPS throughput, A grade
TMIN to TMAX
0.3 × VIO
VIO + 0.3
0.1 × VIO
VIO + 0.3
+1
+1
2.5
2.625
5.5
0.35
70
7.0
7.0
4
1.7
1.3
7.0
−40
With all digital inputs forced to VIO or GND as required.
2 During the acquisition phase.
3 Contact sales for extended temperature range.
1
Rev. F | Page 4 of 26
9.0
10
+125
V
V
µA
µA
µA
V
V
V
V
μA
µW
mW
mW
mW
mW
mW
nJ/sample
°C
Data Sheet
AD7980
TIMING SPECIFICATIONS
−40°C to +125°C, VDD = 2.37 V to 2.63 V, VIO = 3.3 V to 5.5 V, unless otherwise stated. See Figure 2 and Figure 3 for load conditions.
Table 4.
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Period (Chain Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 3 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
Rev. F | Page 5 of 26
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
Min
500
290
1000
10
Typ
Max
710
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9.5
11
12
14
ns
ns
ns
ns
10
15
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10.5
12
13
15
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
11.5
13
14
16
4.5
4.5
3
tEN
tDIS
tSSDICNV
tHSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
5
2
0
5
5
2
3
15
AD7980
Data Sheet
−40°C to +125°C, VDD = 2.37 V to 2.63 V, VIO = 1.71 V to 3.3 V, unless otherwise stated. See Figure 2 and Figure 3 for load conditions.
Table 5.
Symbol
Min
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
tDIS
tSSDICNV
tHSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
500
290
1.2
10
22
23
6
6
3
Timing Diagrams
500µA
VIH2
VIL2
1.4V
CL
20pF
14
18
21
40
20
5
10
0
5
5
2
3
22
VIH2
VIL2
1FOR
VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V X = 70, AND Y = 30.
VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 3.
2MINIMUM
500µA
IOH
Figure 3. Voltage Levels for Timing
Figure 2. Load Circuit for Digital Interface Timing
Rev. F | Page 6 of 26
Unit
kSPS
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDELAY
tDELAY
06513-002
TO SDO
Max
833
800
Y% VIO1
X% VIO1
IOL
Typ
06392-003
Parameter
Throughput Rate
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
Data Sheet
AD7980
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Analog Inputs
IN+, 1 IN−1 to GND
Supply Voltage
REF, VIO to GND
VDD to GND
VDD to VIO
Digital Inputs to GND
Digital Outputs to GND
Storage Temperature Range
Junction Temperature
Thermal Impedance
(10-Lead MSOP)
θJA
θJC
Lead Temperature
Vapor Phase (60 sec)
Infrared (15 sec)
1
Rating
−0.3 V to VREF + 0.3 V or ±130 mA
−0.3 V to +6 V
−0.3 V to +3 V
+3 V to −6 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
200°C/W
44°C/W
215°C
220°C
See the Analog Input section.
Rev. F | Page 7 of 26
AD7980
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF 1
VDD 2
IN+ 3
AD7980
10
VIO
9
SDI
8 SCK
TOP VIEW
(Not to Scale)
7 SDO
IN– 4
GND 5
6
CNV
IN– 4
GND 5
AD7980
TOP VIEW
(Not to Scale)
9
SDI
8
SCK
7
SDO
6
CNV
NOTES
1. CONNECT THE EXPOSED PAD TO GND.
THIS CONNECTION IS NOT REQUIRED TO
MEET THE ELECTRICAL PERFORMANCES.
06392-004
REF 1
IN+ 3
10 VIO
Figure 4. 10-Lead MSOP Pin Configuration
06392-005
VDD 2
Figure 5. 10-Lead LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
MSOP
LFCSP
1
1
Mnemonic
REF
Type 1
AI
2
3
2
3
VDD
IN+
P
AI
4
4
IN−
AI
5
6
5
6
GND
CNV
P
DI
7
8
7
8
SDO
SCK
DO
DI
9
9
SDI
DI
10
10
VIO
P
Not
applicable
0
EPAD
Not
applicable
Description
Reference Input Voltage. The REF range is from 2.4 V to 5.1 V. It is referred to the GND
pin. This pin should be decoupled closely to the pin with a 10 µF capacitor.
Power Supply.
Analog Input. It is referred to IN−. The voltage range, for example, the difference
between IN+ and IN−, is 0 V to VREF.
Analog Input Ground Sense. To be connected to the analog ground plane or to a remote
sense ground.
Power Supply Ground.
Convert Input. This input has multiple functions. On its leading edge, it initiates the
conversions and selects the interface mode of the device, chain, or CS mode. In CS mode,
it enables the SDO pin when low. In chain mode, the data should be read when CNV is high.
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the device is selected, the conversion result is shifted out
by this clock.
Serial Data Input. This input provides multiple features. It selects the interface mode of
the ADC as follows. Chain mode is selected if SDI is low during the CNV rising edge. In
this mode, SDI is used as a data input to daisy-chain the conversion results of two or
more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a
delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In
this mode, either SDI or CNV can enable the serial output signals when low; if SDI or CNV
is low when the conversion is complete, the busy indicator feature is enabled.
Input/Output Interface Digital Power. Nominally at the same supply as the host interface
(1.8 V, 2.5 V, 3 V, or 5 V).
Exposed Pad. Connect the exposed pad to GND. This connection is not required to meet
the electrical performances.
AI = analog input, DI = digital input, DO = digital output, and P = power.
1
Rev. F | Page 8 of 26
Data Sheet
AD7980
TERMINOLOGY
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 26).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Offset Error
The first transition should occur at a level ½ LSB above analog
ground (38.1 µV for the 0 V to 5 V range). The offset error is
the deviation of the actual transition from that point.
Gain Error
The last transition (from 111 … 10 to 111 … 11) should occur
for an analog voltage 1½ LSB below the nominal full scale
(4.999886 V for the 0 V to 5 V range). The gain error is the
deviation of the actual level of the last transition from the ideal
level after the offset is adjusted out.
Effective Resolution
Effective resolution is calculated as
Effective Resolution = log2(2N/RMS Input Noise)
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in dB. It is measured
with a signal at −60 dBFS to include all noise sources and DNL
artifacts.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in dB.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is expressed in bits and related to SINAD by the
following formula:
Aperture Delay
Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.
ENOB = (SINADdB − 1.76)/6.02
Noise-Free Code Resolution
Noise-free code resolution is the number of bits beyond which
it is impossible to distinctly resolve individual codes. It is
calculated as
Transient Response
Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.
Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise)
and is expressed in bits.
Rev. F | Page 9 of 26
AD7980
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 2.5 V, VREF = 5.0 V, VIO = 3.3 V, unless otherwise noted.
1.25
1.00
POSITIVE INL: +0.33 LSB
NEGATIVE INL: –0.39 LSB
1.00
POSITIVE INL: +0.18 LSB
NEGATIVE INL: –0.21 LSB
0.75
0.75
0.50
0.25
DNL (LSB)
INL (LSB)
0.50
0
–0.25
0.25
0
–0.25
–0.50
–0.50
–0.75
16384
0
32768
49152
–1.00
65536
06392-039
–1.25
–0.75
06392-036
–1.00
0
16384
32768
CODE
Figure 6. Integral Nonlinearity vs. Code, REF = 5 V
1.25
65536
Figure 9. Differential Nonlinearity vs. Code, REF = 5 V
1.00
POSITIVE INL: +0.47 LSB
NEGATIVE INL: –0.26 LSB
1.00
49152
CODE
POSITIVE INL: +0.25 LSB
NEGATIVE INL: –0.22 LSB
0.75
0.75
0.50
0.25
DNL (LSB)
INL (LSB)
0.50
0
–0.25
0.25
0
–0.25
–0.50
–0.50
–0.75
0
16384
32768
49152
–1.00
65536
06392-061
–1.25
–0.75
06392-060
–1.00
0
16384
32768
CODE
Figure 7. Integral Nonlinearity vs. Code, REF = 2.5 V
–20
0
–60
AMPLITUDE (dB of FULL SCALE)
SNR = 91.27dB
THD = –114.63dB
SFDR = 110.10dB
SINAD = 91.25dB
–40
–80
–100
–120
–140
–160
100
200
300
400
fS = 1 MSPS
fIN = 10kHz
–20
06392-038
AMPLITUDE (dB of FULL SCALE)
Figure 10. Differential Nonlinearity vs. Code, REF = 2.5 V
fS = 1 MSPS
fIN = 10kHz
0
65536
500
FREQUENCY (kHz)
SNR = 86.8dB
THD = –111.4dB
SFDR = 105.9dB
SINAD = 86.8dB
–40
–60
–80
–100
–120
–140
–160
–180
06392-058
0
–180
49152
CODE
0
100
200
300
FREQUENCY (kHz)
Figure 8. FFT Plot, REF = 5 V
Figure 11. FFT Plot, REF = 2.5 V
Rev. F | Page 10 of 26
400
500
Data Sheet
AD7980
60k
180k
168591
52212
160k
50k
140k
40k
COUNTS
100k
80k
60k
32417
20k
52710
38751
40k
10k
0
27
0
1201
829
33
2
0
0
06392-042
20k
0
31340
30k
0
7225
0
0
8003 8004 8005 8006 8007 8008 8009 800A 800B 800C 800D 800E 800F
0
6807
539
16
502 14
0
06392-059
COUNTS
120k
0
7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006
CODE IN HEX
CODE IN HEX
Figure 15. Histogram of a DC Input at the Code Center, REF = 2.5 V
Figure 12. Histogram of a DC Input at the Code Center, REF = 5 V
95
70k
94
59691 59404
60k
93
92
40k
SNR (dB)
COUNTS
50k
30k
91
90
89
88
20k
0
2
150
93
06392-043
0
6295
5428
0
3
06392-046
87
10k
86
85
–10
7FFF 8000 8001 8002 8003 8004 8005 8006 8007 8008
–9
–7
–6
–5
–4
–3
–2
–1
0
Figure 16. SNR vs. Input Level
Figure 13. Histogram of a DC Input at the Code Transition, REF = 5 V
100
–95
16
SNR
SINAD
ENOB
115
–100
110
SFDR
85
13
105
–110
100
THD
–115
95
2.75
3.25
3.75
4.25
4.75
12
5.25
06392-044
–120
80
2.25
–125
2.25
90
2.75
3.25
3.75
4.25
4.75
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
Figure 14. SNR, SINAD, and ENOB vs. Reference Voltage
Figure 17. THD, SFDR vs. Reference Voltage
Rev. F | Page 11 of 26
SFDR (dB)
14
–105
85
5.25
06392-047
90
THD (dB)
15
ENOB (BITS)
95
SNR, SINAD (dB)
–8
INPUT LEVEL (dB OF FULL SCALE)
CODE IN HEX
AD7980
Data Sheet
100
–85
–90
–95
–100
THD (dB)
90
–105
–110
85
–115
06392-063
–120
80
10
100
06392-064
SINAD (dB)
95
–125
10
1000
100
FREQUENCY (kHz)
Figure 21. THD vs. Frequency
95
–110
93
–112
91
–114
THD (dB)
89
–116
87
06392-049
–118
–35
–15
5
25
45
65
85
105
–120
–55
125
06392-052
SNR (dB)
Figure 18. SINAD vs. Frequency
85
–55
–35
–15
TEMPERATURE (°C)
85
105
125
85
105
125
1.4
1.4
IVDD
IVDD
1.2
1.0
1.0
CURRENT (mA)
1.2
0.8
0.6
IREF
0.4
0.8
0.6
IREF
0.4
IVIO
IVIO
0.2
2.425
2.475
2.525
VDD VOLTAGE (V)
2.575
0
–55
2.625
06392-053
0.2
06392-050
CURRENT (mA)
5
25
45
65
TEMPERATURE (°C)
Figure 22. THD vs. Temperature
Figure 19. SNR vs. Temperature
0
2.375
1000
FREQUENCY (kHz)
–35
–15
5
25
45
65
TEMPERATURE (°C)
Figure 23. Operating Currents vs. Temperature
Figure 20. Operating Currents vs. Supply
Rev. F | Page 12 of 26
Data Sheet
AD7980
8
7
5
4
3
IVDD + IVIO
2
1
0
–55
06392-054
CURRENT (µA)
6
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
105
125
Figure 24. Power-Down Currents vs. Temperature
Rev. F | Page 13 of 26
AD7980
Data Sheet
THEORY OF OPERATION
IN+
MSB
32,768C
16,384C
LSB
4C
2C
C
SWITCHES CONTROL
SW+
C
BUSY
REF
COMP
GND
32,768C
16,384C
4C
2C
C
CONTROL
LOGIC
OUTPUT CODE
C
LSB
SW+
CNV
06392-011
MSB
IN–
Figure 25. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7980 is a fast, low power, single-supply, precise 16-bit
ADC that uses a successive approximation architecture.
The AD7980 is capable of converting 1,000,000 samples per
second (1 MSPS) and powers down between conversions. When
operating at 10 kSPS, for example, it consumes 70 µW typically,
ideal for battery-powered applications.
The AD7980 provides the user with on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The AD7980 can be interfaced to any 1.8 V to 5 V digital logic
family. It is housed in a 10-lead MSOP or a tiny 10-lead LFCSP
that combines space savings and allows flexible configurations.
It is pin-for-pin compatible with the 18-bit AD7982.
CONVERTER OPERATION
The AD7980 is a successive approximation ADC based on a
charge redistribution DAC. Figure 25 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
input of the comparator are connected to GND via SW+ and
SW−. All independent switches are connected to the analog inputs.
Therefore, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on the IN+ and IN− inputs. When
the acquisition phase is completed and the CNV input goes high,
a conversion phase is initiated. When the conversion phase begins,
SW+ and SW− are opened first. The two capacitor arrays are then
disconnected from the inputs and connected to the GND input.
Therefore, the differential voltage between the inputs IN+ and
IN− captured at the end of the acquisition phase are applied to
the comparator inputs, causing the comparator to become
unbalanced. By switching each element of the capacitor array
between GND and REF, the comparator input varies by binary
weighted voltage steps (VREF/2, VREF/4 … VREF/65,536). The control
logic toggles these switches, starting with the MSB, to bring the
comparator back into a balanced condition. After the completion
of this process, the device returns to the acquisition phase and the
control logic generates the ADC output code and a busy signal
indicator.
Because the AD7980 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Rev. F | Page 14 of 26
Data Sheet
AD7980
Transfer Functions
Table 8. Output Codes and Ideal Input Voltages
The ideal transfer characteristic for the AD7980 is shown in
Figure 26 and Table 8.
Description
FSR − 1 LSB
Midscale + 1 LSB
Midscale
Midscale − 1 LSB
−FSR + 1 LSB
−FSR
111 ... 101
1
2
This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
TYPICAL APPLICATION CIRCUIT WITH MULTIPLE
SUPPLIES
000 ... 010
Figure 27 shows an example of a typical application circuit for
the AD7980 when multiple supplies are available.
000 ... 001
–FSR –FSR + 1LSB
–FSR + 0.5LSB
+FSR – 1 LSB
+FSR – 1.5 LSB
ANALOG INPUT
Figure 26. ADC Ideal Transfer Function
REF1
V+
2.5V
10µF2
100nF
V+
1.8V TO 5V
100nF
20Ω
0 TO VREF
2.7nF
V–
IN+
REF
VDD
VIO
SDI
SCK
AD7980
4
IN–
GND
SDO
3- OR 4-WIRE INTERFACE
CNV
06392-013
000 ... 000
Analog Input
Digital Output Code (Hex)
FFFF1
8001
8000
7FFF
0001
00002
06392-012
ADC CODE (STRAIGHT BINARY)
111 ... 111
111 ... 110
VREF = 5 V
4.999924 V
2.500076 V
2.5 V
2.499924 V
76.3 µV
0V
1SEE
THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
3SEE THE DRIVER AMPLIFIER CHOICE SECTION.
4OPTIONAL FILTER. SEE THE ANALOG INPUT SECTION.
5SEE THE DIGITAL INTERFACE FOR THE MOST CONVENIENT INTERFACE MODE.
2C
REF
Figure 27. Typical Application Circuit with Multiple Supplies
Rev. F | Page 15 of 26
AD7980
Data Sheet
ANALOG INPUT
DRIVER AMPLIFIER CHOICE
Figure 28 shows an equivalent circuit of the input structure of
the AD7980.
Although the AD7980 is easy to drive, the driver amplifier
needs to meet the following requirements:
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN−. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V, because this causes these diodes to become forwardbiased and start conducting current. These diodes can handle a
forward-biased current of 130 mA maximum. For instance,
these conditions could eventually occur when the supplies of
the input buffer (U1) are different from VDD. In such a case
(for example, an input buffer with a short circuit), the current
limitation can be used to protect the device.

The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7980. The noise coming from
the driver is filtered by the 1-pole, low-pass filter of the
AD7980 analog input circuit made by RIN and CIN or by the
external filter, if one is used. Because the typical noise of the
AD7980 is 47.3 μV rms, the SNR degradation due to the
amplifier is
REF
SNRLOSS
D1
IN+
OR IN–
CIN
GND






where:
f–3dB is the input bandwidth in MHz of the AD7980
(10 MHz) or the cutoff frequency of the input filter, if
one is used.
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).
eN is the equivalent input noise voltage of the op amp,
in nV/√Hz.
D2
06392-014
CPIN
RIN


47.3
 20 log 

π
2
2
 47.3  f 3dB (Ne N )
2

Figure 28. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.
During the acquisition phase, the impedance of the analog
inputs (IN+ and IN−) can be modeled as a parallel combination of
capacitor, CPIN, and the network formed by the series connection of
RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically
400 Ω and is a lumped component made up of some serial
resistors and the on resistance of the switches. CIN is typically
30 pF and is mainly the ADC sampling capacitor. During the
conversion phase, where the switches are opened, the input
impedance is limited to CPIN. RIN and CIN make a 1-pole, low-pass
filter that reduces undesirable aliasing effects and limits the noise.

When the source impedance of the driving circuit is low, the
AD7980 can be driven directly. Large source impedances
significantly affect the ac performance, especially THD. The dc
performances are less sensitive to the input impedance. The
maximum source impedance depends on the amount of THD
that can be tolerated. The THD degrades as a function of the
source impedance and the maximum input frequency.
Table 9. Recommended Driver Amplifiers1

For ac applications, the driver should have a THD
performance commensurate with the AD7980.
For multichannel multiplexed applications, the driver
amplifier and the AD7980 analog input circuit must settle
for a full-scale step onto the capacitor array at a 16-bit level
(0.0015%, 15 ppm). In the amplifier data sheet, settling at
0.1% to 0.01% is more commonly specified. This can differ
significantly from the settling time at a 16-bit level and
should be verified prior to driver selection.
Amplifier
ADA4805-1
ADA4807-1
ADA4627-1
ADA4522-1
ADA4500-2
1
Typical Application
Low noise, small size, and low power
Very low noise and high frequency
Precision, low noise, and low input bias current
Precision, zero drift, and EMI enhanced
Precision, rail-to-rail input/output, and zero input
crossover distortion
For the latest recommended drivers, see the product recommendations
listed on the product webpage.
Rev. F | Page 16 of 26
Data Sheet
AD7980
10.000
When REF is driven by a very low impedance source, for example,
a reference buffer using the AD8031 or the ADA4805-1, a ceramic
chip capacitor is appropriate for optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR435 reference.
If desired, a reference-decoupling capacitor value as small as
2.2 μF can be used with a minimal impact on performance,
especially DNL.
IREF
0.100
IVIO
0.010
0.001
10000
100000
SAMPLING RATE (SPS)
1000000
DIGITAL INTERFACE
POWER SUPPLY
The AD7980 uses two power supply pins: a core supply, VDD, and
a digital input/output interface supply, VIO. VIO allows direct
interface with any logic between 1.8 V and 5.0 V. To reduce the
number of supplies needed, VIO and VDD can be tied together.
The AD7980 is independent of power supply sequencing between
VIO and VDD. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 29.
80
Though the AD7980 has a reduced number of pins, it offers
flexibility in its serial interface modes.
The AD7980, when in CS mode, is compatible with SPI, QSPI™,
and digital hosts. This interface can use either a 3-wire or 4-wire
interface. A 3-wire interface using the CNV, SCK, and SDO signals
minimizes wiring connections useful, for instance, in isolated
applications. A 4-wire interface using the SDI, CNV, SCK, and
SDO signals allows CNV, which initiates the conversions, to be
independent of the readback timing (SDI). This is useful in low
jitter sampling or simultaneous sampling applications.
The AD7980, when in chain mode, provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
The mode in which the device operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high, and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is selected.
75
PSRR (dB)
IVDD
Figure 30. Operating Currents vs. Sampling Rate
Regardless, there is no need for an additional lower value ceramic
decoupling capacitor (for example, 100 nF) between the REF
and GND pins.
70
65
In either mode, the AD7980 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be
used as a busy signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a busy indicator,
the user must time out the maximum conversion time prior to
readback.
06392-062
60
55
1.000
06392-055
The AD7980 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
OPERATING CURRENTS (mA)
VOLTAGE REFERENCE INPUT
1
10
100
1000
FREQUENCY (kHz)
Figure 29. PSRR vs. Frequency
The AD7980 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate. This makes the device ideal for low sampling
rate (even of a few Hz) and low battery-powered applications.
The busy indicator feature is enabled in the CS mode if CNV or
SDI is low when the ADC conversion ends (see Figure 34 and
Figure 38). The busy indicator feature is enabled in the chain
mode if SCK is high during the CNV rising edge (see Figure 42).
Rev. F | Page 17 of 26
AD7980
Data Sheet
When CNV goes low, the MSB is output onto SDO. The
remaining data bits are then clocked by subsequent SCK falling
edges. The data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate provided that it has
an acceptable hold time. After the 16th SCK falling edge or
when CNV goes high, whichever is earlier, SDO returns to high
impedance.
3-WIRE CS MODE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7980 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 31, and the corresponding timing is given in
Figure 32.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues until
completion irrespective of the state of CNV. This can be useful,
for instance, to bring CNV low to select other SPI devices, such
as analog multiplexers; however, CNV must be returned high
before the minimum conversion time elapses and then held
high for the maximum conversion time to avoid the generation
of the busy signal indicator. When the conversion is complete,
the AD7980 enters the acquisition phase and powers down.
CONVERT
DIGITAL HOST
CNV
VIO
AD7980
SDI
SDO
DATA IN
06392-015
SCK
CLK
Figure 31. 3-Wire CS Mode Without Busy Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
AQUISITION
tCONV
tACQ
CONVERSION
AQUISITION
tSCK
tSCKL
2
3
14
tHSDO
16
tSCKH
tEN
SDO
15
tDIS
tDSDO
D15
D14
D13
D1
D0
Figure 32. 3-Wire CS Mode Without Busy Indicator Serial Interface Timing (SDI High)
Rev. F | Page 18 of 26
06392-016
1
SCK
Data Sheet
AD7980
If multiple AD7980 devices are selected at the same time, the
SDO output pin handles this contention without damage or
induced latch-up. Meanwhile, it is recommended to keep this
contention as short as possible to limit extra power dissipation.
3-WIRE CS MODE WITH BUSY INDICATOR
This mode is usually used when a single AD7980 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 33, and the
corresponding timing is given in Figure 34.
CONVERT
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum conversion time to
guarantee the generation of the busy signal indicator. When the
conversion is complete, SDO goes from high impedance to low.
With a pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data reading controlled by the
digital host. The AD7980 then enters the acquisition phase and
powers down. The data bits are clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate provided it has an acceptable hold time. After the optional
17th SCK falling edge or when CNV goes high, whichever is
earlier, SDO returns to high impedance.
SDI = 1
VIO
CNV
VIO
SDI
AD7980
DIGITAL HOST
47kΩ
SDO
DATA IN
SCK
IRQ
06392-017
CLK
Figure 33. 3-Wire CS Mode with Busy Indicator
Connection Diagram (SDI High)
tCYC
tCNVH
CNV
AQUISITION
tCONV
tACQ
CONVERSION
AQUISITION
tSCK
tSCKL
1
2
3
15
tHSDO
16
17
tSCKH
tDIS
tDSDO
SDO
D15
D14
D1
D0
Figure 34. 3-Wire CS Mode with Busy Indicator Serial Interface Timing (SDI High)
Rev. F | Page 19 of 26
06392-018
SCK
AD7980
Data Sheet
4-WIRE CS MODE WITHOUT BUSY INDICATOR
When the conversion is complete, the AD7980 enters the
acquisition phase and powers down. Each ADC result can be
read by bringing its SDI input low, which consequently outputs
the MSB onto SDO. The remaining data bits are then clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate provided it has an acceptable hold time. After the 16th SCK
falling edge or when SDI goes high, whichever is earlier, SDO
returns to high impedance and another AD7980 can be read.
This mode is usually used when multiple AD7980 devices are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7980 devices is
shown in Figure 35, and the corresponding timing is given in
Figure 36.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum conversion
time to avoid the generation of the busy signal indicator.
CS2
CS1
CONVERT
CNV
SDI
AD7980
CNV
SDO
SDI
DIGITAL HOST
AD7980
SCK
SDO
SCK
06392-019
DATA IN
CLK
Figure 35. 4-Wire CS Mode Without Busy Indicator Connection Diagram
tCYC
CNV
AQUISITION
tCONV
tACQ
CONVERSION
AQUISITION
tSSDICNV
SDI(CS1)
tHSDICNV
SDI(CS2)
tSCK
tSCKL
1
SDO
tEN
2
tHSDO
D15
3
14
tDSDO
D14
D13
15
16
17
18
30
31
32
tSCKH
tDIS
D1
D0
D15
D14
Figure 36. 4-Wire CS Mode Without Busy Indicator Serial Interface Timing
Rev. F | Page 20 of 26
D1
D0
06392-020
SCK
Data Sheet
AD7980
With a pull-up on the SDO line, this transition can be used as
an interrupt signal to initiate the data readback controlled by
the digital host. The AD7980 then enters the acquisition phase
and powers down. The data bits are clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate provided it has an acceptable hold time. After the optional
17th SCK falling edge or SDI going high, whichever is earlier,
the SDO returns to high impedance.
4-WIRE CS MODE WITH BUSY INDICATOR
This mode is usually used when a single AD7980 is connected
to an SPI-compatible digital host that has an interrupt input,
and it is desired to keep CNV, which is used to sample the analog
input, independent of the signal used to select the data reading.
This requirement is particularly important in applications where
low jitter on CNV is desired.
The connection diagram is shown in Figure 37, and the
corresponding timing is given in Figure 38.
With SDI high, a rising edge on CNV initiates a conversion, selects
the CS mode, and forces SDO to high impedance. In this mode,
CNV must be held high during the conversion phase and the
subsequent data readback (if SDI and CNV are low, SDO is driven
low). Prior to the minimum conversion time, SDI can be used
to select other SPI devices, such as analog multiplexers, but SDI
must be returned low before the minimum conversion time
elapses and then held low for the maximum conversion time to
guarantee the generation of the busy signal indicator. When the
conversion is complete, SDO goes from high impedance to low.
CS1
CONVERT
VIO
CNV
AD7980
SDO
DATA IN
SCK
IRQ
06392-021
SDI
DIGITAL HOST
47kΩ
CLK
Figure 37. 4-Wire CS Mode with Busy Indicator Connection Diagram
tCYC
CNV
AQUISITION
tCONV
tACQ
CONVERSION
AQUISITION
tSSDICNV
SDI
tSCK
tHSDICNV
tSCKL
2
3
15
tHSDO
16
17
tSCKH
tDIS
tDSDO
tEN
SDO
D15
D14
D1
Figure 38. 4-Wire CS Mode with Busy Indicator Serial Interface Timing
Rev. F | Page 21 of 26
D0
06392-022
1
SCK
AD7980
Data Sheet
CHAIN MODE WITHOUT BUSY INDICATOR
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7980 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are clocked by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N clocks are required to
readback the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and, consequently, more AD7980 devices in the chain,
provided the digital host has an acceptable hold time. The
maximum conversion rate may be reduced due to the total
readback time.
This mode can be used to daisy-chain multiple AD7980 devices
on a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multi-converter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7980s is shown in
Figure 39, and the corresponding timing is given in Figure 40.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
CONVERT
CNV
CNV
SDI
AD7980
SDI
SDO
DIGITAL HOST
AD7980
SDO
DATA IN
B
SCK
A
SCK
06392-023
CLK
Figure 39. Chain Mode Without Busy Indicator Connection Diagram
SDIA = 0
tCYC
CNV
AQUISITION
tCONV
tACQ
CONVERSION
AQUISITION
tSCK
tSCKL
tSSCKCNV
SCK
1
2
3
15
tSSDISCK
tHSCKCNV
DA15
DA14
DA13
16
17
18
30
31
32
D A1
DA0
tSCKH
tHSDISC
tEN
SDOA = SDIB
14
D A1
D A0
D B1
DB0
tDSDO
SDOB
DB15
DB14
DB13
DA15
DA14
Figure 40. Chain Mode Without Busy Indicator Serial Interface Timing
Rev. F | Page 22 of 26
06392-024
tHSDO
Data Sheet
AD7980
CHAIN MODE WITH BUSY INDICATOR
subsequent data readback. When all ADCs in the chain have
completed their conversions, the SDO pin of the ADC closest to
the digital host (see the AD7980 ADC labeled C in Figure 41) is
driven high. This transition on SDO can be used as a busy
indicator to trigger the data readback controlled by the digital
host. The AD7980 then enters the acquisition phase and powers
down. The data bits stored in the internal shift register are
clocked out, MSB first, by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 16 × N + 1 clocks are required to
readback the N ADCs. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows a
faster reading rate and, consequently, more AD7980 devices in
the chain, provided the digital host has an acceptable hold time.
This mode can also be used to daisy-chain multiple AD7980
devices on a 3-wire serial interface while providing a busy
indicator. This feature is useful for reducing component count
and wiring connections, for example, in isolated multiconverter
applications or for systems with a limited interfacing capacity.
Data readback is analogous to clocking a shift register.
A connection diagram example using three AD7980 devices is
shown in Figure 41, and the corresponding timing is given in
Figure 42.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
CONVERT
CNV
AD7980
SDI
CNV
SDO
SDI
A
AD7980
CNV
SDO
AD7980
SDI
B
SCK
DIGITAL HOST
SDO
DATA IN
C
SCK
SCK
IRQ
06392-025
CLK
Figure 41. Chain Mode with Busy Indicator Connection Diagram
tCYC
CNV = SDIA
AQUISITION
tCONV
tACQ
CONVERSION
AQUISITION
tSCK
tSCKH
tSSCKCNV
1
tHSCKCNV
2
3
15
16
DA15
DA14
tHSDO
tDSDOSDI
DA13
17
18
19
31
32
33
34
35
tSCKL
tHSDISC
tEN
SDOA = SDIB
SDOB = SDIC
4
tSSDISCK
DA1
47
48
tDSDOSDI
DA0
tDSDOSDI
tDSDO
DB15
DB14
DB13
DB 1
DB0
DA15
DA14
DA1
DA0
DC15
DC14
DC13
DC1
DC0
DB15
DB14
D B1
D B0
tDSDOSDI
SDOC
49
tDSDODSI
Figure 42. Chain Mode with Busy Indicator Serial Interface Timing
Rev. F | Page 23 of 26
DA15
DA14
DA1
D A0
06392-026
SCK
AD7980
Data Sheet
APPLICATIONS INFORMATION
LAYOUT
The printed circuit board (PCB) that houses the AD7980
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. The pinout of
the AD7980, with all its analog signals on the left side and all its
digital signals on the right side, eases this task.
AD7980
At least one ground plane should be used. It can be common or
split between the digital and analog section. In the latter case,
the planes should be joined underneath the AD7980 devices.
06392-028
Avoid running digital lines under the device because these couple
noise onto the die, unless a ground plane under the AD7980 is
used as a shield. Fast switching signals, such as CNV or clocks,
should never run near analog signal paths. Crossover of digital
and analog signals should be avoided.
Figure 43. Example Layout of the AD7980 (Top Layer)
The AD7980 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, ideally right up against, the REF and
GND pins and connecting them with wide, low impedance traces.
Finally, the power supplies VDD and VIO of the AD7980
should be decoupled with ceramic capacitors, typically 100 nF,
placed close to the AD7980 and connected using short and wide
traces to provide low impedance paths and reduce the effect of
glitches on the power supply lines.
EVALUATING THE PERFORMANCE OF THE AD7980
Other recommended layouts for the AD7980 are outlined
in the documentation of the evaluation board for the AD7980
(EVAL-AD7980SDZ). The evaluation board package includes
a fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the
EVAL-SDP-CB1Z.
Rev. F | Page 24 of 26
06392-027
An example of a layout following these rules is shown in
Figure 43 and Figure 44.
Figure 44. Example Layout of the AD7980 (Bottom Layer)
Data Sheet
AD7980
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
1
5.15
4.90
4.65
6
5
PIN 1
IDENTIFIER
0.50 BSC
15° MAX
1.10 MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.15
0.70
0.55
0.40
0.23
0.13
6°
0°
091709-A
0.95
0.85
0.75
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 45.10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
10
6
0.50
0.40
0.30
5
TOP VIEW
0.80
0.75
0.70
SEATING
PLANE
1.74
1.64
1.49
EXPOSED
PAD
0.30
0.25
0.20
1
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 MIN
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.20 REF
Figure 46. 10-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-10-9)
Dimensions shown in millimeters
Contact sales for the non-RoHS compliant version of the device.
Rev. F | Page 25 of 26
02-05-2013-C
PIN 1 INDEX
AREA
AD7980
Data Sheet
ORDERING GUIDE
Model 1, 2, 3
AD7980ARMZ
AD7980ARMZRL7
AD7980BRMZ
AD7980BRMZRL7
AD7980ACPZ-RL
AD7980ACPZ-RL7
AD7980BCPZ-RL
AD7980BCPZ-RL7
AD7980BCPZ-R2
EVAL-AD7980SDZ
EVAL-SDP-CB1Z
1
2
3
Integral
Nonlinearity
±2.5 LSB max
±2.5 LSB max
±1.25 LSB max
±1.25 LSB max
±2.5 LSB max
±2.5 LSB max
±1.25 LSB max
±1.25 LSB max
±1.25 LSB max
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
Evaluation Board
Controller Board
Package
Option
RM-10
RM-10
RM-10
RM-10
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
Branding
C5X
C5X
C5D
C5D
C5X
C5X
C5D
C5D
C5D
Ordering
Quantity
Tube, 50
Reel, 1,000
Tube, 50
Reel, 1,000
Reel, 5,000
Reel, 1,000
Reel, 5,000
Reel, 1,000
Reel, 1,000
Z = RoHS Compliant Part.
The EVAL-AD7980SDZ can be used as a standalone evaluation board or in conjunction with the EVAL-SDP-CB1Z for evaluation/demonstration purposes.
The EVAL-SDP-CB1Z allows a PC to control and communicate with all Analog Devices evaluation boards ending in the SD designator.
©2007–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06392-0-10/17(F)
Rev. F | Page 26 of 26