TI1 DP83846AVHG Dsphyter - single 10/100 ethernet transceiver Datasheet

DP83846A
DP83846A DsPHYTER - Single 10/100 Ethernet Transceiver
Literature Number: SNLS063E
DP83846A DsPHYTER — Single 10/100 Ethernet Transceiver
General Description
Features
The DP83846A is a full feature single Physical Layer
device with integrated PMD sublayers to support both
10BASE-T and 100BASE-TX Ethernet protocols over Category 3 (10 Mb/s) or Category 5 Unsheilded twisted pair
cables.
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Applications
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■ Network Interface Cards
■ PCMCIA Cards
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The DP83846A utilizes on chip Digital Signal Processing
(DSP) technology and digital Phase Lock Loops (PLLs) for
robust performance under all operating conditions,
enhanced noise immunity, and lower external component
count when compared to analog solutions.
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The DP83846A is designed for easy implementation of
10/100 Mb/s Ethernet home or office solutions. It interfaces
to Twisted Pair media via an external transformer. This
device interfaces directly to MAC devices through the IEEE
802.3u standard Media Independent Interface (MII) ensuring interoperability between products from different vendors.
IEEE 802.3 ENDEC, 10BASE-T transceivers and filters
IEEE 802.3u PCS, 100BASE-TX transceivers and filters
IEEE 802.3 compliant Auto-Negotiation
Output edge rate control eliminates external filtering for
Transmit outputs
BaseLine Wander compensation
5V/3.3V MAC interface
IEEE 802.3u MII (16 pins/port)
LED support (Link, Rx, Tx, Duplex, Speed, Collision)
Single register access for complete PHY status
10/100 Mb/s packet loopback BIST (Built in Self Test)
Low-power 3.3V, 0.35um CMOS technology
Power consumption < 495mW (typical)
5V tolerant I/Os
80-pin LQFP package (12w) x (12l) x (1.4h) mm
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DP83846A
10/100 Mb/s
Ethernet MAC
DsPHYTER
MII
25 MHz
Clock
Magnetics
System Diagram
RJ-45
10BASE-T
or
100BASE-TX
Status
LEDs
Typical DsPHYTER application
©2002 National Semiconductor Corporation
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DP83846A DsPHYTER — Single 10/100 Ethernet Transceiver
May 2002
DP83846A
RX_CLK
RXD[3:0]
RX_DV
RX_ER
CRS
COL
MDC
MDIO
TX_EN
SERIAL
MANAGEMENT
TX_ER
TX_CLK
HARDWARE
CONFIGURATION
PINS
(AN_EN, AN0, AN1)
(PAUSE_EN)
(LED_CFG, PHYAD)
TXD[3:0]
MII
MII INTERFACE/CONTROL
RX_CLK
TX_DATA
TRANSMIT CHANNELS &
STATE MACHINES
PARALLEL TO
SERIAL
SCRAMBLER
NRZ TO NRZI
ENCODER
BINARY TO
MLT-3
ENCODER
10 Mb/s
REGISTERS
MII
PHY ADDRESS
NRZ TO
MANCHESTER
ENCODER
RECEIVE CHANNELS &
STATE MACHINES
AUTO
NEGOTIATION
BASIC MODE
CONTROL
100 Mb/s
4B/5B
DECODER
CODE GROUP
ALIGNMENT
10 Mb/s
MANCHESTER
TO NRZ
DECODER
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100 Mb/s
4B/5B
ENCODER
RX_CLK
TX_CLK
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TX_DATA
RX_DATA
RX_DATA
PCS CONTROL
LINK PULSE
GENERATOR
CLOCK
RECOVERY
SERIAL TO
PARALLEL
10BASE-T
100BASE-TX
DESCRAMBLER
NRZI TO NRZ
DECODER
TRANSMIT
FILTER
LINK PULSE
DETECTOR
CLOCK
RECOVERY
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AUTO-NEGOTIATION
STATE MACHINE
10/100 COMMON
OUTPUT DRIVER
O
CLOCK
GENERATION
MLT-3 TO
BINARY
DECODER
ADAPTIVE
BLW
AND EQ
COMP
RECEIVE
FILTER
SMART
SQUELCH
10/100 COMMON
INPUT BUFFER
LED
DRIVERS
RD±
LEDS
TD±
SYSTEM CLOCK
REFERENCE
Figure 1. Block Diagram of the 10/100 DSP based core.
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DP83846A
3.0
4.0
5.0
6.0
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7.0
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2.0
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2
10 Mb/s and 100 Mb/s PMD Interface . . . . . . . . . . 6
1.3
Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4
Special Connections . . . . . . . . . . . . . . . . . . . . . . . 6
1.5
LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.6
Strapping Options/Dual Purpose Pins . . . . . . . . . . 7
1.7
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.8
Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . 9
1.9
Package Pin Assignments . . . . . . . . . . . . . . . . . . 10
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1
Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2
PHY Address and LEDs . . . . . . . . . . . . . . . . . . . 12
2.3
LED INTERFACES . . . . . . . . . . . . . . . . . . . . . . . 13
2.4
Half Duplex vs. Full Duplex . . . . . . . . . . . . . . . . . 13
2.5
MII Isolate Mode . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6
Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7
BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
802.3u MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2
100BASE-TX TRANSMITTER . . . . . . . . . . . . . . . 16
3.3
100BASE-TX RECEIVER . . . . . . . . . . . . . . . . . . 20
3.4
10BASE-T TRANSCEIVER MODULE . . . . . . . . . 23
3.5
TPI Network Circuit . . . . . . . . . . . . . . . . . . . . . . . 24
3.6
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.7
Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . 26
Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1
Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2
Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2
Extended Registers . . . . . . . . . . . . . . . . . . . . . . . 37
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . 44
6.1
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.2
PGM Clock Timing . . . . . . . . . . . . . . . . . . . . . . . 47
6.3
MII Serial Management Timing . . . . . . . . . . . . . . 47
6.4
100 Mb/s Timing . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.5
10 Mb/s Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.6
Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.7
Isolation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 60
bs
1.0
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Table of Contents
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DP83846A
COL
TXD_3
TXD_2
IO_VDD
IO_GND
TXD_1
TXD_0
IO_GND
TX_EN
TX_CLK
TX_ER
CORE_VDD
CORE_GND
RESERVED
RX_ER/PAUSE_EN
RX_CLK
RX_DV
IO_VDD
IO_GND
RXD_0
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
Connection Diagram
CRS/LED_CFG
61
40
62
39
63
38
IO_GND
64
IO_VDD
65
X2
66
X1
67
37
36
35
34
69
RESERVED
70
RESERVED
71
CORE_VDD
72
CORE_GND
73
RESERVED
74
RESERVED
75
SUB_GND
76
31
MDC
MDIO
IO_VDD
IO_GND
LED_DPLX/PHYAD0
LED_COL/PHYAD1
LED_GDLNK/PHYAD2
30
LED_TX/PHYAD3
29
LED_RX/PHYAD4
28
LED_SPEED
27
AN_EN
22
RESERVED
80
21
RESERVED
RESERVED
SUB_GND
ANA_GND
TD-
TD+
ANA_GND
ANA_VDD
ANA_GND
ANA_VDD
10
RD+
RD-
9
8
ANA_GND
RESERVED
7
6
ANA_VDD
ANA_GND
5
4
RESERVED
3
ANA_VDD
RESERVED
ANA_GND
O
20
79
19
CORE_GND
18
23
17
78
16
CORE_VDD
15
24
14
77
13
AN_0
12
25
bs
AN_1
1
RESERVED
RXD_3
26
2
SUB_GND
32
DP83846A
DSPHYTER
RBIAS
RESERVED
RESERVED
33
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68
RESERVED
11
RESERVED
RXD_2
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RESET
RESERVED
RXD_1
Plastic Quad Flat Pack (LQFP)
Order Number DP83846AVHG
NS Package Number VHG-80A
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The DP83846A pins are classified into the following interface categories (each interface is described in the sections
that follow):
Note: All DP83846A signal pins are I/O cells regardless of
the particular use. Below definitions define the functionality
of the I/O cells for each pin.
— MII Interface
— 10/100 Mb/s PMD Interface
— Clock Interface
— Special Connect Pins
— LED Interface
— Strapping Options/Dual Function pins
— Reset
— Power and Ground pins
Note: Strapping pin option (BOLD) Please see Section 1.6
for strap definitions.
Type: I
Type: O
Type: I/O
Type OD
Type: PD,PU
Type: S
Inputs
Outputs
Input/Output
Open Drain
Internal Pulldown/Pullup
Strapping Pin (All strap pins except PHYAD[0:4] have internal pull-ups or pulldowns. If the default strap value is needed
to be changed then an external 5 kΩ resistor
should be used. Please see Table 1.6 on
page 7 for details.)
Type
LQFP Pin #
MDC
I
37
MDIO
I/O, OD
36
MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the station management entity or the PHY. This pin requires a 1.5 kΩ pullup resistor.
O, S
61
CARRIER SENSE: Asserted high to indicate the presence of carrier
due to receive or transmit activity in 10BASE-T or 100BASE-TX Half
Duplex Modes, while in full duplex mode carrier sense is asserted to
indicate the presence of carrier due only to receive activity.
O
60
COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10
Mb/s and 100 Mb/s Half Duplex Modes.
CRS/LED_CFG
MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO
management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is
25 MHz with no minimum clock rate.
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COL
Description
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Signal Name
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1.1 MII Interface
While in 10BASE-T Half Duplex mode with Heartbeat enabled this
pin are also asserted for a duration of approximately 1µs at the end
of transmission to indicate heartbeat (SQE test).
In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal
is always logic 0. There is no heartbeat function during 10 Mb/s full
duplex operation.
O
O
TX_CLK
51
TRANSMIT CLOCK: 25 MHz Transmit clock outputs in 100BASETX mode or 2.5 MHz in 10BASE-T mode derived from the 25 MHz
reference clock.
TXD[3]
TXD[2]
TXD[1]
TXD[0]]
I
TX_EN
I
52
TRANSMIT ENABLE: Active high input indicates the presence of
valid nibble data on data inputs, TXD[3:0] for both 100 Mb/s or 10
Mb/s nibble mode.
TX_ER
I
50
TRANSMIT ERROR: In 100MB/s mode, when this signal is high and
the corresponding TX_EN is active the HALT symbol is substituted
for data.
59, 58, 55, 54 TRANSMIT DATA: Transmit data MII input pins that accept nibble
data synchronous to the TX_CLK (2.5 MHz in 10BASE-T Mode or
25 MHz in 100BASE-TX mode.
In 10 Mb/s this input is ignored.
RX_CLK
O, PU
45
RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks
for 100BASE-TX mode and 2.5 MHz for 10BASE-T nibble mode.
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DP83846A
1.0 Pin Descriptions
RXD[3]
Type
LQFP Pin #
O, PU/PD
RXD[2]
RXD[1]
RXD[0]
RX_ER/PAUSE_EN
RX_DV
Description
38, 39, 40, 41 RECEIVE DATA: Nibble wide receive data (synchronous to corresponding RX_CLK, 25 MHz for 100BASE-TX mode, 2.5 MHz for
10BASE-T nibble mode). Data is driven on the falling edge of
RX_CLK. RXD[2] has an internal pulldown resistor. The remaining
RXD pins have pullups.
S, O, PU
46
RECEIVE ERROR: Asserted high to indicate that an invalid symbol
has been detected within a received packet in 100BASE-TX mode.
O
44
RECEIVE DATA VALID: Asserted high to indicate that valid data is
present on the corresponding RXD[3:0] for nibble mode. Data is driven on the falling edge of the corresponding RX_CLK.
1.2 10 Mb/s and 100 Mb/s PMD Interface
Type
LQFP Pin #
Description
O
16, 17
Differential common driver transmit output. These differential outputs are configurable to either 10BASE-T or 100BASE-TX signaling.
TD+, TD-
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Signal Name
The DP83846A will automatically configure the common driver outputs for the proper signal type as a result of either forced configuration or Auto-Negotiation.
RD-, RD+
I
10, 11
Differential receive input. These differential inputs can be configured
to accept either 100BASE-TX or 10BASE-T signaling.
1.3 Clock Interface
Signal Name
X2
Type
LQFP Pin #
Description
I
67
REFERENCE CLOCK INPUT 25 MHz: This pin is the primary
clock reference input for the DP83846A and must be connected to
a 25 MHz 0.005% (±50 ppm) clock source. The DP83846A supports CMOS-level oscillator sources.
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X1
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The DP83846A will automatically configure the receive inputs to accept the proper signal type as a result of either forced configuration
or Auto-Negotiation.
O
66
REFERENCE CLOCK OUTPUT 25 MHz: This pin is the primary
clock reference output.
Type
LQFP Pin #
Description
3
Bias Resistor Connection. A 9.31 kΩ 1% resistor should be connected from RBIAS to ANA_GND.
1.4 Special Connections
O
Signal Name
RBIAS
RESERVED
I
I/O
1, 5, 8, 20, RESERVED: These pins must be left unconnected.
21, 22, 47,
63, 68, 69,
70, 71, 74,
75, 77, 78,
80
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DP83846A
Signal Name
Type
LQFP Pin #
LED_DPLX/PHYAD0
Signal Name
S, O
33
FULL DUPLEX LED STATUS: Indicates Full-Duplex status.
LED_COL/PHYAD1
S, O
32
COLLISION LED STATUS: Indicates Collision activity in Half Duplex
mode.
LED_GDLNK/PHYAD2
S, O
31
GOOD LINK LED STATUS: Indicates Good Link Status for 10BASET and 100BASE-TX.
LED_TX/PHYAD3
S, O
30
TRANSMIT LED STATUS: Indicates transmit activity. LED is on for
activity, off for no activity.
LED_RX/PHYAD4
S, O
29
RECEIVE LED STATUS: Indicates receive activity. LED is on for activity, off for no activity.
O
28
SPEED LED STATUS: Indicates link speed; high for 100 Mb/s, low
for 10 Mb/s.
LED_SPEED
Description
1.6 Strapping Options/Dual Purpose Pins
LED_DPLX/PHYAD0
LED_COL/PHYAD1
LED_GDLNK/PHYAD2
LED_TX/PHYAD3
LED_RX/PHYAD4
Type
LQFP Pin #
Description
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Signal Name
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tors will set the default value. Please note that the
PHYAD[0:4] pins have no internal pull-ups or pull-downs
A 5 kΩ resistor should be used for pull-down or pull-up to and they must be strapped. Since these pins may have
change the default strap option. If the default option is alternate functions after reset is deasserted, they should
required, then there is no need for external pull-up or pull not be connected directly to Vcc or GND.
down resistors, since the internal pull-up or pull down resis-
S, O
33
32
31
30
29
PHY ADDRESS [4:0]: The DP83846A provides five PHY address
pins, the state of which are latched into the PHYCTRL register at
system Hardware-Reset.
The DP83846A supports PHY Address strapping values 0
(<00000>) through 31 (<11111>). PHY Address 0 puts the part
into the MII Isolate Mode. The MII isolate mode must be selected
by strapping Phy Address 0; changing to Address 0 by register
write will not put the Phy in the MII isolate mode.
O
bs
The status of these pins are latched into the PHY Control Register
during Hardware-Reset. (Please note these pins have no internal
pull-up or pull-down resistors and they must be strapped high or low
using 5 kΩ resistors.)
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DP83846A
1.5 LED Interface
AN_EN
Type
S, O, PU
LQFP Pin #
Description
27
Auto-Negotiation Enable: When high enables Auto-Negotiation
with the capability set by ANO and AN1 pins. When low, puts the
part into Forced Mode with the capability set by AN0 and AN1 pins.
AN_1
26
AN_0
25
AN0 / AN1: These input pins control the forced or advertised operating mode of the DP83846A according to the following table. The
value on these pins is set by connecting the input pins to GND (0)
or VCC (1) through 5 kΩ resistors. These pins should NEVER be
connected directly to GND or VCC.
The value set at this input is latched into the DP83846A at Hardware-Reset.
The float/pull-down status of these pins are latched into the Basic
Mode Control Register and the Auto_Negotiation Advertisement
Register during Hardware-Reset. After reset is deasserted, these
pins may switch to outputs so if pull-ups or pull-downs are implemented, they should be pulled through a 5kΩ resistor.
The default is 111 since these pins have pull-ups.
AN0
Forced Mode
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AN_EN AN1
0
0
10BASE-T, Half-Duplex
0
0
1
10BASE-T, Full-Duplex
0
1
0
100BASE-TX, Half-Duplex
0
1
1
100BASE-TX, Full-Duplex
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0
AN_EN AN1
AN0
Advertised Mode
1
0
0
10BASE-T, Half/Full-Duplex
1
0
1
100BASE-TX, Half/Full-Duplex
1
1
0
10BASE-T Half-Duplex
1
1
1
10BASE-T, Half/Full-Duplex
100BASE-TX, Half-Duplex
100BASE-TX, Half/Full-Duplex
S, O, PU
46
PAUSE ENABLE: This strapping option allows advertisement of
whether or not the DTE(MAC) has implemented both the optional
MAC control sublayer and the pause function as specified in clause
31 and annex 31B of the IEEE 802.3x specification (Full Duplex
Flow Control).
bs
RX_ER/PAUSE_EN
O
When left floating the Auto-Negotiation Advertisement Register will
be set to 0, indicating that Full Duplex Flow Control is not supported.
CRS/LED_CFG
S, O,
PU
When tied low through a 5 kΩ, the Auto-Negotiation Advertisement
Register will be set to 1, indicating that Full Duplex Flow Control is
supported.
The float/pull-down status of this pin is latched into the Auto-Negotiation Advertisement Register during Hardware-Reset.
61
LED CONFIGURATION: This strapping option defines the polarity
and function of the FDPLX LED pin.
See Section 2.3 for further descriptions of this strapping option.
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DP83846A
Signal Name
DP83846A
1.7 Reset
Signal Name
Type
LQFP
Pin #
LLP
Pin #
Description
I
62
46
RESET: Active Low input that initializes or re-initializes the
DP83846A. Asserting this pin low for at least 160 µs will
force a reset process to occur which will result in all internal
registers re-initializing to their default states as specified for
each bit in the Register Block section and all strapping options are re-initialized.
RESET
1.8 Power and Ground Pins
Signal Name
LQFP Pin #
Description
TTL/CMOS INPUT/OUTPUT SUPPLY
35, 43, 57, 65
I/O Supply
IO_GND
34, 42, 53, 56, 64
I/O Ground
INTERNAL SUPPLY PAIRS
CORE_VDD
24, 49, 72
CORE_GND
23, 48, 73
ANALOG SUPPLY PINS
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IO_VDD
Digital Core Supply
Digital Core Ground
4, 7, 12, 14
ANA_GND
2, 6, 9, 13, 15, 18,
Analog Ground
19, 76, 79
Bandgap Substrate connection
SUBSTRATE GROUND
O
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SUB_GND
Analog Supply
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ANA_VDD
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DP83846A
1.9 Package Pin Assignments
LQFP Pin # Pin Name
LQFP Pin # Pin Name
RESERVED
41
RXD_0
2
ANA_GND
42
IO_GND
3
RBIAS
43
IO_VDD
4
ANA_VDD
44
RX_DV
5
RESERVED
45
RX_CLK
6
ANA_GND
46
RX_ER/PAUSE_EN
7
ANA_VDD
47
RESERVED
8
RESERVED
48
CORE_GND
9
ANA_GND
49
CORE_VDD
10
RD-
50
TX_ER
11
RD+
ANA_VDD
13
ANA_GND
14
ANA_VDD
15
ANA_GND
16
TD+
17
TD-
18
ANA_GND
19
SUB_GND
20
RESERVED
RESERVED
22
RESERVED
bs
21
51
TX_CLK
52
TX_EN
53
IO_GND
54
TXD_0
55
TXD_1
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12
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1
56
IO_GND
57
IO_VDD
58
TXD_2
59
TXD_3
60
COL
61
CRS/LED_CFG
62
RESET
63
RESERVED
23
CORE_GND
24
CORE_VDD
64
IO_GND
25
AN_0
65
IO_VDD
26
AN_1
66
X2
27
AN_EN
67
X1
28
LED_SPEED
RESERVED
LED_RX /PHYAD4
69
RESERVED
30
LED_TX /PHYAD3
70
RESERVED
31
LED_GDLNK/PHYAD2
71
RESERVED
32
LED_COL /PHYAD1
72
CORE_VDD
33
LED_FDPLX /PHYAD0
73
CORE_GND
34
IO_GND
74
RESERVED
35
IO_VDD
75
RESERVED
36
MDIO
76
SUB_GND
37
MDC
77
RESERVED
38
RXD_3
78
RESERVED
39
RXD_2
79
SUB_GND
40
RXD_1
80
RESERVED
O
68
29
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This section includes information on the various configuration options available with the DP83846A. The configuration options described below include:
—
—
—
—
—
—
—
Table 1. Auto-Negotiation Modes
AN_EN
Device Configuration
Auto-Negotiation
PHY Address and LEDs
Half Duplex vs. Full Duplex
Isolate mode
Loopback mode
BIST
2.1 Auto-Negotiation
AN0
Forced Mode
0
0
0
10BASE-T, Half-Duplex
0
0
1
10BASE-T, Full-Duplex
0
1
0
100BASE-TX, Half-Duplex
0
1
1
100BASE-TX, Full-Duplex
AN_EN
AN1
AN0
1
0
0
10BASE-T, Half/Full-Duplex
1
0
1
100BASE-TX, Half/Full-Duplex
1
1
0
Advertised Mode
10BASE-T Half-Duplex
100BASE-TX, Half-Duplex
1
1
1
10BASE-T, Half/Full-Duplex
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100BASE-TX, Half/Full-Duplex
2.1.2 Auto-Negotiation Register Control
When Auto-Negotiation is enabled, the DP83846A transmits the abilities programmed into the Auto-Negotiation
Advertisement register (ANAR) at address 04h via FLP
Bursts. Any combination of 10 Mb/s, 100 Mb/s, HalfDuplex, and Full Duplex modes may be selected. The
BMCR provides software with a mechanism to control the
operation of the DP83846A. The AN0 and AN1 pins do not
affect the contents of the BMCR and cannot be used by
software to obtain status of the mode selected. Bits 1 & 2 of
the PHYSTS register are only valid if Auto-Negotiation is
disabled or after Auto-Negotiation is complete. The AutoNegotiation protocol compares the contents of the
ANLPAR and ANAR registers and uses the results to automatically configure to the highest performance protocol
between the local and far-end port. The results of AutoNegotiation (Auto-Neg Complete, Duplex Status and
Speed) may be accessed in the PHYSTS register.
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The Auto-Negotiation function provides a mechanism for
exchanging configuration information between two ends of
a link segment and automatically selecting the highest performance mode of operation supported by both devices.
Fast Link Pulse (FLP) Bursts provide the signalling used to
communicate Auto-Negotiation abilities between two
devices at each end of a link segment. For further detail
regarding Auto-Negotiation, refer to Clause 28 of the IEEE
802.3u specification. The DP83846A supports four different Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full
Duplex, 100 Mb/s Half Duplex, and 100 Mb/s Full Duplex),
so the inclusion of Auto-Negotiation ensures that the highest performance protocol will be selected based on the
advertised ability of the Link Partner. The Auto-Negotiation
function within the DP83846A can be controlled either by
internal register access or by the use of the AN_EN, AN1
and AN0 pins.
AN1
2.1.1 Auto-Negotiation Pin Control
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The state of AN_EN, AN0 and AN1 determines whether the
DP83846A is forced into a specific mode or Auto-Negotiation will advertise a specific ability (or set of abilities) as
given in Table 1. These pins allow configuration options to
be selected without requiring internal register access.
The state of AN_EN, AN0 and AN1, upon power-up/reset,
determines the state of bits [8:5] of the ANAR register.
Auto-Negotiation Priority Resolution:
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— (1) 100BASE-TX Full Duplex (Highest Priority)
— (2) 100BASE-TX Half Duplex
The Auto-Negotiation function selected at power-up or
reset can be changed at any time by writing to the Basic — (3) 10BASE-T Full Duplex
Mode Control Register (BMCR) at address 00h.
— (4) 10BASE-T Half Duplex (Lowest Priority)
The Basic Mode Control Register (BMCR) at address 00h
provides control for enabling, disabling, and restarting the
Auto-Negotiation process. When Auto-Negotiation is disabled the Speed Selection bit in the BMCR controls switching between 10 Mb/s or 100 Mb/s operation, and the
Duplex Mode bit controls switching between full duplex
operation and half duplex operation. The Speed Selection
and Duplex Mode bits have no effect on the mode of operation when the Auto-Negotiation Enable bit is set.
The Basic Mode Status Register (BMSR) indicates the set
of available abilities for technology types, Auto-Negotiation
ability, and Extended Register Capability. These bits are
permanently set to indicate the full functionality of the
DP83846A (only the 100BASE-T4 bit is not set since the
DP83846A does not support that function).
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DP83846A
2.0 Configuration
data and link pulse activity until the break_link_timer
expires (~1500 ms). Consequently, the Link Partner will go
into link fail and normal Auto-Negotiation resumes. The
DP83846A will resume Auto-Negotiation after the
break_link_timer has expired by issuing FLP (Fast Link
Pulse) bursts.
— Whether Auto-Negotiation is complete
— Whether the Link Partner is advertising that a remote
fault has occurred
— Whether valid link has been established
— Support for Management Frame Preamble suppression
The Auto-Negotiation Advertisement Register (ANAR) indicates the Auto-Negotiation abilities to be advertised by the
DP83846A. All available abilities are transmitted by default,
but any ability can be suppressed by writing to the ANAR.
Updating the ANAR to suppress an ability is one way for a
management agent to change (force) the technology that is
used.
2.1.5 Enabling Auto-Negotiation via Software
2.2 PHY Address and LEDs
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— Whether the Link Partner supports the Next Page function
— Whether the DP83846A supports the Next Page function
— Whether the current page being exchanged by Auto-Negotiation has been received
— Whether the Link Partner supports Auto-Negotiation
te
It is important to note that if the DP83846A has been initialized upon power-up as a non-auto-negotiating device
(forced technology), and it is then required that Auto-Negotiation or re-Auto-Negotiation be initiated via software,
bit 12 (Auto-Negotiation Enable) of the Basic Mode Control
Register must first be cleared and then set for any AutoThe Auto-Negotiation Link Partner Ability Register Negotiation function to take effect.
(ANLPAR) at address 05h is used to receive the base link
code word as well as all next page code words during the 2.1.6 Auto-Negotiation Complete Time
negotiation. Furthermore, the ANLPAR will be updated to Parallel detection and Auto-Negotiation take approximately
either 0081h or 0021h for parallel detection to either 100 2-3 seconds to complete. In addition, Auto-Negotiation with
Mb/s or 10 Mb/s respectively.
next page should take approximately 2-3 seconds to comThe Auto-Negotiation Expansion Register (ANER) indi- plete, depending on the number of next pages sent.
cates additional Auto-Negotiation status. The ANER pro- Refer to Clause 28 of the IEEE 802.3u standard for a full
vides status on:
description of the individual timers related to Auto-Negotiation.
— Whether a Parallel Detect Fault has occurred
The 5 PHY address inputs pins are shared with the LED
pins as shown below.
Table 2. PHY Address Mapping
2.1.3 Auto-Negotiation Parallel Detection
bs
The DP83846A supports the Parallel Detection function as
defined in the IEEE 802.3u specification. Parallel Detection
requires both the 10 Mb/s and 100 Mb/s receivers to monitor the receive signal and report link status to the AutoNegotiation function. Auto-Negotiation uses this information to configure the correct technology in the event that the
Link Partner does not support Auto-Negotiation but is
transmitting link signals that the 100BASE-TX or 10BASET PMAs recognize as valid link signals.
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If the DP83846A completes Auto-Negotiation as a result of
Parallel Detection, bits 5 and 7 within the ANLPAR register
will be set to reflect the mode of operation present in the
Link Partner. Note that bits 4:0 of the ANLPAR will also be
set to 00001 based on a successful parallel detection to
indicate a valid 802.3 selector field. Software may determine that negotiation completed via Parallel Detection by
reading a zero in the Link Partner Auto-Negotiation Able bit
once the Auto-Negotiation Complete bit is set. If configured
for parallel detect mode and any condition other than a single good link occurs then the parallel detect fault bit will set.
Pin #
PHYAD Function
LED Function
33
PHYAD0
Duplex
32
PHYAD1
COL
31
PHYAD2
Good Link
30
PHYAD3
TX Activity
29
PHYAD4
RX Activity
28
n/a
Speed
The DP83846A can be set to respond to any of 32 possible
PHY addresses. Each DP83846A or port sharing an MDIO
bus in a system must have a unique physical address.
Refer to Section 3.1.4, PHY Address Sensing section for
more details.
The state of each of the PHYAD inputs latched into the
PHYCTRL register bits [4:0] at system power-up/reset
depends on whether a pull-up or pull-down resistor has
been installed for each pin. For further detail relating to the
latch-in timing requirements of the PHY Address pins, as
well as the other hardware configuration pins, refer to the
Reset summary in Section 4.0.
2.1.4 Auto-Negotiation Restart
Since the PHYAD strap options share the LED output pins,
Once Auto-Negotiation has completed, it may be restarted the external components required for strapping and LED
at any time by setting bit 9 (Restart Auto-Negotiation) of the usage must be considered in order to avoid contention.
BMCR to one. If the mode configured by a successful Auto- Specifically, when the LED outputs are used to drive LEDs
Negotiation loses a valid link, then the Auto-Negotiation directly, the active state of each output driver is dependent
process will resume and attempt to determine the configu- on the logic level sampled by the corresponding PHYAD
ration for the link. This function ensures that a valid config- input upon power-up/reset. For example, if a given PHYAD
input is resistively pulled low then the corresponding output
uration is maintained if the cable becomes disconnected.
A renegotiation request from any entity, such as a manage- will be configured as an active high driver. Conversely, if a
ment agent, will cause the DP83846A to halt any transmit given PHYAD input is resistively pulled high, then the corresponding output will be configured as an active low
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DP83846A
The BMSR also provides status on:
LED_FDPLX
LED_COL
LED_GDLNK
LED_TX
LED_RX
1kΩ
te
10kΩ
1kΩ
10kΩ
1kΩ
10kΩ
1kΩ
10kΩ
1kΩ
10kΩ
PHYAD4= 0 PHYAD3 = 0 PHYAD2 = 0 PHYAD1 = 1 PHYAD0 = 1
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VCC
Figure 2. PHYAD Strapping and LED Loading Example
2.3 LED INTERFACES
10 Mb/s Link is established as a result of the reception of at
least seven consecutive normal Link Pulses or the reception of a valid 10BASE-T packet. This will cause the assertion of GD_LINK. GD_LINK will deassert in accordance
with the Link Loss Timer as specified in IEEE 802.3.
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The DP83846A has 6 Light Emitting Diode (LED) outputs,
each capable to drive a maximum of 10 mA, to indicate the
status of Link, Transmit, Receive, Collision, Speed, and
Full/Half Duplex operation. The LED_CFG strap option is
used to configure the LED_FDPLX output for use as an
LED driver or more general purpose control pin. See the
table below:
In 100BASE-T mode, link is established as a result of input
receive amplitude compliant with TP-PMD specifications
which will result in internal generation of signal detect.
The Collision LED indicates the presence of collision activity for 10 Mb/s or 100 Mb/s Half Duplex operation. This bit
has no meaning in Full Duplex operation and will be deasLED_CFG
Mode Description
serted when the port is operating in Full Duplex. Since this
pin is also used as the PHY address strap option, the
1
LED polarity adjusted
polarity of this indicator is adjusted to be the inverse of the
0
Duplex active-high
strap value. In 10 Mb/s half duplex mode, the collision LED
is based on the COL signal. When in this mode, the user
The LED_FDPLX pin indicates the Half or Full Duplex con- should disable the Heartbeat (SQE) to avoid asserting the
figuration of the port in both 10 Mb/s and 100 Mb/s opera- COL LED during transmission. See Section 3.4.2 for more
tion. Since this pin is also used as the PHY address strap information about the Heartbeat signal.
option, the polarity of this indicator may be adjusted so that The LED_RX and LED_TX pins indicate the presence of
in the “active” (FULL DUPLEX selected) state it drives transmit and/or receive activity. Since these pins are also
against the pullup/pulldown strap. In this configuration it is used in PHY address strap options, the polarity is adjusted
suitable for use as an LED. When LED_CFG is high this to be the inverse of the respective strap values.
mode is selected and DsPHYTER automatically adjusts the
polarity of the output. If LED_CFG is low, the output drives
2.4 Half Duplex vs. Full Duplex
high to indicate the “active” state. In this configuration the
output is suitable for use as a control pin. The The DP83846A supports both half and full duplex operation
LED_SPEED pin indicates 10 or 100 Mb/s data rate of the at both 10 Mb/s and 100 Mb/s speeds. Half-duplex is the
port. The standard CMOS driver goes high when operating standard, traditional mode of operation which relies on the
in 100 Mb/s operation. Since this pin is not utilized as a CSMA/CD protocol to handle collisions and network
access. In Half-Duplex mode, CRS responds to both transstrap option, it is not affected by polarity adjustment.
The LED_GDLNK pin indicates the link status of the port. mit and receive activity in order to maintain compliance
Since this pin is also used as the PHY address strap with IEEE 802.3 specification.
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Table 3. LED Mode Select
option, the polarity of this indicator is adjusted to be the
inverse of the strap value.
Since the DP83846A is designed to support simultaneous
transmit and receive activity it is capable of supporting fullduplex switched applications with a throughput of up to
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DP83846A
driver. Refer to Figure 2 for an example of a PHYAD con- The adaptive nature of the LED outputs helps to simplify
nection to external components. In this example, the potential implementation issues of these dual purpose pins.
PHYAD strapping results in address 00011 (03h).
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The DP83846A includes a Loopback Test mode for facilitating system diagnostics. The Loopback mode is selected
through bit 14 (Loopback) of the Basic Mode Control Register (BMCR). Writing 1 to this bit enables MII transmit data
to be routed to the MII receive outputs. Loopback status
may be checked in bit 3 of the PHY Status Register
All modes of operation (100BASE-TX and 10BASE-T) can (PHYSTS). While in Loopback mode the data will not be
run either half-duplex or full-duplex. Additionally, other than transmitted onto the media in 100 Mb/s mode. To ensure
CRS and Collision reporting, all remaining MII signaling that the desired operating mode is maintained, Auto-Negoremains the same regardless of the selected duplex mode. tiation should be disabled before selecting the Loopback
It is important to understand that while Auto-Negotiation mode.
with the use of Fast Link Pulse code words can interpret During 10BASE-T operation, in order to be standard comand configure to full-duplex operation, parallel detection pliant, the loopback mode loops MII transmit data to the MII
can not recognize the difference between full and half- receive data, however, Link Pulses are not looped back. In
duplex from a fixed 10 Mb/s or 100 Mb/s link partner over 100BASE-TX Loopback mode the data is routed through
twisted pair. As specified in 802.3u, if a far-end link partner the PCS and PMA layers into the PMD sublayer before it is
is transmitting forced full duplex 100BASE-TX for example, looped back. In addition to serving as a board diagnostic,
the parallel detection state machine in the receiving station this mode serves as a functional verification of the device.
would be unable to detect the full duplex capability of the
far-end link partner and would negotiate to a half duplex 2.7 BIST
100BASE-TX configuration (same scenario for 10 Mb/s).
The DsPHYTER incorporates an internal Built-in Self Test
(BIST) circuit to accommodate in-circuit testing or diagnos2.5 MII Isolate Mode
tics. The BIST circuit can be utilized to test the integrity of
The DP83846A can be put into MII Isolate mode by writing the transmit and receive data paths. BIST testing can be
to bit 10 of the BMCR register. In addition, the MII isolate performed with the part in the internal loopback mode or
mode can be selected by strapping in Physical Address 0. externally looped back using a loopback cable fixture.
It should be noted that selecting Physical Address 0 via an
MDIO write to PHYCTRL will not put the device in the MII The BIST is implemented with independent transmit and
receive paths, with the transmit block generating a continuisolate mode.
ous stream of a pseudo random sequence. The user can
When in the MII isolate mode, the DP83846A does not select a 9 bit or 15 bit pseudo random sequence from the
respond to packet data present at TXD[3:0], TX_EN, and PSR_15 bit in the PHY Control Register (PHYCTRL). The
TX_ER inputs and presents a high impedance on the looped back data is compared to the data generated by the
TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and BIST Linear Feedback Shift Register (LFSR, which generCRS outputs. The DP83846A will continue to respond to all ates a pseudo random sequence) to determine the BIST
management transactions.
pass/fail status.
While in Isolate mode, the TD± outputs will not transmit The pass/fail status of the BIST is stored in the BIST status
packet data but will continue to source 100BASE-TX bit in the PHYCTRL register. The status bit defaults to 0
scrambled idles or 10BASE-T normal link pulses.
(BIST fail) and will transition on a successful comparison. If
an error (mis-compare) occurs, the status bit is latched and
is cleared upon a subsequent write to the Start/Stop bit.
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DP83846A
2.6 Loopback
200 Mb/s per port when operating in 100BASE-TX mode.
Because the CSMA/CD protocol does not apply to fullduplex operation, the DP83846A disables its own internal
collision sensing and reporting functions and modifies the
behavior of Carrier Sense (CRS) such that it indicates only
receive activity. This allows a full-duplex capable MAC to
operate properly.
3.1 802.3u MII
mat is shown below in Table 4: Typical MDIO Frame Format.
The DP83846A incorporates the Media Independent Interface (MII) as specified in Clause 22 of the IEEE 802.3u
standard. This interface may be used to connect PHY
devices to a MAC in 10/100 Mb/s systems. This section
describes both the serial MII management interface as well
as the nibble wide MII data interface.
The MDIO pin requires a pull-up resistor (1.5 kΩ) which,
during IDLE and turnaround, will pull MDIO high. In order to
initialize the MDIO interface, the station management entity
sends a sequence of 32 contiguous logic ones on MDIO to
provide the DP83846A with a sequence that can be used
to establish synchronization. This preamble may be generThe serial management interface of the MII allows for the ated either by driving MDIO high for 32 consecutive MDC
configuration and control of multiple PHY devices, gather- clock cycles, or by simply allowing the MDIO pull-up resising of status, error information, and the determination of the tor to pull the MDIO pin high during which time 32 MDC
type and capabilities of the attached PHY(s).
clock cycles are provided. In addition 32 MDC clock cycles
The nibble wide MII data interface consists of a receive bus should be used to re-sync the device if an invalid start,
and a transmit bus each with control signals to facilitate opcode, or turnaround bit is detected.
data transfer between the PHY and the upper layer (MAC). The DP83846A waits until it has received this preamble
sequence before responding to any other transaction.
Once the DP83846A serial management port has been iniThe serial management MII specification defines a set of tialized no further preamble sequencing is required until
thirty-two 16-bit status and control registers that are acces- after a power-on/reset, invalid Start, invalid Opcode, or
sible through the management interface pins MDC and invalid turnaround bit has occurred.
MDIO. The DP83846A implements all the required MII reg- The Start code is indicated by a <01> pattern. This assures
isters as well as several optional registers. These registers the MDIO line transitions from the default idle line state.
are fully described in Section 5. A description of the serial
Turnaround is defined as an idle bit time inserted between
management access protocol follows.
the Register Address field and the Data field. To avoid contention during a read transaction, no device shall actively
3.1.2 Serial Management Access Protocol
drive the MDIO signal during the first bit of Turnaround.
The serial control interface consists of two pins, Manage- The addressed DP83846A drives the MDIO with a zero for
ment Data Clock (MDC) and Management Data Input/Out- the second bit of turnaround and follows this with the
put (MDIO). MDC has a maximum clock rate of 25 MHz required data. Figure 3 shows the timing relationship
and no minimum rate. The MDIO line is bi-directional and between MDC and the MDIO as driven/received by the Stamay be shared by up to 32 devices. The MDIO frame for- tion (STA) and the DP83846A (PHY) for a typical register
read access.
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3.1.1 Serial Management Register Access
Table 4. Typical MDIO Frame Format
<idle><start><op code><device addr><reg addr><turnaround><data><idle>
bs
MII Management
Serial Protocol
Read Operation
<idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
Write Operation
<idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
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MDC
MDIO
Z
Z
(STA)
Z
MDIO
Z
(PHY)
Z
Idle
0 1 1 0 0 1 1 0 0 0 0 0 0 0
Start
Opcode
(Read)
PHY Address
(PHYAD = 0Ch)
Z
Register Address
(00h = BMCR)
0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0
Register Data
TA
Z
Idle
Figure 3. Typical MDC/MDIO Read Operation
For write transactions, the station management entity
writes data to the addressed DP83846A thus eliminating
the requirement for MDIO Turnaround. The Turnaround
time is filled by the management entity by inserting <10>.
Figure 4 shows the timing relationship for a typical MII register write access.
3.1.3 Serial Management Preamble Suppression
The DP83846A supports a Preamble Suppression mode
as indicated by a one in bit 6 of the Basic Mode Status
Register (BMSR, address 01h.) If the station management
entity (i.e. MAC or other management controller) determines that all PHYs in the system support Preamble Sup-
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DP83846A
3.0 Functional Description
MDIO
Z
Z
(STA)
Z
Idle
0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Start
Opcode
(Write)
PHY Address
(PHYAD = 0Ch)
Register Address
(00h = BMCR)
Register Data
TA
Z
Idle
Figure 4. Typical MDC/MDIO Write Operation
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pression by returning a one in this bit, then the station 3.1.6 Collision Detect
management entity need not generate preamble for each
For Half Duplex, a 10BASE-T or 100BASE-TX collision is
management transaction.
detected when the receive and transmit channels are
The DP83846A requires a single initialization sequence of active simultaneously. Collisions are reported by the COL
32 bits of preamble following hardware/software reset. This signal on the MII.
requirement is generally met by the mandatory pull-up
resistor on MDIO in conjunction with a continuous MDC, or If the DP83846A is transmitting in 10 Mb/s mode when a
the management access made to determine whether Pre- collision is detected, the collision is not reported until seven
bits have been received while in the collision state. This
amble Suppression is supported.
prevents a collision being reported incorrectly due to noise
While the DP83846A requires an initial preamble sequence on the network. The COL signal remains set for the duraof 32 bits for management initialization, it does not require tion of the collision.
a full 32-bit sequence between each subsequent transaction. A minimum of one idle bit between management If a collision occurs during a receive operation, it is immediately reported by the COL signal.
transactions is required as specified in IEEE 802.3u.
When heartbeat is enabled (only applicable to 10 Mb/s
operation), approximately 1µs after the transmission of
3.1.4 PHY Address Sensing
each packet, a Signal Quality Error (SQE) signal of approxThe DP83846A provides five PHY address pins, the infor- imately 10 bit times is generated (internally) to indicate
mation is latched into the PHYCTRL register (address 19h, successful transmission. SQE is reported as a pulse on the
bits [4:0]) at device power-up/Hardware reset.
COL signal of the MII.
The DP83846A supports PHY Address strapping values 0
(<00000>) through 31 (<11111>). Strapping PHY Address 3.1.7 Carrier Sense
0 puts the part into Isolate Mode. It should also be noted
that selecting PHY Address 0 via an MDIO write to PHYC- Carrier Sense (CRS) may be asserted due to receive activTRL will not put the device in Isolate Mode; Address 0 must ity, once valid data is detected via the squelch function during 10 Mb/s operation. During 100 Mb/s operation CRS is
be strapped in.
asserted when a valid link (SD) and two non-contiguous
zeros are detected on the line.
3.1.5 Nibble-wide MII Data Interface
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Clause 22 of the IEEE 802.3u specification defines the
Media Independent Interface. This interface includes a
dedicated receive bus and a dedicated transmit bus. These
two data buses, along with various control and indicate signals, allow for the simultaneous exchange of data between
the DP83846A and the upper layer agent (MAC).
The receive interface consists of a nibble wide data bus
RXD[3:0], a receive error signal RX_ER, a receive data
valid flag RX_DV, and a receive clock RX_CLK for synchronous transfer of the data. The receive clock can operate at either 2.5 MHz to support 10 Mb/s operation modes
or at 25 MHz to support 100 Mb/s operational modes.
The transmit interface consists of a nibble wide data bus
TXD[3:0], a transmit enable control signal TX_EN, and a
transmit clock TX_CLK which runs at either 2.5 MHz or 25
MHz.
Additionally, the MII includes the carrier sense signal CRS,
as well as a collision detect signal COL. The CRS signal
asserts to indicate the reception of data from the network
or as a function of transmit data in Half Duplex mode. The
COL signal asserts as an indication of a collision which can
occur during half-duplex operation when both a transmit
and receive operation occur simultaneously.
For 10 or 100 Mb/s Half Duplex operation, CRS is asserted
during either packet transmission or reception.
For 10 or 100 Mb/s Full Duplex operation, CRS is asserted
only due to receive activity.
CRS is deasserted following an end of packet.
3.2 100BASE-TX TRANSMITTER
The 100BASE-TX transmitter consists of several functional
blocks which convert synchronous 4-bit nibble data, as provided by the MII, to a scrambled MLT-3 125 Mb/s serial
data stream. Because the 100BASE-TX TP-PMD is integrated, the differential output pins, TD±, can be directly
routed to the magnetics.
The block diagram in Figure 5 provides an overview of
each functional block within the 100BASE-TX transmit section.
The Transmitter section consists of the following functional
blocks:
—
—
—
—
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Code-group Encoder and Injection block (bypass option)
Scrambler block (bypass option)
NRZ to NRZI encoder block
Binary to MLT-3 converter / Common Driver
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DP83846A
MDC
TX_CLK
DP83846A implements the 100BASE-TX transmit state
machine diagram as specified in the IEEE 802.3u Standard, Clause 24.
TXD[3:0] /
tx_er
DIV BY 5
FROM PGM
4B5B Code-group
encoder & injector
mux
te
BP_4B5B
5B parallel
to serial
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scrambler
mux
BP_SCR
nrz to nrzi
encoder
100BASE-TX
Loopback
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binary to mlt-3 /
Common Driver
TD±
Figure 5. 100BASE-TX Transmit Block Diagram
3.2.1 Code-group Encoding and Injection
After the T/R code-group pair, the code-group encoder
continuously injects IDLEs into the transmit data stream
The code-group encoder converts 4-bit (4B) nibble data until the next transmit packet is detected (reassertion of
generated by the MAC into 5-bit (5B) code-groups for
Transmit Enable).
transmission. This conversion is required to allow control
data to be combined with packet data code-groups. Refer 3.2.2 Scrambler
to Table 5: 4B5B Code-Group Encoding/Decoding for 4B to
5B code-group mapping details.
The scrambler is required to control the radiated emissions
The code-group encoder substitutes the first 8-bits of the at the media connector and on the twisted pair cable (for
MAC preamble with a J/K code-group pair (11000 10001) 100BASE-TX applications). By scrambling the data, the
upon transmission. The code-group encoder continues to total energy launched onto the cable is randomly distribreplace subsequent 4B preamble and data nibbles with uted over a wide frequency range. Without the scrambler,
corresponding 5B code-groups. At the end of the transmit energy levels at the PMD and on the cable could peak
packet, upon the deassertion of Transmit Enable signal beyond FCC limitations at frequencies related to repeating
from the MAC, the code-group encoder injects the T/R 5B sequences (i.e., continuous transmission of IDLEs).
code-group pair (01101 00111) indicating the end of frame.
The scrambler is configured as a closed loop linear feedback shift register (LFSR) with an 11-bit polynomial. The
output of the closed loop LFSR is X-ORd with the serial
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DP83846A
The bypass option for the functional blocks within the
100BASE-TX transmitter provides flexibility for applications
where data conversion is not always required. The
3.2.4 Binary to MLT-3 Convertor / Common Driver
The Binary to MLT-3 conversion is accomplished by converting the serial binary data stream output from the NRZI
encoder into two binary data streams with alternately
phased logic one events. These two binary streams are
then fed to the twisted pair output driver which converts the
voltage to current and alternately drives either side of the
transmit transformer primary winding, resulting in a minimal
current (20 mA max) MLT-3 signal. Refer to Figure 6.
3.2.3 NRZ to NRZI Encoder
After the transmit data stream has been serialized and
scrambled, the data must be NRZI encoded in order to
comply with the TP-PMD standard for 100BASE-TX transmission over Category-5 Unsheilded twisted pair cable.
binary_in
binary_plus
Q
D
binary_minus
Q
te
differential MLT-3
binary_plus
binary_in
COMMON
DRIVER
MLT-3
ol
e
binary_minus
O
bs
Figure 6. Binary to MLT-3 conversion
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DP83846A
NRZ data from the code-group encoder. The result is a
scrambled data stream with sufficient randomization to
decrease radiated emissions at certain frequencies by as
much as 20 dB. The DP83846A uses the PHY_ID (pins
PHYAD [4:0]) to set a unique seed value.
DP83846A
PCS 5B Code-group
MII 4B Nibble Code
0
11110
0000
1
01001
0001
2
10100
0010
3
10101
0011
4
01010
0100
5
01011
0101
6
01110
0110
7
01111
0111
8
10010
1000
9
10011
1001
A
10110
1010
B
10111
C
11010
D
11011
E
11100
F
11101
te
Table 5. 4B5B Code-Group Encoding/Decoding
Name
00100
HALT code-group - Error code
11111
Inter-Packet IDLE - 0000 (Note 1)
11000
First Start of Packet - 0101 (Note 1)
DATA CODES
1011
1100
1101
1110
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1111
IDLE AND CONTROL CODES
H
I
J
K
T
Second Start of Packet - 0101 (Note 1)
First End of Packet - 0000 (Note 1)
00111
Second End of Packet - 0000 (Note 1)
bs
R
10001
01101
V
00000
V
00001
V
00010
V
00011
V
00101
O
INVALID CODES
V
00110
V
01000
V
01100
V
10000
V
11001
Note 1: Control code-groups I, J, K, T and R in data fields will be mapped as invalid codes, together with RX_ER asserted.
19
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O
bs
ol
e
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— ADC
— Input and BLW Compensation
— Signal Detect
— Digital Adaptive Equalization
The 100BASE-TX transmit TP-PMD function within the — MLT-3 to Binary Decoder
DP83846A is capable of sourcing only MLT-3 encoded — Clock Recovery Module
data. Binary output from the TD± outputs is not possible in — NRZI to NRZ Decoder
100 Mb/s mode.
— Serial to Parallel
— DESCRAMBLER (bypass option)
3.3 100BASE-TX RECEIVER
The 100BASE-TX receiver consists of several functional — Code Group Alignment
blocks which convert the scrambled MLT-3 125 Mb/s serial — 4B/5B Decoder (bypass option)
data stream to synchronous 4-bit nibble data that is pro- — Link Integrity Monitor
vided to the MII. Because the 100BASE-TX TP-PMD is
integrated, the differential input pins, RD±, can be directly — Bad SSD Detection
The bypass option for the functional blocks within the
routed from the AC coupling magnetics.
100BASE-TX receiver provides flexibility for applications
See Figure 8 for a block diagram of the 100BASE-TX
where data conversion is not always required.
receive function. This provides an overview of each functional block within the 100BASE-TX receive section.
3.3.1 Input and Base Line Wander Compensation
The Receive section consists of the following functional
Unlike the DP83223V Twister, the DP83846A requires no
blocks:
external attenuation circuitry at its receive inputs, RD±. It
accepts TP-PMD compliant waveforms directly, requiring
only a 100Ω termination plus a simple 1:1 transformer.
Figure 7. 100BASE-TX BLW Event
The DP83846A is completely ANSI TP-PMD compliant and
includes Base Line Wander (BLW) compensation. The
BLW compensation block can successfully recover the TPPMD defined “killer” pattern and pass it to the digital adaptive equalization block.
quency response of the AC coupling component(s) within
the transmission system. If the low frequency content of
the digital bit stream goes below the low frequency pole of
the AC coupling transformers then the droop characteristics of the transformers will dominate resulting in potentially
BLW can generally be defined as the change in the aver- serious BLW.
age DC content, over time, of an AC coupled digital trans- The digital oscilloscope plot provided in Figure 7 illustrates
mission over a given transmission medium. (i.e., copper the severity of the BLW event that can theoretically be genwire).
erated during 100BASE-TX packet transmission. This
BLW results from the interaction between the low fre- event consists of approximately 800 mV of DC offset for a
quency components of a transmitted bit stream and the fre20
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DP83846A
The 100BASE-TX MLT-3 signal sourced by the TD± common driver output pins is slew rate controlled. This should
be considered when selecting AC coupling magnetics to
ensure TP-PMD Standard compliant transition times (3 ns
< Tr < 5 ns).
DP83846A
RX_CLK
RXD[3:0] / RX_ER
÷5
mux
BP_4B5B
4b/5b Decoder
te
Serial to
parallel
Code group
alignment
BP_SCR
ol
e
mux
DEscrambler
CLOCK
nrzi to nrz
decoder
bs
Clock
Recovery
Module
LINK STATUS
O
MLT-3 to
Binary decoder
Digital
adaptive
Equalization
AGC
LINK
Monitor
Signal Detect
InPUT BLW
Compensation
ADC
rd±
Figure 8. Receive Block Diagram
21
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The CRM is implemented using an advanced all digital
Phase Locked Loop (PLL) architecture that replaces sensitive analog circuitry. Using digital PLL circuitry allows the
DP83846A to be manufactured and specified to tighter tolerances.
The signal detect function of the DP83846A is incorporated
to meet the specifications mandated by the ANSI FDDI TPPMD Standard as well as the IEEE 802.3 100BASE-TX
Standard for both voltage thresholds and timing parameters.
Note that the reception of normal 10BASE-T link pulses
and fast link pulses per IEEE 802.3u Auto-Negotiation by
the 100BASE-TX receiver do not cause the DP83846A to
assert signal detect.
3.3.5 NRZI to NRZ
In a typical application, the NRZI to NRZ
required in order to present NRZ formatted
descrambler (or to the code-group alignment
descrambler is bypassed, or directly to the
receiver is bypassed).
3.3.3 Digital Adaptive Equalization
The 100BASE-TX receiver includes a Serial to Parallel
converter which supplies 5-bit wide data symbols to the
PCS Rx state machine.
3.3.7 Descrambler
A serial descrambler is used to de-scramble the received
NRZ data. The descrambler has to generate an identical
data scrambling sequence (N) in order to recover the original unscrambled data (UD) from the scrambled data (SD)
as represented in the equations:
ol
e
In order to ensure quality transmission when employing
MLT-3 encoding, the compensation must be able to adapt
to various cable lengths and cable types depending on the
installed environment. The selection of long cable lengths
for a given implementation, requires significant compensation which will over-compensate for shorter, less attenuating lengths. Conversely, the selection of short or
intermediate cable lengths requiring less compensation will
cause serious under-compensation for longer length
cables. The compensation or equalization must be adaptive to ensure proper conditioning of the received signal
independent of the cable length.
3.3.6 Serial to Parallel
te
When transmitting data at high speeds over copper twisted
pair cable, frequency dependent attenuation becomes a
concern. In high-speed twisted pair signalling, the frequency content of the transmitted signal can vary greatly
during normal operation based primarily on the randomness of the scrambled data stream. This variation in signal
attenuation caused by frequency variations must be compensated for to ensure the integrity of the transmission.
decoder is
data to the
block, if the
PCS, if the
SD = ( UD ⊕ N )
UD = ( SD ⊕ N )
O
bs
Synchronization of the descrambler to the original scrambling sequence (N) is achieved based on the knowledge
that the incoming scrambled data stream consists of
scrambled IDLE data. After the descrambler has recogThe DP83846A utilizes a extremely robust equalization nized 12 consecutive IDLE code-groups, where an
scheme referred as ‘Digital Adaptive Equalization’. Tradi- unscrambled IDLE code-group in 5B NRZ is equal to five
tional designs use a pseudo adaptive equalization scheme consecutive ones (11111), it will synchronize to the receive
that determines the approximate cable length by monitor- data stream and generate unscrambled data in the form of
ing signal attenuation at certain frequencies. This attenua- unaligned 5B code-groups.
tion value was compared to the internal receive input In order to maintain synchronization, the descrambler must
reference voltage. This comparison would indicate the continuously monitor the validity of the unscrambled data
amount of equalization to use. Although this scheme is that it generates. To ensure this, a line state monitor and a
used successfully on the DP83223V twister, it is sensitive hold timer are used to constantly monitor the synchronizato transformer mismatch, resistor variation and process
tion status. Upon synchronization of the descrambler the
induced offset. The DP83223V also required an external hold timer starts a 722 µs countdown. Upon detection of
attenuation network to help match the incoming signal sufficient IDLE code-groups (58 bit times) within the 722 µs
amplitude to the internal reference.
period, the hold timer will reset and begin a new countThe Digital Equalizer removes ISI (inter symbol interfer- down. This monitoring operation will continue indefinitely
ence) from the receive data stream by continuously adapt- given a properly operating network connection with good
ing to provide a filter with the inverse frequency response signal integrity. If the line state monitor does not recognize
of the channel. When used in conjunction with a gain sufficient unscrambled IDLE code-groups within the 722 µs
stage, this enables the receive 'eye pattern' to be opened period, the entire descrambler will be forced out of the cursufficiently to allow very reliable data recovery.
rent state of synchronization and reset in order to reTraditionally 'adaptive' equalizers selected 1 of N filters in acquire synchronization.
an attempt to match the cables characteristics. This
approach will typically leave holes at certain cable lengths, 3.3.8 Code-group Alignment
where the performance of the equalizer is not optimized.
The code-group alignment module operates on unaligned
The DP83846A equalizer is truly adaptive to any length of 5-bit data from the descrambler (or, if the descrambler is
bypassed, directly from the NRZI/NRZ decoder) and concable up to 150m.
verts it into 5B code-group data (5 bits). Code-group alignment occurs after the J/K code-group pair is detected.
3.3.4 Clock Recovery Module
Once the J/K code-group pair (11000 10001) is detected,
The Clock Recovery Module (CRM) accepts 125 Mb/s subsequent data is aligned on a fixed boundary.
MLT3 data from the equalizer. The DPLL locks onto the
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DP83846A
period of 120 µs. Left uncompensated, events such as this 125 Mb/s data stream and extracts a 125 MHz recovered
can cause packet loss.
clock. The extracted and synchronized clock and data are
used as required by the synchronous receive operations as
3.3.2 Signal Detect
generally depicted in Figure 8.
3.4.2 Collision Detection and SQE
The code-group decoder functions as a look up table that
translates incoming 5B code-groups into 4B nibbles. The
code-group decoder first detects the J/K code-group pair
preceded by IDLE code-groups and replaces the J/K with
MAC preamble. Specifically, the J/K 10-bit code-group pair
is replaced by the nibble pair (0101 0101). All subsequent
5B code-groups are converted to the corresponding 4B
nibbles for the duration of the entire packet. This conversion ceases upon the detection of the T/R code-group pair
denoting the End of Stream Delimiter (ESD) or with the
reception of a minimum of two IDLE code-groups.
When in Half Duplex, a 10BASE-T collision is detected
when the receive and transmit channels are active simultaneously. Collisions are reported by the COL signal on the
MII. Collisions are also reported when a jabber condition is
detected.
The COL signal remains set for the duration of the collision.
If the ENDEC is receiving when a collision is detected it is
reported immediately (through the COL pin).
When heartbeat is enabled, approximately 1 µs after the
transmission of each packet, a Signal Quality Error (SQE)
signal of approximately 10-bit times is generated to indicate successful transmission. SQE is reported as a pulse
on the COL signal of the MII.
3.3.10 100BASE-TX Link Integrity Monitor
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The 100 Base TX Link monitor ensures that a valid and stable link is established before enabling both the Transmit The SQE test is inhibited when the PHY is set in full duplex
mode. SQE can also be inhibited by setting the
and Receive PCS layer.
HEARTBEAT_DIS bit in the 10BTSCR register.
Signal detect must be valid for 395us to allow the link monitor to enter the 'Link Up' state, and enable the transmit and 3.4.3 Carrier Sense
receive functions.
Carrier Sense (CRS) may be asserted due to receive activity once valid data is detected via the squelch function.
3.3.11 Bad SSD Detection
A Bad Start of Stream Delimiter (Bad SSD) is any transition For 10 Mb/s Half Duplex operation, CRS is asserted during
from consecutive idle code-groups to non-idle code-groups either packet transmission or reception.
which is not prefixed by the code-group pair /J/K.
For 10 Mb/s Full Duplex operation, CRS is asserted only
If this condition is detected, the DP83846A will assert during receive activity.
RX_ER and present RXD[3:0] = 1110 to the MII for the CRS is deasserted following an end of packet.
cycles that correspond to received 5B code-groups until at
least two IDLE code groups are detected. In addition, the 3.4.4 Normal Link Pulse Detection/Generation
False Carrier Sense Counter register (FCSCR) will be
The link pulse generator produces pulses as defined in the
incremented by one.
IEEE 802.3 10BASE-T standard. Each link pulse is nomiOnce at least two IDLE code groups are detected, RX_ER nally 100 ns in duration and transmitted every 16 ms in the
and CRS become de-asserted.
absence of transmit data.
Link pulses are used to check the integrity of the connection with the remote end. If valid link pulses are not
The 10BASE-T Transceiver Module is IEEE 802.3 compli- received, the link detector disables the 10BASE-T twisted
ant. It includes the receiver, transmitter, collision, heart- pair transmitter, receiver and collision detection functions.
beat, loopback, jabber, and link integrity functions, as When
the
link
integrity
function
is
disabled
defined in the standard. An external filter is not required on (FORCE_LINK_10 of the 10BTSCR register), good link is
the 10BASE-T interface since this is integrated inside the forced and the 10BASE-T transceiver will operate regardDP83846A. This section focuses on the general 10BASE-T less of the presence of link pulses.
system level operation.
bs
3.4 10BASE-T TRANSCEIVER MODULE
3.4.1 Operational Modes
3.4.5 Jabber Function
O
The jabber function monitors the DP83846A's output and
The DP83846A has two basic 10BASE-T operational disables the transmitter if it attempts to transmit a packet of
modes:
longer than legal size. A jabber timer monitors the transmit— Half Duplex mode
ter and disables the transmission if the transmitter is active
beyond the Jab time (20-150 ms).
— Full Duplex mode
Once disabled by the Jabber function, the transmitter stays
disabled for the entire time that the ENDEC module's interIn Half Duplex mode the DP83846A functions as a stan- nal transmit enable is asserted. This signal has to be dedard IEEE 802.3 10BASE-T transceiver supporting the asserted for approximately 250-750 ms (the “unjab” time)
before the Jabber function re-enables the transmit outputs.
CSMA/CD protocol.
Half Duplex Mode
The Jabber function is only relevant in 10BASE-T mode.
Full Duplex Mode
3.4.6 Automatic Link Polarity Detection and Correction
In Full Duplex mode the DP83846A is capable of simultaneously transmitting and receiving without asserting the The DP83846A's 10BASE-T transceiver module incorpocollision signal. The DP83846A's 10 Mb/s ENDEC is rates an automatic link polarity detection circuit. When
seven consecutive inverted link pulses are received,
designed to encode and decode simultaneously.
inverted polarity is reported.
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DP83846A
3.3.9 4B/5B Decoder
valid on the rising edge of Transmit Clock (TX_CLK).
Transmission ends when TX_EN deasserts. The last transition is always positive; it occurs at the center of the bit cell
The inverse polarity condition is latched in the 10BTSCR if the last bit is a one, or at the end of the bit cell if the last
register. The DP83846A's 10BASE-T transceiver module bit is a zero.
corrects for this error internally and will continue to decode
received data correctly. This eliminates the need to correct 3.4.9 Receiver
the wiring error immediately.
The decoder consists of a differential receiver and a PLL to
The user is cautioned that if Auto Polarity Detection and separate a Manchester encoded data stream into internal
Correction is disabled and inverted Polarity is detected but clock signals and data. The differential input must be externot corrected, the DsPHYTER may falsely report Good nally terminated with a differential 100Ω termination netLink status and allow Transmission and Reception of work to accommodate UTP cable. The impedance of RD±
inverted data. It is recommended that Auto Polarity Detec- (typically 1.1KΩ) is in parallel with the two 54.9Ω resistors
tion and Correction not be disabled during normal opera- as is shown in Figure 9 below to approximate the 100Ω
termination.
tion.
The decoder detects the end of a frame when no additional
mid-bit transitions are detected. Within one and a half bit
times after the last bit, carrier sense is de-asserted.
3.4.7 Transmit and Receive Filtering
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External 10BASE-T filters are not required when using the
DP83846A, as the required signal conditioning is inte3.5 TPI Network Circuit
grated into the device.
Only isolation/step-up transformers and impedance match- Figure 9 shows the recommended circuit for a 10/100 Mb/s
ing resistors are required for the 10BASE-T transmit and twisted pair interface. Below is a partial list of recomreceive interface. The internal transmit filtering ensures mended transformers. Is is important that the user realize
that all the harmonics in the transmit signal are attenuated that variations with PCB and component characteristics
requires that the application be tested to ensure that the
by at least 30 dB.
circuit meets the requirements of the intended application.
3.4.8 Transmitter
Pulse H1012B, PE-68515L
Halo TG22-S052ND
The encoder begins operation when the Transmit Enable
Valor PT4171
input (TX_EN) goes high and converts NRZ data to preBELFUSE S558-5999-K2
emphasized Manchester data for the transceiver. For the
BELFUSE S558-5999-46
duration of TX_EN, the serialized Transmit Data (TXD) is
encoded for the transmit-driver pair (TD±). TXD must be
bs
Common Mode Chokes may
be required.
1:1
RD-
RD+
RD-
0.1µF*
RD+
Vdd
O
TD-
TD+
TDTD+
0.1µF*
RJ45
1:1
54.9Ω
54.9Ω
49.9 Ω 49.9 Ω
T1
* Place capacitors close to
the transformer center taps
0.1µF
Figure 9. 10/100 Mb/s Twisted Pair Interface
24
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DP83846A
A polarity reversal can be caused by a wiring error at either
end of the cable, usually at the Main Distribution Frame
(MDF) or patch panel in the wiring closet.
For applications where high reliability is required, it is recommended that additional ESD protection diodes be added
as shown below. There are numerous dual series connected diode pairs that are available specifically for ESD
protection. The level of protection will vary dependent upon
the diode ratings. The primary parameter that affects the
level of ESD protection is peak forward surge current. Typical specifications for diodes intended for ESD protection
range from 500mA (Motorola BAV99LT1 single pair diodes)
to 12A (STM DA108S1 Quad pair array). The user should
also select diodes with low input capacitance to minimize
the effect on system performance.
Typically, ESD precautions are predominantly in effect
when handling the devices or board before being installed
in a system. In those cases, strict handling procedures can
be implemented during the manufacturing process to
greatly reduce the occurrences of catastrophic ESD
events. After the system is assembled, internal components are usually relatively immune from ESD events.
In the case of an installed Ethernet system however, the
network interface pins are still susceptible to external ESD
events. For example, a category 5 cable being dragged
across a carpet has the potential of developing a charge Since performance is dependent upon components used,
well above the typical ESD rating of a semiconductor board impedance characteristics, and layout, the circuit
device.
should be completely tested to ensure performance to the
required levels.
DP83846A 10/100
3.3V Vcc
te
Vcc
RJ-45
Pin 1
ol
e
TX±
Vcc
bs
Diodes placed on
the device side of
the isolation
transformer
Pin 2
Pin 3
O
RX±
Pin 6
Figure 10. Typical DP83846A Network Interface with additional ESD protection
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DP83846A
3.6 ESD Protection
As a starting point for evaluating an oscillator circuit, if the
requirements for the crystal are not known, CL1 and CL2
should be set at 22 pF, and R1 should be set at 0Ω.
The DsPHYTER supports an external CMOS level oscillator source or a crystal resonator device. If an external clock
source is used, X1 should be tied to the clock source and
X2 should be left floating. In either case, the clock source
must be a 25 MHz 0.005% (50 PPM) CMOS oscillator, or a
25 MHz (50 PPM), parallel, 20 pF load crystal resonator.
Figure 11 below shows a typical connection for a crystal
resonator circuit. The load capacitor values will vary with
the crystal vendors; check with the vendor for the recommended loads.
X1
X2
R1
The oscillator circuit was designed to drive a parallel resonance AT cut crystal with a maximum drive level of 500µW.
If a crystal is specified for a lower drive level, a current limiting resistor should be placed in series between X2 and
the crystal.
CL1
CL2
Figure 11. Crystal Oscillator Circuit
4.0 Reset Operation
4.2 Software Reset
A software reset is accomplished by setting the reset bit
(bit 15) of the Basic Mode Control Register (BMCR). The
period from the point in time when the reset bit is set to the
point in time when software reset has concluded is approximately 160 µs.
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e
While either the hardware or software reset can be implemented at any time after device initialization, a hardware
reset, as described in Section 4.1 must be provided upon
device power-up/initialization. Omitting the hardware reset
operation during the device power-up/initialization
sequence can result in improper device operation.
device such that all registers will be reset to default values
and the hardware configuration values will be re-latched
into the device (similar to the power-up/reset operation).
te
The DP83846A can be reset either by hardware or software. A hardware reset may be accomplished by asserting
the RESET pin after powering up the device (this is
required) or during normal operation when a reset is
needed. A software reset is accomplished by setting the
reset bit in the Basic Mode Control Register.
O
bs
The software reset will reset the device such that all registers will be reset to default values and the hardware configuration values will be re-latched into the device (similar to
4.1 Hardware Reset
the power-up/reset operation). Software driver code should
A hardware reset is accomplished by applying a low pulse wait 500 µs following a software reset before allowing fur(TTL level), with a duration of at least 160 µs, to the ther serial MII operations with the DP83846A.
RESET pin during normal operation. This will reset the
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DP83846A
3.7 Crystal Oscillator Circuit
DP83846A
5.0 Register Block
Table 6. Register Map
Offset
Hex
Decimal
Access
Tag
Description
00h
0
RW
BMCR
Basic Mode Control Register
01h
1
RO
BMSR
Basic Mode Status Register
02h
2
RO
PHYIDR1
PHY Identifier Register #1
03h
3
RO
PHYIDR2
PHY Identifier Register #2
04h
4
RW
ANAR
Auto-Negotiation Advertisement Register
05h
5
RW
ANLPAR
Auto-Negotiation Link Partner Ability Register (Base Page)
05h
5
RW
ANLPARNP
Auto-Negotiation Link Partner Ability Register (Next Page)
06h
6
RW
ANER
Auto-Negotiation Expansion Register
RW
7
8-15
10h
16
11h-13h
17-19
14h
20
ANNPTR
Auto-Negotiation Next Page TX
RESERVED
RESERVED
te
07h
08h-Fh
Extended Registers
21
16h
22
17h
23
18h
24
19h
25
1Ah
26
27
28
PHY Status Register
RESERVED
RESERVED
RW
FCSCR
False Carrier Sense Counter Register
RW
RECR
Receive Error Counter Register
RW
PCSR
PCS Sub-Layer Configuration and Status Register
RW
RESERVED
RESERVED
RW
RESERVED
RESERVED
RW
PHYCTRL
PHY Control Register
RW
10BTSCR
10Base-T Status/Control Register
RW
CDCTRL
CD Test Control Register
RW
RESERVED
RESERVED
O
bs
1Bh
1Ch-1Fh
PHYSTS
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15h
RO
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Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00h
Addr
BMCR
Tag
Reset
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Loopback
Speed Select
Auto-Neg
Enable
Power
down
Isolate
Restart
Auto-Neg
Duplex
Collision
Test
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Basic Mode Status Register
01h
BMSR
100BaseT4
100BaseTX FDX
100BaseTX HDX
10BaseT
FDXx
10BaseT
HDX
Reserved
Reserved
Reserved
Reserved
MF Preamble
Suppress
Auto-Neg
Complete
Remote
Fault
Auto-Neg
Ability
Link
Status
Jabber
Detect
Extended
Capability
PHY Identifier Register 1
02h
PHYIDR1
OUI MSB
OUI MSB
OUI MSB
OUI MSB
OUI MSB
OUI MSB
OUI MSB
OUI MSB
OUI MSB
OUI MSB
OUI MSB
OUI MSB
OUI MSB
OUI MSB
OUI MSB
OUI MSB
PHY Identifier Register 2
03h
PHYIDR2
OUI LSB
OUI LSB
OUI LSB
OUI LSB
OUI LSB
OUI LSB
VNDR_
MDL
VNDR_
MDL
VNDR_
MDL
VNDR_
MDL
VNDR_
MDL
VNDR_
MDL
MDL_
REV
MDL_
REV
MDL_
REV
MDL_
REV
Auto-Negotiation Advertisement Register
04h
ANAR
Next Page
Ind
Reserved
Remote
Fault
Reserved
Auto-Negotiation Link Partner Ability Register (Base Page)
05h
ANLPAR
Next Page
Ind
ACK
Remote
Fault
Reserved
Auto-Negotiation Link Partner Ability Register Next Page
05h
ANLPARNP
Next Page
Ind
ACK
Message
Page
ACK2
Reserved
PAUSE
T4
TX_FD
TX
10_FD
10
Protocol
Selection
Protocol
Selection
Protocol
Selection
Protocol
Selection
Protocol
Selection
Reserved
Reserved
T4
TX_FD
TX
10_FD
10
Protocol
Selection
Protocol
Selection
Protocol
Selection
Protocol
Selection
Protocol
Selection
Toggle
Code
Code
Code
Code
Code
Code
Code
Code
Code
Code
Code
bs
ol
e
Register Name
te
Bit 9
Basic Mode Control Register
Auto-Negotiation Expansion Register
06h
ANER
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PDF
LP_NP_
ABLE
NP_
ABLE
PAGE_
RX
LP_AN_
ABLE
Auto-Negotiation Next Page TX Register
07h
ANNPTR
Next Page
Ind
Reserved
Message
Page
ACK2
TOG_TX
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
RESERVED
08-0fh
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
10h
PHYSTS
Reserved
Reserved
Rx Err
Latch
Polarity
Status
False Carrier Sense
Signal Detect
Descram
Lock
Page
Receive
Reserved
Remote
Fault
Jabber
Detect
Auto-Neg
Complete
Loopback
Status
Duplex
Status
Speed
Status
Link
Status
EXTENDED REGISTERS
RESERVED
11-13h
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
False Carrier Sense Counter Register
14h
FCSCR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
FCSCNT
FCSCNT
FCSCNT
FCSCNT
FCSCNT
FCSCNT
FCSCNT
FCSCNT
Receive Error Counter Register
15h
RECR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RXERCNT
RXERCNT
RXERCNT
RXERCNT
RXERCNT
RXERCNT
RXERCNT
RXERCNT
PCS Sub-Layer Configuration and Status
Register
16h
PCSR
Reserved
Reserved
Reserved
BYP_
4B5B
FREE_
CLK
TQ_EN
SD_FOR
CE_PMA
SD_
OPTION
Unused
Reserved
FORCE_
100_OK
Reserved
Reserved
NRZI_
BYPASS
SCRAM_
BYPASS
DE
SCRAM_
BYPASS
RESERVED
17-18h
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
19h
PHYCTRL
Unused
Unused
Unused
Unused
PSR_15
BIST_
STATUS
BIST_
START
BP_
STRETC
H
PAUSE_
STS
LED_
CNFG
LED_
CNFG
PHY
ADDR
PHY
ADDR
PHY
ADDR
PHY
ADDR
PHY
ADDR
1Ah
10BTSCR
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Loopback
_10_dis
LP_DIS
Force_
Link_10
Force_
Pol_Cor
Polarity
Autopol
_Dis
Reserved
Hrtbeat
_Dis
Jabber
_Dis
CD Test Control Register
1Bh
CDCTRL
CD_Enabl
e
DCD_
Comp
FIL_TTL
riseTime[1]
riseTime[0]
fallTime[1]
fallTime[0]
cdTestEn
Reserved
Reserved
Reserved
cdPattEn_
10
cdPatEn_
100
10meg_
patt_gap
cdPattSel[1]
cdPattSel[0]
RESERVED
1C-1Fh
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PHY Control Register
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O
10Base-T Status/Control Register
DP83846A
28
PHY Status Register
DP83846A
5.1 Register Definition
In the register definitions under the ‘Default’ heading, the following definitions hold true:
— RW=Read Write access
SC=Register sets on event occurrence and Self-Clears when event ends
RW/SC =Read Write access/Self Clearing bit
RO=Read Only access
COR = Clear on Read
RO/COR=Read Only, Clear on Read
RO/P=Read Only, Permanently set to a default value
LL=Latched Low and held until read, based upon the occurrence of the corresponding event
LH=Latched High and held until read, based upon the occurrence of the corresponding event
O
bs
ol
e
te
—
—
—
—
—
—
—
—
29
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DP83846A
Table 7. Basic Mode Control Register (BMCR), Address 0x00
Bit
Bit Name
15
Reset
Default
Description
0, RW/SC Reset:
1 = Initiate software Reset / Reset in Process.
0 = Normal operation.
This bit, which is self-clearing, returns a value of one until the reset process is
complete. The configuration is re-strapped.
14
Loopback
0, RW
Loopback:
1 = Loopback enabled.
0 = Normal operation.
The loopback function enables MII transmit data to be routed to the MII receive
data path.
Setting this bit may cause the descrambler to lose synchronization and produce a
500 µs “dead time” before any valid data will appear at the MII receive outputs.
13
Speed Selection Strap, RW Speed Select:
1 = 100 Mb/s.
0 = 10 Mb/s.
Auto-Negotiation Strap, RW Auto-Negotiation Enable:
Enable
Strap controls initial value at reset.
ol
e
12
te
When auto-negotiation is disabled writing to this bit allows the port speed to be selected.
1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored when this
bit is set.
0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex
mode.
11
Power Down
0, RW
Power Down:
1 = Power down.
0 = Normal operation.
10
bs
Setting this bit powers down the PHY. Only the register block is enabled during a
power down condition.
Isolate
0, RW
Isolate:
1 = Isolates the Port from the MII with the exception of the serial management.
0 = Normal operation.
Restart AutoNegotiation
0, RW/SC Restart Auto-Negotiation:
O
9
8
Duplex Mode
1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If AutoNegotiation is disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing and
will return a value of 1 until Auto-Negotiation is initiated, whereupon it will selfclear. Operation of the Auto-Negotiation process is not affected by the management entity clearing this bit.
0 = Normal operation.
Strap, RW Duplex Mode:
When auto-negotiation is disabled writing to this bit allows the port Duplex capability to be selected.
1 = Full Duplex operation.
0 = Half Duplex operation.
7
Collision Test
0, RW
Collision Test:
1 = Collision test enabled.
0 = Normal operation.
When set, this bit will cause the COL signal to be asserted in response to the assertion of TX_EN within 512-bit times. The COL signal will be de-asserted within
4-bit times in response to the de-assertion of TX_EN.
6:0
RESERVED
0, RO
RESERVED: Write ignored, read as 0.
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DP83846A
Table 8. Basic Mode Status Register (BMSR), address 0x01
Bit
Bit Name
Default
15
100BASE-T4
0, RO/P
Description
100BASE-T4 Capable:
0 = Device not able to perform 100BASE-T4 mode.
14
100BASE-TX
1, RO/P
Full Duplex
13
1 = Device able to perform 100BASE-TX in full duplex mode.
100BASE-TX
1, RO/P
Half Duplex
12
100BASE-TX Half Duplex Capable:
1 = Device able to perform 100BASE-TX in half duplex mode.
10BASE-T
1, RO/P
10BASE-T Full Duplex Capable:
1, RO/P
10BASE-T Half Duplex Capable:
Full Duplex
11
100BASE-TX Full Duplex Capable:
1 = Device able to perform 10BASE-T in full duplex mode.
10BASE-T
Half Duplex
1 = Device able to perform 10BASE-T in half duplex mode.
10:7
RESERVED
0, RO
RESERVED: Write as 0, read as 0.
6
MF Preamble
1, RO/P
Preamble suppression Capable:
1 = Device able to perform management transaction with preamble
suppressed, 32-bits of preamble needed only once after reset, invalid
opcode or invalid turnaround.
te
Suppression
0 = Normal management operation.
Auto-Negotiation
Complete
0, RO
Auto-Negotiation Complete:
1 = Auto-Negotiation process complete.
ol
e
5
0 = Auto-Negotiation process not complete.
4
Remote Fault
0, RO/LH
Remote Fault:
1 = Remote Fault condition detected (cleared on read or by reset).
Fault criteria: Far End Fault Indication or notification from Link Partner of Remote Fault.
0 = No remote fault condition detected.
3
Auto-Negotiation
Ability
1, RO/P
Auto Negotiation Ability:
1 = Device is able to perform Auto-Negotiation.
2
bs
0 = Device is not able to perform Auto-Negotiation.
Link Status
0, RO/LL
Link Status:
1 = Valid link established (for either 10 or 100 Mb/s operation).
O
0 = Link not established.
1
0
Jabber Detect
Extended Capability
The criteria for link validity is implementation specific. The occurrence
of a link failure condition will causes the Link Status bit to clear. Once
cleared, this bit may only be set by establishing a good link condition
and a read via the management interface.
0, RO/LH
Jabber Detect: This bit only has meaning in 10 Mb/s mode.
1 = Jabber condition detected.
0 = No Jabber.
This bit is implemented with a latching function, such that the occurrence of a jabber condition causes it to set until it is cleared by a read
to this register by the management interface or by a reset.
1, RO/P
Extended Capability:
1 = Extended register capabilities.
0 = Basic register set capabilities only.
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Table 9. PHY Identifier Register #1 (PHYIDR1), address 0x02
Bit
Bit Name
15:0
OUI_MSB
Bit
Bit Name
15:10
OUI_LSB
Default
Description
<0010 0000 0000 OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are
0000>, RO/P
stored in bits 15 to 0 of this register. The most significant two bits
of the OUI are ignored (the IEEE standard refers to these as bits 1
and 2).
Table 10. PHY Identifier Register #2 (PHYIDR2), address 0x03
Default
Description
<01 0111>, RO/P OUI Least Significant Bits:
9:4
VNDR_MDL
te
Bits 19 to 24 of the OUI (080017h) are mapped to bits 15 to 10 of
this register respectively.
<00 0010>, RO/P Vendor Model Number:
The six bits of vendor model number are mapped to bits 9 to 4
(most significant bit to bit 9).
3:0
MDL_REV
<0011>, RO/P
Model Revision Number:
O
bs
ol
e
Four bits of the vendor model revision number are mapped to bits
3 to 0 (most significant bit to bit 3). This field will be incremented for
all major device changes.
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DP83846A
The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83846A. The Identifier consists of a
concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended
to support network management. National's IEEE assigned OUI is 080017h.
Table 11. Auto-Negotiation Advertisement Register (ANAR), address 0x04
Bit
Bit Name
Default
15
NP
0, RW
Description
Next Page Indication:
0 = Next Page Transfer not desired.
1 = Next Page Transfer desired.
14
RESERVED
0, RO/P
13
RF
0, RW
RESERVED by IEEE: Writes ignored, Read as 0.
Remote Fault:
1 = Advertises that this device has detected a Remote Fault.
0 = No Remote Fault detected.
12:11
RESERVED
0, RW
10
PAUSE
Strap, RW
RESERVED for Future IEEE use: Write as 0, Read as 0
PAUSE: The default is set by the strap option for PAUSE_EN pin.
te
1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer and the pause function as specified in
clause 31 and annex 31B of 802.3u.
0= No MAC based full duplex flow control.
9
T4
0, RO/P
100BASE-T4 Support:
1= 100BASE-T4 is supported by the local device.
8
TX_FD
ol
e
0 = 100BASE-T4 not supported.
Strap, RW
100BASE-TX Full Duplex Support:
1 = 100BASE-TX Full Duplex is supported by the local device.
0 = 100BASE-TX Full Duplex not supported.
7
TX
Strap, RW
100BASE-TX Support:
1 = 100BASE-TX is supported by the local device.
0 = 100BASE-TX not supported.
6
10_FD
Strap, RW
10BASE-T Full Duplex Support:
bs
1 = 10BASE-T Full Duplex is supported by the local device.
0 = 10BASE-T Full Duplex not supported.
5
10
Strap, RW
10BASE-T Support:
1 = 10BASE-T is supported by the local device.
0 = 10BASE-T not supported.
Selector
O
4:0
<00001>, RW
Protocol Selection Bits:
These bits contain the binary encoded protocol selector supported
by this port. <00001> indicates that this device supports IEEE
802.3u.
33
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DP83846A
This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-Negotiation.
Table 12. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 0x05
Bit
Bit Name
Default
15
NP
0, RO
Description
Next Page Indication:
0 = Link Partner does not desire Next Page Transfer.
1 = Link Partner desires Next Page Transfer.
14
ACK
0, RO
Acknowledge:
1 = Link Partner acknowledges reception of the ability data word.
0 = Not acknowledged.
The Device's Auto-Negotiation state machine will automatically
control the this bit based on the incoming FLP bursts.
13
RF
0, RO
Remote Fault:
1 = Remote Fault indicated by Link Partner.
12:10
RESERVED
0, RO
te
0 = No Remote Fault indicated by Link Partner.
RESERVED for Future IEEE use:
Write as 0, read as 0.
9
T4
0, RO
100BASE-T4 Support:
1 = 100BASE-T4 is supported by the Link Partner.
8
TX_FD
ol
e
0 = 100BASE-T4 not supported by the Link Partner.
0, RO
100BASE-TX Full Duplex Support:
1 = 100BASE-TX Full Duplex is supported by the Link Partner.
0 = 100BASE-TX Full Duplex not supported by the Link Partner.
7
TX
0, RO
100BASE-TX Support:
1 = 100BASE-TX is supported by the Link Partner.
0 = 100BASE-TX not supported by the Link Partner.
6
10_FD
0, RO
10BASE-T Full Duplex Support:
bs
1 = 10BASE-T Full Duplex is supported by the Link Partner.
0 = 10BASE-T Full Duplex not supported by the Link Partner.
5
10
0, RO
10BASE-T Support:
1 = 10BASE-T is supported by the Link Partner.
0 = 10BASE-T not supported by the Link Partner.
Selector
O
4:0
<0 0000>, RO
Protocol Selection Bits:
Link Partner’s binary encoded protocol selector.
34
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DP83846A
This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content
changes after the successful auto negotiation if Next-pages are supported.
Bit
Bit Name
Default
15
NP
0, RO
Description
Next Page Indication:
1 = Link Partner desires Next Page Transfer.
0 = Link Partner does not desire Next Page Transfer.
14
ACK
0, RO
Acknowledge:
1 = Link Partner acknowledges reception of the ability data word.
0 = Not acknowledged.
The Device's Auto-Negotiation state machine will automatically
control the this bit based on the incoming FLP bursts. Software
should not attempt to write to this bit.
13
MP
0, RO
Message Page:
1 = Message Page.
0 = Unformatted Page.
ACK2
0, RO
Acknowledge 2:
te
12
1 = Link Partner does have the ability to comply to next page message.
0 = Link Partner does not have the ability to comply to next page
message.
11
Toggle
0, RO
Toggle:
ol
e
1 = Previous value of the transmitted Link Code word equalled 0.
0 = Previous value of the transmitted Link Code word equalled 1.
10:0
CODE
<000 0000 0000>, Code:
RO
This field represents the code field of the next page transmission.
If the MP bit is set (bit 13 of this register), then the code shall be
interpreted as a “Message Page”, as defined in annex 28C of
Clause 28. Otherwise, the code shall be interpreted as an “Unformatted Page”, and the interpretation is application specific.
bs
This register contains additional Local Device and Link Partner status information.
Table 14. Auto-Negotiate Expansion Register (ANER), address 0x06
Bit
Bit Name
Default
15:5
RESERVED
0, RO
4
PDF
0, RO/LH/COR
Description
RESERVED: Writes ignored, Read as 0.
Parallel Detection Fault:
O
1 = A fault has been detected via the Parallel Detection function.
3
LP_NP_ABLE
0 = A fault has not been detected.
0, RO
Link Partner Next Page Able:
1 = Link Partner does support Next Page.
0 = Link Partner does not support Next Page.
2
NP_ABLE
1, RO/P
1
PAGE_RX
0, RO/LH/COR
Next Page Able:
1 = Indicates local device is able to send additional “Next Pages”.
Link Code Word Page Received:
1 = Link Code Word has been received, cleared on a read.
0 = Link Code Word has not been received.
0
LP_AN_ABLE
0, RO
Link Partner Auto-Negotiation Able:
1 = indicates that the Link Partner supports Auto-Negotiation.
0 = indicates that the Link Partner does not support Auto-Negotiation.
35
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DP83846A
Table 13. Auto-Negotiation Link Partner Ability Register (ANLPAR) Next Page, address 0x05
Table 15. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07
Bit
Bit Name
Default
15
NP
0, RW
Description
Next Page Indication:
0 = No other Next Page Transfer desired.
1 = Another Next Page desired.
14
RESERVED
0, RO
RESERVED: Writes ignored, read as 0.
13
MP
1, RW
Message Page:
1 = Message Page.
0 = Unformatted Page.
12
ACK2
0, RW
Acknowledge2:
1 = Will comply with message.
0 = Cannot comply with message.
11
TOG_TX
0, RO
te
Acknowledge2 is used by the next page function to indicate that Local Device has the ability to comply with the message received.
Toggle:
1 = Value of toggle bit in previously transmitted Link Code Word
was 0.
ol
e
0 = Value of toggle bit in previously transmitted Link Code Word
was 1.
Toggle is used by the Arbitration function within Auto-Negotiation
to ensure synchronization with the Link Partner during Next Page
exchange. This bit shall always take the opposite value of the Toggle bit in the previously exchanged Link Code Word.
10:0
CODE
<000 0000 0001>, This field represents the code field of the next page transmission.
RW
If the MP bit is set (bit 13 of this register), then the code shall be
interpreted as a "Message Page”, as defined in annex 28C of IEEE
802.3u. Otherwise, the code shall be interpreted as an "Unformatted Page”, and the interpretation is application specific.
O
bs
The default value of the CODE represents a Null Page as defined
in Annex 28C of IEEE 802.3u.
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DP83846A
This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation.
This register provides a single location within the register set for quick access to commonly accessed information.
Table 16. PHY Status Register (PHYSTS), address 0x10
Bit
Bit Name
Default
15:14
RESERVED
0, RO
13
Receive Error Latch
0, RO/LH
Description
RESERVED: Write ignored, read as 0.
Receive Error Latch:
This bit will be cleared upon a read of the RECR register.
1 = Receive error event has occurred since last read of RXERCNT
(address 0x15, Page 0).
0 = No receive error event has occurred.
12
Polarity Status
0, RO
Polarity Status:
This bit is a duplication of bit 4 in the 10BTSCR register. This bit will
be cleared upon a read of the 10BTSCR register, but not upon a
read of the PHYSTS register.
te
1 = Inverted Polarity detected.
0 = Correct Polarity detected.
11
False Carrier Sense
Latch
0, RO/LH
False Carrier Sense Latch:
This bit will be cleared upon a read of the FCSR register.
ol
e
1 = False Carrier event has occurred since last read of FCSCR (address 0x14).
0 = No False Carrier event has occurred.
10
Signal Detect
0, RO/LL
100Base-TX unconditional Signal Detect from PMD.
9
Descrambler Lock
0, RO/LL
100Base-TX Descrambler Lock from PMD.
8
Page Received
0, RO
Link Code Word Page Received:
This is a duplicate of the Page Received bit in the ANER register,
but this bit will not be cleared upon a read of the PHYSTS register.
1 = A new Link Code Word Page has been received. Cleared on
read of the ANER (address 0x06, bit 1).
O
bs
0 = Link Code Word Page has not been received.
37
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DP83846A
5.2 Extended Registers
DP83846A
Table 16. PHY Status Register (PHYSTS), address 0x10 (Continued)
Bit
Bit Name
Default
Description
7
RESERVED
0, RO
RESERVED: Writes ignored, Read as 0.
6
Remote Fault
0, RO
Remote Fault:
1 = Remote Fault condition detected (cleared on read of BMSR (address 01h) register or by reset). Fault criteria: notification from Link
Partner of Remote Fault via Auto-Negotiation.
0 = No remote fault condition detected.
5
Jabber Detect
0, RO
Jabber Detect: This bit only has meaning in 10 Mb/s mode
This bit is a duplicate of the Jabber Detect bit in the BMSR register,
except that it is not cleared upon a read of the PHYSTS register.
1 = Jabber condition detected.
0 = No Jabber.
4
Auto-Neg Complete
0, RO
Auto-Negotiation Complete:
1 = Auto-Negotiation complete.
3
Loopback Status
0, RO
te
0 = Auto-Negotiation not complete.
Loopback:
1 = Loopback enabled.
0 = Normal operation.
2
Duplex Status
0, RO
Duplex:
ol
e
This bit indicates duplex status and is determined from Auto-Negotiation or Forced Modes.
1 = Full duplex mode.
0 = Half duplex mode.
Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid link or if Auto-Negotiation is disabled and
there is a valid link.
1
Speed Status
0, RO
Speed10:
bs
This bit indicates the status of the speed and is determined from
Auto-Negotiation or Forced Modes.
1 = 10 Mb/s mode.
0 = 100 Mb/s mode.
Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid link or if Auto-Negotiation is disabled and
there is a valid link.
Link Status
O
0
0, RO
Link Status:
This bit is a duplicate of the Link Status bit in the BMSR register,
except that it will no be cleared upon a read of the PHYSTS register.
1 = Valid link established (for either 10 or 100 Mb/s operation).
0 = Link not established.
38
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Table 17. False Carrier Sense Counter Register (FCSCR), address 0x14
Bit
Bit Name
Default
15:8
RESERVED
0, RO
7:0
FCSCNT[7:0]
0, RW / COR
Description
RESERVED: Writes ignored, Read as 0.
False Carrier Event Counter:
This 8-bit counter increments on every false carrier event. This
counter sticks when it reaches its max count (FFh).
This counter provides information required to implement the “SymbolErrorDuringCarrier” attribute within the PHY managed object class of Clause 30 of the IEEE 802.3u specification.
Table 18. Receiver Error Counter Register (RECR), address 0x15
Bit Name
Default
RESERVED
0, RO
7:0
RXERCNT[7:0]
0, RW / COR
Description
RESERVED: Writes ignored, Read as 0
te
Bit
15:8
RX_ER Counter:
ol
e
This 8-bit counter increments for each receive error detected.
When a valid carrier is present and there is at least one occurrence
of an invalid data symbol. This event can increment only once per
valid carrier event. If a collision is present, the attribute will not increment. The counter sticks when it reaches its max count.
Table 19. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16
Bit
Bit Name
15:13
RESERVED
12
BYP_4B5B
Default
<00>, RO
0, RW
Description
RESERVED: Writes ignored, Read as 0.
Bypass 4B/5B Encoding:
1 = 4B5B encoder functions bypassed.
0 = Normal 4B5B operation.
FREE_CLK
0, RW
Receive Clock:
bs
11
1 = RX_CK is free-running.
0 = RX_CK phase adjusted based on alignment.
10
TQ_EN
0, RW
100Mbs True Quiet Mode Enable:
1 = Transmit True Quiet Mode.
0 = Normal Transmit Mode.
SD FORCE PMA
O
9
8
SD_OPTION
0, RW
Signal Detect Force PMA:
1 = Forces Signal Detection in PMA.
0 = Normal SD operation.
1, RW
Signal Detect Option:
1 = Enhanced signal detect algorithm.
0 = Reduced signal detect algorithm.
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DP83846A
This counter provides information required to implement the “FalseCarriers” attribute within the MAU managed object
class of Clause 30 of the IEEE 802.3u specification.
Bit
Bit Name
Default
7
Unused
0,RO
6
RESERVED
0
Description
RESERVED:
Must be zero.
5
FORCE_100_OK
0, RW
Force 100Mb/s Good Link:
1 = Forces 100Mb/s Good Link.
0 = Normal 100Mb/s operation.
4
RESERVED
0
RESERVED:
Must be zero.
3
RESERVED
0
2
NRZI_BYPASS
0, RW
RESERVED:
Must be zero.
NRZI Bypass Enable:
1 = NRZI Bypass Enabled.
1
SCRAM_BYPASS
0, RW
te
0 = NRZI Bypass Disabled.
Scrambler Bypass Enable:
1 = Scrambler Bypass Enabled.
0 = Scrambler Bypass Disabled.
DESCRAM_BYPA
SS
0, RW
Descrambler Bypass Enable:
1 = Descrambler Bypass Enabled.
ol
e
0
0 = Descrambler Bypass Disabled.
Table 20. Reserved Registers, addresses 0x17, 0x18
Bit Name
15:0
RESERVED
Default
none, RW
Description
RESERVED: Must not be written to during normal operation.
O
bs
Bit
40
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DP83846A
Table 19. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16 (Continued)
DP83846A
Table 21. PHY Control Register (PHYCTRL), address 0x19
Bit
Bit Name
Default
15:12
Unused
0, RO
11
PSR_15
0, RW
Description
BIST Sequence select:
1 = PSR15 selected.
0 = PSR9 selected.
10
BIST_STATUS
0, RO/LL
BIST Test Status:
1 = BIST pass.
0 = BIST fail. Latched, cleared by write to BIST_ START bit.
9
BIST_START
0, RW
BIST Start:
1 = BIST start.
0 = BIST stop.
8
BP_STRETCH
0, RW
Bypass LED Stretching:
te
This will bypass the LED stretching for the Receive, Transmit and
Collision LEDs.
1 = Bypass LED stretching.
0 = Normal operation.
7
PAUSE_STS
0, RO
Pause Compare Status:
0 = Local Device and the Link Partner are not Pause capable.
6
RESERVED
5
LED_CNFG
ol
e
1 = Local Device and the Link Partner are both Pause capable.
1, RO/P
Strap, RW
Reserved: Must be 1.
This bit is used to bypass the selective inversion on the LED output
for DPLX - this enables its use in non-LED applications.
Mode Description
1 = Led polarity adjusted - DPLX selected.
0 = DPLX active HIGH.
PHYADDR[4:0]
Strap, RW
PHY Address: PHY address for port.
O
bs
4:0
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DP83846A
Table 22. 10Base-T Status/Control Register (10BTSCR), Address 0x1A
Bit
Bit Name
Default
15:9
Unused
0, RO
8
LOOPBACK_10_DIS
0, RW
Description
10BASE-T Loopback Disable:
If bit 14 (Loopback) in the BMCR is 0:
1 = 10 Mb/s Loopback is disabled.
If bit 14 (Loopback) in the BMCR is 1:
1 = 10 Mb/s Loopback is enabled.
7
LP_DIS
0, RW
Normal Link Pulse Disable:
1 = Transmission of NLPs is disabled.
0 = Transmission of NLPs is enabled.
6
FORCE_LINK_10
0, RW
Force 10Mb Good Link:
1 = Forced Good 10Mb Link.
0 = Normal Link Status.
FORCE_POL_COR
0, RW
Force 10Mb Polarity Correction:
te
5
1 = Force inverted polarity.
0 = Normal polarity.
4
POLARITY
RO/LH
10Mb Polarity Status:
ol
e
This bit is a duplication of bit 12 in the PHYSTS register. Both bits
will be cleared upon a read of 10BTSCR register, but not upon a
read of the PHYSIS register.
1 = Inverted Polarity detected.
0 = Correct Polarity detected.
3
AUTOPOL_DIS
0, RW
Auto Polarity Detection & Correction Disable:
1 = Polarity Sense & Correction disabled.
0 = Polarity Sense & Correction enabled.
2
RESERVED
1, RW
RESERVED:
1
bs
Must be set to one.
HEARTBEAT_DIS
0, RW
Heartbeat Disable: This bit only has influence in half-duplex 10Mb
mode.
1 = Heartbeat function disabled.
0 = Heartbeat function enabled.
O
When the device is operating at 100Mb or configured for full
duplex operation, this bit will be ignored - the heartbeat function is disabled.
0
JABBER_DIS
0, RW
Jabber Disable:
Applicable only in 10BASE-T.
1 = Jabber function disabled.
0 = Jabber function enabled.
42
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Bit
Bit Name
Default
15
CD_ENABLE
1, RW
Description
CD Enable:
1 = CD Enabled - power-down mode, outputs high impedance.
0 = CD Disabled.
14
DCDCOMP
0, RW
Duty Cycle Distortion Compensation:
1 = Increases the amount of DCD compensation.
13
FIL_TTL
0, RW
Waveshaper Current Source Test:
To check ability of waveshaper current sources to switch on/off.
1 = Test mode; waveshaping is done, but the output is a square
wave. All sources are either on or off.
0 = Normal mode; sinusoidal.
RESERVED
none, RW
Reserved: This bit should be written with a 0 if write access is required on this register.
11
RISETIME
Strap, RW
CD Rise Time Control:
10
RESERVED
none, RW
Reserved: This bit should be written with a 0 if write access is required on this register.
9
FALLTIME
Strap, RW
CD Fall Time Control:
8
CDTESTEN
0, RW
CD Test Mode Enable:
te
12
ol
e
1 = Enable CD test mode - differs based on speed of operation
(10/100Mb).
0 = Normal operation.
7:5
RESERVED[2:0]
000, RW
4
CDPATTEN_10
0, RW
RESERVED:
Must be zero.
CD Pattern Enable for 10meg:
1 = Enabled.
0 = Disabled.
3
CDPATTEN_100
0, RW
CD Pattern Enable for 100meg:
bs
1 = Enabled.
0 = Disabled.
2
10MEG_PATT_GAP
0, RW
Defines gap between data or NLP test sequences:
1 = 15 µs.
0 = 10 µs.
CDPATTSEL[1:0]
O
1:0
00, RW
CD Pattern Select[1:0]:
If CDPATTEN_100 = 1:
00 = All 0’s (True quiet)
01 = All 1’s
10 = 2 1’s, 2 0’s repeating pattern
11 = 14 1’s, 6 0’s repeating pattern
If CDPATTEN_10 = 1:
00 = Data, EOP0 sequence
01 = Data, EOP1 sequence
10 = NLPs
11 = Constant Manchester 1s (10mhz sine wave) for harmonic distortion testing.
43
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DP83846A
Table 23. CD Test Register (CDCTRL), Address 0x1B
Absolute Maximum Ratings
Recommended Operating Conditions
Supply voltage (VCC)
Supply Voltage (VCC)
-0.5 V to 4.2 V
DC Input Voltage (VIN)
-0.5V to 5.5V
Ambient Temperature (TA)
DC Output Voltage (VOUT)
-0.5V to 5.5V
Max. die temperature (Tj)
Storage Temperature (TSTG)
260°C
ESD Rating
(RZAP = 1.5k, CZAP = 120 pF)
1.0 kV
0 to 70 °C
107°C
Max case temp
-65oC to 150°C
Lead Temp. (TL)
(Soldering, 10 sec)
3.3 Volts + 0.3V
96°C
Absolute maximum ratings are those values beyond which
the safety of the device cannot be guaranteed. They are
not meant to imply that the device should be operated at
these limits.
Thermal Characteristic
Units
te
Max
15
Theta Junction to Case (Tjc)
°C / W
51
°C / W
Theta Junction to Ambient (Tja) degrees Celsius/Watt - 225 LFPM Airflow @ 1.0W
42
°C / W
Theta Junction to Ambient (Tja) degrees Celsius/Watt - 500 LFPM Airflow @ 1.0W
37
°C / W
Theta Junction to Ambient (Tja) degrees Celsius/Watt - 900 LFPM Airflow @ 1.0W
33
°C / W
ol
e
Theta Junction to Ambient (Tja) degrees Celsius/Watt - No Airflow @ 1.0W
Note:0 DC Electrical Specification
Symbol
Pin Types
Parameter
Conditions
Min
Typ
Max
Units
I
I/O
Input High Voltage Nominal VCC
VIL
I
I/O
Input Low Voltage
0.8
V
IIH
I
I/O
Input High Current VIN = VCC
10
µA
I
I/O
Input Low Current VIN = GND
10
µA
O,
I/O
Output Low
Voltage
IOL = 4 mA
0.4
V
O,
I/O
Output High
Voltage
IOH = -4 mA
VledOL
LED
Output Low
Voltage
* IOL = 2.5 mA
VledOH
LED
Output High
Voltage
IOH = -2.5 mA
IOZH
I/O,
O
TRI-STATE
Leakage
VOUT = VCC
10
µA
I5IH
I/O,
O
5 Volt Tolerant
MII Leakage
VIN = 5.25 V
10
µA
I5OZH
I/O,
O
5 Volt Tolerant
MII Leakage
VOUT = 5.25 V
10
µA
RINdiff
RD+/−
Differential Input
Resistance
VTPTD_100
TD+/−
100M Transmit
Voltage
IIL
VOL
O
VOH
bs
VIH
2.0
V
VCC - 0.5
V
0.4
VCC - 0.5
V
1.1
.95
44
V
1
kΩ
1.05
V
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DP83846A
6.0 Electrical Specifications
Pin Types
Parameter
VTPTDsym
TD+/−
100M Transmit
Voltage Symmetry
VTPTD_10
TD+/−
10M Transmit
Voltage
I
CMOS Input
Capacitance
CIN1
Conditions
Min
2.2
Parameter is not
100% tested
Units
2.5
%
2.8
V
8
RD+/−
100BASE-TX
Signal detect turnon threshold
SDTHoff
RD+/−
100BASE-TX
Signal detect turnoff threshold
200
VTH1
RD+/−
10BASE-T Receive Threshold
300
Idd100
Supply
100BASE-TX
(Full Duplex)
IOUT = 0 mA
10BASE-T
(Full Duplex)
IOUT = 0 mA
pF
1000
See Note
mV diff pk-pk
585
mV
150
200
mA
100
130
mA
te
See Note
mV diff pk-pk
ol
e
Supply
Max
±2
SDTHon
Idd10
Typ
O
bs
Note: For Idd Measurements, outputs are not loaded.
45
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DP83846A
Symbol
DP83846A
6.1 Reset Timing
VCC
X1 Clock
T1.0.1
T1.0.4
HARDWARE
RSTN
32 CLOCKS
te
MDC
T1.0.2
ol
e
Latch-In of Hardware
Configuration Pins
T1.0.3
INPUT
OUTPUT
Dual Function Pins
Become Enabled As Outputs
T1.0.1
T1.0.2
T1.0.4
Notes
Min
Typ
Max
Units
MDIO is pulled high for 32-bit serial management initialization
3
µs
Hardware Configuration Latch-in Hardware Configuration Pins are
Time from the Deassertion of RE- described in the Pin Description
SET (either soft or hard)
section
3
µs
3.5
µs
Post RESET Stabilization time
prior to MDC preamble for register accesses
Hardware Configuration pins
transition to output drivers
O
T1.0.3
Description
bs
Parameter
RESET pulse width
X1 Clock must be stable for a
minimum of 160us during RESET
pulse low time.
160
µs
Note1: Software Reset should be initiated no sooner then 500 µs after power-up or the deassertion of hardware reset.
Note2: It is important to choose pull-up and/or pull-down resistors for each of the hardware configuration pins that provide
fast RC time constants in order to latch-in the proper value prior to the pin transitioning to an output driver.
46
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DP83846A
6.2 PGM Clock Timing
X1
TX_CLK
Parameter
T2.0.1
te
T2.0.1
Description
Notes
TX_CLK Duty Cycle
Typ
35
Max
Units
65
%
Max
Units
300
ns
ol
e
6.3 MII Serial Management Timing
MDC
Min
T3.0.1
T3.0.4
bs
MDIO (output)
MDC
T3.0.2
O
MDIO (input)
Parameter
Description
T3.0.3
Valid Data
Notes
Min
Typ
T3.0.1
MDC to MDIO (Output) Delay Time
0
T3.0.2
MDIO (Input) to MDC Setup Time
10
ns
T3.0.3
MDIO (Input) to MDC Hold Time
10
ns
T3.0.4
MDC Frequency
2.5
47
MHz
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DP83846A
6.4 100 Mb/s Timing
6.4.1 100 Mb/s MII Transmit Timing
TX_CLK
T4.1.2
T4.1.1
TXD[3:0]
TX_EN
TX_ER
Parameter
Valid Data
Description
Notes
Min
Typ
Max Units
TXD[3:0], TX_EN, TX_ER Data Setup to
TX_CLK
10
ns
T4.1.2
TXD[3:0], TX_EN, TX_ER Data Hold from
TX_CLK
5
ns
te
T4.1.1
6.4.2 100 Mb/s MII Receive Timing
RX_CLK
ol
e
T4.2.1
T4.2.2
Parameter
T4.2.1
Description
Notes
Min
Typ
Max
Units
RX_CLK Duty Cycle
35
65
%
RX_CLK to RXD[3:0], RX_DV, RX_ER Delay
10
30
ns
O
T4.2.2
Valid Data
bs
RXD[3:0]
RX_DV
RX_ER
48
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DP83846A
6.4.3 100BASE-TX Transmit Packet Latency Timing
TX_CLK
TX_EN
TXD
IDLE
TD±
Parameter
Description
(J/K)
DATA
Notes
TX_CLK to TD± Latency
Min
Typ
ol
e
T4.3.1
te
T4.3.1
Max
Units
6.0
bit times
Note: Latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of
TX_EN to the first bit of the “J” code group as output from the TD± pins.
6.4.4 100BASE-TX Transmit Packet Deassertion Timing
bs
TX_CLK
O
TX_EN
TXD
TD±
Parameter
T4.4.1
T4.4.1
DATA
(T/R)
DATA
(T/R)
Description
Notes
TX_CLK to TD± Deassertion
IDLE
IDLE
Min
Typ
Max
Units
6.0
bit times
Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the first bit of the “T” code group as output from the TD± pins.
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DP83846A
6.4.5 100BASE-TX Transmit Timing (tR/F & Jitter)
T4.5.1
+1 rise
90%
10%
TD±
10%
+1 fall
90%
T4.5.1
-1 fall
-1 rise
T4.5.1
te
T4.5.1
T4.5.2
TD±
eye pattern
T4.5.1
Description
Notes
Min
Typ
Max
Units
3
4
5
ns
100 Mb/s tR and tF Mismatch
500
ps
100 Mb/s TD± Transmit Jitter
1.4
ns
100 Mb/s TD± tR and tF
bs
T4.5.2
ol
e
Parameter
T4.5.2
Note1: Normal Mismatch is the difference between the maximum and minimum of all rise and fall times.
O
Note2: Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude.
50
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DP83846A
6.4.6 100BASE-TX Receive Packet Latency Timing
RD±
IDLE
Data
(J/K)
T4.6.1
CRS
T4.6.2
Parameter
te
RXD[3:0]
RX_DV
RX_ER/RXD[4]
Description
T4.6.1
Carrier Sense ON Delay
T4.6.2
Receive Data Latency
Notes
Min
Typ
Max
Units
17.5
bit times
21
bit times
ol
e
Note: Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion
of Carrier Sense.
Note: RD± voltage amplitude is greater than the Signal Detect Turn-On Threshold Value.
6.4.7 100BASE-TX Receive Packet Deassertion Timing
RD±
DATA
IDLE
(T/R)
bs
T4.7.1
O
CRS
RXD[3:0]
RX_DV
RX_ER/RXD[4]
Parameter
T4.7.1
Description
Notes
Carrier Sense OFF Delay
Min
Typ
Max
Units
21.5
bit times
Note: Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense.
51
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DP83846A
6.5 10 Mb/s Timing
6.5.1 10 Mb/s MII Transmit Timing
TX_CLK
T5.1.2
T5.1.1
TXD[3:0]
TX_EN
Parameter
Valid Data
Description
Notes
Min
Typ
Max Units
TXD[3:0], TX_EN Data Setup to TX_CLK
25
ns
T5.1.2
TXD[3:0], TX_EN Data Hold from TX_CLK
5
ns
te
T5.1.1
6.5.2 10 Mb/s MII Receive Timing
RX_CLK
Parameter
T5.2.1
Valid Data
Description
Notes
Min
Typ
Max
Units
RX_CLK Duty Cycle
35
65
%
RX_CLK to RXD[3:0], RX_DV
190
210
ns
O
T5.2.2
T5.2.2
bs
RXD[3:0]
RX_DV
ol
e
T5.2.1
52
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DP83846A
6.5.3 10BASE-T Transmit Timing (Start of Packet)
TX_CLK
T5.3.1
TX_EN
T5.3.2
T5.3.3
TXD[0]
TPTD±
Parameter
te
T5.3.4
Description
Notes
Transmit Enable Setup Time from the
Falling Edge of TX_CLK
T5.3.2
Transmit Data Setup Time from the
Falling Edge of TX_CLK
T5.3.3
Transmit Data Hold Time from the
Falling Edge of TX_CLK
T5.3.4
Transmit Output Delay from the
Falling Edge of TX_CLK
Typ
Max
Units
25
ns
25
ns
ol
e
T5.3.1
Min
5
ns
6.8
bit times
6.5.4 10BASE-T Transmit Timing (End of Packet)
bs
TX_CLK
T5.4.1
TX_EN
O
TPTD±
TPTD±
Parameter
0
1
0
T5.4.3
1
Description
T5.4.1
Transmit Enable Hold Time from the
Falling Edge of TX_CLK
T5.4.2
End of Packet High Time
T5.4.2
Notes
Min
Typ
Max
Units
5
ns
250
ns
250
ns
(with ‘0’ ending bit)
T5.4.3
End of Packet High Time
(with ‘1’ ending bit)
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DP83846A
6.5.5 10BASE-T Receive Timing (Start of Packet)
1st SFD bit decoded
1
0
1
TPRD±
T5.5.1
CRS
T5.5.2
RX_CLK
T5.5.4
te
RXD[0]
T5.5.3
Parameter
ol
e
RX_DV
Description
Notes
Min
Typ
Max
Units
1
µs
T5.5.1
Carrier Sense Turn On Delay
(TPRD± to CRS)
T5.5.2
Decoder Acquisition Time
3.6
µs
T5.5.3
Receive Data Latency
17.3
bit times
T5.5.4
SFD Propagation Delay
10
bit times
bs
Note: 10BASE-T receive Data Latency is measured from first bit of preamble on the wire to the assertion of RX_DV.
6.5.6 10BASE-T Receive Timing (End of Packet)
1
0
1
IDLE
O
TPRD±
RX_CLK
T5.6.1
CRS
Parameter
T5.6.1
Description
Notes
Carrier Sense Turn Off Delay
54
Min
Typ
Max
Units
1.1
µs
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DP83846A
6.5.7 10 Mb/s Heartbeat Timing
TXE
TXC
T5.7.2
T5.7.1
COL
Parameter
Description
Notes
Min
Typ
Max
Units
CD Heartbeat Delay
600
1600
ns
T5.7.2
CD Heartbeat Duration
500
1500
ns
Max
Units
te
T5.7.1
6.5.8 10 Mb/s Jabber Timing
ol
e
TXE
T5.8.1
T5.8.2
TPTD±
bs
COL
Parameter
T5.8.1
T5.8.2
Description
Notes
Min
Typ
Jabber Activation Time
20
150
ms
Jabber Deactivation Time
250
750
ms
Max
Units
O
6.5.9 10BASE-T Normal Link Pulse Timing
T5.9.2
T5.9.1
Normal Link Pulse(s)
Parameter
Description
T5.9.1
Pulse Width
T5.9.2
Pulse Period
Notes
Min
Typ
100
8
55
16
ns
24
ms
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DP83846A
6.5.10 Auto-Negotiation Fast Link Pulse (FLP) Timing
T5.10.2
T5.10.3
T5.10.1
T5.10.1
Fast Link Pulse(s)
clock
pulse
data
pulse
clock
pulse
T5.10.6
T5.10.5
FLP Burst
Parameter
Description
Clock, Data Pulse Width
T5.10.2
Clock Pulse to Clock Pulse
Period
T5.10.3
Clock Pulse to Data Pulse
Period
T5.10.4
Number of Pulses in a Burst
T5.10.5
Burst Width
T5.10.6
FLP Burst to FLP Burst Period
FLP Burst
Notes
Min
Typ
Max
100
ol
e
T5.10.1
te
T5.10.4
Data = 1
Units
ns
139
µs
55.5
69.5
µs
17
33
#
111
125
2
8
ms
24
ms
bs
6.5.11 100BASE-TX Signal Detect Timing
RD±
T5.11.1
O
T5.11.2
SD+ internal
Max
Units
T5.11.1
Parameter
SD Internal Turn-on Time
Description
Notes
Min
Typ
1
ms
T5.11.2
SD Internal Turn-off Time
300
µs
Note: The signal amplitude at RD± is TP-PMD compliant.
56
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DP83846A
6.6 Loopback Timing
6.6.1 100 Mb/s Internal Loopback Mode
TX_CLK
TX_EN
CRS
T6.1.1
RX_DV
bs
RXD[3:0]
Parameter
T6.1.1
ol
e
RX_CLK
te
TXD[3:0]
Description
Notes
Min
TX_EN to RX_DV Loopback
Typ
Max
Units
240
ns
Note1: Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time”
of up to 550 µs during which time no data will be present at the receive MII outputs. The 100BASE-TX timing specified is
based on device delays after the initial 550µs “dead-time”.
O
Note2: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
57
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DP83846A
6.6.2 10 Mb/s Internal Loopback Mode
TX_CLK
TX_EN
TXD[3:0]
CRS
te
T6.2.1
RX_DV
RXD[3:0]
T6.2.1
Description
Notes
bs
Parameter
ol
e
RX_CLK
Min
TX_EN to RX_DV Loopback
Typ
Max
Units
2
µs
O
Note: Measurement is made from the first falling edge of TX_CLK after assertion of TX_EN.
58
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DP83846A
6.7 Isolation Timing
Clear bit 10 of BMCR
(return to normal operation
from Isolate mode)
T7.0.1
H/W or S/W Reset
(with PHYAD = 00000)
T7.0.2
MODE
NORMAL
Parameter
Description
From software clear of bit 10 in
the BMCR register to the transition from Isolate to Normal Mode
T7.0.2
From Deassertion of S/W or H/W
Reset to transition from Isolate to
Normal mode
Notes
Min
Typ
Max
Units
100
µs
500
µs
O
bs
ol
e
T7.0.1
te
ISOLATE
59
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te
ol
e
bs
Plastic Quad Flat Pack (LQFP)
Order Number DP83846AVHG
NS Package Number VHG-80A
LIFE SUPPORT POLICY
O
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
National Semiconductor
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Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: [email protected]
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Fax: +49 (0) 180-530 85 86
Email: [email protected]
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Francais Tel: +33 (0) 1 41 91 8790
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: [email protected]
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
DP83846A DsPHYTER — Single 10/100 Ethernet Transceiver
7.0 Physical Dimensions
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