Low Power, Precision Analog Microcontroller with Dual Sigma-Delta ADCs, ARM Cortex-M3 ADuCM362/ADuCM363 Data Sheet FEATURES Pin compatible with the ADuCM360/ADuCM361 Analog input/output Dual 24-bit ADCs (ADuCM362) Single 24-bit ADC (ADuCM363) Programmable ADC output rate (3.5 Hz to 3.906 kHz) Simultaneous 50 Hz/60 Hz noise rejection At 50 SPS continuous conversion mode At 16.67 SPS single conversion mode Flexible input mux for input channel selection to both ADCs Two 24-bit multichannel ADCs (ADC0 and ADC1) 6 differential or 12 single-ended input channels 4 internal channels for monitoring DAC, temperature sensor, IOVDD/4, and AVDD/4 (ADC1 only) Programmable gain (1 to 128) Gain of 1 with input buffer on/off supported RMS noise: 52 nV at 3.53 Hz, 200 nV at 50 Hz Programmable sensor excitation current sources On-chip precision voltage reference Two external reference options supported by both ADCs Single 12-bit voltage output DAC NPN mode for 4 mA to 20 mA loop applications Microcontroller ARM Cortex-M3 32-bit processor Serial wire download and debug Internal watch crystal for wake-up timer 16 MHz oscillator with 8-way programmable divider Memory Up to 256 kB Flash/EE memory, 24 kB SRAM In-circuit debug/download via serial wire and UART Rev. 0 Power supply range: 1.8 V to 3.6 V (maximum) Power consumption, MCU active mode Core consumes 290 μA/MHz Overall system current consumption of 1.0 mA with core operating at 500 kHz (both ADCs on, input buffers off, PGA gain of 4, one SPI port on, and all timers on) Power consumption, power-down mode: 4 μA (wake-up timer active) On-chip peripherals 2× UART, I2C, and 2 × SPI serial input/output (I/O) 16-bit pulse-width modulation (PWM) controller 19-pin multifunction GPIO port 2 general-purpose timers Wake-up timer/watchdog timer Multichannel DMA and interrupt controller DMA support for both SPI channels Package and temperature range 48-lead, 7 mm × 7 mm LFCSP Specified for −40°C to +125°C operation Development tools Low cost QuickStart Development System Third-party compiler and emulator tool support Multiple diagnostic functions that support SIL certification APPLICATIONS Industrial automation and process control Intelligent precision sensing systems 4 mA to 20 mA loop-powered smart sensor systems Medical devices, patient monitoring Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. 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Technical Support www.analog.com ADuCM362/ADuCM363 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 SPI Timing Specifications ......................................................... 16 Applications ....................................................................................... 1 Absolute Maximum Ratings ......................................................... 18 Revision History ............................................................................... 2 Thermal Resistance .................................................................... 18 General Description ......................................................................... 3 ESD Caution................................................................................ 18 Functional Block Diagrams ............................................................. 4 Pin Configuration and Function Descriptions........................... 19 Specifications..................................................................................... 6 Typical Performance Characteristics ........................................... 22 Microcontroller Electrical Specifications .................................. 6 Typical System Configuration ...................................................... 23 RMS Noise Resolution of ADC0 and ADC1 .......................... 11 Outline Dimensions ....................................................................... 24 2 I C Timing Specifications .......................................................... 15 Ordering Guide .......................................................................... 24 REVISION HISTORY 10/2016—Revision 0: Initial Version Rev. 0| Page 2 of 24 Data Sheet ADuCM362/ADuCM363 GENERAL DESCRIPTION The ADuCM362/ADuCM363 are fully integrated, 3.9 kSPS, 24-bit data acquisition systems that incorporate dual, high performance, multichannel sigma-delta (Σ-Δ) analog-to-digital converters (ADCs), a 32-bit ARM Cortex™-M3 processor, and Flash/EE memory on a single chip. The ADuCM362/ ADuCM363 are designed for direct interfacing to external precision sensors in both wired and battery-powered applications. The ADuCM363 contains all the features of the ADuCM362, except that only one 24-bit Σ-Δ ADC (ADC1) is available. The ADuCM362/ADuCM363 contain an on-chip 32 kHz oscillator and an internal 16 MHz high frequency oscillator. The high frequency oscillator is routed through a programmable clock divider from which the operating frequency of the processor core clock is generated. The maximum core clock speed is 16 MHz; this speed is not limited by operating voltage or temperature. The microcontroller core is a low power ARM Cortex-M3 processor, a 32-bit RISC machine that offers up to 20 MIPS peak performance. The Cortex-M3 processor incorporates a flexible, 11-channel DMA controller that supports all wired communication peripherals (both SPIs, both UARTs, and I2C). Also integrated on chip are up to 256 kB of nonvolatile Flash/EE memory and 24 kB of SRAM. The analog subsystem consists of dual ADCs, each connected to a flexible input mux. Both ADCs can operate in fully differential and single-ended modes. Other on-chip ADC features include dual programmable excitation current sources, diagnostic current sources, and a bias voltage generator of AVDD_REG/2 (900 mV) to set the common-mode voltage of an input channel. A low-side internal ground switch is provided to allow power-down of an external circuit (for example, a bridge circuit) between conversions. Optional input buffers are provided for the analog inputs and the external reference inputs. These buffers can be enabled for all PGA gain settings. The ADCs contain two parallel filters: a sinc3 or sinc4 filter in parallel with a sinc2 filter. The sinc3 or sinc4 filter is used for precision measurements. The sinc2 filter is used for fast measurements and for the detection of step changes in the input signal. The devices contain a low noise, low drift internal band gap reference, but they can be configured to accept one or two external reference sources in ratiometric measurement configurations. An option to buffer the external reference inputs is provided on chip. A single-channel buffered voltage output DAC is also provided on chip. The ADuCM362/ADuCM363 integrate a range of on-chip peripherals, which can be configured under microcontroller software control as required in the application. The peripherals include two UARTs, I2C, and dual SPI serial I/O communication controllers; a 19-pin GPIO port; two general-purpose timers; a wake-up timer; and a system watchdog timer. A 16-bit PWM controller with six output channels is also provided. The ADuCM362/ADuCM363 are specifically designed to operate in battery-powered applications where low power operation is critical. The microcontroller core can be configured in a normal operating mode that consumes 290 μA/MHz (including flash/ SRAM IDD). An overall system current consumption of 1 mA can be achieved with both ADCs on (input buffers off), PGA gain of 4, one SPI port on, and all timers on. The ADuCM362/ADuCM363 can be configured in a number of low power operating modes under direct program control, including a hibernate mode (internal wake-up timer active) that consumes only 4 μA. In hibernate mode, peripherals, such as external interrupts or the internal wake-up timer, can wake up the devices. This mode allows the devices to operate with ultralow power while still responding to asynchronous external or periodic events. On-chip factory firmware supports in-circuit serial download via a serial wire interface (2-pin JTAG system) and UART; nonintrusive emulation is also supported via the serial wire interface. These features are incorporated into a low cost QuickStart™ Development System that supports this precision analog microcontroller family. The devices operate from an external 1.8 V to 3.6 V voltage supply and are specified over an industrial temperature range of −40°C to +125°C. Rev. 0 | Page 3 of 24 ADuCM362/ADuCM363 Data Sheet FUNCTIONAL BLOCK DIAGRAMS ON-CHIP 1.8V ANALOG LDO 12-BIT DAC BUFFER AMP BUF MOD2 GAIN VREF 24-BIT Σ-∆ ADC Σ-∆ MODULATOR SINC3/ SINC4 FILTER AIN6/IEXC AIN8/EXTREF2IN– AIN9/DACBUFF+ AIN10 AIN11/VBIAS1 SINC2 FILTER MUX AMP BUF MOD2 GAIN RESET ON-CHIP OSCILLATOR (1% TYP) 16MHz XTALO VREF 24-BIT Σ-∆ ADC Σ-∆ MODULATOR SINC3/ SINC4 FILTER ARM CORTEX-M3 PROCESSOR 16MHz XTALI GPIO PORTS UART PORTS 2 × SPI PORTS I2 C PORTS MEMORY 256kB FLASH 24kB SRAM TIMER0 TIMER1 WATCHDOG WAKE-UP TIMER PWM DMA AND INTERRUPT CONTROLLER SERIAL WIRE DEBUG, PROGRAMMING AND DEBUG SELECTABLE VREF SOURCES DAC, TEMP, IOVDD/4, AVDD/4 19 GENERALPURPOSE I/O PORTS SWDIO SWCLK PRECISION REFERENCE IREF POWER-ON RESET VBIAS GENERATOR AIN0 AIN1 AIN2 AIN3 AIN4/IEXC AIN5/IEXC AIN7/VBIAS0/IEXC/ EXTREF2IN+ ON-CHIP 1.8V DIGITAL LDO ADuCM362 DVDD_REG BUFFER CURRENT SOURCES AVDD_REG BUFFER GND_SW VREF– VREF+ INT_REF Figure 1. ADuCM362 Functional Block Diagram Rev. 0| Page 4 of 24 IOVDD IOVDD 14919-001 DAC AVDD AGND Data Sheet ON-CHIP 1.8V ANALOG LDO 12-BIT DAC BUFFER ARM CORTEX-M3 PROCESSOR 16MHz AIN6/IEXC AIN8/EXTREF2IN– AIN9/DACBUFF+ AIN10 AIN11/VBIAS1 SINC2 FILTER MUX AMP BUF MOD2 GAIN RESET ON-CHIP OSCILLATOR (1% TYP) 16MHz XTALO VREF 24-BIT Σ-∆ ADC Σ-∆ MODULATOR SINC3/ SINC4 FILTER XTALI GPIO PORTS UART PORTS 2 × SPI PORTS I2C PORTS MEMORY 256kB FLASH 24kB SRAM TIMER0 TIMER1 WATCHDOG WAKE-UP TIMER PWM DMA AND INTERRUPT CONTROLLER SERIAL WIRE DEBUG, PROGRAMMING AND DEBUG SELECTABLE VREF SOURCES DAC, TEMP, IOVDD/4, AVDD/4 19 GENERALPURPOSE I/O PORTS SWDIO SWCLK PRECISION REFERENCE IREF POWER-ON RESET VBIAS GENERATOR AIN0 AIN1 AIN2 AIN3 AIN4/IEXC AIN5/IEXC AIN7/VBIAS0/IEXC/ EXTREF2IN+ ON-CHIP 1.8V DIGITAL LDO ADuCM363 DVDD_REG BUFFER CURRENT SOURCES AVDD_REG BUFFER GND_SW VREF– VREF+ INT_REF Figure 2. ADuCM363 Functional Block Diagram Rev. 0 | Page 5 of 24 IOVDD IOVDD 14919-014 DAC AVDD AGND ADuCM362/ADuCM363 ADuCM362/ADuCM363 Data Sheet SPECIFICATIONS MICROCONTROLLER ELECTRICAL SPECIFICATIONS AVDD/IOVDD = 1.8 V to 3.6 V, internal 1.2 V reference, fCORE = 16 MHz, all specifications at TA = −40°C to +125°C, unless otherwise noted. Table 1. Parameter ADC SPECIFICATIONS Conversion Rate1 No Missing Codes1 RMS Noise and Data Output Rates Integral Nonlinearity1 Offset Error2, 3, 4, 6, 7 Offset Error Drift vs. Temperature1, 4, 6 Offset Error Lifetime Stability5 Full-Scale Error1, 4, 6, 7, 8 Full-Scale Error Lifetime Stability5 Gain Error Drift vs. Temperature1, 4, 6 PGA Gain Mismatch Error Power Supply Rejection1 Test Conditions/Comments ADC0 and ADC1 Chop off Chop on Chop off, fADC ≤ 500 Hz Chop on, fADC ≤ 250 Hz See Table 2 through Table 9 Gain = 1, input buffer off Gain = 2, 4, 8, or 16 Gain = 32, 64, or 128 Chop off; offset error is in the order of the noise for the programmed gain and update rate following calibration Chop on1 Chop off, gain ≤ 4 Chop off, gain ≥ 8 Chop on Gain = 128 External reference Chop on, ADC input = 0.25 V, gain = 4 Chop off, ADC input = 7.8 mV, gain = 128 Chop off, ADC input = 1 V, gain = 1 Common-Mode Voltage, VCM1 Available for all gain settings G = 1 to 128 For gain = 32, 64, and 128, see Table 3 and Table 7 for allowable input ranges and noise values Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Ideally, VCM = ((AIN+) + (AIN−))/2; gain = 2 to 128; input current varies with VCM (see Figure 9 and Figure 10) Rev. 0| Page 6 of 24 Typ 3.5 3.5 24 24 Gain = 128 External reference Gain = 1, 2, 4, 8, or 16 Gain = 32, 64, or 128 Absolute Input Voltage Range Unbuffered Mode Buffered Mode Differential Input Voltage Ranges1 Min Max Unit 3906 1302 Hz Hz Bits Bits ±10 ±15 ±20 ±230/gain ppm of FSR ppm of FSR ppm of FSR μV ±1.0 1/gain 230 10 1 ±0.5/gain 70 μV μV/°C nV/°C nV/°C μV/1000 Hr mV μV/1000 Hr ±3 ±6 ±0.15 ppm/°C ppm/°C % 95 80 90 dB dB dB AGND AVDD V AGND + 0.1 AVDD − 0.1 V AGND ±VREF ±500 ±250 ±125 ±62.5 AVDD V mV mV mV mV V Data Sheet Parameter Input Current9 Buffered Mode Unbuffered Mode Average Input Current Drift1 Buffered Mode Unbuffered Mode Common-Mode Rejection, DC1 Common-Mode Rejection, 50 Hz/60 Hz1 Normal Mode Rejection, 50 Hz/60 Hz1 TEMPERATURE SENSOR1 Voltage Output at 25°C Voltage Temperature Coefficient (TC) Accuracy GROUND SWITCH On Resistance (RON) Allowable Current1 VOLTAGE REFERENCE Internal VREF Initial Accuracy Reference Temperature Coefficient (TC)1, 10 Power Supply Rejection1 EXTERNAL REFERENCE INPUTS Input Range Buffered Mode Unbuffered Mode ADuCM362/ADuCM363 Test Conditions/Comments Min Typ Max Unit Gain > 1 (excluding AIN4, AIN5, AIN6, and AIN7 pins) Gain > 1 (AIN4, AIN5, AIN6, and AIN7 pins) Input current varies with input voltage 1 nA 2 860 nA nA/V AIN1, AIN3, AIN5, AIN7, and AIN11 AIN0, AIN4, AIN9, and AIN10 AIN2, AIN6, and AIN8 ±5 ±9 ±15 ±250 pA/°C pA/°C pA/°C pA/V/°C 100 100 dB dB dB On ADC input ADC gain = 1, AVDD < 2 V ADC gain = 1, AVDD > 2 V ADC gain = 2 to 128 50 Hz/60 Hz ± 1 Hz; fADC = 16.67 Hz, chop on; fADC = 50 Hz, chop off ADC gain = 1 ADC gain = 2 to 128 On ADC input 50 Hz/60 Hz ± 1 Hz; fADC = 16.67 Hz, chop on; fADC = 50 Hz, chop off After user calibration Processor powered down or in standby mode before measurement 65 80 80 97 90 60 3.7 dB dB 80 dB 82.1 mV 250 6 μV/°C °C 10 20 kΩ resistor off, direct short to ground ADC internal reference 19 20 Ω mA +0.1 +15 V % ppm/°C 1.2 Measured at TA = 25°C Minimum differential voltage between VREF+ and VREF− pins is 400 mV Input Current Buffered Mode Unbuffered Mode Normal Mode Rejection1 Common-Mode Rejection1 Reference Detect Levels1 −0.1 −15 ±5 82 90 AGND + 0.1 0 −20 85 Rev. 0 | Page 7 of 24 +10 500 80 100 400 dB AVDD − 0.1 AVDD V V +27 nA nA/V dB dB mV ADuCM362/ADuCM363 Parameter EXCITATION CURRENT SOURCES Output Current Initial Tolerance at 25°C1 Drift1 Initial Current Matching at 25°C1 Drift Matching1 Load Regulation, AVDD1 Output Compliance1 DAC CHANNEL SPECIFICATIONS Voltage Range DC Specifications11 Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error NPN Mode1 Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Output Current Range Interpolation Mode1, 12 Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error DAC AC CHARACTERISTICS1 Voltage Output Settling Time Digital-to-Analog Glitch Energy POWER-ON RESET (POR) POR Trip Level Timeout from POR1 WATCHDOG TIMER (WDT)1 Timeout Period Timeout Step Size FLASH/EE MEMORY1 Endurance13 Data Retention14 Data Sheet Test Conditions/Comments Min Available from each current source; value programmable from 10 μA to 1 mA IOUT ≥ 50 μA Using internal reference resistor Using external 150 kΩ reference resistor between IREF pin and AGND; resistor must have drift specification of 5 ppm/°C Matching between both current sources 10 AVDD = 3.3 V IOUT = 10 μA to 210 μA IOUT > 210 μA RL = 5 kΩ, CL = 100 pF Internal reference External reference Typ Max Unit 1000 μA 400 400 % ppm/°C ppm/°C AGND − 0.03 AGND − 0.03 AVDD − 0.85 AVDD − 1.1 % ppm/°C %/V V V 0 0 VREF 1.8 V V ±1 ±10 ±0.5 Bits LSB LSB mV % 23.6 Bits LSB LSB mA mA mA ±5 100 75 ±0.5 50 0.2 12 ±3 ±0.5 ±2 Guaranteed monotonic 1.2 V internal reference VREF range (reference = 1.2 V) 12 ±3 ±0.5 ±0.35 ±0.75 0.008 Only monotonic to 14 bits For 14-bit resolution Monotonic (14 bits) 1.2 V internal reference VREF range (reference = 1.2 V) AVDD range 1 LSB change at major carry (maximum number of bits changes simultaneously in the DAC0DAT register) Voltage at DVDD pin Power-on level Power-down level 14 ±6 ±0.6 ±2 ±1 ±1 Bits LSB LSB mV % % 10 ±20 μs nV-sec 1.65 1.65 50 V V ms 0.00003 T3CON[3:2] = 10 8192 7.8125 10,000 10 TJ = 85°C Rev. 0| Page 8 of 24 sec ms Cycles Years Data Sheet Parameter DIGITAL INPUTS Input Leakage Current Logic 1 Logic 0 Input Leakage Current Logic 1 Logic 0 Input Capacitance1 Logic Input Voltage Low, VINL High, VINH Logic Output Voltage High, VOH Low, VOL CRYSTAL OSCILLATOR1 Logic Input Voltage, XTALI Only15 Low, VINL High, VINH XTALI Capacitance XTALO Capacitance ON-CHIP LOW POWER OSCILLATOR Oscillator Frequency Accuracy ON-CHIP HIGH FREQUENCY OSCILLATOR Oscillator Frequency Accuracy Long Term Stability5 PROCESSOR CLOCK RATE1 Using an External Clock PROCESSOR START-UP TIME1 At Power-On After Reset Event From Processor Power-Down (Mode 1, Mode 2, and Mode 3) From Total Halt or Hibernate Mode (Mode 4 or Mode 5) ADuCM362/ADuCM363 Test Conditions/Comments All digital inputs Digital inputs except for the RESET, SWCLK, and SWDIO pins VINH = IOVDD or VINH = 1.8 V Internal pull-up disabled VINL = 0 V Internal pull-up disabled RESET, SWCLK, and SWDIO pins Min Typ Max 140 1 160 10 μA nA μA nA 140 160 10 μA μA pF 0.2 × IOVDD 0.7 × IOVDD ISOURCE = 1 mA ISINK = 1 mA 32.768 kHz crystal inputs IOVDD − 0.4 0.4 0.8 1.7 6 6 −30 32.768 ±10 +30 16 −40°C to +125°C −1.8 Nine programmable core clock selections within specified range 0.0625 0.8 0.5 Rev. 0 | Page 9 of 24 V V V V V V pF pF kHz % 16 MHz % °C/1000 Hr MHz 16 MHz +1.4 0.032768 Includes kernel power-on execution time Includes kernel power-on execution time fCLK is the Cortex-M3 core clock Unit 41 ms 1.44 ms 3 to 5 fCLK 30.8 μs ADuCM362/ADuCM363 Parameter POWER REQUIREMENTS Power Supply Voltages, VDD Power Consumption IDD (MCU Active Mode)16, 17 IDD (MCU Powered Down) IDD, Total (ADC0)17 PGA Input Buffers Digital Interface and Modulator IDD (ADC1) External Reference Input Buffers Data Sheet Test Conditions/Comments Min AVDD, IOVDD 1.8 Processor clock rate = 16 MHz; all peripherals on (CLKSYSDIV = 0) Processor clock rate = 8 MHz; all peripherals on (CLKSYSDIV = 1) Processor clock rate = 500 kHz; both ADCs on (input buffers off ) with PGA gain = 4, 1 × SPI port on, all timers on Full temperature range, total halt mode (Mode 4) PGA enabled, gain ≥ 32 Gain = 4, 8, or 16, PGA only Gain = 32, 64, or 128, PGA only 2 × input buffers = 70 μA Input buffers off, gain = 4, 8, or 16 only 60 μA each 1 Typ Max Unit 3.6 V 5.5 mA 3 mA 1 mA 4 μA 320 130 180 70 70 200 120 μA μA μA μA μA μA μA These numbers are not production tested, but are guaranteed by design and/or characterization data at production release. Tested at gain = 4 after initial offset calibration. Measured with an internal short. A system zero-scale calibration removes this error. 4 A recalibration at any temperature removes these errors. 5 The long term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period. 6 These numbers do not include internal reference temperature drift. 7 Factory calibrated at gain = 1. 8 System calibration at a specific gain removes the error at this gain. 9 Input current is measured with one ADC measuring a channel. If both ADCs measure the same input channel, the input current increases (approximately doubles). 10 Measured using the box method. 11 Reference DAC linearity is calculated using a reduced code range of 0x0AB to 0xF30. 12 Measured using a low-pass filter with R = 1 kΩ, C = 100 nF. 13 Endurance is qualified to 10,000 cycles as per JEDEC Standard 22, Method A117, and is measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles. 14 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22, Method A117. Retention lifetime derates with junction temperature. 15 Voltage input levels are relevant only if driving XTAL input from a voltage source. If a crystal is connected directly, the internal crystal interface determines the common-mode voltage. 16 Typical additional supply current consumed during Flash/EE memory program and erase cycles is 7 mA. 17 Total IDD for ADC includes figures for PGA ≥ 32, input buffers, digital interface, and the Σ-Δ modulator. 2 3 Rev. 0| Page 10 of 24 Data Sheet ADuCM362/ADuCM363 RMS NOISE RESOLUTION OF ADC0 AND ADC1 Internal Reference (1.2 V) Table 2 through Table 5 provide rms noise specifications for ADC0 and ADC1 using the internal reference (1.2 V). Table 2 and Table 3 list the rms noise for both ADCs with various gain and output update rate values. Table 4 and Table 5 list the typical output rms noise effective number of bits (ENOB) in normal mode for both ADCs with various gain and output update rate values. (Peak-to-peak ENOB is shown in parentheses.) Table 2. RMS Noise vs. Gain and Output Update Rate, Internal Reference (1.2 V), Gain = 1, 2, 4, 8, and 16 Update Rate (Hz) 3.53 30 50 100 488 976 1953 3906 Chop/Sinc On/sinc3 Off/sinc3 Off/sinc3 Off/sinc3 Off/sinc4 Off/sinc4 Off/sinc4 Off/sinc4 ADCFLT Register Value 0x8E7C 0x007E 0x007D 0x004D 0x100F 0x1007 0x1003 0x1001 Gain = 1, ±VREF, ADCxMDE = 0x01 1.05 2.1 3.7 5.45 10 13.5 19.3 67.0 RMS Noise (μV) Gain = 4, ±250 mV, ADCxMDE = 0x21 0.23 0.63 0.83 1.13 2.2 3.3 4.7 16.6 Gain = 2, ±500 mV, ADCxMDE = 0x11 0.45 1.37 1.6 2.41 4.7 6.5 10 36 Gain = 8, ±125 mV, ADCxMDE = 0x31 0.135 0.37 0.47 0.63 1.3 1.7 2.6 8.8 Gain = 16, ±62.5 mV, ADCxMDE = 0x41 0.072 0.22 0.29 0.38 0.79 1.1 1.55 4.9 Table 3. RMS Noise vs. Gain and Output Update Rate, Internal Reference (1.2 V), Gain = 32, 64, and 128 Update Rate (Hz) 3.53 30 50 100 488 976 1953 3906 Chop/ Sinc On/sinc3 Off/sinc3 Off/sinc3 Off/sinc3 Off/sinc4 Off/sinc4 Off/sinc4 Off/sinc4 ADCFLT Register Value 0x8E7C 0x007E 0x007D 0x004D 0x100F 0x1007 0x1003 0x1001 Gain = 32,1 ±62.5 mV, ADCxMDE = 0x49 0.067 0.202 0.24 0.35 0.7 0.99 1.78 6.44 Gain = 32,1, 2 ±22.18 mV, ADCxMDE = 0x51 0.064 0.2 0.24 0.32 0.67 0.91 1.3 2.68 RMS Noise (μV) Gain = 64,3, 4 Gain = 64,3 ±15.625 mV, ±10.3125 mV, ADCxMDE = ADCxMDE = 0x59 0x61 0.073 0.055 0.196 0.16 0.25 0.21 0.36 0.27 0.71 0.58 1.01 0.74 1.48 1.15 3.59 1.4 1 Gain = 128,5 ±7.8125 mV, ADCxMDE = 0x69 0.058 0.174 0.21 0.31 0.62 0.83 1.25 2.2 Gain = 128,5, 6 ±3.98 mV, ADCxMDE = 0x71 0.052 0.155 0.2 0.25 0.57 0.7 1.0 1.4 ADCxMDE = 0x49 sets the PGA for a gain of 16 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the modulator. ADCxMDE = 0x51 sets the PGA for a gain of 32 with the modulator gain off. ADCxMDE = 0x49 has slightly higher noise but supports a wider input range. 2 If AVDD < 2.0 V and ADCxMDE = 0x51, the input range is ±17.5 mV. 3 ADCxMDE = 0x59 sets the PGA for a gain of 32 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the modulator. ADCxMDE = 0x61 sets the PGA for a gain of 64 with the modulator gain off. ADCxMDE = 0x59 has slightly higher noise but supports a wider input range. 4 If AVDD < 2.0 V and ADCxMDE = 0x61, the input range is ±8.715 mV. 5 ADCxMDE = 0x69 sets the PGA for a gain of 64 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the modulator. ADCxMDE = 0x71 sets the PGA for a gain of 128 with the modulator gain off. ADCxMDE = 0x69 has slightly higher noise but supports a wider input range. 6 If AVDD < 2.0 V and ADCxMDE = 0x71, the input range is ±3.828 mV. Rev. 0 | Page 11 of 24 ADuCM362/ADuCM363 Data Sheet Table 4. Typical Output RMS Noise ENOB in Normal Mode, Internal Reference (1.2 V), Gain = 1, 2, 4, 8, and 16 Update Rate (Hz) 3.53 30 50 100 488 976 1953 3906 1 Chop/Sinc On/sinc3 Off/sinc3 Off/sinc3 Off/sinc3 Off/sinc4 Off/sinc4 Off/sinc4 Off/sinc4 Gain = 1, ±VREF, ADCxMDE = 0x01 21.1 (18.4 p-p) 20.1 (17.4 p-p) 19.3 (16.6 p-p) 18.7 (16.0 p-p) 17.9 (15.2 p-p) 17.4 (14.7 p-p) 16.9 (14.2 p-p) 15.1 (12.4 p-p) ENOB by Input Voltage Range and Gain1 Gain = 2, Gain = 4, Gain = 8, ±500 mV, ±250 mV, ±125 mV, ADCxMDE = 0x11 ADCxMDE = 0x21 ADCxMDE = 0x31 21.1 (18.4 p-p) 21.1 (18.3 p-p) 20.8 (18.1 p-p) 19.5 (16.8 p-p) 19.6 (16.9 p-p) 19.4 (16.6 p-p) 19.25 (16.5 p-p) 19.2 (16.5 p-p) 19.0 (16.3 p-p) 18.66 (15.9 p-p) 18.75 (16.0 p-p) 18.6 (15.9 p-p) 17.7 (15.0 p-p) 17.8 (15.1 p-p) 17.55 (14.8 p-p) 17.2 (14.5 p-p) 17.2 (14.5 p-p) 17.2 (14.4 p-p) 16.6 (13.9 p-p) 16.7 (14.0 p-p) 16.55 (13.8 p-p) 14.8 (12.0 p-p) 14.9 (12.2 p-p) 14.8 (12.1 p-p) Gain = 16, ±62.5 mV, ADCxMDE = 0x41 20.7 (18.0 p-p) 19.1 (16.4 p-p) 18.7 (16.0 p-p) 18.3 (15.6 p-p) 17.3 (14.5 p-p) 16.8 (14.1 p-p) 16.3 (13.6 p-p) 14.6 (11.9 p-p) RMS bits are calculated as follows: log2 ((2 × Input Range)/RMS Noise); peak-to-peak (p-p) bits are calculated as follows: log2 ((2 × Input Range)/(6.6 × RMS Noise)). Table 5. Typical Output RMS Noise ENOB in Normal Mode, Internal Reference (1.2 V), Gain = 32, 64, and 128 Update Rate (Hz) 3.53 30 50 100 488 976 1953 3906 1 Chop/Sinc On/sinc3 Off/sinc3 Off/sinc3 Off/sinc3 Off/sinc4 Off/sinc4 Off/sinc4 Off/sinc4 Gain = 32, ±62.5 mV, ADCxMDE = 0x49 19.8 (17.1 p-p) 18.2 (15.5 p-p) 18.0 (15.2 p-p) 17.4 (14.7 p-p) 16.4 (13.7 p-p) 15.9 (13.2 p-p) 15.1 (12.4 p-p) 13.2 (10.5 p-p) ENOB by Input Voltage Range and Gain1 Gain = 64, Gain = 32, Gain = 64, Gain = 128, ±22.18 mV, ±15.625 mV, ±10.3125 mV, ±7.8125 mV, ADCxMDE = ADCxMDE = ADCxMDE = ADCxMDE = 0x51 0x59 0x61 0x69 19.4 (16.7 p-p) 18.7 (16.0 p-p) 18.5 (15.8 p-p) 18.0 (15.3 p-p) 17.75 (15.0 p-p) 17.3 (14.6 p-p) 17.0 (14.25 p-p) 16.45 (13.7 p-p) 17.5 (14.8 p-p) 16.93 (14.2 p-p) 16.6 (13.86 p-p) 16.2 (13.5 p-p) 17.1 (14.35 p-p) 16.4 (13.7 p-p) 16.2 (13.5 p-p) 15.6 (12.9 p-p) 16.0 (13.3 p-p) 15.4 (12.7 p-p) 15.1 (12.4 p-p) 14.6 (11.9 p-p) 15.6 (12.85 p-p) 14.91 (12.2 p-p) 14.8 (12.0 p-p) 14.2 (11.5 p-p) 15.05 (12.3 p-p) 14.4 (11.6 p-p) 14.1 (11.4 p-p) 13.6 (10.9 p-p) 14.0 (11.3 p-p) 13.1 (10.4 p-p) 13.8 (11.1 p-p) 12.8 (10.1 p-p) Gain = 128, ±3.98 mV, ADCxMDE = 0x71 17.2 (14.5 p-p) 15.6 (12.9 p-p) 15.3 (12.55 p-p) 15.0 (12.2 p-p) 13.8 (11.0 p-p) 13.4 (10.75 p-p) 13.0 (10.2 p-p) 12.5 (9.75 p-p) RMS bits are calculated as follows: log2 ((2 × Input Range)/RMS Noise); peak-to-peak (p-p) bits are calculated as follows: log2 ((2 × Input Range)/(6.6 × RMS Noise)). Rev. 0| Page 12 of 24 Data Sheet ADuCM362/ADuCM363 External Reference (2.5 V) Table 6 through Table 9 provide rms noise specifications for ADC0 and ADC1 using the external reference (2.5 V). Table 6 and Table 7 list the rms noise for both ADCs with various gain and output update rate values. Table 8 and Table 9 list the typical output rms noise effective ENOB in normal mode for both ADCs with various gain and output update rate values. (Peak-to-peak ENOB is shown in parentheses.) Table 6. RMS Noise vs. Gain and Output Update Rate, External Reference (2.5 V), Gain = 1, 2, 4, 8, and 16 Update Rate (Hz) 3.53 30 50 100 488 976 1953 3906 Chop/Sinc On/sinc3 Off/sinc3 Off/sinc3 Off/sinc3 Off/sinc4 Off/sinc4 Off/sinc4 Off/sinc4 ADCFLT Register Value 0x8E7C 0x007E 0x007D 0x004D 0x100F 0x1007 0x1003 0x1001 Gain = 1, ±VREF, ADCxMDE = 0x01 1.1 3 3.9 5.2 9.3 12.5 20.0 140.0 RMS Noise (μV) Gain = 4, ±250 mV, ADCxMDE = 0x21 0.27 0.85 0.92 1.25 2.5 3.5 5.7 35.0 Gain = 2, ±500 mV, ADCxMDE = 0x11 0.5 1.4 2.2 2.8 5.0 7 10 70.0 Gain = 8, ±125 mV, ADCxMDE = 0x31 0.17 0.44 0.46 0.63 1.2 1.75 2.6 17.2 Gain = 16, ±62.5 mV, ADCxMDE = 0x41 0.088 0.27 0.3 0.38 0.75 1.2 1.71 8.9 Table 7. RMS Noise vs. Gain and Output Update Rate, External Reference (2.5 V), Gain = 32, 64, and 128 Update Rate (Hz) 3.53 30 50 100 488 976 1953 3906 Chop/ Sinc On/sinc3 Off/sinc3 Off/sinc3 Off/sinc3 Off/sinc4 Off/sinc4 Off/sinc4 Off/sinc4 ADCFLT Register Value 0x8E7C 0x007E 0x007D 0x004D 0x100F 0x1007 0x1003 0x1001 Gain = 32,1 ±62.5 mV, ADCxMDE = 0x49 0.076 0.21 0.265 0.37 0.73 1.1 2.05 9.4 Gain = 32,1, 2 ±22.18 mV, ADCxMDE = 0x51 0.07 0.22 0.21 0.32 0.7 0.83 1.3 4.8 RMS Noise (μV) Gain = 64,3, 4 Gain = 64,3 ±15.625 mV, ±10.3125 mV, ADCxMDE = ADCxMDE = 0x59 0x61 0.088 0.06 0.21 0.19 0.27 0.2 0.366 0.28 0.73 0.57 1.01 0.77 1.6 1.24 5.1 2.65 1 Gain = 128,5 ±7.8125 mV, ADCxMDE = 0x69 0.068 0.175 0.225 0.32 0.64 0.89 1.3 3.2 Gain = 128,5, 6 ±3.98 mV, ADCxMDE = 0x71 0.58 0.17 0.19 0.26 0.5 0.75 1.1 1.88 ADCxMDE = 0x49 sets the PGA for a gain of 16 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the modulator. ADCxMDE = 0x51 sets the PGA for a gain of 32 with the modulator gain off. ADCxMDE = 0x49 has slightly higher noise but supports a wider input range. 2 If AVDD < 2.0 V and ADCxMDE = 0x51, the input range is ±17.5 mV. 3 ADCxMDE = 0x59 sets the PGA for a gain of 32 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the modulator. ADCxMDE = 0x61 sets the PGA for a gain of 64 with the modulator gain off. ADCxMDE = 0x59 has slightly higher noise but supports a wider input range. 4 If AVDD < 2.0 V and ADCxMDE = 0x61, the input range is ±8.715 mV. 5 ADCxMDE = 0x69 sets the PGA for a gain of 64 with a modulator gain of 2. The modulator gain of 2 is implemented by adjusting the sampling capacitors into the modulator. ADCxMDE = 0x71 sets the PGA for a gain of 128 with the modulator gain off. ADCxMDE = 0x69 has slightly higher noise but supports a wider input range. 6 If AVDD < 2.0 V and ADCxMDE = 0x71, the input range is ±3.828 mV. Rev. 0 | Page 13 of 24 ADuCM362/ADuCM363 Data Sheet Table 8. Typical Output RMS Noise ENOB in Normal Mode, External Reference (2.5 V), Gain = 1, 2, 4, 8, and 16 ENOB by Input Voltage Range and Gain1 Update Rate (Hz) 3.53 30 50 100 488 976 1953 3906 1 Chop/Sinc On/sinc3 Off/sinc3 Off/sinc3 Off/sinc3 Off/sinc4 Off/sinc4 Off/sinc4 Off/sinc4 Gain = 1, ±VREF, ADCxMDE = 0x01 22.1 (19.4 p-p) 20.7 (18.0 p-p) 20.3 (17.6 p-p) 19.9 (17.2 p-p) 19.0 (16.3 p-p) 18.6 (15.9 p-p) 17.9 (15.2 p-p) 15.1 (12.4 p-p) Gain = 2, ±500 mV, ADCxMDE = 0x11 20.9 (18.2 p-p) 19.4 (16.7 p-p) 18.8 (16.1 p-p) 18.4 (15.7 p-p) 17.6 (14.9 p-p) 17.1 (14.4 p-p) 16.6 (13.9 p-p) 13.8 (11.1 p-p) Gain = 4, ±250 mV, ADCxMDE = 0x21 20.8 (18.1 p-p) 19.2 (16.4 p-p) 19.05 (16.3 p-p) 18.6 (15.9 p-p) 17.6 (14.9 p-p) 17.1 (14.4 p-p) 16.4 (13.7 p-p) 13.8 (11.1 p-p) Gain = 8, ±125 mV, ADCxMDE = 0x31 20.5 (17.7 p-p) 19.1 (16.4 p-p) 19.05 (16.3 p-p) 18.6 (15.9 p-p) 17.7 (14.9 p-p) 17.1 (14.4 p-p) 16.55 (13.8 p-p) 13.8 (11.1 p-p) Gain = 16, ±62.5 mV, ADCxMDE = 0x41 20.43 (17.7 p-p) 18.82 (16.1 p-p) 18.66 (15.9 p-p) 18.32 (15.6 p-p) 17.34 (14.6 p-p) 16.66 (13.9 p-p) 16.15 (13.4 p-p) 13.77 (11.05 p-p) RMS bits are calculated as follows: log2 ((2 × Input Range)/RMS Noise); peak-to-peak (p-p) bits are calculated as follows: log2 ((2 × Input Range)/(6.6 × RMS Noise)). Table 9. Typical Output RMS Noise ENOB in Normal Mode, External Reference (2.5 V), Gain = 32, 64, and 128 Update Rate (Hz) 3.53 30 50 100 488 976 1953 3906 1 Chop/Sinc On/sinc3 Off/sinc3 Off/sinc3 Off/sinc3 Off/sinc4 Off/sinc4 Off/sinc4 Off/sinc4 Gain = 32, ±62.5 mV, ADCxMDE = 0x49 19.6 (16.9 p-p) 18.2 (15.5 p-p) 17.8 (15.1 p-p) 17.4 (14.6 p-p) 16.4 (13.7 p-p) 15.8 (13.1 p-p) 14.9 (12.1 p-p) 12.7 (10.0 p-p) ENOB by Input Voltage Range and Gain1 Gain = 64, Gain = 32, Gain = 64, Gain = 128, ±22.18 mV, ±15.625 mV, ±10.3125 mV, ±7.8125 mV, ADCxMDE = ADCxMDE = ADCxMDE = ADCxMDE = 0x51 0x59 0x61 0x69 19.3 (16.55 p-p) 18.4 (15.7 p-p) 18.4 (15.7 p-p) 17.8 (15.1 p-p) 17.6 (14.9 p-p) 17.2 (14.5 p-p) 16.7 (14.0 p-p) 16.4 (13.7 p-p) 17.7 (15.0 p-p) 16.8 (14.1 p-p) 16.65 (13.9 p-p) 16.1 (13.4 p-p) 17.1 (14.35 p-p) 16.4 (13.7 p-p) 16.2 (13.4 p-p) 15.6 (12.85 p-p) 16.0 (13.2 p-p) 15.4 (12.7 p-p) 15.1 (12.4 p-p) 14.6 (11.85 p-p) 15.7 (13.0 p-p) 14.9 (12.2 p-p) 14.7 (12.0 p-p) 14.1 (11.4 p-p) 15.1 (12.3 p-p) 14.25 (11.5 p-p) 14.0 (11.3 p-p) 13.55 (10.8 p-p) 13.2 (10.4 p-p) 12.6 (9.9 p-p) 12.9 (10.2 p-p) 12.25 (9.5 p-p) Gain = 128, ±3.98 mV, ADCxMDE = 0x71 17.1 (14.3 p-p) 15.5 (12.8 p-p) 15.35 (12.6 p-p) 14.9 (12.2 p-p) 14.0 (11.2 p-p) 13.4 (10.6 p-p) 12.8 (10.1 p-p) 12.0 (9.3 p-p) RMS bits are calculated as follows: log2 ((2 × Input Range)/RMS Noise); peak-to-peak (p-p) bits are calculated as follows: log2 ((2 × Input Range)/(6.6 × RMS Noise)). Rev. 0| Page 14 of 24 Data Sheet ADuCM362/ADuCM363 I2C TIMING SPECIFICATIONS The capacitive load for each I2C bus line (CB) is 400 pF maximum as per the I2C bus specifications. I2C timing is guaranteed by design, but is not production tested. Table 10. I2C Timing in Fast Mode (400 kHz) Parameter tL tH tSHD tDSU tDHD tRSU tPSU tBUF tR tF tSUP Description Serial clock (SCL) low pulse width SCL high pulse width Start condition hold time Data setup time Data hold time Setup time for repeated start Stop condition setup time Bus free time between a stop condition and a start condition Rise time for both SCL and serial data (SDA) Fall time for both SCL and SDA Pulse width of suppressed spike Min 1300 600 600 100 0 600 600 1.3 20 + 0.1 CB 20 + 0.1 CB 0 Max Min 4.7 4.0 4.7 250 0 4.0 4.0 4.7 Max Unit ns ns ns ns ns ns ns s ns ns ns 300 300 50 Table 11. I2C Timing in Standard Mode (100 kHz) Parameter tL tH tSHD tDSU tDHD tRSU tPSU tBUF tR tF Description SCL low pulse width SCL high pulse width Start condition hold time Data setup time Data hold time Setup time for repeated start Stop condition setup time Bus free time between a stop condition and a start condition Rise time for both SCL and SDA Fall time for both SCL and SDA tBUF Unit μs ns μs ns μs μs μs μs μs ns 1 300 tSUP tR MSB tDSU LSB tSHD P S tF tDHD tR tRSU tH 1 SCL (I) MSB tDSU tDHD tPSU ACK 8 tL 9 tSUP STOP START CONDITION CONDITION 1 S(R) REPEATED START Figure 3. I2C-Compatible Interface Timing Rev. 0 | Page 15 of 24 tF 14919-002 SDA (I/O) ADuCM362/ADuCM363 Data Sheet SPI TIMING SPECIFICATIONS Table 12. SPI Master Mode Timing Parameter tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF Min Typ (SPIDIV + 1) × tUCLK (SPIDIV + 1) × tUCLK 0 Max 12 12 12 12 35.5 35.5 35.5 35.5 35.5 (SPIDIV + 1) × tUCLK 58.7 16 Unit ns ns ns ns ns ns ns ns ns ns tUCLK = 62.5 ns. It corresponds to the internal 16 MHz clock before the clock divider. CS 1/2 SCLK CYCLE 3/4 SCLK CYCLE tCS tSFS SCLK (POLARITY = 0) tSH tSL tSR SCLK (POLARITY = 1) tDAV tDF MOSI MSB MISO tSF tDR BIT 6 TO BIT 1 MSB IN LSB BIT 6 TO BIT 1 LSB IN 14919-003 tDSU tDHD Figure 4. SPI Master Mode Timing (Phase Mode = 1) CS 1 SCLK CYCLE 1 SCLK CYCLE tCS tSFS SCLK (POLARITY = 0) tSH tSL tSR SCLK (POLARITY = 1) tDAV tDOSU MOSI MISO tSF tDF MSB MSB IN tDR BIT 6 TO BIT 1 BIT 6 TO BIT 1 LSB LSB IN 14919-004 1 Description SCLK low pulse width1 SCLK high pulse width1 Data output valid after SCLK edge Data output setup time before SCLK edge1 Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time Data output rise time SCLK rise time SCLK fall time tDSU tDHD Figure 5. SPI Master Mode Timing (Phase Mode = 0) Rev. 0| Page 16 of 24 Data Sheet ADuCM362/ADuCM363 Table 13. SPI Slave Mode Timing Parameter tCS Description CS to SCLK edge tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS SCLK low pulse width1 SCLK high pulse width1 Data output valid after SCLK edge Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time Data output rise time SCLK rise time SCLK fall time CS high after SCLK edge Typ Max (SPIDIV + 1) × tUCLK (SPIDIV + 1) × tUCLK 62.5 49.1 20.2 10.1 12 12 12 12 35.5 35.5 35.5 35.5 0 Unit ns ns ns ns ns ns ns ns ns ns ns tUCLK = 62.5 ns. It corresponds to the internal 16 MHz clock before the clock divider. CS tSFS tCS SCLK (POLARITY = 0) tSH tSL tSR tSF SCLK (POLARITY = 1) tDAV tDF MISO tDR MSB MOSI BIT 6 TO BIT 1 MSB IN LSB BIT 6 TO BIT 1 LSB IN 14919-005 tDSU tDHD Figure 6. SPI Slave Mode Timing (Phase Mode = 1) CS tCS tSFS SCLK (POLARITY = 0) tSH tSL tSR tSF SCLK (POLARITY = 1) tDAV tDOCS tDF MISO MOSI MSB MSB IN tDSU tDR BIT 6 TO BIT 1 BIT 6 TO BIT 1 LSB LSB IN 14919-006 1 Min 62.5 tDHD Figure 7. SPI Slave Mode Timing (Phase Mode = 0) Rev. 0 | Page 17 of 24 ADuCM362/ADuCM363 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 14. Parameter AVDD to AGND IOVDD to DGND Digital Input Voltage to DGND Digital Output Voltage to DGND Analog Inputs to AGND Operating Temperature Range Storage Temperature Range Junction Temperature ESD Rating, All Pins Human Body Model (HBM) Field-Induced Charged Device Model (FICDM) Peak Solder Reflow Temperature SnPb Assemblies (10 sec to 30 sec) Pb-Free Assemblies (20 sec to 40 sec) Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required. Rating −0.3 V to +3.96 V −0.3 V to +3.96 V −0.3 V to +3.96 V −0.3 V to +3.96 V −0.3 V to +3.96 V −40°C to +125°C −65°C to +150°C 150°C Table 15. Thermal Resistance Package Type CP-48-4 ESD CAUTION ±2 kV ±850 V 240°C 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Rev. 0| Page 18 of 24 θJA 27 Unit °C/W Data Sheet ADuCM362/ADuCM363 48 47 46 45 44 43 42 41 40 39 38 37 SWDIO SWCLK P2.0/SCL/UARTCLK P1.7/IRQ7/PWM5/CS0 P1.6/IRQ6/PWM4/MOSI0 P1.5/IRQ5/PWM3/SCLK0 P1.4/PWM2/MISO0/SDA P1.3/PWM1/DSR P1.2/PWM0/RI P1.1/IRQ4/PWMTRIP/DTR P1.0/IRQ3/PWMSYNC/EXTCLK IOVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADuCM362/ ADuCM363 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 P0.7/POR/TxD1 P0.6/IRQ2/RxD1 P0.5/IRQ1/CTS P0.4/RTS/ECLKO/RTS1 P0.3/IRQ0/CS1/RTS1/RTS P0.2/MOSI1/SDA/TxD P0.1/SCLK1/SCL/RxD P0.0/MISO1/UART1DCD/UARTDCD AIN11/VBIAS1 AIN10 AIN9/DACBUFF+ AIN8/EXTREF2IN– NOTES 1. EXPOSED PAD. THE LFCSP HAS AN EXPOSED PAD THAT MUST BE SOLDERED TO A METAL PLATE ON THE PCB AND TO DGND FOR MECHANICAL REASONS. 14919-007 GND_SW VREF+ VREF– AGND AVDD AVDD_REG DAC INT_REF IREF AIN5/IEXC AIN6/IEXC AIN7/VBIAS0/IEXC/EXTREF2IN+ 13 14 15 16 17 18 19 20 21 22 23 24 RESET 1 P2.1/SDA/UART1DCD/UARTDCD 2 P2.2/BM 3 XTALO 4 XTALI 5 IOVDD 6 DVDD_REG 7 AIN0 8 AIN1 9 AIN2 10 AIN3 11 AIN4/IEXC 12 Figure 8. Pin Configuration Table 16. Pin Function Descriptions Pin No. 1 2 Mnemonic RESET P2.1/SDA/UART1DCD/UARTDCD 3 P2.2/BM 4 5 6 7 XTALO XTALI IOVDD DVDD_REG 8 AIN0 9 AIN1 10 AIN2 11 AIN3 12 AIN4/IEXC Description Reset Pin, Active Low Input. An internal pull-up is provided. General-Purpose Input/Output P2.1/I2C Serial Data Pin/UART1 Data Carrier Detect Pin/UART Data Carrier Detect Pin. General-Purpose Input/Output P2.2/Boot Mode Input Select Pin. When this pin is held low during and for a short time after any reset sequence, the devices enter UART download mode. External Crystal Oscillator Output Pin. Optional 32.768 kHz source for real-time clock. External Crystal Oscillator Input Pin. Optional 32.768 kHz source for real-time clock. Digital System Supply Pin. This pin must be connected to DGND via a 0.1 μF capacitor. Digital Regulator Supply. This pin must be connected to DGND via a 470 nF capacitor and to Pin 18, AVDD_REG. ADC Analog Input 0. This pin can be configured as a positive or negative input to either ADC in differential or single-ended mode. ADC Analog Input 1. This pin can be configured as a positive or negative input to either ADC in differential or single-ended mode. ADC Analog Input 2. This pin can be configured as a positive or negative input to either ADC in differential or single-ended mode. ADC Analog Input 3. This pin can be configured as a positive or negative input to either ADC in differential or single-ended mode. ADC Analog Input 4/Excitation Current Source. This pin can be configured as a positive or negative input to either ADC in differential or single-ended mode (AIN4). This pin can also be configured as the output pin for Excitation Current Source 0 or Excitation Current Source 1 (IEXC). Rev. 0 | Page 19 of 24 ADuCM362/ADuCM363 Pin No. 13 14 Mnemonic GND_SW VREF+ 15 VREF− 16 17 18 AGND AVDD AVDD_REG 19 20 21 DAC INT_REF IREF 22 AIN5/IEXC 23 AIN6/IEXC 24 AIN7/VBIAS0/IEXC/EXTREF2IN+ 25 AIN8/EXTREF2IN− 26 AIN9/DACBUFF+ 27 AIN10 28 AIN11/VBIAS1 29 30 P0.0/MISO1/UART1DCD/ UARTDCD P0.1/SCLK1/SCL/RxD 31 P0.2/MOSI1/SDA/TxD 32 P0.3/IRQ0/CS1/RTS1/RTS 33 P0.4/RTS/ECLKO/RTS1 34 35 36 37 38 P0.5/IRQ1/CTS P0.6/IRQ2/RxD1 P0.7/POR/TxD1 IOVDD P1.0/IRQ3/PWMSYNC/EXTCLK 39 P1.1/IRQ4/PWMTRIP/DTR 40 P1.2/PWM0/RI Data Sheet Description Sensor Power Switch to Analog Ground Reference. External Reference Positive Input. An external reference can be applied between the VREF+ and VREF− pins. External Reference Negative Input. An external reference can be applied between the VREF+ and VREF− pins. Analog System Ground Reference Pin. Analog System Supply Pin. This pin must be connected to AGND via a 0.1 μF capacitor. Internal Analog Regulator Supply Output. This pin must be connected to AGND via a 470 nF capacitor and to Pin 7, DVDD_REG. DAC Voltage Output. Internal Reference. This pin must be connected to ground via a 470 nF decoupling capacitor. Optional Reference Current Resistor Connection for the Excitation Current Sources. The reference current used for the excitation current sources is set by a low drift (5 ppm/°C) external resistor connected to this pin. ADC Analog Input 5/Excitation Current Source. This pin can be configured as a positive or negative input to either ADC in differential or single-ended mode (AIN5). This pin can also be configured as the output pin for Excitation Current Source 0 or Excitation Current Source 1 (IEXC). ADC Analog Input 6/Excitation Current Source. This pin can be configured as a positive or negative input to either ADC in differential or single-ended mode (AIN6). This pin can also be configured as the output pin for Excitation Current Source 0 or Excitation Current Source 1 (IEXC). ADC Analog Input 7/Bias Voltage Output/Excitation Current Source/External Reference 2 Positive Input. This pin can be configured as a positive or negative input to either ADC in differential or single-ended mode (AIN7). This pin can also be configured as an analog output pin to generate a bias voltage, VBIAS0 of AVDD_REG/2 (VBIAS0); as the output pin for Excitation Current Source 0 or Excitation Current Source 1 (IEXC); or as the positive input for External Reference 2 (EXTREF2IN+). ADC Analog Input 8/External Reference 2 Negative Input. This pin can be configured as a positive or negative input to either ADC in differential or single-ended mode (AIN8). This pin can also be configured as the negative input for External Reference 2 (EXTREF2IN−). ADC Analog Input 9/Noninverting Input to the DAC Output Buffer. This pin can be configured as a positive or negative input to either ADC in differential or single-ended mode (AIN9). This pin can also be configured as the noninverting input to the DAC output buffer when the DAC is configured for NPN mode (DACBUFF+). ADC Analog Input 10. This pin can be configured as a positive or negative input to either ADC in differential or single-ended mode. ADC Analog Input 11/Bias Voltage Output. This pin can be configured as a positive or negative input to either ADC in differential or single-ended mode (AIN11). This pin can also be configured as an analog output pin to generate a bias voltage, VBIAS1 of AVDD_REG/2 (VBIAS1). General-Purpose Input/Output P0.0/SPI1 Master Input, Slave Output Pin/UART1 Data Carrier Detect Pin/ UART Data Carrier Detect Pin. General-Purpose Input/Output P0.1/SPI1 Serial Clock Pin/I2C Serial Clock Pin/UART Serial Input (Data Input for the UART Downloader). General-Purpose Input/Output P0.2/SPI1 Master Output, Slave Input Pin/I2C Serial Data Pin/ UART Serial Output (Data Output for the UART Downloader). General-Purpose Input/Output P0.3/External Interrupt Request 0/SPI1 Chip Select Pin (Active Low) (when using SPI1, configure this pin as CS1)/UART1 Request to Send Signal/UART Request to Send Signal. General-Purpose Input/Output P0.4/UART Request to Send Signal/External Clock Output Pin for Test Purposes/UART1 Request to Send Signal. General-Purpose Input/Output P0.5/External Interrupt Request 1/UART Clear to Send Signal. General-Purpose Input/Output P0.6/External Interrupt Request 2/UART1 Serial Input. General-Purpose Input/Output P0.7/Power-On Reset Pin (Active High)/UART1 Serial Output. Digital System Supply Pin. This pin must be connected to DGND via a 0.1 μF capacitor. General-Purpose Input/Output P1.0/External Interrupt Request 3/PWM External Synchronization Input/External Clock Input Pin. General-Purpose Input/Output P1.1/External Interrupt Request 4/PWM External Trip Input/ UART Data Terminal Ready Pin. General-Purpose Input/Output P1.2/PWM0 Output/UART Ring Indicator Pin. Rev. 0| Page 20 of 24 Data Sheet Pin No. 41 42 Mnemonic P1.3/PWM1/DSR P1.4/PWM2/MISO0/SDA 43 P1.5/IRQ5/PWM3/SCLK0 44 P1.6/IRQ6/PWM4/MOSI0 45 P1.7/IRQ7/PWM5/CS0 46 47 48 P2.0/SCL/UARTCLK SWCLK SWDIO EP ADuCM362/ADuCM363 Description General-Purpose Input/Output P1.3/PWM1 Output/UART Data Set Ready Pin. General-Purpose Input/Output P1.4/PWM2 Output/SPI0 Master Input, Slave Output Pin/I2C Serial Data Pin. General-Purpose Input/Output P1.5/External Interrupt Request 5/PWM3 Output/SPI0 Serial Clock Pin. General-Purpose Input/Output P1.6/External Interrupt Request 6/PWM4 Output/SPI0 Master Output, Slave Input Pin. General-Purpose Input/Output P1.7/External Interrupt Request 7/PWM5 Output/SPI0 Chip Select Pin (Active Low) (when using SPI0, configure this pin as CS0). General-Purpose Input/Output P2.0/I2C Serial Clock Pin/Input Clock Pin for UART Block Only. Serial Wire Debug Clock Input Pin. Serial Wire Debug Data Input/Output Pin. Exposed Pad. The LFCSP has an exposed pad that must be soldered to a metal plate on the PCB and to DGND for mechanical reasons. Rev. 0 | Page 21 of 24 ADuCM362/ADuCM363 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 250 60 50 200 SETTLING TIME (ms) 30 IP IN IP – IN 20 10 0 –10 150 BOOST = 0 100 50 –20 BOOST = 30 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 COMMON-MODE VOLTAGE (V) 0 14919-008 –30 0 200 400 600 800 1000 14919-011 INPUT CURRENT (nA) 40 1200 CAPACITANCE (nF) Figure 9. Input Current vs. Common-Mode Voltage (VCM), Gain = 4, ADC Input = 250 mV, AVDD = 3.6 V, TA = 25°C, VCM = ((AIN+) + (AIN−))/2 Figure 12. VBIASx Output Settling Time vs. Load Capacitance, TA = 25°C, IOVDD and AVDD = 3.3 V 30 5 4 25 PULL-UP RESISTANCE (kΩ) 2 1 0 –1 –2 IP IN IP – IN –4 0.5 1.0 1.5 2.0 2.5 3.0 3.5 COMMON-MODE VOLTAGE (V) 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOLTAGE (V) Figure 10. Input Current vs. Common-Mode Voltage (VCM), Gain = 128, ADC Input = 7.8125 mV, AVDD = 3.6 V, TA = 25°C, VCM = ((AIN+) + (AIN−))/2 Figure 13. Digital Input Pin Pull-Up Resistance Value vs. Voltage Applied to Digital Pin, TA = 25°C, IOVDD = 3.4 V 60 12000000 50 PULL-UP RESISTANCE (kΩ) 14000000 10000000 8000000 6000000 4000000 40 30 20 –40 –20 0 40 20 60 TEMPERATURE (°C) 80 100 120 Figure 11. ADC Codes (Decimal Values) vs. Die Temperature 0 0 0.5 1.0 VOLTAGE (V) 1.5 2.0 14919-013 10 2000000 14919-010 ADC CODES 15 5 –5 0 20 14919-012 –3 14919-009 INPUT CURRENT (nA) 3 Figure 14. Digital Input Pin Pull-Up Resistance Value vs. Voltage Applied to Digital Pin, TA = 25°C, IOVDD = 1.8 V Rev. 0| Page 22 of 24 Data Sheet ADuCM362/ADuCM363 TYPICAL SYSTEM CONFIGURATION ground. Place the 0.47 μF capacitor on the AVDD_REG and DVDD_REG pins as close to the pins as possible. In noisy environments, an additional 1 nF capacitor can be added to IOVDD and AVDD. 46 45 44 43 SWCLK P2.0/SCL/ UARTCLK P1.7/IRQ7/ PWM5/CS0 P1.6/IRQ6/ PWM4/MOSI0 P1.5/IRQ5/ PWM3/SCLK0 RESET XTALO 5 XTALI P0.7/POR/TxD1 36 6 IOVDD P0.6/IRQ2/RxD1 35 7 DVDD_REG 8 AIN0 9 AIN1 10 AIN2 P0.2/MOSI1/SDA/TxD 31 11 AIN3 P0.1/SCLK1/SCL/RxD 30 IOVDD 37 DGND P0.4/RTS/ECLKO/RTS1 33 ADuCM362/ ADuCM363 P0.3/IRQ0/CS1/RTS1/RTS 32 12 AIN4/IEXC 13 GND_SW 14 VREF+ AIN10 27 15 VREF– AIN9/DACBUFF+ 26 16 AGND AIN8/EXTREF2IN– 25 P0.0/MISO1/UART1DCD/UARTDCD 29 AIN7/VBIAS0/ IEXC/ EXTREF2IN+ AIN11/VBIAS1 28 17 AVDD 0.1µF P0.5/CTS/IRQ1 34 AVDD DGND 4 DVDD P1.0/IRQ3/PWMSYNC/EXTCLK 38 AIN6/IEXC 0.47µF P2.2/BM AIN5/IEXC DGND 3 P1.2/PWM0/RI 40 P1.1/IRQ4/PWMTRIP/DTR 39 IREF 0.1µF P2.1/SDA/UART1DCD/UARTDCD INT_REF 12pF RESET 2 DAC DVDD 18 19 20 21 22 23 24 0.1µF 0.47µF 150kΩ ADP1720ARMZ-3.3 DVDD INTERFACE BOARD CONNECTOR 0.47µF RESET RESET GND DGND SWIO SWDIO TX SWCLK SWCLK RX 5V USB 1µF DGND IN AVDD 1.6Ω OUT 560Ω EN 4.7µF 0.1µF 4.7µF 0.1µF GND AGND DGND DGND Figure 15. Typical System Configuration Rev. 0 | Page 23 of 24 AGND AGND 14919-115 DGND 1 AVDD_REG 12pF 41 42 P1.3/PWM1/ DSR SWCLK 47 P1.4/PWM2/ MISO0 SWDIO 48 SWDIO Figure 15 shows a typical ADuCM362/ADuCM363 configuration. This figure illustrates some of the hardware considerations. The bottom of the LFCSP package has an exposed pad that must be soldered to a metal plate on the PCB for mechanical reasons and to DGND. The metal plate of the PCB can be connected to ADuCM362/ADuCM363 Data Sheet OUTLINE DIMENSIONS 0.30 0.23 0.18 PIN 1 INDICATOR 48 37 36 1 0.50 BSC TOP VIEW 0.80 0.75 0.70 0.45 0.40 0.35 5.20 5.10 SQ 5.00 EXPOSED PAD 12 25 24 13 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WKKD. 112408-B 7.00 BSC SQ Figure 16. 48-Lead Lead Frame Chip Scale Package [LFCSP] 7 mm × 7 mm Body and 0.75 mm Package Height (CP-48-4) Dimensions shown in millimeters ORDERING GUIDE Model1 ADuCM362BCPZ256 ADuCM362BCPZ256RL7 ADuCM362BCPZ128 ADuCM362BCPZ128RL7 ADuCM363BCPZ256 ADuCM363BCPZ256RL7 ADuCM363BCPZ128 ADuCM363BCPZ128RL7 EVAL-ADuCM362QSPZ ADCs Dual 24-Bit Dual 24-Bit Dual 24-Bit Dual 24-Bit Single 24-Bit Single 24-Bit Single 24-Bit Single 24-Bit Flash/SRAM 256 kB/24 kB 256 kB/24 kB 128 kB/16 kB 128 kB/16 kB 256 kB/24 kB 256 kB/24 kB 128 kB/16 kB 128 kB/16 kB Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C EVAL-ADuCM363QSPZ 1 Package Description 48-Lead LFCSP 48-Lead LFCSP 48-Lead LFCSP 48-Lead LFCSP 48-Lead LFCSP 48-Lead LFCSP 48-Lead LFCSP 48-Lead LFCSP ADuCM362 QuickStart Plus Development System ADuCM363 QuickStart Plus Development System Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D14919-0-10/16(0) Rev. 0| Page 24 of 24 Package Option CP-48-4 CP-48-4 CP-48-4 CP-48-4 CP-48-4 CP-48-4 CP-48-4 CP-48-4 Ordering Quantity 750 750 750 750