ICST ICS85214AGIL Low skew, 1-to-5 differential-to-hstl fanout buffer Datasheet

ICS85214I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS85214I is a low skew, high performance
ICS
1-to-5 Differential-to-HSTL Fanout Buffer and a
HiPerClockS™
member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
CLK0, nCLK0 pair can accept most standard differential input levels. The single ended CLK1 input accepts
LVCMOS or LVTTL input levels. Guaranteed output and partto-par t skew characteristics make the ICS85214I ideal
for those clock distribution applications demanding well
defined performance and repeatability.
• 5 differential HSTL compatible outputs
• Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL
clock inputs
• CLK0, nCLK0 pair can accept the following differential
input levels: LVDS, LVPECL, HSTL, SSTL, HCSL
• CLK1 can accept the following input levels:
LVCMOS or LVTTL
• Output frequency up to 700MHz
• Translates any single ended input signal to HSTL levels
with resistor bias on nCLK0 input
• Output skew: 40ps (maximum)
• Part-to-part skew: 300ps (maximum)
• Propagation delay: 1.8ns (maximum)
• 3.3V core, 1.8V output operating supply
• Lead-Free package fully RoHS compliant
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
D
nCLK_EN
Q
LE
CLK0
nCLK0
CLK1
00
1
Q0
nQ0
1
Q1
nQ1
CLK_SEL
Q2
nQ2
20
19
18
17
16
15
14
13
12
11
VDDO
nCLK_EN
VDD
nc
CLK1
CLK0
nCLK0
nc
CLK_SEL
GND
ICS85214I
Q3
nQ3
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
G Package
Top View
Q4
nQ4
85214AGI
1
2
3
4
5
6
7
8
9
10
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1
REV. A JUNE 1, 2005
ICS85214I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1, 2
Q0, nQ0
Type
Description
Output
Differential output pair. HSTL interface levels.
3, 4
Q1, nQ1
Output
Differential output pair. HSTL interface levels.
5, 6
Q2, nQ2
Output
Differential output pair. HSTL interface levels.
7, 8
Q3, nQ3
Output
Differential output pair. HSTL interface levels.
9, 10
Q4, nQ4
Output
11
GND
Power
12
CLK_SEL
Input
13, 17
nc
Unused
14
nCLK0
Input
Differential output pair. HSTL interface levels.
Power supply ground.
Clock select input. When HIGH, selects CLK1 input.
Pulldown
When LOW, selects CLK0, nCLK0 input. LVTTL / LVCMOS interface levels.
No connect.
Pullup
Inver ting differential clock input.
15
CLK0
Input
Pulldown Non-inver ting differential clock input.
16
CLK1
Input
Pulldown Clock input. LVTTL / LVCMOS interface levels.
18
VDD
Power
19
nCLK_EN
Input
20
VDDO
Power
Core supply pin.
Synchronizing clock enable. When LOW, clock outputs follow clock input.
Pulldown When HIGH, Q outputs are forced low, nQ outputs are forced high.
LVTTL / LVCMOS interface levels.
Output supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
85214AGI
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ICS85214I
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Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
nCLK_EN
Q0:Q4
nQ0:nQ4
0
Enabled
Enabled
1
Disabled; LOW
Disabled; HIGH
After nCLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0, nCLK0 inputs as described in Table 3B.
Enabled
Disabled
nCLK0
CLK0
nCLK_EN
nQ0:nQ4
Q0:Q4
FIGURE 1. nCLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
HIGH
Differential to Differential
Non Inver ting
HIGH
LOW
Differential to Differential
Non Inver ting
CLK_SEL
CLK0
nCLK0
CLK1
Q0:Q4
nQ0:nQ4
0
0
1
X
LOW
0
1
0
X
0
0
Biased; NOTE 1
X
LOW
HIGH
Single Ended to Differential
Non Inver ting
0
1
Biased; NOTE 1
X
HIGH
LOW
Single Ended to Differential
Non Inver ting
0
Biased; NOTE 1
0
X
HIGH
LOW
Single Ended to Differential
Inver ting
0
Biased; NOTE 1
1
X
LOW
HIGH
Single Ended to Differential
Inver ting
1
X
X
0
LOW
HIGH
Single Ended to Differential
Non Inver ting
1
X
X
1
HIGH
LOW
Single Ended to Differential
Non Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
85214AGI
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ICS85214I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
73.2°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 85°C
Symbol
Parameter
VDD
Input Power Supply Voltage
Test Conditions
VDDO
Output Power Supply Voltage
IDD
Power Supply Current
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
1.6
1.8
2.0
V
80
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 85°C
Symbol
VIH
Parameter
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
IIL
Input Low Current
Test Conditions
nCLK_EN, CLK_SEL
CLK1
Minimum
Maximum
Units
2
Typical
VDD + 0.3
V
2
VDD + 0.3
V
nCLK_EN, CLK_SEL
-0.3
0.8
V
CLK1
CLK1, CLK_SEL,
nCLK_EN
CLK1, CLK_SEL,
nCLK_EN
-0.3
1.3
V
150
µA
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
-5
µA
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 85°C
Symbol
Parameter
IIH
Input High Current
IIL
Input Low Current
Test Conditions
Minimum
Typical
Units
nCLK0
VDD = VIN = 3.465V
5
µA
CLK0
VDD = VIN = 3.465V
150
µA
nCLK0
VDD = 3.465V, VIN = 0V
-150
CLK0
VDD = 3.465V, VIN = 0V
-5
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
VCMR
0.5
NOTE 1, 2
NOTE 1: For single ended applications the maximum input voltage for CLK0, nCLK0 is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
VPP
85214AGI
Maximum
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4
µA
µA
1.3
V
VDD - 0.85
V
REV. A JUNE 1, 2005
ICS85214I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 4D. HSTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 85°C
Symbol Parameter
Output High Voltage;
VOH
NOTE 1
Output Low Voltage;
VOL
NOTE 1
VOX
Test Conditions
Output Crossover Voltage
Minimum
Maximum
Units
1
1.4
V
0
0.4
V
38% x (VOH - VOL) + VOL
60% x (VOH - VOL) + VOL
V
0.6
1.1
V
Peak-to-Peak
Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to ground.
VSWING
Typical
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 85°C
Symbol
Parameter
Test Conditions
fMAX
Output Frequency
tPD
Propagation Delay; NOTE 1
Minimum
Typical
Maximum
Units
CLK0, nCLK0
700
MHz
CLK1
300
MHZ
1.8
ns
IJ 700MHz
1.0
t sk(o)
Output Skew; NOTE 2, 4
40
ps
t sk(pp)
Par t-to-Par t Skew; NOTE 3, 4
300
ps
tR / tF
Output Rise/Fall Time
200
800
ps
46
54
%
56
%
odc
Output Duty Cycle
20% to 80%
CLK0, nCLK0
CLK1
IJ 266MHz
44
All parameters measured at fMAX unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The par t does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A JUNE 1, 2005
ICS85214I
Integrated
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Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
3.3V±5%
1.8V±0.2V
V DD
VDD
Qx
SCOPE
nCLK0
VDDO
V
V
Cross Points
PP
HSTL
CMR
CLK0
GND
nQx
GND
0V
3.3V/1.8V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
PART 1
Qx
nQx
Qx
nQy
nQy
Qy
PART 2
Qy
tsk(pp)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
80%
80%
CLK1
VSW I N G
Clock
Outputs
nQ0:nQ4
20%
20%
tF
tR
Q0:Q4
tPD
OUTPUT RISE/FALL TIME
nCLK0
nQ0:nQ4
CLK0
Q0:Q4
t PW
t
nQ0:nQ4
Q0:Q4
odc =
tPD
t PW
x 100%
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
PROPAGATION DELAY
85214AGI
PERIOD
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REV. A JUNE 1, 2005
ICS85214I
Integrated
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Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
CLK_IN
+
V_REF
C1
0.1uF
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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REV. A JUNE 1, 2005
ICS85214I
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Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 3A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
R1
50
HiPerClockS
Input
R2
50
R2
50
R3
50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
3.3V LVPECL DRIVER
BY
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
BY
R4
125
Zo = 50 Ohm
LVDS_Driv er
Zo = 50 Ohm
CLK
CLK
R1
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
HiPerClockS
Input
nCLK
Receiv er
Zo = 50 Ohm
R2
84
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
3.3V LVDS DRIVER
BY
BY
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
Zo = 50 Ohm
C2
R3
125
R4
125
CLK
nCLK
R5
100 - 200
R6
100 - 200
R1
84
HiPerClockS
Input
R2
84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN
3.3V LVPECL DRIVER WITH AC COUPLE
85214AGI
BY
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REV. A JUNE 1, 2005
ICS85214I
Integrated
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Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
SCHEMATIC EXAMPLE
Figure 4 shows a schematic example of the ICS85214I. In
this example, the input is driven by an ICS HiPerClockS HSTL
driver. The decoupling capacitors should be physically located
near the power pin. For ICS85214I, the unused outputs can
be left floating.
Zo = 50
+
Zo = 50
R2
50
U1
1.8V
R12
1K
Zo = 50 Ohm
3.3V
Zo = 50 Ohm
C2
LVHSTL Driver
R9
50
R10
50
11
12
13
14
15
16
17
18
19
1.8V 20
-
GND
CLK_SEL
nc
nCLK
CLK
SCLK
nc
VDD
nCLK_EN
VDDO
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
nQ0
Q0
10
9
8
7
6
5
4
3
2
1
R1
50
Zo = 50
+
Zo = 50
R4
50
R3
50
0.1u
C1
0.1u
ICS85214I
ICS85214
Zo = 50
+
R11
1K
Zo = 50
R8
50
R7
50
FIGURE 4. ICS85214I HSTL BUFFER SCHEMATIC EXAMPLE
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ICS85214I
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LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85214I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85214I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 80mA = 227.2mW
Power (outputs)MAX = 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 32.8mW = 164mW
Total Power_MAX (3.465V, with all outputs switching) = 227.2mW + 164mW = 391.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.391W * 66.6°C/W = 111°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
200
500
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in Figure 5.
VDDO
Q1
VOUT
RL
50Ω
FIGURE 5. HSTL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
/R ) * (V
OH_MIN
Pd_L = (V
OL_MAX
L
-V
DDO_MAX
/R ) * (V
L
DDO_MAX
)
OH_MIN
-V
)
OL_MAX
Pd_H = (1.0V/50Ω) * (2V - 1.0V) = 20mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
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ICS85214I
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LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
FOR
20 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
200
500
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85214I is: 674
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REV. A JUNE 1, 2005
ICS85214I
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Systems, Inc.
PACKAGE OUTLINE - G SUFFIX
FOR
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
20 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
N
A
Maximum
20
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
6.40
6.60
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
ICS85214AGI
ICS85214AGI
ICS85214AGI
ICS85214AGI
ICS85214AGILF
ICS85214AGIL
ICS85214AGILF
ICS85214AGIL
Count
Temperature
20 lead TSSOP
tube
-40°C to 85°C
20 Lead TSSOP
2500 tape & reel
-40°C to 85°C
20 Lead "Lead-Free" TSSOP
tube
-40°C to 85°C
20 Lead "Lead-Free" TSSOP
2500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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14
REV. A JUNE 1, 2005
ICS85214I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
REVISION HISTORY SHEET
Rev
Table
Page
A
T9
14
85214AGI
Description of Change
Added Lead-Free marking in Ordering Information table.
www.icst.com/products/hiperclocks.html
15
Date
6/1/05
REV. A JUNE 1, 2005
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