PSEMI EK44820-01 Ultracmos rf digital phase shifter 8-bit, 1.7-2.2 ghz Datasheet

PE44820
Document Category: Product Specification
UltraCMOS® RF Digital Phase Shifter 8-bit, 1.7–2.2 GHz
Features
Figure 1 • PE44820 Functional Diagram
• 8-bit full-range phase shifter of 358.6°; 180°, 90°,
45°, 22.5°, 11.2°, 5.6°, 2.8° and 1.4° bits
• Low RMS phase and amplitude error
1.4°
2.8°
5.6°
11.2°
22.5°
45°
90°
RF1
180°
▪ RMS phase error of 1.0°
RF2
• High linearity of +60 dBm IIP3
• Extended narrow band frequency operation of
1.1–3.0 GHz
• +105 °C operating temperature
• Packaging – 32-lead 5 × 5 × 0.85 mm QFN
Serial Interface
▪ RMS amplitude error of 0.1 dB
SI
VDD
CLK
Digital Interface
VSS_EXT
GND
LE
8
• Active antenna arrays
S/P = Parallel
S/P
P0... P7
Parallel
Interface
• Weather and military radar
OPT
• Base station transceivers
4
A0... A3
Serial
Address
SDO2
SDO1
CLKO
LEO
Applications
S/P = Serial
Product Description
The PE44820 is a HaRP™ technology-enhanced 8-bit digital phase shifter (DPS) designed for use in a broad
range of applications including: beamforming networks, distributed antenna systems, active antenna systems
and phased array applications. This DPS covers a phase range of 358.6 degrees in 1.4 degree steps,
maintaining excellent phase and amplitude accuracy across the nominal frequency band of 1.7–2.2 GHz. The
PE44820 is also capable of extended frequency operation from 1.1–3.0 GHz for narrow band applications, as
detailed in Application Note 45. An integrated digital control interface supports both serial and parallel
programming of the phase setting. The PE44820 also features an external negative supply option for a faster
switching frequency, and is offered in a 32-lead 5 × 5 × 0.85 mm QFN package. In addition, no external blocking
capacitors are required if 0 VDC is present on the RF ports.
The PE44820 is manufactured on Peregrine’s UltraCMOS® process, a patented variation of silicon-on-insulator
(SOI) technology on a sapphire substrate.
Peregrine’s HaRP technology enhancements deliver high linearity and excellent harmonics performance. It is an
innovative feature of the UltraCMOS process, offering the performance of GaAs with the economy and
integration of conventional CMOS.
©2015, Peregrine Semiconductor Corporation. All rights reserved. • Headquarters: 9380 Carroll Park Drive, San Diego, CA, 92121
Product Specification
DOC-43214-5 – (11/2015)
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PE44820
Digital Phase Shifter
Optional External VSS
For proper operation, the VSS_EXT pin must be grounded or tied to the VSS voltage specified in Table 2. When the
VSS_EXT pin is grounded, FETs in the switch are biased with an internal negative voltage generator. For applications that require the lowest possible spur performance, VSS_EXT can be applied externally to bypass the internal
negative voltage generator.
Absolute Maximum Ratings
Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be
restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for
extended periods may reduce reliability.
ESD Precautions
When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices.
Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to
avoid exceeding the rating specified in Table 1.
Latch-up Immunity
Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up.
Table 1 • Absolute Maximum Ratings for PE44820
Parameter/Condition
Min
Max
Unit
Supply voltage, VDD
–0.3
5.5
V
Negative supply voltage, VSS_EXT
–3.6
–2.4
V
Digital input voltage
–0.3
3.6
V
28
dBm
+150
°C
500
V
Maximum input power
Storage temperature range
–65
ESD voltage HBM, all pins(*)
Note: * Human body model (MIL-STD 883 Method 3015).
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PE44820
Digital Phase Shifter
Recommended Operating Conditions
Table 2 lists the recommended operating conditions for the PE44820. Devices should not be operated outside
the recommended operating conditions listed below.
Table 2 • Recommended Operating Conditions for PE44820
Parameter
Min
Typ
Max
Unit
5.5
V
130
200
µA
Supply voltage, VDD
3.3
5.5
V
Supply current, IDD
50
80
µA
–3.2
V
Normal mode, VSS_EXT = 0V(1)
Supply voltage, VDD
2.3
Supply current, IDD
Bypass mode, VSS_EXT = –3.3V(2)
Negative supply voltage, VSS_EXT
–3.6
Negative supply current, ISS
–40
–16
µA
Normal or Bypass mode
Digital input high
1.17
3.6
V
Digital input low
–0.3
0.6
V
15
µA
Digital input current
Digital input current, D4–D7(3)
200
RF input power, CW
Operating temperature range
–40
+25
µA
25
dBm
+105
°C
Notes:
1) Normal mode: connect VSS_EXT (pin 20) to GND (VSS_EXT = 0V) to enable internal negative voltage generator.
2) Bypass mode: use VSS_EXT (pin 20) to bypass and disable internal negative voltage generator.
3) Typical current draw 200 µA @ 3.6V. Recommended operation at 1.8V reduces input current draw to 0.6 µA.
DOC-43214-5 – (11/2015)
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PE44820
Digital Phase Shifter
Electrical Specifications
Table 3 provides the PE44820 key electrical specifications at +25 °C (ZS = ZL = 50Ω), unless otherwise
specified. Normal mode(1) is at VDD = 3.3V and VSS_EXT = 0V. Bypass mode(2) is at VDD = 3.3V and VSS_EXT =
–3.3V.
Table 3 • PE44820 Electrical Specifications
Parameter
Condition
Operating frequency
Phase shift range
LSB = 1.4°
Number of bits
Min
Typ
Max
Unit
1.7
1.95
2.2
GHz
+0
358.6
deg
8
bits
Insertion loss
Across all states
RMS phase error
Over all 256 states
1.0
deg
RMS amplitude error
Over all 256 states
0.1
dB
Phase accuracy
Across all states
±3
deg
Attenuation variation
Across all states
±0.50
dB
1.4° bit
–0.60
deg
2.8° bit
–0.40
deg
5.6° bit
+0.05
deg
11.2° bit
+0.25
deg
22.5° bit
+0.50
deg
45° bit
+0.25
deg
90° bit
+1.75
deg
180° bit
–0.65
deg
Return loss
13
dB
Input 0.1dB compression
point(3)
28
dBm
Input IP3
60
dBm
365
ns
Phase accuracy relative
to reference phase @
1.95 GHz
Settling time(4)
6
RF settled within 2 deg of final value
7.1
dB
Notes:
1) Normal mode: single external positive supply used.
2) Bypass mode: both external positive supply and external negative supply used.
3) The input P0.1dB compression point is a linearity figure of merit. Refer to Table 2 for the operating RF input power (50Ω).
4) Use of VSS_EXT reduces the settling time.
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PE44820
Digital Phase Shifter
Switching Frequency
Control Logic
The PE44820 has a maximum 25 kHz switching
frequency in normal mode (pin 20 tied to ground). A
faster switching frequency is available in bypass
mode (pin 20 tied to VSS_EXT).
Table 4 and Table 5 provide the serial/parallel
selection truth table and the serial and parallel truth
table for the PE44820.
Switching frequency describes the time duration
between switching events. Switching time is the time
between the point the control signal LE reaches 50%
of its final value and the point the RF output signal
reaches within 10% or 90% of its target value.
Table 4 • Serial/Parallel Selection Truth Table for
PE44820
S/P Pin
Control Mode
L
Parallel
H
Serial
Table 5 • Serial and Parallel Truth Table(*)
Phase Control Setting
Phase Shift Setting
RF1–RF2
D0
D1
D2
D3
D4
D5
D6
D7
OPT
L
L
L
L
L
L
L
L
L
Reference phase
H
L
L
L
L
L
L
L
L
1.4 deg
L
H
L
L
L
L
L
L
L
2.8 deg
L
L
H
L
L
L
L
L
L
5.6 deg
L
L
L
H
L
L
L
L
L
11.2 deg
L
L
L
L
H
L
L
L
L
22.5 deg
L
L
L
L
L
H
L
L
L
45 deg
L
L
L
L
L
L
H
L
H
90 deg
L
L
L
L
L
L
L
H
L
180 deg
H
H
H
H
H
H
H
H
H
358.6 deg
L
L
L
L
L
L
L
L
H
1.4 deg
Note: * Normal mode operation uses the OPT bit to synchronize the 90 degree bit optimizing the phase accuracy across all states. For additional information on the OPT bit, reference Application Note 45.
DOC-43214-5 – (11/2015)
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PE44820
Digital Phase Shifter
Figure 2 • Serial Control Register Map
SDO1
LSB (first in)
SI
MSB (last in)
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
D0
D1
D2
D3
D4
D5
D6
D7
OPT
A0
A1
A2
A3
Phase Setting Word
SDO2
Unit Address Word
Phase Setting Word is derived directly from the Phase Setting. For example, to
program the 205.3 degree setting at unit address 3:
Unit Address Word: 1100 (Unit Address = 1 + 2)
Phase Setting Word: Multiply the degree desired by 256 states divided by 360° and convert to binary
205.3° × (256 states / 360°) = state 146
state 146 → 01001001
LSB→MSB (205.3 deg setting = 2.8° + 22.5° + 180°)
Program Word (LSB→MSB): 010010010 + 1100, OPT bit is synchronized to 90° bit
Figure 3 • Buffered SDO1 Serial Interface
TSCLK
LE
TOV
TH
TSU
TSCLKH
TSCLKL
TLCLKH
TSettle
CLK
D0 D1 D2 D3 D4 D5 D6 D7 OPT A0 A1 A2 A3
SI
D0 D1 D2 D3 D4 D5 D6 D7 OPT A0 A1 A2 A3
SDO1
Register Data
Default/Current Value
New Value
TOH
Note: SDO1 data buffered with respect to SI and valid on rising edge of CLK
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PE44820
Digital Phase Shifter
Figure 4 • SDO2 (Last Bit of Shift Register)—Single Write with Readback
TSU
TSCLK
LE
TOV
TH
TSCLKH
TSCLKL
TSettle
CLK
D0 D1 D2 D3 D4 D5 D6 D7 OPT A0 A1 A2 A3
D0 D1 D2 D3 D4 D5 D6 D7 OPT A0 A1 A2 A3
SI
D0 D1 D2 D3 D4 D5 D6 D7 OPT A0 A1 A2 A3
D0 D1 D2 D3 D4 D5 D6 D7 OPT A0 A1 A2 A3
SDO2
TOH
Register Data
Default/Current Value
New Value
Note: SDO2 data is valid on the falling edge of SCLK
Table 6 • Latch and Clock Specifications
Latch
Enable
Shift
Clock
Function
0
↑
Shift register clocked
↑
×
Contents of shift register transferred
to phase shifter core
DOC-43214-5 – (11/2015)
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PE44820
Digital Phase Shifter
Typical Performance Data
Figure 5–Figure 18 show the typical performance data at +25 °C, VDD = 3.3V and VSS_EXT = 0V, unless
otherwise specified.
Figure 5 • Relative Phase Error: OPT Bit
Phase Error: OPT Bit
5
4
3
2
[deg]
1
0
-1
-2
-3
-4
-5
1700
1750
1800
1850
1900
1950
2000
2050
2100
2150
2200
Frequency [MHz]
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PE44820
Digital Phase Shifter
Figure 6 • Relative Phase Error: 180 Deg Bit
Phase Error: 180°
5
4
3
2
[deg]
1
0
-1
-2
-3
-4
-5
1700
1750
1800
1850
1900
1950
2000
2050
2100
2150
2200
2050
2100
2150
2200
Frequency [MHz]
Figure 7 • Relative Phase Error: 90 Deg Bit
Phase Error: 90°
5
4
3
2
[deg]
1
0
-1
-2
-3
-4
-5
1700
1750
1800
1850
1900
1950
2000
Frequency [MHz]
DOC-43214-5 – (11/2015)
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PE44820
Digital Phase Shifter
Figure 8 • Relative Phase Error: 45 Deg Bit
Phase Error: 45°
5
4
3
2
[deg]
1
0
-1
-2
-3
-4
-5
1700
1750
1800
1850
1900
1950
2000
2050
2100
2150
2200
Frequency [MHz]
Figure 9 • Relative Phase Error: 22.5 Deg Bit
Phase Error: 22.5°
5
4
3
2
[deg]
1
0
-1
-2
-3
-4
-5
1700
1750
1800
1850
1900
1950
2000
2050
2100
2150
2200
Frequency [MHz]
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PE44820
Digital Phase Shifter
Figure 10 • Relative Phase Error: 11.25 Deg Bit
Phase Error: 11.25°
5
4
3
2
[deg]
1
0
-1
-2
-3
-4
-5
1700
1750
1800
1850
1900
1950
2000
2050
2100
2150
2200
2050
2100
2150
2200
Frequency [MHz]
Figure 11 • Relative Phase Error: 5.6 Deg Bit
Phase Error: 5.6°
5
4
3
2
[deg]
1
0
-1
-2
-3
-4
-5
1700
1750
1800
1850
1900
1950
2000
Frequency [MHz]
DOC-43214-5 – (11/2015)
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PE44820
Digital Phase Shifter
Figure 12 • Relative Phase Error: 2.8 Deg Bit
Phase Error: 2.8°
5
4
3
2
[deg]
1
0
-1
-2
-3
-4
-5
1700
1750
1800
1850
1900
1950
2000
2050
2100
2150
2200
2050
2100
2150
2200
Frequency [MHz]
Figure 13 • Relative Phase Error: 1.4 Deg Bit
Phase Error: 1.4°
5
4
3
2
[deg]
1
0
-1
-2
-3
-4
-5
1700
1750
1800
1850
1900
1950
2000
Frequency [MHz]
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PE44820
Digital Phase Shifter
Figure 14 • RMS Amplitude Error
-40 °C
25 °C
85 °C
105 °C
1
0.9
0.8
0.7
[dB]
0.6
0.5
0.4
0.3
0.2
0.1
0
1700
1750
1800
1850
1900
1950
2000
2050
2100
2150
2200
Frequency [MHz]
Figure 15 • RMS Phase Error
-40°C
25°C
85°C
105°C
3
2.5
[deg]
2
1.5
1
0.5
0
1700
1750
1800
1850
1900
1950
2000
2050
2100
2150
2200
Frequency [MHz]
DOC-43214-5 – (11/2015)
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PE44820
Digital Phase Shifter
Figure 16 • Maximum Return Loss S11 Over All Major States
-40 °C
25 °C
85 °C
105 °C
-10
-15
-20
[dB]
-25
-30
-35
-40
-45
-50
1700
1750
1800
1850
1900
1950
2000
2050
2100
2150
2200
2100
2150
2200
Frequency [MHz]
Figure 17 • Maximum Return Loss S22 Over All Major States
-40 °C
25 °C
85 °C
105 °C
-10
-15
-20
[dB]
-25
-30
-35
-40
-45
-50
1700
1750
1800
1850
1900
1950
2000
2050
Frequency [MHz]
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PE44820
Digital Phase Shifter
Figure 18 • Insertion Loss—Reference States
-40 °C
25 °C
85 °C
105 °C
-4
-4.5
-5
-5.5
[dB]
-6
-6.5
-7
-7.5
-8
-8.5
-9
1700
1750
1800
1850
1900
1950
2000
2050
2100
2150
2200
Frequency [MHz]
DOC-43214-5 – (11/2015)
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PE44820
Digital Phase Shifter
Evaluation Kit
The PE44820 evaluation kit (EVK) includes hardware required to control and evaluate the functionality of the
DPS. The DPS evaluation software can be downloaded at www.psemi.com and requires a PC running
Windows® operating system to control the USB interface board. Refer to the PE44820 Evaluation Kit User’s
Manual for more information.
Figure 19 • Evaluation Kit Layout for PE44820
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PE44820
Digital Phase Shifter
Pin Information
Table 7 • Pin Descriptions for PE44820 (Cont.)
This section provides pinout information for the
PE44820. Figure 20 shows the pin map of this device
for the available package. Table 7 provides a
description for each pin.
Pin No.
Pin Name
20
VSS_EXT(3)
External VSS negative supply
voltage.
22
LE
Serial interface latch enable
input.
23
CLK
Serial interface clock input.
24
SI
Serial interface data input.
25
D7/SDO2(4)(6)
Parallel—D7 180° bit/serial data
out 2.
26
D6/SDO1(4)(6)
Parallel—D6 90° bit/serial data
out 1.
27
D5/CLK0(6)
Parallel—D5 45° bit/serial-buffered CLK out.
28
D4/LE0(6)
29
D3/A3
Parallel—D3 11.2° bit/serial A3
address bit.
30
D2/A2
Parallel—D2 5.6° bit/serial A2
address bit.
31
D1/A1
Parallel—D1 2.8° bit/serial A1
address bit.
32
D0/A0
Parallel—D0 1.4° bit/serial A0
address bit.
Pad
GND
Exposed pad: Ground for proper
operation.
D0/A0
D1/A1
D2/A2
D3/A3
D4/LE0
D5/CLK0
D6/SDO1
D7/SDO2
31
30
29
28
27
26
25
Pin 1 Dot
Marking
32
Figure 20 • Pin Configuration (Top View)
OPT
1
24
SI
VDD
2
23
CLK
S/P
3
22
LE
GND
4
21
GND
GND
5
20
VSS_EXT
GND
6
19
GND
RF1
7
18
RF2
GND
8
17
GND
16
GND
15
GND
14
GND
13
GND
12
GND
11
GND
10
GND
GND
9
Exposed
Ground Pad
Table 7 • Pin Descriptions for PE44820
Pin No.
Pin Name
Description
1
OPT(1)
Phase accuracy optimization bit.
2
VDD
Supply voltage.
3
S/P
Serial/parallel mode select.
4–6, 8–17,
19, 21
GND
Ground.
7
RF1(2)
RF1 port.
18
RF2(2)
RF2 port
Description
Parallel—D4 22.4° bit/serial buffered LE out.
Notes:
1) OPT bit is used to optimize the phase accuracy across all states.
OPT bit (pin 1) must be synchronized to the 90° bit (pin 26) for
normal operation.
2) RF1 and RF2 (pins 7 and 18) are bi-directional.
3) Use VSS_EXT (pin 20) with negative supply (VSS_EXT = –3.6V) to
bypass and disable internal negative voltage generator. Connect
VSS_EXT (pin 20) to GND (VSS_EXT = 0V) to enable internal negative voltage generator.
4) SDO2 is buffered output of the last bit of the internal shift register.
5) SDO1 is a buffered output of the serial data input.
6) D4–D7 (pins 25–28) are bi-directional pins.
DOC-43214-5 – (11/2015)
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PE44820
Digital Phase Shifter
Packaging Information
This section provides packaging data including the moisture sensitivity level, package drawing, package
marking and tape and reel information.
Moisture Sensitivity Level
The moisture sensitivity level rating for the PE44820 in the 32-lead 5 × 5 × 0.85 mm QFN package is MSL1.
Package Drawing
Figure 21 • Package Mechanical Drawing for 32-lead 5 × 5 × 0.85 mm QFN
0.10 C
A
5.00
(2X)
3.60±0.05
0.40±0.05
(x32)
B
17
0.60
(x32)
24
0.30
(x32)
0.50
(x28)
0.50
(x28)
16
25
3.60±0.05
5.00
0.25±0.05
(x32)
0.10 C
3.65
5.40
32
9
8
1
(2X)
3.65
3.50
REF
PIN #1 CORNER
TOP VIEW
5.40
BOTTOM VIEW
RECOMMENDED LAND PATTERN
0.10 C
0.10
0.05
0.85±0.05
0.05 C
SEATING PLANE
0.203
REF
C A B
C
ALL FEATURES
0.05
REF
C
SIDE VIEW
Top-Marking Specification
Figure 22 • Package Marking Specifications for PE44820
44820
YYWW
ZZZZZZZ
=
YY =
WW =
ZZZZZZZ =
Pin 1 indicator
Last two digits of assembly year
Assembly work week
Assembly lot code (maximum seven characters)
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PE44820
Digital Phase Shifter
Tape and Reel Specification
Figure 23 • Tape and Reel Specifications for 32-lead 5 × 5 × 0.85 mm QFN
Direction of Feed
Section A-A
P1
P0
see
note 1
T
P2
see note 3
D1
D0
A
E
F
see note 3
B0
A0
K0
A0
B0
K0
D0
D1
E
F
P0
P1
P2
T
W0
5.25
5.25
1.10
1.50 + 0.1/ -0.0
1.5 min
1.75 ± 0.10
5.50 ± 0.05
4.00
8.00
2.00 ± 0.05
0.30 ± 0.05
12.00 ± 0.30
A
W0
Pin 1
Notes:
1. 10 Sprocket hole pitch cumulative tolerance ±0.2
2. Camber in compliance with EIA 481
3. Pocket position relative to sprocket hole measured
as true position of pocket, not pocket hole
Dimensions are in millimeters unless otherwise specified
DOC-43214-5 – (11/2015)
Device Orientation in Tape
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PE44820
Digital Phase Shifter
Ordering Information
Table 8 lists the available ordering codes for the PE44820 as well as available shipping methods.
Table 8 • Order Codes for PE44820
Order Codes
Description
Packaging
Shipping Method
PE44820A–X
PE44820 Digital phase shifter
Green 32-lead 5 × 5 mm QFN
500 units/T&R
EK44820–01
PE44820 Evaluation kit
Evaluation kit
1/Box
Document Categories
Advance Information
Product Brief
The product is in a formative or design stage. The datasheet contains
design target specifications for product development. Specifications
and features may change in any manner without notice.
This document contains a shortened version of the datasheet. For the
full datasheet, contact [email protected].
Preliminary Specification
Not Recommended for New Designs (NRND)
This product is in production but is not recommended for new designs.
The datasheet contains preliminary data. Additional data may be added
at a later date. Peregrine reserves the right to change specifications at
any time without notice in order to supply the best possible product.
Product Specification
The datasheet contains final data. In the event Peregrine decides to
change the specifications, Peregrine will notify customers of the
intended changes by issuing a CNF (Customer Notification Form).
End of Life (EOL)
This product is currently going through the EOL process. It has a
specific last-time buy date.
Obsolete
This product is discontinued. Orders are no longer accepted for this
product.
Sales Contact
For additional information, contact Sales at [email protected].
Disclaimers
The information in this document is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be
entirely at the user’s own risk. No patent rights or licenses to any circuits described in this document are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to
support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death
might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in
such applications.
Patent Statement
Peregrine products are protected under one or more of the following U.S. patents: patents.psemi.com
Copyright and Trademark
©2015, Peregrine Semiconductor Corporation. All rights reserved. The Peregrine name, logo, UTSi and UltraCMOS are registered trademarks and
HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp.
Product Specification
www.psemi.com
DOC-43214-5 – (11/2015)