Cypress CY7C1548V18 72-mbit ddr-ii sram 2-word burst architecture (2.0 cycle read latency) Datasheet

CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
72-Mbit DDR-II+ SRAM 2-Word Burst
Architecture (2.0 Cycle Read Latency)
Features
Functional Description
■
72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
■
300 MHz to 375 MHz clock for high bandwidth
■
2-Word burst for reducing address bus frequency
■
Double Data Rate (DDR) interfaces
(data transferred at 750 MHz) at 375 MHz
■
Read latency of 2.0 clock cycles
■
Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■
Data valid pin (QVLD) to indicate valid data on the output
■
Synchronous internally self-timed writes
■
Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD[1]
■
HSTL inputs and Variable drive HSTL output buffers
■
Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
■
Offered in both Pb-free and non Pb-free packages
■
JTAG 1149.1 compatible test access port
■
Delay Lock Loop (DLL) for accurate data placement
The CY7C1546V18, CY7C1557V18, CY7C1548V18, and
CY7C1550V18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II+ architecture. The DDR-II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of both K and K. Each address location is associated with two
8-bit words (CY7C1546V18), 9-bit words (CY7C1557V18),
18-bit words (CY7C1548V18), or 36-bit words (CY7C1550V18)
that burst sequentially into or out of the device.
Asynchronous inputs include output impedance matching input
(ZQ). Synchronous data outputs (Q, that share the same
physical pins with the data inputs, D) are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need to capture
data separately from individual DDR SRAMs in the system
design.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Configurations
With Read Cycle Latency of 2.0 cycles:
CY7C1546V18 – 8M x 8
CY7C1557V18 – 8M x 9
CY7C1548V18 – 4M x 18
CY7C1550V18 – 2M x 36
Selection Guide
375 MHz
333 MHz
300 MHz
Unit
375
333
300
MHz
x8
1300
1200
1100
mA
x9
1300
1200
1100
x18
1300
1200
1100
x36
1300
1200
1100
Maximum Operating Frequency
Maximum Operating Current
Note
1. The QDR consortium specification for VDDQ is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting VDDQ
= 1.4V to VDD.
Cypress Semiconductor Corporation
Document Number: 001-06550 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 7, 2007
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
K
K
DOFF
VREF
R/W
NWS[1:0]
CLK
Gen.
Write
Reg
Write Add. Decode
LD
Address
Register
Write
Reg
4M x 8 Array
22
4M x 8 Array
A(21:0)
Read Add. Decode
Logic Block Diagram (CY7C1546V18)
8
Output
Logic
Control
R/W
Read Data Reg.
16
Control
Logic
8
Reg.
Reg.
CQ
8
CQ
8
8
DQ[7:0]
8
Reg.
QVLD
K
K
DOFF
VREF
R/W
BWS[0]
CLK
Gen.
Write Add. Decode
LD
Address
Register
Write
Reg
Write
Reg
4M x 9 Array
22
4M x 9 Array
A(21:0)
Read Add. Decode
Logic Block Diagram (CY7C1557V18)
9
Output
Logic
Control
R/W
Read Data Reg.
18
Control
Logic
9
9
Reg.
Reg.
CQ
9
CQ
9
Reg.
9
DQ[8:0]
QVLD
Document Number: 001-06550 Rev. *D
Page 2 of 27
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
K
K
DOFF
VREF
R/W
BWS[1:0]
CLK
Gen.
Write Add. Decode
LD
Address
Register
Write
Reg
Write
Reg
2M x 18 Array
21
2M x 18 Array
A(20:0)
Read Add. Decode
Logic Block Diagram (CY7C1548V18)
18
Output
Logic
Control
R/W
Read Data Reg.
36
18
Control
Logic
Reg.
18
Reg.
18
Reg.
CQ
18
CQ
DQ[17:0]
18
QVLD
K
K
DOFF
VREF
R/W
BWS[3:0]
CLK
Gen.
Write Add. Decode
LD
Address
Register
Write
Reg
Write
Reg
1M x 36 Array
20
1M x 36 Array
A(19:0)
Read Add. Decode
Logic Block Diagram (CY7C1550V18)
36
Output
Logic
Control
R/W
Read Data Reg.
72
Control
Logic
36
36
Reg.
Reg.
Reg.
CQ
36
36
CQ
36
DQ[35:0]
QVLD
Document Number: 001-06550 Rev. *D
Page 3 of 27
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
Pin Configuration
The Pin Configuration for CY7C1546V18, CY7C1557V18, CY7C1548V18, and CY7C1550V18 follows.[2]
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1546V18 (8M x 8)
A
1
2
3
4
5
6
7
8
9
10
11
CQ
A
A
R/W
NWS1
K
NC/144M
LD
A
A
CQ
B
NC
NC
NC
A
NC/288M
K
NWS0
A
NC
NC
DQ3
C
NC
NC
NC
VSS
A
A
A
VSS
NC
NC
NC
D
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
DQ4
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
NC
DQ5
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ1
NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
DQ6
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ0
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
N
NC
NC
NC
VSS
A
A
A
VSS
NC
NC
NC
P
NC
NC
DQ7
A
A
C
A
A
NC
NC
NC
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
CY7C1557V18 (8M x 9)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
A
A
R/W
NC
K
NC/144M
LD
A
A
CQ
B
NC
NC
NC
A
NC/288M
K
BWS0
A
NC
NC
DQ3
C
NC
NC
NC
VSS
A
A
A
VSS
NC
NC
NC
D
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
DQ4
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
NC
DQ5
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ1
NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
DQ6
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ0
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
N
NC
NC
NC
VSS
A
A
A
VSS
NC
NC
NC
P
NC
NC
DQ7
A
A
QVLD
A
A
NC
NC
DQ8
R
TDO
TCK
A
A
A
NC
A
A
A
TMS
TDI
Note
2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-06550 Rev. *D
Page 4 of 27
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
Pin Configuration
The Pin Configuration for CY7C1546V18, CY7C1557V18, CY7C1548V18, and CY7C1550V18 follows.[2] (continued)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1548V18 (4M x 18)
A
1
2
3
4
5
6
7
8
9
10
11
CQ
A
A
R/W
BWS1
K
NC/144M
LD
A
A
CQ
B
NC
DQ9
NC
A
NC/288M
K
BWS0
A
NC
NC
DQ8
C
NC
NC
NC
VSS
A
NC
A
VSS
NC
DQ7
NC
D
NC
NC
DQ10
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
DQ11
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ6
F
NC
DQ12
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
G
NC
NC
DQ13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ4
NC
K
NC
NC
DQ14
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ3
L
NC
DQ15
NC
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
DQ1
NC
N
NC
NC
DQ16
VSS
A
A
A
VSS
NC
NC
NC
P
NC
NC
DQ17
A
A
QVLD
A
A
NC
NC
DQ0
R
TDO
TCK
A
A
A
NC
A
A
A
TMS
TDI
CY7C1550V18 (2M x 36)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
NC/144M
A
R/W
BWS2
K
BWS1
LD
A
A
CQ
B
NC
DQ27
DQ18
A
BWS3
K
BWS0
A
NC
NC
DQ8
C
NC
NC
DQ28
VSS
A
NC
A
VSS
NC
DQ17
DQ7
D
NC
DQ29
DQ19
VSS
VSS
VSS
VSS
VSS
NC
NC
DQ16
E
NC
NC
DQ20
VDDQ
VSS
VSS
VSS
VDDQ
NC
DQ15
DQ6
F
NC
DQ30
DQ21
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
G
NC
DQ31
DQ22
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ14
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
DQ32
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ13
DQ4
K
NC
NC
DQ23
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ12
DQ3
L
NC
DQ33
DQ24
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
M
NC
NC
DQ34
VSS
VSS
VSS
VSS
VSS
NC
DQ11
DQ1
N
NC
DQ35
DQ25
VSS
A
A
A
VSS
NC
NC
DQ10
P
NC
NC
DQ26
A
A
QVLD
A
A
NC
DQ9
DQ0
R
TDO
TCK
A
A
A
NC
A
A
A
TMS
TDI
Document Number: 001-06550 Rev. *D
Page 5 of 27
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
Pin Definitions
Pin Name
IO
Pin Description
DQ[x:0]
Data Input or Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid
Input and
write operations. These pins drive out the requested data during a read operation. Valid data is driven
Output
Synchronous out on the rising edge of both the K and K clocks during read operations. When read access is
deselected, Q[x:0] are automatically tri-stated.
CY7C1546V18 − DQ[7:0]
CY7C1557V18 − DQ[8:0]
CY7C1548V18 − DQ[17:0]
CY7C1550V18 − DQ[35:0]
LD
Input
Synchronous Load. Sampled on the rising edge of the K clock. This input is brought LOW when a
Synchronous bus cycle sequence is defined. This definition includes address and read or write direction. All transactions operate on a burst of 2 data. LD must meet the setup and hold times around edge of K.
NWS0, NWS1 Input
Synchronous
Nibble Write Select 0, 1, Active LOW (CY7C1546V18 only). Sampled on the rising edge of the K
and K clocks during write operations. Used to select the nibble that is written into the device during
the current portion of the write operations. Nibbles not written remain unaltered.
NWS0 controls D[3:0] and NWS1 controls D[7:4].
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write
Select ignores the corresponding nibble of data and does not write into the device.
BWS0, BWS1,
BWS2, BWS3
Input
Byte Write Select 0, 1, 2, and 3, Active LOW. Sampled on the rising edge of the K and K clocks
Synchronous during write operations. Used to select the byte written into the device during the current portion of
the write operations. Bytes not written remain unaltered.
CY7C1557V18 − BWS0 controls D[8:0]
CY7C1548V18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1550V18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and does not write into the device.
A
Input
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.
Synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 8M x 8 (2 arrays each of 4M x 8) for CY7C1546V18, 8M x 9 (2 arrays each of 4M x 9)
for CY7C1557V18, 4M x 18 (2 arrays each of 2M x 18) for CY7C1548V18, and 2M x 36 (2 arrays
each of 1M x 36) for CY7C1550V18.
R/W
Input
Synchronous Read or Write Input. When LD is LOW, this input designates the access type (read
Synchronous when R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold
times around edge of K.
QVLD
Valid output
indicator
Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and
CQ.
K
Input
Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
edge of K.
K
Input
Clock
Negative Input Clock Input. K is used to capture synchronous data presented to the device and to
drive out data through Q[x:0] when in single clock mode.
CQ
Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
clock (K) of the DDR-II+. The timing for the echo clocks is shown in “Switching Characteristics” on
page 22.
CQ
Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
clock (K) of the DDR-II+. The timing for the echo clocks is shown in “Switching Characteristics” on
page 22.
Document Number: 001-06550 Rev. *D
Page 6 of 27
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
Pin Definitions
Pin Name
(continued)
IO
Pin Description
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin is connected directly to VDDQ and enables
the minimum impedance mode. This pin is not connected directly to GND or left unconnected.
DOFF
Input
DLL Turn Off, Active LOW. Connecting this pin to ground turns off the DLL inside the device. The
timing in the DLL turned off operation is different from that listed in this datasheet. For normal
operation, this pin is connected to a pull up through a 10 Kohm or less pull up resistor. The device
behaves in DDR-I mode when the DLL is turned off. In this mode, the device is operated at a
frequency of up to 167 MHz with DDR-I timing.
TDO
Output
TCK
Input
TCK Pin for JTAG.
TDI
Input
TDI Pin for JTAG.
TMS
Input
TMS Pin for JTAG.
NC
N/A
Not Connected to the Die. Is tied to any voltage level.
NC/72M
N/A
Not Connected to the Die. Is tied to any voltage level.
NC/144M
N/A
Not Connected to the Die. Is tied to any voltage level.
NC/288M
N/A
Not Connected to the Die. Is tied to any voltage level.
VREF
VDD
VSS
VDDQ
Input
Reference
TDO for JTAG.
Reference Voltage Input. Static input is used to set the reference level for HSTL inputs, outputs,
and AC measurement points.
Power Supply Power Supply Inputs to the Core of the Device.
Ground
Ground for the Device.
Power Supply Power Supply Inputs for the Outputs of the Device.
Document Number: 001-06550 Rev. *D
Page 7 of 27
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
Functional Overview
The CY7C1546V18, CY7C1557V18, CY7C1548V18, and
CY7C1550V18 are synchronous pipelined Burst SRAMs
equipped with a DDR interface.
Accesses for both ports are initiated on the Positive Input Clock
(K). All synchronous input and output timing refer to the rising
edge of the input clocks (K and K).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the rising edge of the input clocks (K and K). All
synchronous data outputs (Q[x:0]) pass through output registers
controlled by the rising edge of the input clocks (K and K).
All synchronous control (R/W, LD, NWS[0:X], BWS[0:X]) inputs
pass through input registers controlled by the rising edge of the
input clock (K\K).
CY7C1548V18 is described in the following sections. The same
basic descriptions apply to CY7C1546V18, CY7C1557V18, and
CY7C1550V18.
Read Operations
The CY7C1548V18 is organized internally as two arrays of 4M x
18. Accesses are completed in a burst of two sequential 18-bit
data words. Read operations are initiated by asserting R/W
HIGH and LD LOW at the rising edge of the positive input clock
(K). Following the next two K clock rising edges, drive the corresponding 18-bit word of data from this address location onto the
Q[17:0] using K as the output timing reference. On the subsequent rising edge of K, drive the next 18-bit data word onto the
Q[17:0]. The requested data is valid 0.45 ns from the rising edge
of the input clock (K and K). To maintain the internal logic, each
read access is allowed to complete. Read accesses are initiated
on every rising edge of the positive input clock (K).
When read access is deselected, the CY7C1548V18 completes
the pending read transactions. Synchronous internal circuitry
automatically tri-states the outputs following the next rising edge
of the positive input clock (K). This enables a seamless transition
between devices without the insertion of wait states in a depth
expanded memory.
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to address inputs is stored in the Write
Address register. On the following K clock rise, the data
presented to D[17:0] is latched and stored into the 18-bit Write
Data register, provided BWS[1:0] are both asserted active. On the
subsequent rising edge of the Negative Input Clock (K), the information presented to D[17:0] is also stored into the Write Data
register, provided BWS[1:0] are both asserted active. The 36 bits
of data is then written into the memory array at the specified
location. Write accesses are initiated on every rising edge of the
positive input clock (K). This pipelines the data flow such that 18
bits of data is transferred into the device on every rising edge of
the input clocks (K and K).
When write access is deselected, the device ignores all inputs
after the pending write operations are completed.
Document Number: 001-06550 Rev. *D
Byte Write Operations
Byte write operations are supported by the CY7C1548V18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, that are sampled with each set of 18-bit data words. The
data presented is latched and written into the device by asserting
the appropriate Byte Write Select input during the data portion of
a write. Deasserting the Byte Write Select input during the data
portion of a write enables the data stored in the device for that
byte to remain unaltered. This feature is used to simplify read,
modify, and write operations to a byte write operation.
Double Date Rate Operation
The CY7C1548V18 enables high performance operation
through high clock frequencies (achieved through pipelining) and
DDR mode of operation. The CY7C1548V18 requires two No
Operation (NOP) cycles when transitioning from a read to a write
cycle. At higher frequencies, some applications require a third
NOP cycle to avoid contention.
If a read occurs after a write cycle, address and data for the write
are stored in registers. The write information is stored because
the SRAM cannot perform the last word write to the array without
conflicting with the read. The data stays in this register until the
next write cycle occurs. On the first write cycle after the read(s),
the stored data from the earlier write is written into the SRAM
array. This is called a Posted Write.
If a read is performed on the same address where a write is
performed in the previous cycle, the SRAM reads out the most
current data. The SRAM does this by bypassing the memory
array and reading the data from the registers.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals are common between banks
as appropriate.
Programmable Impedance
An external resistor, RQ, is connected between the ZQ pin on the
SRAM and VSS to enable the SRAM to adjust its output driver
impedance. The value of RQ is 5x the value of the intended line
impedance driven by the SRAM. The allowable range of RQ to
guarantee impedance matching with a tolerance of ±15% is
between 175Ω and 350Ω, with VDDQ = 1.5V. The output
impedance is adjusted every 1024 cycles upon power up to
account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the DDR-II+ to simplify data capture
on high speed systems. Two echo clocks are generated by the
DDR-II+. CQ is referenced with respect to K and CQ is referenced with respect to K. These are free running clocks and are
synchronized to the input clock of the DDR-II+. The timing for the
echo clocks is shown in “Switching Characteristics” on page 22.
Valid Data Indicator (QVLD)
QVLD is provided on the DDR-II+ to simplify data capture on high
speed systems. The QVLD is generated by the DDR-II+ device
along with data output. This signal is also edge aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
Page 8 of 27
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
DLL
These chips use a DLL that is designed to function between 120
MHz and the specified maximum clock frequency. The DLL is
disabled by applying ground to the DOFF pin. When the DLL is
turned off, the device behaves in DDR-I mode (with 1.0 cycle
latency and a longer access time). For more information, refer to
the
application
note,
DLL
Considerations
in
QDRII/DDRII/QDRII+/DDRII+. The DLL is reset by slowing or
stopping the input clocks K and K for a minimum of 30 ns.
However, it is not necessary to reset the DLL to lock at the
desired frequency. During power up, when the DOFF is tied
HIGH, the DLL gets locked after 2048 cycles of stable clock.
Application Example
Figure 1. Application Example
DQ
A
SRAM#1
LD
R/W
ZQ
CQ/CQ
K K
DQ
A
R = 250ohms
SRAM#2
LD
R/W
ZQ
CQ/CQ
K K
R = 250ohms
DQ
Addresses
BUS
MASTER Cycle Start
R/W
(CPU or ASIC)
Source CLK
Source CLK
Echo Clock1/Echo Clock1
Echo Clock2/Echo Clock2
Truth Table
The truth table for CY7C1546V18, CY7C1557V18, CY7C1548V18, and CY7C1550V18 follows.[3, 4, 5, 6, 7, 8]
Operation
K
LD
R/W
Write Cycle:
Load address; wait one cycle;
input write data on consecutive K and K rising edges.
L-H
L
L
D(A) at K(t + 1) ↑
D(A+1) at K(t + 1) ↑
Read Cycle: (2.0 cycle Latency)
Load address; wait two cycle;
read data on consecutive K and K rising edges.
L-H
L
H
Q(A) at K(t + 2) ↑
Q(A+1) at K(t + 2) ↑
NOP: No Operation
L-H
H
X
High Z
High Z
Stopped
X
X
Previous State
Previous State
Standby: Clock Stopped
DQ
DQ
Notes
3. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
4. Device powers up deselected with the outputs in a tri-state condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst.
6. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.
8. Cypress recommends that K = K = HIGH when clock is stopped. This is not essential but permits most rapid restart by overcoming transmission line charging
symmetrically.
Document Number: 001-06550 Rev. *D
Page 9 of 27
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
Write Cycle Descriptions
The write cycle description table for CY7C1546V18 and CY7C1548V18 follows. [3, 9]
BWS0/ BWS1/
K
K
L
L–H
–
L
L
–
L
H
L–H
L
H
–
H
L
L–H
H
L
–
H
H
L–H
H
H
–
NWS0
NWS1
L
Comments
During the data portion of a write sequence :
CY7C1546V18 − both nibbles (D[7:0]) are written into the device,
CY7C1548V18 − both bytes (D[17:0]) are written into the device.
L-H During the data portion of a write sequence :
CY7C1546V18 − both nibbles (D[7:0]) are written into the device,
CY7C1548V18 − both bytes (D[17:0]) are written into the device.
–
During the data portion of a write sequence :
CY7C1546V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1548V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L–H During the data portion of a write sequence :
CY7C1546V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1548V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
–
During the data portion of a write sequence :
CY7C1546V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1548V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
L–H During the data portion of a write sequence :
CY7C1546V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1548V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
The write cycle description table for CY7C1557V18 follows. [3, 9]
BWS0
K
K
L
L–H
–
During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
L
–
L–H
During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
H
L–H
–
No data is written into the device during this portion of a write operation.
H
–
L–H
No data is written into the device during this portion of a write operation.
Note
9. Assumes a write cycle is initiated as per the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 is altered on different portions of a write
cycle, as long as the setup and hold requirements are met.
Document Number: 001-06550 Rev. *D
Page 10 of 27
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
Write Cycle Descriptions
The write cycle description table for CY7C1550V18 follows. [3, 9]
BWS0
BWS1
BWS2
BWS3
K
K
Comments
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
–
L
H
H
H
L–H
L
H
H
H
–
H
L
H
H
L–H
H
L
H
H
–
H
H
L
H
L–H
H
H
L
H
–
H
H
H
L
L–H
H
H
H
L
–
H
H
H
H
L–H
H
H
H
H
–
Document Number: 001-06550 Rev. *D
L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
–
During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
–
During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remain unaltered.
L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remain unaltered.
–
During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remain unaltered.
L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remain unaltered.
–
During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Page 11 of 27
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard 1149.1-2001. The TAP operates using JEDEC
standard 1.8V IO logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, tie TCK LOW (VSS) to
prevent device clocking. TDI and TMS are internally pulled up
and are unconnected. They are alternately connected to VDD
through a pull up resistor. TDO is left unconnected. Upon power
up, the device comes up in a reset state that does not interfere
with the operation of the device.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. Leave this pin unconnected if the TAP is not used. The pin is pulled up internally,
resulting in a logic HIGH level.
Test Data In (TDI)
The TDI pin is used to serially input information into the registers
and is connected to the input of any of the registers. The register
between TDI and TDO is selected by the instruction that is
loaded into the TAP instruction register. For information about
loading the Instruction register, see “TAP Controller State
Diagram” on page 14. TDI is internally pulled up and is unconnected if the TAP is unused in an application. TDI is connected
to the most significant bit (MSb) on any register.
Instruction Register
Three-bit instructions is serially loaded into the Instruction
register. This register placed between the TDI and TDO pins is
loaded as shown in “TAP Controller Block Diagram” on page 15.
Upon power up, the Instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the Performing a TAP Reset.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to enable fault
isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The Bypass
register is a single-bit register that is placed between TDI and
TDO pins. This enables data shifting through the SRAM with
minimal delay. The Bypass register is set LOW (VSS) when the
BYPASS instruction is executed.
Boundary Scan Register
The Boundary Scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are also
included in the Scan register to reserve pins for higher density
devices.
The Boundary Scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state. It is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions are
used to capture the contents of the input and output ring.
“Boundary Scan Order” on page 18 shows the order of the bits
that are connected. Each bit corresponds to one of the bumps on
the SRAM package. The MSb of the register is connected to TDI
and the LSb is connected to TDO.
Test Data Out (TDO)
Identification (ID) Register
The TDO output pin is used to serially clock data out from the
registers. The active state of the output depends on the current
state of the TAP state machine (see “Instruction Codes” on
page 17). The output changes on the falling edge of TCK. TDO
is connected to the least significant bit (LSb) of any register.
The ID register is loaded with a vendor specific 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the Instruction register. The IDCODE is hardwired into
the SRAM and is shifted out, when the TAP controller is in the
Shift-DR state. The ID register has a vendor code and other information described in “Identification Register Definitions” on
page 17.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and is performed while the SRAM is operating. At power
up, the TAP is reset internally to ensure that TDO comes up in a
High Z state.
TAP Instruction Set
TAP Registers
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in “Instruction
Codes” on page 17. Three of these instructions are listed as
RESERVED and are not used. The other five instructions are
described in this section.
Registers are connected between the TDI and TDO pins
enabling data scanning into and out of the SRAM test circuitry.
Only one register is selected at a time through the Instruction
registers. Data is serially loaded into the TDI pin on the rising
edge of TCK. Data is output on the TDO pin on the falling edge
of TCK.
Instructions are loaded into the TAP controller during the Shift-IR
state when the Instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
Instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller is moved
into the Update-IR state.
Document Number: 001-06550 Rev. *D
Page 12 of 27
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
IDCODE
A vendor specific 32-bit code is loaded into the Instruction
register by the IDCODE instruction. It also places the Instruction
register between the TDI and TDO pins and enables shifting the
IDCODE out of the device when the TAP controller enters the
Shift-DR state. The IDCODE instruction is loaded into the
Instruction register upon power up or whenever the TAP
controller is in a Test-Logic-Reset state.
SAMPLE Z
The Boundary Scan register is connected between the TDI and
TDO pins when the TAP controller is in a Shift-DR state by the
SAMPLE Z instruction. The SAMPLE Z command puts the
output bus into a High Z state until the next command is issued
during the Update-IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
Instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the Boundary Scan register.
The TAP controller clock only operates at a frequency up to 20
MHz, while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in the clock
frequencies, it is possible that during the Capture-DR state an
input or output may undergo a transition. The TAP then tries to
capture a signal while in transition (metastable state). This does
not harm the device but there is no guarantee as to the value that
is captured. Repeatable results are not possible.
To guarantee that the Boundary Scan register captures the
correct value of a signal, the SRAM signal is stabilized long
enough to meet the TAP controller's capture setup plus hold
times (tCS and tCH). The SRAM clock input is not captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the Boundary Scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the Boundary
Scan register between the TDI and TDO pins.
The shifting of data for the SAMPLE and PRELOAD phases
occur concurrently when required — that is, while data captured
is shifted out, the preloaded data is shifted in.
BYPASS
When the BYPASS instruction is loaded in the Instruction
register and the TAP is placed in a Shift-DR state, the Bypass
register is placed between the TDI and TDO pins. The advantage
of the BYPASS instruction is that it shortens the boundary scan
path when multiple devices are connected together on a board.
EXTEST
The preloaded data is driven out through the system output pins
by the EXTEST instruction. This instruction also selects the
Boundary Scan register connected for serial access between the
TDI and TDO in the Shift-DR controller state.
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller puts the
output bus into a tri-state mode.
The Boundary Scan register has a special bit located at bit 108
called the “extest output bus tri-state”. When this scan cell is
latched into the Preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a High
Z condition.
This bit is set by entering the SAMPLE/PRELOAD or EXTEST
command, and then shifting the desired bit into that cell during
the Shift-DR state. During Update-DR, the value loaded into that
shift register cell latches into the Preload register. When the
EXTEST instruction is entered, this bit directly controls the output
Q-bus pins. Note that this bit is preset HIGH to enable the output
when the device is powered up and also when the TAP controller
is in the Test-Logic-Reset state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions
An initial data pattern is placed at the latched parallel outputs of
the Boundary Scan register cells before the selection of another
boundary scan test operation by PRELOAD.
Document Number: 001-06550 Rev. *D
Page 13 of 27
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
TAP Controller State Diagram
The state diagram for the TAP controller follows.[10]
1
TEST LOGIC
RESET
0
0
TEST LOGIC/
IDLE
1
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
0
SHIFT-DR
0
SHIFT-IR
1
1
1
EXIT1-DR
1
EXIT1-IR
0
0
0
PAUSE-DR
0
PAUSE-IR
1
1
0
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
UPDATE-IR
1
0
Note
10. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-06550 Rev. *D
Page 14 of 27
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
TAP Controller Block Diagram
0
Bypass Register
2
Selection
Circuitry
TDI
1
0
Selection
Circuitry
Instruction Register
31 30
29
.
.
2
1
0
1
0
TDO
Identification Register
108 .
.
.
.
2
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics
Over the Operating Range [11, 12, 13]
Parameter
Description
Test Conditions
Min
Max
Unit
VOH1
Output HIGH Voltage
IOH = −2.0 mA
1.4
V
1.6
V
VOH2
Output HIGH Voltage
IOH = −100 µA
VOL1
Output LOW Voltage
IOL = 2.0 mA
0.4
V
VOL2
Output LOW Voltage
IOL = 100 µA
0.2
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input and Output Load Current
0.65VDD VDD + 0.3
GND ≤ VI ≤ VDD
V
–0.3
0.35VDD
V
–5
5
µA
Notes
11. These characteristics apply to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in “Electrical Characteristics” on page 20.
12. Overshoot: VIH(AC) < VDDQ + 0.3V (pulse width less than tCYC/2). Undershoot: VIL(AC) > − 0.3V (pulse width less than tCYC/2).
13. All voltage refers to ground.
Document Number: 001-06550 Rev. *D
Page 15 of 27
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
TAP AC Switching Characteristics
Over the Operating Range [14, 15]
Parameter
Description
Min
Max
Unit
20
MHz
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH
20
ns
tTL
TCK Clock LOW
20
ns
tTMSS
TMS Setup to TCK Clock Rise
5
ns
tTDIS
TDI Setup to TCK Clock Rise
5
ns
tCS
Capture Setup to TCK Rise
5
ns
tTMSH
TMS Hold After TCK Clock Rise
5
ns
tTDIH
TDI Hold After Clock Rise
5
ns
tCH
Capture Hold After Clock Rise
5
ns
50
ns
Setup Times
Hold Times
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
10
0
ns
ns
TAP Timing and Test Conditions
Figure 2. TAP Timing and Test Conditions [15]
0.9V
ALL INPUT PULSES
50Ω
1.8V
0.9V
TDO
0V
Z0 = 50Ω
(a)
CL = 20 pF
GND
tTH
tTL
Test Clock
TCK
tTCYC
tTMSH
tTMSS
Test Mode Select
TMS
tTDIS
tTDIH
Test Data In
TDI
Test Data Out
TDO
tTDOV
tTDOX
Notes
14. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
15. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document Number: 001-06550 Rev. *D
Page 16 of 27
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
Identification Register Definitions
Instruction Field
Value
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
000
000
000
000
Revision Number
(31:29)
Description
Version number.
Cypress Device ID 11010111100000100 11010111100001100 11010111100010100 11010111100100100 Defines the type of
(28:12)
SRAM.
Cypress JEDEC ID
(11:1)
00000110100
00000110100
00000110100
00000110100
1
1
1
1
ID Register
Presence (0)
Enables unique
identification of
SRAM vendor.
Indicates the
presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
109
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the Boundary Scan register between TDI and
TDO. Forces all SRAM output drivers to a High Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the input and output ring contents. Places the Boundary Scan register between TDI
and TDO. Does not affect the SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the Bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 001-06550 Rev. *D
Page 17 of 27
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
Boundary Scan Order
Bit Number
Bump ID
Bit Number
Bump ID
Bit Number
Bump ID
Bit Number
Bump ID
0
6R
28
10G
56
6A
84
1J
1
6P
29
9G
57
5B
85
2J
2
6N
30
11F
58
5A
86
3K
3
7P
31
11G
59
4A
87
3J
4
7N
32
9F
60
5C
88
2K
5
7R
33
10F
61
4B
89
1K
6
8R
34
11E
62
3A
90
2L
7
8P
35
10E
63
2A
91
3L
8
9R
36
10D
64
1A
92
1M
9
11P
37
9E
65
2B
93
1L
10
10P
38
10C
66
3B
94
3N
11
10N
39
11D
67
1C
95
3M
12
9P
40
9C
68
1B
96
1N
13
10M
41
9D
69
3D
97
2M
14
11N
42
11B
70
3C
98
3P
15
9M
43
11C
71
1D
99
2N
16
9N
44
9B
72
2C
100
2P
17
11L
45
10B
73
3E
101
1P
18
11M
46
11A
74
2D
102
3R
19
9L
47
10A
75
2E
103
4R
20
10L
48
9A
76
1E
104
4P
21
11K
49
8B
77
2F
105
5P
22
10K
50
7C
78
3F
106
5N
23
9J
51
6C
79
1G
107
5R
24
9K
52
8A
80
1F
108
Internal
25
10J
53
7A
81
3G
26
11J
54
7B
82
2G
27
11H
55
6B
83
1H
Document Number: 001-06550 Rev. *D
Page 18 of 27
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Power Up Sequence in DDR-II+ SRAM
DLL Constraints
DDR-II+ SRAMs is powered up and initialized in a pre-defined
manner to prevent undefined operations. During power up, when
the DOFF is tied HIGH, the DLL is locked after 2048 cycles of
stable clock.
■
DLL uses K clock as its synchronizing input. The input has low
phase jitter that is specified as tKC Var.
■
The DLL functions at frequencies down to 120 MHz.
■
If the input clock is unstable and the DLL is enabled, then the
DLL locks onto an incorrect frequency. This causes unstable
SRAM behavior. To avoid this, provide 2048 cycles stable clock
to relock to the desired clock frequency.
Power Up Sequence
■
Apply power with DOFF tied HIGH (All other inputs are HIGH
or LOW)
❐ Apply VDD before VDDQ
❐ Apply VDDQ before VREF or at the same time as VREF
■
Provide stable power and clock (K, K) for 2048 cycles to lock
the DLL.
Power Up Waveforms
~
~
Figure 3. Power Up Waveforms
K
~
~
K
Unstable Clock
> 2048 Stable Clock
Start Normal
Operation
Clock Start (Clock Starts after VDD/VDDQ is Stable)
VDD/VDDQ
DOFF
Document Number: 001-06550 Rev. *D
VDD/VDDQ Stable (< + 0.1V DC per 50 ns)
Fix HIGH (tie to VDDQ)
Page 19 of 27
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Maximum Ratings
Current into Outputs (LOW) ........................................ 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Power Applied.. –55°C to +125°C
Supply Voltage on VDD Relative to GND ........–0.5V to +2.9V
Static Discharge Voltage (MIL-STD-883, M. 3015)... >2001V
Latch up Current..................................................... >200 mA
Operating Range
Range
Supply Voltage on VDDQ Relative to GND.......–0.5V to +VDD
Commercial
DC Applied to Outputs in High Z ........ –0.5V to VDDQ + 0.3V
Industrial
[12]
DC Input Voltage
Ambient
Temperature (TA)
VDD[16]
VDDQ[16]
0°C to +70°C
1.8 ± 0.1V
1.4V to
VDD
–40°C to +85°C
............................... –0.5V to VDD + 0.3V
Electrical Characteristics
Over the Operating Range[13]
DC Electrical Characteristics
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VDD
Power Supply Voltage
1.7
1.8
1.9
V
VDDQ
IO Supply Voltage
1.4
1.5
VDD
V
VOH
Output HIGH Voltage
Note 17
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOL
Output LOW Voltage
Note 18
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOH(LOW)
Output HIGH Voltage
IOH = –0.1 mA, Nominal Impedance
VDDQ – 0.2
VDDQ
V
VOL(LOW)
Output LOW Voltage
IOL = 0.1 mA, Nominal Impedance
VSS
0.2
V
VIH
Input HIGH Voltage
VREF + 0.1
VDDQ + 0.15
V
VIL
Input LOW Voltage
–0.15
VREF – 0.1
V
IX
Input Leakage Current
GND ≤ VI ≤ VDDQ
–2
2
µA
IOZ
Output Leakage Current
GND ≤ VI ≤ VDDQ, Output Disabled
–2
2
µA
VREF
Input Reference Voltage[19] Typical Value = 0.75V
0.95
V
IDD (x8)
VDD Operating Supply
mA
IDD (x9)
IDD (x18)
IDD (x36)
ISB1
VDD Operating Supply
VDD Operating Supply
VDD Operating Supply
Automatic Power Down
Current
0.68
0.75
VDD = Max,
IOUT = 0 mA,
f = fMAX = 1/tCYC
300 MHz
1100
333 MHz
1200
375 MHz
1300
VDD = Max,
IOUT = 0 mA,
f = fMAX = 1/tCYC
300 MHz
1100
333 MHz
1200
375 MHz
1300
VDD = Max,
IOUT = 0 mA,
f = fMAX = 1/tCYC
300 MHz
1100
333 MHz
1200
375 MHz
1300
VDD = Max,
IOUT = 0 mA,
f = fMAX = 1/tCYC
300 MHz
1100
333 MHz
1200
375 MHz
1300
Max VDD,
300 MHz
Both Ports Deselected,
333 MHz
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC, Inputs Static 375 MHz
450
mA
mA
mA
mA
500
525
Notes
16. Power up: assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
17. Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
18. Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
19. VREF (min) = 0.68V or 0.46VDDQ, whichever is larger. VREF (max) = 0.95V or 0.54VDDQ, whichever is smaller.
Document Number: 001-06550 Rev. *D
Page 20 of 27
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AC Electrical Characteristics
Over the Operating Range[12]
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VIH
Input HIGH Voltage
VREF + 0.2
–
VDDQ + 0.24
V
VIL
Input LOW Voltage
–0.24
–
VREF – 0.2
V
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Max
Unit
5.5
pF
8.5
pF
8
pF
Test Conditions
165 FBGA
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
11.82
°C/W
2.33
°C/W
Description
Test Conditions
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CO
Output Capacitance
TA = 25°C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
VREF = 0.75V
VREF
0.75V
VREF
OUTPUT
Z0 = 50Ω
Device
Under
Test
ZQ
RL = 50Ω
VREF = 0.75V
R = 50Ω
ALL INPUT PULSES
1.25V
0.75V
OUTPUT
Device
Under
Test ZQ
RQ =
250Ω
(a)
0.75V
INCLUDING
JIG AND
SCOPE
5 pF
[20]
0.25V
Slew Rate = 2 V/ns
RQ =
250Ω
(b)
Note
20. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, VREF = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input pulse
levels of 0.25V to 1.25V, output loading of the specified IOL/IOH, and load capacitance shown in (a) of AC Test Loads and Waveforms.
Document Number: 001-06550 Rev. *D
Page 21 of 27
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Switching Characteristics
Over the Operating Range [20, 21]
Cypress Consortium
Parameter Parameter
Description
VDD(Typical) to the First Access[22]
375 MHz
333 MHz
300 MHz
Min Max Min Max Min Max
1
–
1
–
ms
tCYC
tKHKH
K Clock Cycle Time
2.66 8.40
3.0
8.40
3.3
8.40
ns
tPOWER
1
–
Unit
tKH
tKHKL
Input Clock (K/K) HIGH
0.4
–
0.4
–
0.4
–
tCYC
tKL
tKLKH
Input Clock (K/K) LOW
0.4
–
0.4
–
0.4
–
tCYC
tKHKH
tKHKH
K Clock Rise to K Clock Rise (rising edge to rising edge)
1.13
–
1.28
–
1.40
–
ns
0.4
–
0.4
–
0.4
–
ns
Setup Times
tSA
tAVKH
Address Setup to K Clock Rise
tSC
tIVKH
Control Setup to K Clock Rise (LD, R/W)
0.4
–
0.4
–
0.4
–
ns
tSCDDR
tIVKH
Double Data Rate Control Setup to Clock (K/K) Rise
(BWS0, BWS1, BWS2, BWS3)
0.28
–
0.28
–
0.28
–
ns
tSD
tDVKH
D[X:0] Setup to Clock (K/K) Rise
0.28
–
0.28
–
0.28
–
ns
Hold Times
tHA
tKHAX
Address Hold After K Clock Rise
0.4
–
0.4
–
0.4
–
ns
tHC
tKHIX
Control Hold After K Clock Rise (LD, R/W)
0.4
–
0.4
–
0.4
–
ns
tHCDDR
tKHIX
Double Data Rate Control Hold After Clock (K/K) Rise
(BWS0, BWS1, BWS2, BWS3)
0.28
–
0.28
–
0.28
–
ns
tHD
tKHDX
D[X:0] Hold After Clock (K/K) Rise
0.28
–
0.28
–
0.28
–
ns
–
0.45
–
0.45
–
0.45
ns
–0.45
–
–0.45
–
–0.45
–
ns
–
0.45
–
0.45
–
0.45
ns
–0.45
–
–0.45
–
–0.45
–
ns
Output Times
tCO
tCHQV
K/K Clock Rise to Data Valid
tDOH
tCHQX
Data Output Hold After K/K Clock Rise (Active to Active)
tCCQO
tCHCQV
K/K Clock Rise to Echo Clock Valid
tCQOH
tCHCQX
Echo Clock Hold After K/K Clock Rise
tCQD
tCQHQV
Echo Clock High to Data Valid
tCQDOH
tCQHQX
Echo Clock High to Data Invalid
[23]
tCQH
tCQHCQL
Output Clock (CQ/CQ) HIGH
tCQHCQH
tCQHCQH
CQ Clock Rise to CQ Clock Rise [23]
(rising edge to rising edge)
tCHZ
tCHQZ
Clock (K/K) Rise to High Z (Active to High Z) [24, 25]
tCLZ
tQVLD
tCHQX1
tQVLD
Clock (K/K) Rise to Low Z
[24, 25]
Echo Clock High to QVLD Valid
[26]
–
0.2
–
0.2
–
0.2
ns
–0.2
–
–0.2
–
–0.2
–
ns
0.88
–
1.03
–
1.15
–
ns
0.88
–
1.03
–
1.15
–
ns
–
0.45
–
0.45
–
0.45
ns
–0.45
–
–0.45
–
–0.45
–
ns
–0.20 0.20 –0.20 0.20 –0.20 0.20
ns
DLL Timing
tKC Var
tKC Var
Clock Phase Jitter
–
0.20
–
0.20
–
0.20
ns
tKC lock
tKC lock
DLL Lock Time (K)
2048
–
2048
–
2048
–
Cycles
tKC Reset
tKC Reset
K Static to DLL Reset [27]
30
–
30
–
30
–
ns
Notes
21. When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is operated
and outputs data with the output timings of that frequency range.
22. This part has a voltage regulator internally; tPOWER is the time that the power is supplied above VDD minimum initially before a read or write operation is initiated.
23. These parameters are extrapolated from the input timing parameters (tKHKH - 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (tKC Var) is already
included in the tKHKH). These parameters are only guaranteed by design and are not tested in production
24. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ±100 mV from steady-state voltage.
25. At any given voltage and temperature, tCHZ is less than tCLZ and tCHZ less than tCO.
26. tQVLD specification is applicable for both rising and falling edges of QVLD signal.
27. Hold to >VIH or <VIL.
Document Number: 001-06550 Rev. *D
Page 22 of 27
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Switching Waveforms
Read/Write/Deselect Sequence [28, 29, 30]
Figure 5. Waveform for 2.0 Cycle Read Latency
READ
2
NOP
1
READ
3
NOP
5
NOP
4
NOP
6
WRITE
7
WRITE
8
READ
9
NOP
10
NOP
11
12
K
t KH
tCYC
t KL
t KHKH
K
LD
tSC tHC
R/W
A
A0
t SA t HA
A3
A2
A1
A4
t QVLD
tQVLD
t QVLD
QVLD
tHD
t HD
tSD
Q00
DQ
t
Q01 Q10
tCO
t CQOH
CQ
t CQOH
D20 D21
D30
D31
Q40 Q41
t CHZ
t DOH
CLZ
(Read Latency = 2.0 Cycles)
Q11
tSD
t CQD
t CCQO
t CCQO
t CQDOH
t CQH
t CQHCQH
CQ
DON’T CARE
UNDEFINED
Notes
28. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
29. Outputs are disabled (High-Z) one clock cycle after a NOP.
30. The third NOP cycle between read to write transition is not necessary for correct device operation when Read Latency = 2.0 cycles; however at high frequency operation,
it is required to avoid bus contention.
Document Number: 001-06550 Rev. *D
Page 23 of 27
CY7C1546V18
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CY7C1550V18
Ordering Information
Not all of the speed, package, and temperature ranges are available. Contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
375
Ordering Code
CY7C1546V18-375BZC
Package
Diagram
Package Type
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Operating
Range
Commercial
CY7C1557V18-375BZC
CY7C1548V18-375BZC
CY7C1550V18-375BZC
CY7C1546V18-375BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1557V18-375BZXC
CY7C1548V18-375BZXC
CY7C1550V18-375BZXC
CY7C1546V18-375BZI
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Industrial
CY7C1557V18-375BZI
CY7C1548V18-375BZI
CY7C1550V18-375BZI
CY7C1546V18-375BZXI
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1557V18-375BZXI
CY7C1548V18-375BZXI
CY7C1550V18-375BZXI
333
CY7C1546V18-333BZC
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Commercial
CY7C1557V18-333BZC
CY7C1548V18-333BZC
CY7C1550V18-333BZC
CY7C1546V18-333BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1557V18-333BZXC
CY7C1548V18-333BZXC
CY7C1550V18-333BZXC
CY7C1546V18-333BZI
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Industrial
CY7C1557V18-333BZI
CY7C1548V18-333BZI
CY7C1550V18-333BZI
CY7C1546V18-333BZXI
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1557V18-333BZXI
CY7C1548V18-333BZXI
CY7C1550V18-333BZXI
Document Number: 001-06550 Rev. *D
Page 24 of 27
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
Ordering Information
(continued)
Not all of the speed, package, and temperature ranges are available. Contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
300
Ordering Code
CY7C1546V18-300BZC
Package
Diagram
Package Type
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Operating
Range
Commercial
CY7C1557V18-300BZC
CY7C1548V18-300BZC
CY7C1550V18-300BZC
CY7C1546V18-300BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1557V18-300BZXC
CY7C1548V18-300BZXC
CY7C1550V18-300BZXC
CY7C1546V18-300BZI
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Industrial
CY7C1557V18-300BZI
CY7C1548V18-300BZI
CY7C1550V18-300BZI
CY7C1546V18-300BZXI
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1557V18-300BZXI
CY7C1548V18-300BZXI
CY7C1550V18-300BZXI
Document Number: 001-06550 Rev. *D
Page 25 of 27
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
Package Diagram
Figure 6. 165-Ball FBGA (15 x 17 x 1.40 mm)
"/44/- 6)%7
4/0 6)%7
Π- # ! "
Œ
0). #/2.%2
Π- #
0). #/2.%2
8
!
"
"
#
#
!
$
$
&
&
'
'
(
*
%
¼
%
(
*
+
,
,
+
-
-
.
.
0
0
2
2
!
"
¼
#
¼
¼
#
8
./4%3 3/,$%2 0!$ 490% ./. 3/,$%2 -!3+ $%&).%$ .3-$
0!#+!'% 7%)'(4 G
*%$%# 2%&%2%.#% -/ $%3)'. #
0!#+!'% #/$% ""!$
-!8
3%!4).' 0,!.%
#
51-85195-*A
Document Number: 001-06550 Rev. *D
Page 26 of 27
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
Document History Page
Document Title: CY7C1546V18/CY7C1557V18/CY7C1548V18/CY7C1550V18, 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
Document Number: 001-06550
REV.
ECN No.
Issue
Date
Orig. of
Change
**
432718
See ECN
NXR
Description of Change
New datasheet
*A
437000
See ECN
IGS
ECN for show on web
*B
461934
See ECN
NXR
Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH
from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching
Characteristics table
Modified Power up waveform
*C
497567
See ECN
NXR
Changed the VDDQ operating voltage to 1.4V to VDD in the Features section, Operating
Range table, and the DC Electrical Characteristics table
Added foot note in page 1
Changed the Maximum rating of ambient temperature with power applied from –10°C
to +85°C to –55°C to +125°C
Changed VREF (Max) specification from 0.85V to 0.95V in the DC Electrical Characteristics table and in the note below the table
Updated footnote 18 to specify overshoot and undershoot specifications
Updated IDD and ISB values
Updated ΘJA and ΘJC values
Removed x9 part and its related information
Updated footnote 25
*D
1351504 See ECN VKN/AESA Converted from preliminary to final
Added x8 and x9 parts
Updated logic block diagram for x18 and x36 parts
Changed tCYC max spec to 8.4 ns for all speed bins
Updated footnote# 21
Updated Ordering Information table
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-06550 Rev. *D
Revised August 7, 2007
Page 27 of 27
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
are the trademarks of their respective holders.