Cypress CY7C185 8k x 8 static ram Datasheet

1bCY7C185
CY7C185
8K x 8 Static RAM
Functional Description[1]
Features
• High speed
The CY7C185 is a high-performance CMOS static RAM
organized as 8192 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE1), an active
HIGH chip enable (CE2), and active LOW output enable (OE)
and tri-state drivers. This device has an automatic
power-down feature (CE1 or CE2), reducing the power
consumption by 70% when deselected. The CY7C185 is in a
standard 300-mil-wide DIP, SOJ, or SOIC package.
— 15 ns
• Fast tDOE
• Low active power
— 715 mW
• Low standby power
— 85 mW
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE1 and WE
inputs are both LOW and CE2 is HIGH, data on the eight data
input/output pins (I/O0 through I/O7) is written into the memory
location addressed by the address present on the address
pins (A0 through A12). Reading the device is accomplished by
selecting the device and enabling the outputs, CE1 and OE
active LOW, CE2 active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins are present on
the eight data input/output pins.
• CMOS for optimum speed/power
• Easy memory expansion with CE1, CE2 and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Available in non Pb-free 28-pin (300-Mil) Molded SOJ,
28-pin (300-Mil) Molded SOIC and both Pb-free and non
Pb-free in 28-pin (300-Mil) Molded DIP
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configurations
DIP/SOJ
Top View
I/O0
INPUT BUFFER
I/O2
SENSE AMPS
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
I/O1
8K x 8
ARRAY
I/O3
I/O4
I/O5
I/O6
CE1
CE2
WE
COLUMN DECODER
POWER
DOWN
NC
A4
A5
A6
A7
A8
A9
A10
A11
A12
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
CE2
A3
A2
A1
OE
A0
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
I/O7
A12
A11
A10
A0
A9
OE
Selection Guide
-15
15
130
15
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
-20
20
110
15
-25
25
100
15
-35
35
100
15
Notes:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05043 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 24, 2006
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CY7C185
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Operating Range
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
Range
DC Voltage Applied to Outputs
in High Z State[2] ............................................ –0.5V to +7.0V
Commercial
DC Input Voltage[2] ......................................... –0.5V to +7.0V
Industrial
Ambient
Temperature
VCC
0°C to +70°C
5V ± 10%
–40°C to +85°C
5V ± 10%
Electrical Characteristics Over the Operating Range
–15
Parameter
Description
Test Conditions
Min.
–20
Max.
Min.
2.4
–25, -35
Max.
Min.
VOH
Output HIGH
Voltage
VCC = Min.,
IOH = –4.0 mA
2.4
VOL
Output LOW
Voltage
VCC = Min.,
IOL = 8.0 mA
VIH
Input HIGH
Voltage
2.2
VCC + 0.3V
2.2
VCC + 0.3V
VIL
Input LOW
Voltage[2]
–0.5
0.8
–0.5
IIX
Input Leakage
Current
GND ≤ VI ≤ VCC
–5
+5
IOZ
Output Leakage GND ≤ VI ≤ VCC,
Current
Output Disabled
–5
+5
ICC
VCC Operating VCC = Max.,
Supply Current IOUT = 0 mA
130
ISB1
Automatic
Power-Down
Current
Max. VCC,
CE1 ≥ VIH or CE2 ≤ VIL
Min. Duty Cycle =100%
ISB2
Automatic
Power-Down
Current
Max. VCC,
CE1 ≥ VCC – 0.3V,
or CE2 ≤ 0.3V
VIN ≥ VCC – 0.3V or
VIN ≤ 0.3V
0.4
Max.
2.4
0.4
Unit
V
0.4
V
2.2
VCC + 0.3V
V
0.8
–0.5
0.8
V
–5
+5
–5
+5
µA
–5
+5
–5
+5
µA
110
100
mA
40
20
20
mA
15
15
15
mA
Capacitance[3]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
7
pF
7
pF
Notes:
2. Minimum voltage is equal to –3.0V for pulse durations less than 30 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05043 Rev. *B
Page 2 of 12
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CY7C185
AC Test Loads and Waveforms
R1 481 Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R1 481 Ω
5V
OUTPUT
5 pF
R2
255Ω
INCLUDING
JIGAND
SCOPE
(a)
ALL INPUT PULSES
3.0V
10%
GND
R2
255Ω
90%
10%
90%
≤ 5 ns
≤ 5 ns
Equivalent to:
(b)
THÉVENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Switching Characteristics Over the Operating Range[4]
-15
Parameter
Description
Min.
-20
Max.
Min.
-25
Max.
Min.
-35
Max.
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
15
20
tOHA
Data Hold from Address Change
tACE1
CE1 LOW to Data Valid
15
20
25
35
ns
tACE2
CE2 HIGH to Data Valid
15
20
25
35
ns
tDOE
OE LOW to Data Valid
8
9
12
15
ns
tLZOE
OE LOW to Low Z
15
3
5
3
Z[5]
25
20
5
3
7
35
25
5
3
ns
3
ns
OE HIGH to High
tLZCE1
CE1 LOW to Low Z[6]
3
5
5
5
ns
tLZCE2
CE2 HIGH to Low Z
3
3
3
3
ns
tHZCE
CE1 HIGH to High
CE2 LOW to High Z
tPU
CE1 LOW to Power-Up
CE2 to HIGH to Power-Up
tPD
CE1 HIGH to Power-Down
CE2 LOW to Power-Down
7
0
10
ns
tHZOE
Z[5, 6]
8
ns
35
8
0
15
10
10
0
20
10
0
20
ns
ns
ns
20
ns
Write Cycle[7]
tWC
Write Cycle Time
15
20
25
35
ns
tSCE1
CE1 LOW to Write End
12
15
20
20
ns
tSCE2
CE2 HIGH to Write End
12
15
20
20
ns
tAW
Address Set-up to Write End
12
15
20
25
ns
tHA
Address Hold from Write End
0
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
0
ns
tPWE
WE Pulse Width
12
15
15
20
ns
tSD
Data Set-up to Write End
8
10
10
12
ns
tHD
Data Hold from Write End
0
tHZWE
WE LOW to High Z[5]
tLZWE
WE HIGH to Low Z
0
7
3
0
7
5
0
7
5
ns
8
5
ns
ns
Notes:
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE1 and tLZCE2 for any given device.
7. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All 3 signals must be active to initiate a write and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05043 Rev. *B
Page 3 of 12
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CY7C185
Switching Waveforms
Read Cycle No.1[8,9]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No.2[10,11]
tRC
CE1
CE2
tACE
OE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
tHZCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPD
tPU
ICC
50%
50%
ISB
Notes:
8. Device is continuously selected. OE, CE1 = VIL. CE2 = VIH.
9. WE is HIGH for read cycle.
10. Data I/O is High Z if OE = VIH, CE1 = VIH, WE = VIL, or CE2=VIL.
11. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. CE1 and WE must be LOW and CE2 must be HIGH
to initiate write. A write can be terminated by CE1 or WE going HIGH or CE2 going LOW. The data input set-up and hold timing should be referenced to the
rising edge of the signal that terminates the write.
Document #: 38-05043 Rev. *B
Page 4 of 12
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CY7C185
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[9,11]
tWC
ADDRESS
tSCEI
CE1
tAW
tHA
tSCE2
CE
CE
2
tSA
WE
tPWE
OE
tSD
DATA I/O
tHD
DATA IN VALID
NOTE 12
tHZOE
Write Cycle No. 2 (CE Controlled)[11,12,13]
tWC
ADDRESS
tSCE1
CE1
tSA
tSCE2
CE2
tAW
tHA
WE
tSD
DATA I/O
tHD
DATA IN VALID
Notes:
12. During this period, the I/Os are in the output state and input signals should not be applied.
13. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05043 Rev. *B
Page 5 of 12
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CY7C185
Switching Waveforms (continued)
Write Cycle No. 3(WE Controlled, OE LOW)[11,12,13,14]
tWC
ADDRESS
CE1
tSCE1
CE2
tSCE2
tAW
tHA
tSA
WE
tSD
DATA I/O
NOTE 12
tHD
DATA IN VALID
tHZWE
tLZWE
Note:
14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05043 Rev. *B
Page 6 of 12
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CY7C185
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.2
SB
1.2
I CC
0.8
0.6
0.4
4.5
5.0
0.8
0.6
0.4
V CC=5.0V
V IN=5.0V
5.5
ISB
0.0
–55
6.0
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.6
1.4
1.3
NORMALIZED tAA
NORMALIZED t AA
125
1.2
1.1
TA =25°C
1.0
1.4
1.2
1.0
VCC =5.0V
0.8
0.9
0.8
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
0.6
–55
6.0
2.5
25.0
DELTA tAA (ns)
30.0
2.0
1.5
1.0
0.5
25
3.0
4.0
SUPPLY VOLTAGE (V)
Document #: 38-05043 Rev. *B
80
VCC =5.0V
TA =25°C
60
40
20
0
0.0
5.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
140
120
100
VCC =5.0V
TA =25°C
80
60
40
20
0
0.0
125
20.0
15.0
10.0
0.0
1.0
1.0
2.0
3.0
OUTPUT VOLTAGE (V)
4.0
NORMALIZED I CC vs. CYCLE TIME
1.25
VCC =4.5V
TA =25°C
5.0
2.0
100
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
3.0
1.0
120
AMBIENT TEMPERATURE (°C)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
0.0
0.0
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
NORMALIZED I PO
25
OUTPUT SINK CURRENT (mA)
0.0
4.0
I CC
0.2
I SB
0.2
1.0
0
200
400
600
800 1000
CAPACITANCE (pF)
NORMALIZED I CC
1.0
NORMALIZED I,CC
I
NORMALIZED I,CCI
SB
1.4
OUTPUT SOURCE CURRENT (mA)
Typical DC and AC Characteristics
VCC =5.0V
TA =25°C
VCC =0.5V
1.00
0.75
0.50
10
20
30
40
CYCLE FREQUENCY (MHz)
Page 7 of 12
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CY7C185
Truth Table
CE1
CE2
WE
OE
H
X
X
X
High Z
Input/Output
Deselect/Power-Down
Mode
X
L
X
X
High Z
Deselect/Power-Down
L
H
H
L
Data Out
Read
L
H
L
X
Data In
Write
L
H
H
H
High Z
Deselect
Address Designators
Address
Name
Address
Function
Pin
Number
A4
X3
2
A5
X4
3
A6
X5
4
A7
X6
5
A8
X7
6
A9
Y1
7
A10
Y4
8
A11
Y3
9
A12
Y0
10
A0
Y2
21
A1
X0
23
A2
X1
24
A3
X2
25
Ordering Information
Speed
(ns)
15
Ordering Code
CY7C185-15VC
Package
Name
51-85031
CY7C185-15VI
20
CY7C185-20PC
51-85014
CY7C185-20PXC
25
35
Package Type
28-pin (300-Mil) Molded SOJ
Commercial
28-pin (300-Mil) Molded SOJ
Industrial
28-pin (300-Mil) Molded DIP
Commercial
28-pin (300-Mil) Molded DIP (Pb-free)
CY7C185-20VC
51-85031
28-pin (300-Mil) Molded SOJ
CY7C185-25PC
51-85014
28-pin (300-Mil) Molded DIP
CY7C185-25VC
51-85031
28-pin (300-Mil) Molded SOJ
CY7C185-35PC
51-85014
28-pin (300-Mil) Molded DIP
CY7C185-35SC
51-85026
28-pin (300-Mil) Molded SOIC
Document #: 38-05043 Rev. *B
Operating
Range
Commercial
Commercial
Page 8 of 12
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CY7C185
Package Diagrams
28-pin (300-Mil) PDIP (51-85014)
SEE LEAD END OPTION
14
1
DIMENSIONS IN INCHES [MM] MIN.
MAX.
REFERENCE JEDEC MO-095
0.260[6.60]
0.295[7.49]
15
PACKAGE WEIGHT: 2.15 gms
28
0.030[0.76]
0.080[2.03]
SEATING PLANE
1.345[34.16]
1.385[35.18]
0.290[7.36]
0.325[8.25]
0.120[3.05]
0.140[3.55]
0.140[3.55]
0.190[4.82]
0.115[2.92]
0.160[4.06]
0.015[0.38]
0.060[1.52]
0.090[2.28]
0.110[2.79]
0.009[0.23]
0.012[0.30]
0.055[1.39]
0.065[1.65]
0.310[7.87]
0.385[9.78]
0.015[0.38]
0.020[0.50]
LEAD END OPTION
3° MIN.
SEE LEAD END OPTION
51-85014-*D
(LEAD #1, 14, 15 & 28)
Document #: 38-05043 Rev. *B
Page 9 of 12
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CY7C185
Package Diagrams (continued)
28-pin (300-Mil) Molded SOIC (51-85026)
NOTE :
PIN 1 ID
1. JEDEC STD REF MO-119
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT
14
DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE.
1
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE
3. DIMENSIONS IN INCHES
0.291[7.39]
MIN.
MAX.
4. PACKAGE WEIGHT 0.85gms
0.300[7.62]
0.394[10.01]
*
0.419[10.64]
15
28
PART #
S28.3 STANDARD PKG.
SZ28.3 LEAD FREE PKG.
0.026[0.66]
0.032[0.81]
SEATING PLANE
0.697[17.70]
0.713[18.11]
0.092[2.33]
0.105[2.67]
0.004[0.10]
0.050[1.27]
0.013[0.33]
0.004[0.10]
0.019[0.48]
0.0118[0.30]
*
0.015[0.38]
0.050[1.27]
0.0091[0.23]
0.0125[3.17]
*
TYP.
51-85026-*D
Document #: 38-05043 Rev. *B
Page 10 of 12
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CY7C185
Package Diagrams (continued)
28-pin (300-Mil) Molded SOJ (51-85031)
NOTE :
1. JEDEC STD REF MO088
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE
MIN.
MAX.
3. DIMENSIONS IN INCHES
DETAIL
A
EXTERNAL LEAD DESIGN
PIN 1 ID
14
1
0.291
0.300
15
0.330
0.350
28
OPTION 1
0.697
0.713
0.014
0.020
OPTION 2
SEATING PLANE
0.120
0.140
0.050
TYP.
0.026
0.032
0.013
0.019
A
0.007
0.013
0.004
0.025 MIN.
0.262
0.272
51-85031-*C
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05043 Rev. *B
Page 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C185
Document History Page
Document Title: CY7C185 8K x 8 Static RAM
Document Number: 38-05043
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
107145
09/10/01
SZV
Change from Spec number: 38-00037 to 38-05043
*A
116470
09/16/02
CEA
Add applications foot note to data sheet
*B
486744
See ECN
NXR
Changed Low standby power from 220mW to 85mW
Changed the description of IIX from Input Load Current to Input Leakage
Current in DC Electrical Characteristics table
Removed IOS parameter from DC Electrical Characteristics table
Updated the Ordering Information table
Document #: 38-05043 Rev. *B
Page 12 of 12
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