PD - 94365E IRF6604 Application Specific MOSFETs l Ideal for CPU Core DC-DC Converters l Low Conduction Losses l Low Switching Losses l Low Profile (<0.7 mm) l Dual Sided Cooling Compatible l Compatible with existing Surface Mount Techniques l HEXFET® Power MOSFET VDSS RDS(on) max Qg 30V 11.5mΩ@VGS = 7.0V 13mΩ@VGS = 4.5V 17nC DirectFET ISOMETRIC MQ Applicable DirectFET Outline and Substrate Outline (see p.9,10 for details) SQ SX ST MQ MX MT Description The IRF6604 combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to achieve the lowest on-state resistance charge product in a package that has the footprint of an SO-8 and only 0.7 mm profile. The DirectFET package is compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering techniques, when application note AN-1035 is followed regarding the manufacturing methods and process. The DirectFET package allows dual sided cooling to maximize thermal transfer in power systems, IMPROVING previous best thermal resistance by 80%. The IRF6604 balances both low resistance and low charge along with ultra low package inductance to reduce both conduction and switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power the latest generation of processors operating at higher frequencies. The IRF6604 has been optimized for parameters that are critical in synchronous buck converters including Rds(on) and gate charge to minimize losses in the control FET socket. Absolute Maximum Ratings Parameter VDS VGS ID @ TC = 25°C ID @ TA = 25°C ID @ TA = 70°C IDM PD @TA = 25°C PD @TA = 70°C PD @TC = 25°C Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 7.0V Continuous Drain Current, VGS @ 7.0V Continuous Drain Current, VGS @ 7.0V c TJ TSTG Pulsed Drain Current Power Dissipation Power Dissipation Power Dissipation Linear Derating Factor Operating Junction and Storage Temperature Range RθJA RθJA RθJA RθJC RθJ-PCB Junction-to-Ambient Junction-to-Ambient Junction-to-Ambient Junction-to-Case Junction-to-PCB Mounted g g Max. Units 30 ±12 49 12 9.2 92 2.3 1.5 42 0.018 -40 to + 150 V A W W/°C °C Thermal Resistance Parameter fj gj hj ij Notes through are on page 11 www.irf.com Typ. Max. Units ––– 12.5 20 ––– 1.0 55 ––– ––– 3.0 ––– °C/W 1 11/16/05 IRF6604 Static @ TJ = 25°C (unless otherwise specified) Parameter Min. Typ. Max. Units BVDSS ∆ΒVDSS/∆TJ RDS(on) Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance VGS(th) ∆VGS(th)/∆TJ IDSS Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current IGSS Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw Qoss RG td(on) tr td(off) tf Ciss Coss Crss Output Charge Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 30 ––– ––– ––– 1.3 ––– ––– ––– ––– ––– ––– 38 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 27 9.0 10 ––– -4.5 ––– ––– ––– ––– ––– ––– 17 4.1 1.0 6.3 5.6 7.3 9.5 1.1 11 4.3 18 25 2270 420 190 Conditions ––– V VGS = 0V, ID = 250µA ––– mV/°C Reference to 25°C, ID = 1mA mΩ VGS = 7.0V, ID = 12A 11.5 13 VGS = 4.5V, ID = 9.6A 2.1 V VDS = VGS, ID = 250µA ––– mV/°C 30 µA VDS = 24V, VGS = 0V 50 µA VDS = 30V, VGS = 0V VDS = 24V, VGS = 0V, TJ = 125°C 100 100 nA VGS = 12V -100 VGS = -12V ––– S VDS = 15V, ID = 9.6A 26 ––– VDS = 15V ––– nC VGS = 4.5V ––– ID = 9.6A ––– See Fig. 16 ––– ––– nC VDS = 16V, VGS = 0V 2.0 Ω ––– VDD = 15V, VGS = 4.5V ––– ID = 9.6A ––– ns Clamped Inductive Load ––– ––– VGS = 0V ––– pF VDS = 15V ƒ = 1.0MHz ––– e e e Avalanche Characteristics EAS Parameter Single Pulse Avalanche Energy IAR Avalanche Current EAR Repetitive Avalanche Energy c Typ. ––– d c Units mJ Max. 32 ––– 9.6 A ––– 0.23 mJ Diode Characteristics Parameter Min. Typ. Max. Units IS Continuous Source Current ––– ––– 42 ISM (Body Diode) Pulsed Source Current ––– ––– 92 VSD trr Qrr (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge ––– ––– ––– 0.94 31 26 1.2 47 39 2 c Conditions MOSFET symbol A V ns nC D showing the integral reverse G S p-n junction diode. TJ = 25°C, IS = 9.6A, VGS = 0V TJ = 25°C, IF = 9.6A di/dt = 100A/µs e e www.irf.com IRF6604 1000 1000 VGS 10V 7.0V 4.5V 4.0V 3.5V 3.3V 3.0V BOTTOM 2.7V VGS 10V 7.0V 4.5V 4.0V 3.5V 3.3V 3.0V BOTTOM 2.7V 100 TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP 2.7V 10 100 2.7V 10 20µs PULSE WIDTH Tj = 150°C 20µs PULSE WIDTH Tj = 25°C 1 1 0.1 1 10 0.1 100 1 100 VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 100.00 2.0 I D = 12A T J = 150°C 10.00 VDS = 15V 20µs PULSE WIDTH 1.00 2.5 3.0 3.5 VGS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics www.irf.com 4.0 1.5 (Normalized) T J = 25°C RDS(on) , Drain-to-Source On Resistance ID, Drain-to-Source Current (Α) 10 1.0 0.5 V GS = 7.0V 0.0 -60 -40 -20 0 20 40 60 TJ , Junction Temperature 80 100 120 140 160 ( ° C) Fig 4. Normalized On-Resistance Vs. Temperature 3 IRF6604 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd C, Capacitance(pF) Coss = Cds + Cgd Ciss 1000 Coss Crss 100 1 10 100 6.0 ID= 9.6A VGS , Gate-to-Source Voltage (V) 10000 VDS= 24V VDS= 15V 5.0 4.0 3.0 2.0 1.0 0.0 0 5 VDS, Drain-to-Source Voltage (V) 20 25 1000 ID, Drain-to-Source Current (A) 100 I SD , Reverse Drain Current (A) 15 Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage TJ = 25 ° C 1 V GS= 0 V 0.0 0.5 OPERATION IN THIS AREA LIMITED BY RDS(on) 100 TJ = 150 ° C 10 0.1 1.0 1.5 V SD,Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 4 10 Q G Total Gate Charge (nC) 10 100µsec 1msec 1 0.1 2.0 10msec Tc = 25°C Tj = 150°C Single Pulse 0 1 10 100 1000 VDS , Drain-toSource Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRF6604 2.0 VGS(th) Gate threshold Voltage (V) 12 ID , Drain Current (A) 9 6 3 1.8 1.6 1.4 ID = 250µA 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 25 50 75 100 125 150 ° -75 -50 -25 TA, Ambient Temperature (°C) 0 25 50 75 100 125 150 T J , Temperature ( °C ) Fig 9. Maximum Drain Current Vs. Ambient Temperature Fig 10. Threshold Voltage Vs. Temperature (Z thJA ) 100 D = 0.50 0.20 10 Thermal Response 0.10 0.05 P DM 0.02 1 t1 0.01 t2 SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = 2. Peak T 0.1 0.00001 0.0001 0.001 0.01 0.1 t1/ t 2 J = P DM x Z thJA 1 +TA 10 100 t 1, Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient www.irf.com 5 IRF6604 80 15V TOP VGS 20V + V - DD IAS A 0.01Ω tp Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp EAS , Single Pulse Avalanche Energy (mJ) D.U.T RG BOTTOM DRIVER L VDS ID 4.3A 7.7A 9.6A 60 40 20 0 25 50 75 100 125 150 ( ° C) Starting Tj, Junction Temperature Fig 12c. Maximum Avalanche Energy Vs. Drain Current LD I AS VDS Fig 12b. Unclamped Inductive Waveforms + VDD D.U.T Current Regulator Same Type as D.U.T. VGS Pulse Width < 1µs Duty Factor < 0.1% 50KΩ 12V .2µF Fig 14a. Switching Time Test Circuit .3µF D.U.T. + V - DS VDS 90% VGS 3mA 10% IG ID Current Sampling Resistors Fig 13. Gate Charge Test Circuit 6 VGS td(on) tr td(off) tf Fig 14b. Switching Time Waveforms www.irf.com IRF6604 D.U.T Driver Gate Drive + • • • • D.U.T. ISD Waveform Reverse Recovery Current + dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test P.W. Period * RG D= VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer - - Period P.W. + VDD + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent ISD Ripple ≤ 5% * VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs Id Vds Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Waveform www.irf.com 7 IRF6604 Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Synchronous FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. The power loss equation for Q2 is approximated by; * Ploss = Pconduction + Pdrive + Poutput ( 2 Ploss = Irms × Rds(on) ) Power losses in the control switch Q1 are given by; + (Qg × Vg × f ) Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput ⎛Q ⎞ + ⎜ oss × Vin × f + (Qrr × Vin × f ) ⎝ 2 ⎠ This can be expanded and approximated by; Ploss = (Irms × Rds(on ) ) 2 ⎛ ⎞ ⎛ Qgs 2 ⎞ Qgd +⎜I × × Vin × f ⎟ + ⎜ I × × Vin × f ⎟ ig ig ⎝ ⎠ ⎝ ⎠ + (Qg × Vg × f ) + ⎛ Qoss × Vin × f ⎞ ⎝ 2 ⎠ This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage. 8 *dissipated primarily in Q1. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Qoss Characteristic www.irf.com IRF6604 DirectFET Outline Dimension, MQ Outline (Medium Size Can, Q-Designation). Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET. This includes all recommendations for stencil and substrate designs. DIMENSIONS IMPERIAL METRIC MAX MIN CODE MIN MAX 6.35 0.246 A 0.250 6.25 5.05 0.189 B 4.80 0.199 3.95 0.152 C 0.156 3.85 0.45 0.014 D 0.35 0.018 0.72 0.027 E 0.028 0.68 0.72 0.027 F 0.028 0.68 0.73 0.027 G 0.69 0.029 0.61 0.022 H 0.024 0.57 0.27 0.009 J 0.23 0.011 1.70 0.062 K 0.067 1.57 3.12 0.116 L 0.123 2.95 0.70 0.023 M 0.59 0.028 0.08 0.001 N 0.003 0.03 0.17 0.003 P 0.08 0.007 www.irf.com 9 IRF6604 DirectFET Substrate and PCB Layout, MQ Outline (MediumSize Can, Q-Designation). Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET. This includes all recommendations for stencil and substrate designs. G = GATE D = DRAIN S = SOURCE D D G D 10 S S D www.irf.com IRF6604 DirectFET Tape & Reel Dimension (Showing component orientation). NOTE: Controlling dimensions in mm Std reel quantity is 4800 parts. (ordered as IRF6604). For 1000 parts on 7" reel, order IRF6604TR1 REEL DIMENSIONS STANDARD OPTION (QTY 4800) TR1 OPTION (QTY 1000) IMPERIAL IMPERIAL METRIC METRIC MAX CODE MIN MIN MAX MIN MIN MAX MAX N.C A 6.9 12.992 330.0 N.C 177.77 N.C N.C B 0.75 0.795 N.C 20.2 N.C 19.06 N.C N.C C 0.53 0.504 0.50 12.8 0.520 13.5 13.2 12.8 D 0.059 0.059 N.C 1.5 1.5 N.C N.C N.C E 2.31 3.937 N.C 100.0 58.72 N.C N.C N.C F N.C N.C 0.53 N.C N.C 0.724 18.4 13.50 G 0.47 0.488 N.C 12.4 0.567 11.9 14.4 12.01 H 0.47 0.469 N.C 11.9 11.9 0.606 15.4 12.01 LOADED TAPE FEED DIRECTION CODE A B C D E F G H www.irf.com DIMENSIONS IMPERIAL METRIC MIN MAX MIN MAX 0.311 0.319 7.90 8.10 0.154 0.161 3.90 4.10 0.469 0.484 11.90 12.30 0.215 0.219 5.45 5.55 0.201 0.209 5.10 5.30 0.256 0.264 6.50 6.70 0.059 N.C 1.50 N.C 0.059 0.063 1.50 1.60 11 IRF6604 DirectFET Part Marking Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25°C, L = 0.70mH RG = 25Ω, IAS = 9.6A. Pulse width ≤ 400µs; duty cycle ≤ 2%. Surface mounted on 1 in. square Cu board. Used double sided cooling , mounting pad. Mounted on minimum footprint full size board with metalized back and with small clip heatsink. TC measured with thermal couple mounted to top (Drain) of part. Rθ is measured at TJ of approximately 90°C. Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 11/05 12 www.irf.com Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/