Cypress CY7C1059DV33 8-mbit (1m x 8) static ram Datasheet

CY7C1059DV33
8-Mbit (1M x 8) Static RAM
Features
Functional Description
■
High speed
❐ tAA = 10 ns
■
Low active power
❐ ICC = 110 mA at 10 ns
■
Low CMOS standby power
❐ ISB2 = 20 mA
The CY7C1059DV33[1] is a high performance CMOS Static RAM
organized as 1M words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE), and tri-state drivers. To write to the device,
take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data
on the eight IO pins (IO0 through IO7) is then written into the
location specified on the address pins (A0 through A19).
■
2.0V data retention
■
Automatic power down when deselected
■
TTL-compatible inputs and outputs
■
Easy memory expansion with CE and OE features
■
Available in Pb-free 44-pin TSOP II package
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the IO pins.
The eight input or output pins (IO0 through IO7) are placed in a
high-impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), or a write operation is in
progress (CE LOW, and WE LOW).
The CY7C1059DV33 is available in 36-ball FBGA and 44-pin
TSOP II packages with center power and ground (revolutionary)
pinout.
Logic Block Diagram
IO0
INPUT BUFFER
IO1
IO2
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
1M x 8
ARRAY
IO3
IO4
IO5
IO6
CE
COLUMN DECODER
WE
A11
A12
A13
A14
A15
A16
A17
A18
A19
OE
IO7
POWER
DOWN
Note
1. For guidelines about SRAM system design, refer to the Cypress application note AN1064, SRAM System Guidelines available at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-00061 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 26, 2007
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CY7C1059DV33
Pin Configuration
Figure 1. Pin Diagram - 44-Pin TSOP II
Top View
NC
NC
A0
A1
A2
A3
A4
CE
IO0
IO1
VCC
VSS
IO2
IO3
WE
A5
A6
A7
A8
A9
NC
NC
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A18
A17
A16
A15
OE
IO 7
IO 6
VSS
VCC
IO 5
IO 4
A14
A13
A12
A11
A10
A19
NC
NC
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Document #: 001-00061 Rev. *C
–10
10
110
20
–12
12
100
20
Unit
ns
mA
mA
Page 2 of 9
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CY7C1059DV33
DC Input Voltage[2] ................................ –0.3V to VCC + 0.3V
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage............. ...............................>2001V
(MIL-STD-883, Method 3015)
Latch up Current...................................................... >200 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Operating Range
Supply Voltage on VCC to Relative GND[2] .....–0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State[2] .................................... –0.3V to VCC + 0.3V
Range
Ambient Temperature
VCC
Industrial
–40°C to +85°C
3.3V ± 0.3V
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
Voltage[2]
–10
Min
–12
Max
Min
2.4
Unit
Max
2.4
0.4
V
0.4
V
2.0
VCC + 0.3
2.0
VCC + 0.3
V
–0.3
0.8
–0.3
0.8
V
VIL
Input LOW
IIX
Input Leakage Current
GND < VI < VCC
–1
+1
–1
+1
μA
IOZ
Output Leakage Current
GND < VOUT < VCC, Output Disabled
–1
+1
–1
+1
μA
ICC
VCC Operating
Supply Current
VCC = Max., f = fMAX = 1/tRC
110
100
mA
ISB1
Automatic CE Power Down
Current —TTL Inputs
Max. VCC, CE > VIH VIN > VIH
or VIN < VIL, f = fMAX
40
35
mA
ISB2
Automatic CE Power Down
Current —CMOS Inputs
Max. VCC, CE > VCC – 0.3V,
VIN > VCC – 0.3V, or VIN < 0.3V, f = 0
20
20
mA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.]
Parameter
Description
CIN
Input Capacitance
COUT
IO Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Max
Unit
12
pF
12
pF
Test Conditions
TSOP II
Unit
Still Air, soldered on a 3 × 4.5 inch, four-layer printed
circuit board
51.43
°C/W
15.8
°C/W
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Notes
2. VIL(min) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-00061 Rev. *C
Page 3 of 9
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CY7C1059DV33
AC Test Loads and Waveforms
AC characteristics (except High-Z) are tested using the load conditions shown in Figure 2 (a). High-Z characteristics are tested for all
speeds using the test load shown in Figure 2 (c).
Figure 2. AC Test Loads and Waveforms
Z = 50Ω
ALL INPUT PULSES
3.0V
OUTPUT
90%
50Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
30 pF*
GND
90%
10%
10%
1.5V
High-Z characteristics:
(b)
Rise Time: 1 V/ns
(a)
Fall Time: 1 V/ns
R 317Ω
3.3V
OUTPUT
R2
351Ω
5 pF
(c)
Data Retention Characteristics
Over the Operating Range
Parameter
Conditions[4]
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR[3]
Chip Deselect to Data
Retention Time
tR[5]
Operation Recovery Time
Min
Max
Unit
20
mA
2.0
VCC = VDR = 2.0V, CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
V
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
3.0V
VDR > 2V
tCDR
3.0V
tR
CE
Notes
4. No inputs may exceed VCC + 0.3V.
5. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 μs or stable at VCC(min) > 50 μs.
Document #: 001-00061 Rev. *C
Page 4 of 9
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CY7C1059DV33
AC Switching Characteristics
Over the Operating Range[6]
Parameter
Description
–10
Min
–12
Max
Min
Max
Unit
Read Cycle
tpower[7]
VCC(typical) to the First Access
100
100
μs
tRC
Read Cycle Time
10
12
ns
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
10
2.5
12
2.5
ns
ns
tACE
CE LOW to Data Valid
10
12
ns
tDOE
OE LOW to Data Valid
5
6
ns
tLZOE
OE LOW to Low-Z
tHZOE
OE HIGH to
Low-Z[9]
tLZCE
CE LOW to
tHZCE
CE HIGH to High-Z[8, 9]
tPU
CE LOW to Power up
tPD
Write Cycle
0
High-Z[8, 9]
0
5
3
6
3
5
0
CE HIGH to Power down
ns
ns
6
0
10
ns
ns
ns
12
ns
[10, 11]
tWC
Write Cycle Time
10
12
ns
tSCE
CE LOW to Write End
7
8
ns
tAW
Address Setup to Write End
7
8
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Setup to Write Start
0
0
ns
tPWE
WE Pulse Width
7
8
ns
tSD
Data Setup to Write End
5
6
ns
tHD
Data Hold from Write End
0
0
ns
tLZWE
WE HIGH to Low-Z[9]
3
3
ns
tHZWE
WE LOW to
High-Z[8, 9]
5
6
ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
7. tPOWER is the minimum amount of time that the power supply must be at stable, typical VCC values until the first memory access can be performed.
8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of “AC Test Loads and Waveforms” on page 4. Transition is measured when
the outputs enter a high impedance state.
9. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
10. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either
of these signals can terminate the write. The input data setup and hold timing must refer to the leading edge of the signal that terminates the Write.
11. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 001-00061 Rev. *C
Page 5 of 9
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CY7C1059DV33
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
Figure 3. Read Cycle No. 1[12, 13]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
Figure 4. Read Cycle No. 2[13, 14]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZCE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
ICC
50%
ISB
Notes
12. Device is continuously selected. OE, CE = VIL.
13. WE is HIGH for Read cycle.
14. Address valid before or coincident with CE transition LOW.
Document #: 001-00061 Rev. *C
Page 6 of 9
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CY7C1059DV33
Switching Waveforms(continued)
Write Cycle No. 1(WE Controlled, OE HIGH During Write)
Figure 5. Write Cycle No. 1[15, 16]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 17
tHZOE
Write Cycle No. 2 (WE Controlled, OE LOW)
Figure 6. Write Cycle No. 2[16]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
DATA I/O
NOTE 17
tHD
DATA VALID
tHZWE
tLZWE
Notes
15. Data IO is high-impedance if OE = VIH.
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
17. During this period the IOs are in the output state and input signals must not be applied.
Document #: 001-00061 Rev. *C
Page 7 of 9
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CY7C1059DV33
Truth Table
CE
H
OE
X
WE
X
IO0–IO7
High-Z
Mode
Power Down
Power
Standby (ISB)
L
L
H
Data Out
Read
Active (ICC)
L
X
L
Data In
Write
Active (ICC)
L
H
H
High-Z
Selected, Outputs Disabled
Active (ICC)
Ordering Information
Speed
(ns)
Ordering Code
Package
Diagram
Package Type
10
CY7C1059DV33-10ZSXI
51-85087
44-pin TSOP II (Pb-Free)
12
CY7C1059DV33-12ZSXI
51-85087
44-pin TSOP II (Pb-Free)
Operating
Range
Industrial
Contact your local Cypress sales representative for availability of these parts.
Package Diagrams
Figure 7. 44-Pin TSOP II (51-85087)
51-85087-*A
Document #: 001-00061 Rev. *C
Page 8 of 9
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CY7C1059DV33
Document History Page
Document Title: CY7C1059DV33, 8-Mbit (1M x 8) Static RAM
Document Number: 001-00061
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
342195
See ECN
PCI
New Data Sheet
*A
380574
See ECN
SYT
Redefined ICC values for Com’l and Ind’l temperature ranges
ICC (Com’l): Changed from 110, 90 and 80 mA to 110, 100 and 95 mA for 8,
10 and 12 ns speed bins respectively
ICC (Ind’l): Changed from 110, 90 and 80 mA to 120, 110 and 105 mA for 8,
10 and 12 ns speed bins respectively
Changed the Capacitance values from 8 pF to 10 pF on Page # 3
*B
485796
See ECN
NXR
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Removed -8 and -12 Speed bins from product offering,
Removed Commercial Operating Range option,
Modified Maximum Ratings for DC input voltage from -0.5V to -0.3V and
VCC + 0.5V to VCC + 0.3V
Updated footnote #7 on High-Z parameter measurement
Added footnote #11
Changed the Description of IIX from Input Load Current to
Input Leakage Current.
Updated the Ordering Information table and Replaced Package Name column
with Package Diagram.
*C
1513285
See ECN
VKN/AESA Converted from preliminary to final
Added 12 ns speed bin
Changed CIN and COUT specs from 16 pF to 12 pF
Changed tOHA spec from 3 ns to 2.5 ns
Updated Ordering information table
© Cypress Semiconductor Corporation, 2005-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-00061 Rev. *C
Revised September 26, 2007
Page 9 of 9
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